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us Press here Embedded System PART 5 (Timers) ENG.KEROLES SHENOUDA
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us Press here Previous Session covered .. 2
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us Press here Previous session 3 Covered those points Interrupt
definition & Servicing Interrupts IVT & ISR & Vector
Section Polling vs. Interrupt Steps in executing an interrupt
Sequential interrupt processing VS Nested interrupt processing
Types of Interrupts Interrupt Controller Examples On Interrupt
Controllers Interrupt Controller On Atmega32
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us Press here How to generate assembly file from elf image
(executable file)? 4
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us Press here Disable auto generate MakeFile 5
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us Press here Add this command on your MakeFile 6
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us Press here Then Build you will see
ATMEGA32_Drivers_disassemply.txt is generated 7 Now you can see the
_Vectors section
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us Press here 8 Interrupts & Timers Interrupt Latency: Time
from event to execution of service routine Interrupt Response Time:
Interrupt latency + Time for service routine Interrupt Termination:
Time taken after interrupt service routine
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us Press here Timer EMBEDDED MODULE (GENERIC CONCEPT) 9
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us Press here What is a timer ? At a high level, a timer is just a
Counter register that counts up or down automatically. A Counter
can be used to keep track of time. It can increment/decrement a
count register based on a clock and to check if the count has
reached some value and trigger an action. 17 Peripherals Timers
generally have a resolution of 8 or 16 or 32 Bits. So a 8 bit timer
is 8Bits wide so capable of holding value within 0-255. But this
register has a magical property ! Its value increases/decreases
automatically at a predefined rate (supplied by user). This is the
timer clock. And this operation does not need CPUs attention.
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us Press here Counters Counter: like a timer, but counts pulses on
a general input signal rather than clock e.g., count cars passing
over a sensor Can often configure device as either a timer or
counter 11 16-bit up counter Clk 16 Cnt_in 2x1 mux Mode
Timer/counter Top Reset Cnt
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us Press here HOW TO COUNT Up: the timer starts at zero, then
counts up until it hits some maximum value. The maximum value is
stored in a special register called a compare register. The maximum
value can be the largest value the timer register can hold (like
0xFF for 1Byte Counter) or some arbitrary value. Down: the timer
starts at some value you set and counts down until it reaches zero.
Up/Down: the timer counts up until it reaches the value in the
compare register, and then counts down until it reaches zero. 12
Counter register External source Oscillator Counter/Timer COUT 0 1
Flag
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us Press here Timer used to timer will produce a regular output
with the same accuracy as the input clock. This output could be
used to generate a periodic interrupt like a real-time operating
system (RTOS) timer tick. provide a baud rate clock to a UART.
drive any device that requires a regular pulse. Delay generating
Counting Wave-form generating Capturing 13
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us Press here Timer Infra Structure 14 If we want to calculate 1ms
CLK Oscillator = 24 MHz Timer clock= (24 / 12) MHz = 2 MHz Timer
cycle = 500ns Delay count = delay time / cycle time 1 ms / 500 ns =
2000 Counter numbers= (216 -1)-2000 = 63535 Set Count value 63535
to max or set count 0 > 2000-1 16-bit counterClk 16 External
Clock 2x1 mux Mode Controller irq Reset Cnt Clock Divider External
Input Pin Output pin
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us Press here Timer Infra Structure Timer May have a number of
counters is called Channel Each channel have a counter 15
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us Press here Timer Modes Group 16 Synchronous Modes/ Cascaded
counters Asynchronous Mode/ Independent Modes The Master Channel
Out will Control the other Channels Maybe each channel/counter runs
in different Mode
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us Press here Watchdog (WDOG) 17
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us Press here Watchdog (WDOG) WDOG is intended to be used to apply
a reset to a system in the event of a failure. WDOG consists of
counter with a programmable timeout interval that has the
capability to generate an interrupt and a reset signal on timing
out. For normal operation the software has to ensure that the
counter never reaches zero (kicking the dog) Usually WDOG interrupt
is set with highest priority. 18
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us Press here Timers in ATMEGA32 TWO 8-BIT TIMERS AND ONE 16-BIT
TIMER IN ATMEGA32 19
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us Press here Timers in ATMEGA32 TCNTn (Timer/Counter register)
TOVn (Timer Overflow flag) TCCRn (Timer Counter control register)
OCRn (output compare register) OCFn (output compare match flag) 20
Flag Counter register External source Oscillator Counter/Timer
TCNTn TCCRn TOVn OCRn = OCFn Comment: All of the timer registers
are byte-addressable I/O registers
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us Press here Atmega 32 Timer 0 Modes Normal Mode Clear Timer on
Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode
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us Press here Hand Writing Notes 22
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us Press here Hand Writing Notes 23
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us Press here Hand Writing Notes 24
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us Press here Normal Mode The simplest mode of operation is the
Normal mode (WGM01:0 = 0). In this mode the counting direction is
always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP
= 0xFF) and then restarts from the bottom (0x00). In normal
operation the Timer/Counter Overflow Flag (TOV0) will be set in the
same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in
this case behaves like a ninth bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that
automatically clears the TOV0 Flag, the timer resolution can be
increased by software. There are no special cases to consider in
the Normal mode, a new counter value can be written anytime. The
Output Compare unit can be used to generate interrupts at some
given time. Using the Output Compare to generate waveforms in
Normal mode is not recommended, since this will occupy too much
ofthe CPU time. 25
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us Press here Example 1: write a program that waits 14 machine
cycles in Normal mode. DDRB = 1
