Ic tech unit 5- VLSI Process Integration

IC TECHNOLOGY VIII SEM.(ECE)

By:Kritica Sharma

Assistant Professor (ECE)

ARYA GROUP OF COLLEGES

Unit- V

VLSI PROCESS INTEGRATION

CONTENTS

2

Junction and Oxide Isolation LOCOS methods Trench Isolation SOI; Metallization, Planarization Fundamental consideration for IC Processing: NMOS IC Technology CMOS IC Technology Bipolar IC Technology Fault diagnosis and characterization techniques.

Blown up

1. Junction & oxide isolation

1.1 Device isolation1.2 Isolation technique1.3 Junction & oxide isolation1.4 Emitter isolation1.5 Isolation length

2. LOCOS

2.1 Definition

2.2 Basic concepts

2.3 Steps of fabricating LOCOS

Blown up

3. Trench isolation

3.1 Definition of shallow trench3.2 Definition of deep trench isolation3.3 Comparison of STI & LOCOS3.4 Shallow trench isolation3.5 CMP for STI3.6 Deep trench isolation3.7 Fabrication process of deep trench isolation

4. Silicon on insulator techniques(SOI)

4.1 Definition of SOI4.2 Industrial need of SOI4.3 SOI techniques4.4 Methods of SOI isolation4.5 Dielectric isolation4.6 Wafer bonding

Blown up

5. Metallization

5.1 Definition5.2 Multilevel metallization5.3 Interconnection material5.4 Metal requirement5.5 Junction spiking5.6 Stress migration5.7 Electromigration

6. Planarization

6.1 Definition 6.2 Process of planarization6.3 Working principle

7. NMOS IC technology

7.1 Definition & basic concepts 7.2 Fabrication process for NMOS7.3 Advantages/Disadvantages of NMOS

Blown up

8. CMOS IC technology

8.1 Basic concepts8.2 Fabrication process for CMOS8.3 Advantages/Disadvantages

9. Bipolar IC technology

9.1 Basic concepts9.2 Steps of fabrication9.3 Advantages and limitations

10. Fault diagnosis & characterization technique

10.1 Basic concepts10.2 Combinational fault diagnosis methods10.3 Sequential fault diagnosis methods10.4 Characterization techniques

BASIC DEFINITIONS

1. VLSI Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip.

2. Device isolation It is the ability of the technology to allow each device to operate independently of the state of the other. Unless the technology is limited to discrete devices.

3. LOCOS LOCOS, short for LOCal Oxidation of Silicon, is a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si-SiO2 interface at a lower point than the rest of the silicon surface.

4. Trench isolation A trench is a type of excavation or depression in the ground that is generally deeper than it is wide (as opposed to a wider gully, or ditch), and narrow compared to its length (as opposed to a simple hole).

5. Shallow trench isolation

Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller.

6. Deep trench isolation

It is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components using trenches of fixed width.

7. Silicon on insulator

Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance.

8. Dielectric isolation

Dielectric isolation, is the process of electrically isolating various components in the IC chip from the substrate and from each other by an insulating layer.

9. Metallization Metallization is the process that makes accessible the IC to the outside world through conducting pads

10. Junction spiking

The penetration of a junction by aluminum, which occurs when silicon near the junction dissolves in aluminum and migrates along the interconnect lines. Aluminum then replaces silicon at the junction.

11. Stress migration Stress migration is a failure mechanism that often occurs in integrated circuit metallization (aluminum, copper). Voids form as result of vacancy migration driven by the hydrostatic stress gradient. Large voids may lead to open circuit or unacceptable resistance increase that impedes the IC performance.

12. Electromigration Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms.

13. Planarization Chemical mechanical polishing/planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing.

14. NMOS IC technology

N-type metal-oxide-semiconductor logic uses n-type field effect transistors to implement logic gates and other digital circuits.

15. Diagnostic resolution A unit under test (UUT) fails when its observed behavior is different from its expected behavior. Diagnosis consists of locating the physical fault(s) in a structural model of the UUT. The degree of accuracy to which faults can be located is called diagnostic resolution.

16. Functionally equivalent faults

Functionally equivalent faults (FEF) cannot be distinguished. The partition of all faults into distinct subsets of FEF defines the maximal fault resolution. A test that achieves the maximal fault resolution is said to be a complete fault-location test.

17. Fault table A fault table is a matrix where columns Fj represent faults, rows Ti represent test patterns, and aij = 1 if the test pattern Ti detects the fault Fj, otherwise if the test pattern Ti does not detect the fault Fj, aij = 0.

18. Fault dictionaries Fault dictionaries (FD) contain the same data as the fault tables with the difference that the data is reorganized. In FD a mapping between the potential results of test experiments and the faults is represented in a more compressed and ordered form.

19. Adaptive testing In sequential fault diagnosis the process of fault location is carried out step by step, where each step depends on the result of the diagnostic experiment at the previous step. Such a test experiment is called adaptive testing.

20. Diagnostic tree Sequential experiments can be carried out either by observing only output responses of the UUT or by pinpointing by a special probe also internal control points of the UUT (guided probing). Sequential diagnosis procedure can be graphically represented as diagnostic tree.

VLSI DEFINITION: Very-large-scale integration (VLSI) is

the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip.

https://www.youtube.com/watch?v=Q5paWn7bFg4&list=PLJqogrYlIWSsCOGWb5MmwohySBWrM2ofm



VLSI

DEVICE ISOLATION Definition: It is the ability of the technology to allow each device to

operate independently of the state of the other. Unless the technology is limited to discrete devices.

Isolation Techniques: Diffusion isolation with reverse biased diodes:• Historically used for bipolar• Currently used to isolate NMOS from PMOS through a well. Oxide isolation:• Used in early days of MOS • Field can’t be implanted for parasitic transistor Vt control • Step height is too much

CONTD.. Local oxidation of silicon (LOCOS) • Main method used today in a variety of forms e. g., semi-recessed

LOCOS, fully-recessed LOCOS, SWAMI, poly-buffered LOCOS.• 0.6 µm pitch: LOCOS limit if thick (>300 nm) field oxides are

required. 0.4 µm pitch with recessed LOCOS (200 nm field oxide) Trench isolation • Cutting edge technology today

JUNCTION AND OXIDE ISOLATION

There are several options for device isolation in Si and GaAs technologies and evaluate each according to the density, yield, planarity and parasitic effects.

Steps for construction of Bipolar ICs:1. Diffuse a deep p layer and a shallower N+ layer into an n type

substrate.2. The substrate acts as the common collector.3. An insulating layer is then deposited on substrate, contacts are

patterned and etched and the interconnect is applied and patterned.

https://www.youtube.com/watch?v=slxAEdmgODg



JUNCTION ISOLATION TO LOCOS

Simple junction isolation in a bipolar transistors technology with a common collector

CONTD..4. Emitter isolation: Emitter of two adjacent transistors are

automatically isolated from each other by the fact that each emitter is totally enclosed in the base diffusion.

5. Base layer isolation: for base layer to be isolated from each other, there must be a large energy barrier between the holes in the two base regions.

As the height of the barrier decreases, the leakage between the bases increases exponentially.

Measure of isolation: Depletion layer associated with the two base collector junction do

no touch.

CONTD.. For a simple one sided step junction, the depletion layer thickness is:

Where, = the relative permittivity of Si = built in voltage of junction

= intrinsic carrier concentration

D

CBbisD qN

VVkW )(2 0

skbiV

2lni

DAbi n

NNq

kTV

in

Simple calculation of average isolation distance required between transistors as a

function of device density

CONTD.. Isolation length: to get an estimate for the isolation length required

for a technology, consider the densest portion of the circuit. According to the graph displayed in previous slide; it reads off the

maximum permissible isolation distance. If the densest portion of the circuit is transistors/sqcm and 50%

of the area is active in that region, the device separation must be 10µm or less.

For a random logic circuit, the isolation distance should be less than twice the first metal pitch.

One more aspect about the graph is that the circuit density is a sensitive function of the isolation distance

Reducing the isolation distance by a factor of 3 allows an order of magnitude increase in the circuit density.

510

CONTD.. Steps for construction of MOSFET:1. Add an insulating layer and a metal line that happens to pass over

on the bipolar transistor, but does not contact both transistors.2. The collector of the two transistors acts as the source and drain of

the MOSFET, and the metal line acts as gate.3. If a large positive bias exists on the line, the surface under the line

may invert, turning on the parasitic MOSFET.4. This effect will short out the two collectors, even if they are

sufficiently far apart so that the depletion regions do not touch.

Cross section of simple bipolar technology with a metal line crossing the junction isolation region,

forming a parasitic MOSFET

CONTD.. The MOSFET threshold for NMOS transistors on p type substrate is

given by:

Where:

= the metal semiconductor work function

0

42

s

fA

ox

oxsfmsT k

qNktkV

i

Af n

Nq

kT ln

ms

CONTD.. Since the intrinsic carrier concentration increases with temperature,

the parasitic threshold voltage may shift by several volts when operating at high temperatures.

The source to drain current of an MOS device increases exponentially with gate voltage in the sub-threshold regime.

We need to make the threshold of these parasitic transistors at least 2 times the supply voltage.

It ensures that they will not turn on, even in the presence of an excessive supply voltage and voltage spikes on the supply line, nor will the leakage currents be excessive.

as a function of the assuming no . Solid lines are a perfect interface, dotted lines are for

TVAN 0ms

21110 cmN it

CONTD.. The graph shows a plot of threshold voltage versus the substrate

concentration with oxide thickness as a parameter. He oxide thickness was varied from 0.2 to 1.0 µm in 0.2µm

increments. Also included is the threshold voltage if a total fixed charge of is present. To achieve a suitably large parasitic threshold, one must select a

thick field oxide and a large substrate concentration. The large substrate concentration degrades the performance due to

junction capacitance. The thicker oxide improves both performance and parasitic turn on,

but obviously due to effect of oxide charge, some substrate doping is required even for very thick field oxide.

21110 cm

Guard ring isolation for the bipolar technology

CONTD.. The device separation can be reduced and the parasitic threshold

increased by adding a p+ diffused barrier ring around each device. Guard rings require an additional masks that must be aligned to the

transistor. The guard ring must be deep(at least 2µm) or the depletion region

will simply extend beneath the guard ring, shorting out the devices. The large thermal cycle needed to produce such a deep junction

must be done early in process.

ADVANTAGES Junction isolation is simple and produce a planar isolation. It have a high yield . Density is not large. Increasing the substrate concentration increases the density but also

increases the capacitance. Guard rings improves the prevention of turning on parasitic MOS

devices. It is cheap.

LOCOS Definition: LOCOS, short for LOCal Oxidation of Silicon, is

a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si-SiO2 interface at a lower point than the rest of the silicon surface.

https://www.youtube.com/watch?v=9IbID_ajhak



LOCOS

LOCOS DEFINED LOCOS = LOCal Oxidation of Silicon Defines a set of fabrication technologies where

the wafer is masked to cover all active regions thick field oxide (FOX) is grown in all non-active regions

Used for electrical isolation of CMOS devices

Relatively simple to understand so often used to introduce/describe CMOS fabrication flows

Not commonly used in modern fabrication other techniques, such as Shallow Trench Isolation (STI) are

currently more common than LOCOS

LOCOS –STEP 1Form N-Well regions Grow oxide Deposit photoresist

Layout view

Cross section view

p-type substrate

NWELL mask

NWELL mask

oxide photoresist

LOCOS –STEP 1Form N-Well regions Grow oxide Deposit photoresist Pattern photoresist

NWELL Mask expose only n-well areas

Layout view

Cross section view

p-type substrate

NWELL mask

NWELL mask

oxide photoresist



Etch oxide Remove photoresist

Layout view

Cross section view

p-type substrate

oxide



Etch oxide Remove photoresist Diffuse n-type dopants through oxide mask layer

Layout view

Cross section view

p-type substrate

n-well

LOCOS –STEP 2Form Active Regions Deposit SiN over wafer Deposit photoresist over SiN layer

ACTIVE mask

ACTIVE mask

SiN photoresist

p-type substrate

n-well

LOCOS –STEP 2Form Active Regions Deposit SiN over wafer Deposit photoresist over SiN layer Pattern photoresist

*ACTIVE MASK

ACTIVE mask

ACTIVE mask

SiN photoresist

p-type substrate

n-well


*ACTIVE MASK Etch SiN in exposed areas

leaves SiN mask which blocks oxide growth

ACTIVE mask

SiN photoresist

p-type substrate

n-well




Remove photoresist Grow Field Oxide (FOX)

thermal oxidation

ACTIVE mask

p-type substrate

n-well

FOX




Remove photoresist Grow Field Oxide (FOX)

thermal oxidation Remove SiN

ACTIVE mask

p-type substrate

n-well

FOX

LOCOS –STEP 3Form Gate (Poly layer) Grow thin Gate Oxide

over entire wafer negligible effect on FOX regions

gate oxide


over entire wafer negligible effect on

FOX regions Deposit Polysilicon Deposit Photoresist

gate oxide

POLY mask

POLY mask

polysilicon



FOX regions Deposit Polysilicon Deposit Photoresist Pattern Photoresist

*POLY MASK Etch Poly in exposed

areas Etch/remove Oxide

gate protected by poly

gate oxide

POLY mask

POLY mask



FOX regions Deposit Polysilicon Deposit Photoresist Pattern Photoresist

*POLY MASK Etch Poly in exposed

areas Etch/remove Oxide

gate protected by poly

gate oxide

LOCOS –STEP 4Form pmos S/D Cover with photoresist

PSELECT mask

PSELECT mask

LOCOS –STEP 4Form pmos S/D Cover with photoresist Pattern photoresist

*PSELECT MASK

POLY mask

PSELECT mask

LOCOS –STEP 4Form pmos S/D Cover with photoresist Pattern photoresist

*PSELECT MASK Implant p-type dopants Remove photoresist

p+ dopant

POLY mask

p+ dopant

LOCOS –STEP 5Form nmos S/D Cover with photoresist

POLY mask

NSELECT mask

p+p+ p+n

LOCOS –STEP 5Form nmos S/D Cover with photoresist Pattern photoresist

*NSELECT MASK

POLY mask

NSELECT mask

p+p+ p+n

LOCOS –STEP 5Form nmos S/D Cover with photoresist Pattern photoresist

*NSELECT MASK Implant n-type dopants Remove photoresist

n+ dopant

POLY mask

n+ dopant

p+p+ p+n

n+ n+ n+

LOCOS –STEP 6Form Contacts Deposit oxide Deposit photoresist

CONTACT mask

p+p+ p+n

n+ n+ n+

CONTACT mask

LOCOS –STEP 6Form Contacts Deposit oxide Deposit photoresist Pattern photoresist

*CONTACT Mask One mask for both

active and poly contact shown

CONTACT mask

p+p+ p+n

n+ n+ n+

CONTACT mask




Etch oxide

p+p+ p+n

n+ n+ n+




Etch oxide Remove photoresist Deposit metal

immediately after opening contacts so no native oxide grows in contacts

Planerize make top level

p+p+ p+n

n+ n+ n+

LOCOS –STEP 7Form Metal 1 Traces Deposit photoresist

p+p+ p+n

n+ n+ n+

METAL1 mask

METAL1 mask

LOCOS –STEP 7Form Metal 1 Traces Deposit photoresist Pattern photoresist

*METAL1 Mask p+p+ p+n

n+ n+ n+

METAL1 mask

METAL1 mask


*METAL1 Mask Etch metal

p+p+ p+n

n+ n+ n+

metal over poly outside of cross section


*METAL1 Mask Etch metal Remove photoresist

p+p+ p+n

n+ n+ n+

LOCOS –STEP 8Form Vias to Metal 1 Deposit oxide Planerize oxide Deposit photoresist

p+p+ p+n

n+ n+ n+

VIA mask

VIA mask

LOCOS –STEP 8Form Vias to Metal1 Deposit oxide Planerize Deposit photoresist Pattern photoresist

*VIA Mask

p+p+ p+n

n+ n+ n+

VIA mask

VIA mask


*VIA Mask Etch oxide Remove photoresist

p+p+ p+n

n+ n+ n+


*VIA Mask Etch oxide Remove photoresist Deposit Metal2

p+p+ p+n

n+ n+ n+

LOCOS –STEP 9

Form Metal2 Traces Deposit photoresist

p+p+ p+n

n+ n+ n+

METAL2 mask

METAL2 mask

LOCOS –STEP 9Form Metal2 Traces Deposit photoresist Pattern photoresist

*METAL2 Maskp+p+ p+

n

n+ n+ n+

METAL2 mask

METAL2 mask


*METAL2 Mask Etch metal

p+p+ p+n

n+ n+ n+


*METAL2 Mask Etch metal Remove photoresist

p+p+ p+n

n+ n+ n+

LOCOS –STEP 10+Form Additional Traces Deposit oxide Deposit photoresist Pattern photoresist Etch oxide Deposit metal Deposit photresist Pattern photoresist Etch metal Repeat for each

additional metal

p+p+ p+n

n+ n+ n+

p-type substrate

SIMPLIFICATIONS FROM COMPLETE PROCESS

Skipped several substrate doping steps: channel implant to adjust threshold voltages surface implant to increase breakdown voltage

no LDD, lightly-doped drain no deposition of contact interface materials metal patterning simplified

more complex “lift-off” process often used no overglass (thick top dielectric) layer no bonding pad layer simplified use of dark/clear field masks and positive/negative

photoresist

TRENCH ISOLATION Definition of Trench: A trench is a type of excavation or

depression in the ground that is generally deeper than it is wide (as opposed to a wider gully, or ditch), and narrow compared to its length (as opposed to a simple hole).

Trench isolation is a method used to prevent latch-up and isolate transistors from each other.

Many new isolation process approaches have been developed around the idea of etching away part of the substrate and refilling it with an insulator.

These can be divided into two classes: Shallow trench isolation Deep trench isolation

TYPES OF TRENCH ISOLATION Definition of Shallow trench isolation:

Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller.

Definition of Deep trench isolation: it is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components using trenches of fixed width.

SCHEMATIC DIAGRAM OF TYPES OF TRENCH

ISOLATION

ISOLATION OF TRANSISTORS Isolation of Transistors :The use of reverse bias pn junctions to

isolate transistors becomes impractical as the transistor sizes decrease.

USE OF SHALLOW TRENCH ISOLATION TECHNOLOGY

Use of Shallow Trench Isolation Technology: Shallow trench isolation (STI) allows closer spacing of transistors by eliminating the depletion region at the surface.

COMPARISON OF STI AND LOCOS

If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniques such as poly buffered LOCOS

At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads to undesirable stress effects in the transistor.

An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+ isolation compared to LOCOS. This is a significant advantage for any process where there are implants before STI.

https://www.youtube.com/watch?v=MGNMAKiXV4Y



LOCOS AND STI

THE SHALLOW TRENCH ISOLATION (STI)

It is the preferred isolation technique for the sub-0.5m technology, because it completely avoids the bird's beak shape characteristic.

With its zero oxide field encroachment STI is more suitable for the increased density requirements, because it allows to form smaller isolation regions.

https://www.youtube.com/watch?v=CllgoLmICWo



SHALLOW TRENCH ISOLATION

CONTD.. The STI process starts in the same way as the LOCOS process. The

first difference compared to LOCOS is that a shallow trench is etched into the silicon substrate, as shown in Fig. 1.2a.

After underetching of the oxide pad, also a thermal oxide in the trench is grown, the so-called liner oxide (see Fig. 1.2c).

But unlike with LOCOS, the thermal oxidation process is stopped after the formation of a thin oxide layer, and the rest of the trench is filled with a deposited oxide (see Fig. 1.2d).

Next, the excessive (deposited) oxide is removed with chemical mechanical planarization. At last the nitride mask is also removed. The price for saving space with STI is the larger number of different process steps.

http://www.iue.tuwien.ac.at/phd/hollauer/node7.html#sti1



SHALLOW TRENCH ISOLATION (STI)

1. Cover the wafer with pad oxide and silicon nitride.

2. First etch nitride and pad oxide. Next, an anisotropic etch is made in the silicon to a depth of 0.4 to 0.5 microns.

3. Grow a thin thermal oxide layer on the trench walls.

4. A CVD dielectric film is used to fill the trench. 5. A chemical mechanical polishing (CMP) step is

used to polish back the dielectric layer until the nitride is reached. The nitride acts like a CMP stop layer.

6. Densify the dielectric material at 900°C and strip the nitride and pad oxide.

CMP FOR STI STI is the mainstream CMOS isolation technology In STI, substrate trenches filled with oxide surround devices or group of

devices that need to be isolated Relevant process steps:

Diffusion (OD) regions covered with nitride (acts as CMP-stop) Trenches created where nitride absent and filled with oxide CMP to remove excess oxide over nitride (overburden oxide)

Si

Oxide Nitride

Before CMP After Perfect CMP CMP goal: Complete removal of oxide over nitride, perfectly planar

nitride and trench oxide surface

IMPERFECT CMP

Planarization window: Time window to stop CMP Stopping sooner leaves oxide over nitride Stopping later polishes silicon under nitride Larger planarization window desirable

Step height: Oxide thickness variation after CMP Quantifies oxide dishing Smaller step height desirable

CMP quality depends on nitride and oxide density Control nitride and oxide density to enlarge planarization window and to

decrease step height

Failure to clear oxide Nitride erosion Oxide dishing

Key Failures Caused by Imperfect CMP

CONCLUSIONS Imperfect STI CMP causes functional and parametric yield loss Our fill insertion approach focuses on: (1) oxide density variation minimization, (2) nitride density maximization Large nitride fill features contribute to nitride and oxide densities, small ones to

nitride only shape fill to control both densities Proposed max. nitride fill insertion with holes to control oxide density and

achieve high nitride density Results indicate significant decrease in oxide density variation and increase in

nitride density over tile-based fill CMP simulation shows superior CMP characteristics, planarization window

increases by 17%, and step height decreases by 9%

DEEP TRENCH ISOLATION A high quality thermal oxide liner is grown

along the side-walls of the deep trench and the remaining oxide is deposited at low temperature.

A polysilicon stress-relief layer is deposited so that it fills the deep trench and is recessed below the silicon surface.

The deep trench process integration is designed to minimize the impact on the shallow trench isolation module which is used for logic isolation.

Hence, maximum re-use of shallow trench process steps becomes critical.

CONTD.. The deep trench oxide thickness is sufficient to sustain a breakdown

voltage from nwell to substrate of 74V. This breakdown voltage has been found to be stable even with

repeated stress, which is made possible by interface between the deep trench silicon sidewall and the high quality thermal oxide liner.

The deep trench in this technology is used to significantly increase the analog packing density by bringing devices adjacent to each other across the deep trench, thereby enabling shrinks ranging from 50% for medium-voltage analog to >80% for high-voltage analog components compared to the 0.35µm SMOS7 technology.

In SMOS7, high-energy implant chains replaced the deep diffused implants, which were present in older diffusion based technologies

FABRICATION PROCESS1. Take a standard LOCOS structure.2. After nitride patterning trenches are etched.3. It must have smooth walls at no more than 85º with respect the

plane of a wafer.4. Trench etch is made by depositing while etching silicon

anisotropically. This will create a small cusp of at the top of the trench.

5. The thickness of this cusp increase with time, producing the desired taper.

6. A thin local oxidation is done by using thinner oxides to increase capacitance.

7. Finally a layer of polysilicon is deposited etched back.

2SiO2SiO

CONTD.. we have developed and qualified a 0.25µm CMOS based high-side

capable 70V smart power process on a P++ substrate with a deep trench high-voltage isolation and logic shallow trench isolation.

By using a deep trench combined with a P++ substrate, we have realized significant analog shrink, reduction of substrate parasitics and 74V high side capability without affecting analog matching and process complexity

SILICON ON INSULATOR ISOLATION TECHNIQUES(SOI)

Definition: Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance.

SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS).

CONTD.. To completely encase each device in an insulating material The choice of insulator depends largely on intended application,

with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short channel effects in microelectronics devices.

INDUSTRY NEED OF SOI Lower parasitic capacitance due to isolation from the bulk silicon,

which improves power consumption at matched performance. Resistance to latch up due to complete isolation of the n- and p-well

structures. Higher performance at equivalent VDD. Can work at low VDD's. Reduced temperature dependency due to no doping. Better yield due to high density, better wafer utilization. Reduced antenna issues No body or well taps are needed. Lower leakage currents due to isolation thus higher power

efficiency. Inherently radiation hardened ( resistant to soft errors ), thus

reducing the need for redundancy

SOI TECHNIQUE1. In this process, a thin layer of single-crystal silicon can be

produced on top of a thermal SiO2 layer on a silicon wafer. 2. Strips of oxide are produced by patterning the oxide layer using

photolithography. 3. a thin layer of silicon is then deposited on the wafer.4. It will be polycrystalline in the regions where the deposited silicon

layer overlays the oxide and it will be single crystal in the regions where there is direct contact with silicon substrate.

5. In the next step we will directionally recrystalise the silicon layer, which in turn recrystallises the substrate to act as the nucleation centre.

6. As the heated zone is scanned across the wafer the crystal growth, propagates from these nucleation regions to the regions of the silicon film on top of the oxide islands or strips.

7. Thus we form a complete single crystal layer of silicon.

METHODS OF SOI ISOLATION1. Dielectric isolation2. Wafer bonding

DIELECTRIC ISOLATION

Definition: Dielectric isolation, is the process of electrically isolating various components in the IC chip from the substrate and from each other by an insulating layer.

It's main use is to eliminate undesirable parasitic junction capacitance or leakage currents associated with certain applications.

It is used to build high voltage telecommunication ICs that required electrically isolated bidirectional switches.

V-GROOVE ISOLATION

1. V-groove isolation is formed with an n-type substrate, on which an n+ diffusion is performed.

2. An SiO2 layer is formed, which is then patterned to form a grid of intersecting lines opening in the oxide

3. The wafer formed is then exposed to an orientation dependent etching (ODE) process, where the patterned layer is used as the etching mask; which results in the formation of V-shaped grooves as shown in the picture (b).

4. In this the <111> plane sidewalls are at an angle of 54.74 degree with respect to the <100> top surface of the silicon wafer.

Dielectric isolation of IC

CONTD..5. As a result the starting material is <111> oriented crystal, which is

normally used for p-n junction isolation. But for dielectric isolation the starting material is <100> oriental silicon.

6. The etchant used in the above step etches away the exposed silicon anisotropically, this means that the etch rate is much faster along the <111> planes than along the <100> crystal planes.

7. This kind of preferential etching is the key reason behind the formation of V-groove.

CONTD..8. The depth D of the isolation groove can be determined in the

initial oxide cut width W as

9. Cover the sidewalls of the V-groove with an oxide layer, therefore the wafer is subjected to a thermal oxidation process.

10. After completing the oxide layer, a very thick layer of polycrystalline silicon is deposited as shown in picture (c).

2WD

CONTD..11. The most critical step in the V-groove isolation process is

explained in figure (d). 12. Keeping polycrystalline surface side of the wafer down, silicon

wafers are mounted on the lapping plate.13. In the next step, n-type silicon substrate is then carefully lapped

down to the level at which the vertices of the V-grooves become exposed.

14. So now we get an array of n-type single crystal silicon regions that are isolated from the polycrystalline silicon substrate.

15. Polycrystalline silicon now serves to provide the mechanical support for the IC.

16. This material is ideal for the function because of its good thermal expansion coefficient, it can withstand high processing temperatures, and is a good match to single crystal silicon.

CONTD..17. The n-type silicon has now moved down to vertices of the V-

grooves because of the lapping operation. 18. If the lapping is recessive, then proper isolation will not be

achieved.19. But if excessive lapping is done, it may lead to thinner n-type

regions.20. Wafer diameter is approx 100mm and the V-groove depth is about

10 micro meters, thus precise lapping is necessary.21. The n+ diffused layer serves as a buried layer to reduce the

collector series resistance of the n-p-n transistors.22. The rest of the processing sequence for the dialectically isolated

ICs follows along the same line as for the conventional junction isolated IC.

ADVANTAGES OF DIELECTRIC ISOLATION

Permittivity of SiO2 is one reason, which is 1/3rd of Silicon and hence capacitance is reduced.

Oxide is thicker than the depletion region of the substrate junction and capacitance is inversely proportional to the thickness of oxide.

No need of applying negative potential to the substrate.

DRAWBACKS OF DIELECTRIC ISOLATION

The wafer are not as planar as normal starting material. Wafers made by this process are expensive.

WAFER BONDING In this process two wafers

are pressed together at high temperature until they fuse.

The wafers are fused at low temperature by anodic bonding.

If the wafers are oxidized before bonding, a layer of oxide remains at the centre of the fused wafer.

CONTD.. The wafer can be ground back to thickness of 2 to 3µmusing

standard grinding and polishing techniques. If thinner layers are required, additional processing can be done to

produce submicrometer semiconductor films on top of the oxide. Device can be isolated with a simple etch process that produces

single crystal islands on top of the insulating oxide.

METALLIZATION Definition: Metallization is the process that makes accessible the IC

to the outside world through conducting pads. Doped silicon conduct electricity but have large resistance and lack

interconnecting facility. Thin conductive metal films (Al, Cu, Au, Ag etc) are used as

interconnects between Si and external leads.

WHY INTERCONNECT STRUCTURES ARE IMPORTANT? Rough Estimation of Interconnect RC Time Delay As technology progresses, Ls decreases RC delay increases. To decrease RC delay - ρ, ε, L should take low values

NEEDS OF NEW TECHNOLOGY Lower resistivity metal for interconnect wiring. Lower dielectric constant material for the interlayer

dielectric. Smaller wire lengths-Multilevel Metallization

MULTI LEVEL METALLIZATION Metal interconnections. Span several planes. Isolated by the insulating dielectric layers Interconnected by the wiring in the third dimension through the

holes in the dielectric planes. Three dimensional network of interconnections is given the name

multilevel interconnections.

USES -MULTI LEVEL METALLIZATION

Reduced interconnection lengths-enhanced performance due to reduced RC.

Densification-higher package densities. Design flexibility

https://www.youtube.com/watch?v=h2xrTtuzIg0



MULTI LEVEL METALLIZATION

INTERCONNECTION MATERIALS

Metals Metal Issues Junction spiking Electromigration Stress migration Important metals Aluminum Copper Tungsten Silver, Gold Dielectrics Diffusion barriers and Adhesion promoters

METALS REQUIREMENTS Low resistivity Easy to deposit Easy to etch and planarize High melting point High electromigration resistance Mechanical stability, adherence to interlayer

dielectrics and other materials on chip Substrate matched coefficient of thermal expansion Low stress, high stress migration resistance

https://www.youtube.com/watch?v=8wYI7EFAeMw



METALLIZATION OF PCB

CONTD.. Controlled microstructure Preferably uniform large grains and smooth surfaces Oxidation/corrosion resistance Low chemical reactivity Ideally passivates itself Compatible with surrounding materials and their processing Bondable to wirings in package Environmentally safe material during processing and actual use, and

recyclable Reliable Low cost

Property/ metal Cu Ag Au Al w

Resistivity 1.67 1.59 2.35 2.66 5.65Youngs modulus 12.98 8.27 7.85 7.06 41.1

Thermal conductivity 3.98 4.25 3.15 2.358 1.74

Coeff. Of thermal expansion CTE

17 19.1 14.2 23.5 4.5

M.P(ºC) 1085 962 1064 660 3387Specific heat capacity

38 234 132 917 138

Corrosion in air Poor Poor Excellent Good Good

Adhesion to Sio2 Poor Poor Poor Good Good

Delay 2.3 2.2 3.2 3.7 7.8Thermal stress per degree for films on Si

2.5 1.9 1.2 2.1 0.8

ALUMINUM Early ICs used pure Al as the interconnect material Low resistivity Strong adhesion with Si Corrosion resistantProblems with pure Al Junction spiking Electromigration Stress migration Later ICs used Al alloyed with Cu

JUNCTION SPIKING

Definition of junction spiking: the penetration of a junction by aluminum, which occurs when silicon near the junction dissolves in aluminum and migrates along the interconnect lines. Aluminum then replaces silicon at the junction.

Consider Al-Si contact Solubility of Si in Al is 0. 5 wt% at 4500C •Si will dissolve into the Al during annealing (at 4500C) Solution Add Si to the Al Introduce a barrier metal layer between the Al and the Si substrate. (TiN)

STRESS MIGRATION Definition: Stress migration is a failure mechanism

that often occurs in integrated circuit metallization (aluminum, copper). Voids form as result of vacancy migration driven by the hydrostatic stress gradient. Large voids may lead to open circuit or unacceptable resistance increase that impedes the IC performance.

Due to difference between coefficient of thermal expansion for Al and Si.

Al – 23 x 10-6 0C-1 and Si – 2.6 x 10-6 0C-1 High compressive stresses in Al at high temperatures

CONTD.. Movement of Al occurs along grain boundaries Whole grains of Al pushed upward forming hillocks Under tensile stress voids are formed Consequences • Electrical shorts between interconnect levels • Rough surface topography making lithography and etch difficult Solution Addition of elements that have limited solubility Ex:- Cu atoms segregate and precipitate preferentially along the

grain boundaries suppressing hillock formation

ELECTROMIGRATION

Definition: Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms.

ELECTROMIGRATION Transport of mass in metals under the influence of high current Occurs by transfer of momentum from electrons to the positive metal ions High current densities in the smaller devices are responsible for electron migration Grain boundary diffusion is the primary vehicle of mass transport Metal in some regions pile up and voids form in other regions

SOLUTIONS - ELECTROMIGRATION

Alloying with copper (Al with 0.5%Cu) • Multilayer structure – Shunt layer provides alternative path for current flow – If shunt layer has high melting point and strong mechanical

properties, they can be more rigid and act as barrier to hillock and void

formation

PROPERTIES OF METALSTungsten Gold copper

Good corrosion resistance

Low resistivity Higher conductivity

Electromigration and stress migration stability

Very inert More electromigration resistance

Excellent deposition methods

Adheres poorly Higher ultimate tensile strength

Sometimes used for filling of vias called plugs

Very costly Higher melting poit, low CTE

High resistivity High thermal conductivity

Poor adhesion High specific heat

PLANARIZATION DEFINITION: Chemical mechanical polishing/planarization is a

process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing.

PROCESS OF PLANARIZATION The process uses an abrasive and corrosive chemical slurry in

conjunction with a polishing pad and retaining ring, typically of a greater diameter than the wafer.

The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring.

The dynamic polishing head is rotated with different axes of rotation .

This removes material and tends to even out any irregular topography, making the wafer flat or planar.

https://www.youtube.com/watch?v=2z4lq-Ms_OU



CHEMICAL MECHANICAL PLANARIZATION

CONTD.. This may be necessary to set up the wafer

for the formation of additional circuit elements.

For example, CMP can bring the entire surface within the depth of field of a photolithography system, or selectively remove material based on its position.

Typical depth-of-field requirements are down to Angstrom levels for the latest 22 nm technology.

WORKING PRINCIPLE Physical action Typical CMP tools, such as the ones seen on the right, consist of a

rotating and extremely flat platen which is covered by a pad. The wafer that is being polished is mounted upside-down in a

carrier/spindle on a backing film. The retaining ring (Figure 1) keeps the wafer in the correct

horizontal position. During the process of loading and unloading the wafer onto the

tool, the wafer is held by vacuum by the carrier to prevent unwanted particles from building up on the wafer surface.

CONTD.. A slurry introduction mechanism deposits the slurry on the pad,

represented by the slurry supply in Figure 1. Both the platen and the carrier are then rotated and the carrier is

kept oscillating; this can be better seen in the top view of Figure 2. A downward pressure/down force is applied to the carrier, pushing

it against the pad; typically the down force is an average force, but local pressure is needed for the removal mechanisms.

Down force depends on the contact area which, in turn, is dependent on the structures of both the wafer and the pad.

CONTD.. Typically the pads have a roughness of 50 µm; contact is made by

asperities (which typically are the high points on the wafer) and, as a result, the contact area is only a fraction of the wafer area.

In CMP, the mechanical properties of the wafer itself must be considered too.

If the wafer has a slightly bowed structure, the pressure will be greater on the edges than it would on the center, which causes non-uniform polishing.

In order to compensate for the wafer bow, pressure can be applied to the wafer's backside which, in turn, will equalize the centre-edge differences.

CONTD.. The pads used in the CMP tool should be rigid in order to uniformly

polish the wafer surface. However, these rigid pads must be kept in alignment with the wafer

at all times. Therefore, real pads are often just stacks of soft and hard materials

that conform to wafer topography to some extent. Generally, these pads are made from porous polymeric materials

with a pore size between 30-50 µm, and because they are consumed in the process, they must be regularly reconditioned.

In most cases the pads are very much proprietary, and are usually referred to by their trademark names rather than their chemical or other properties.

CHEMICAL ACTION Before about 1990 CMP was

viewed as too "dirty" to be included in high-precision fabrication processes, since abrasion tends to create particles and the abrasives themselves are not without impurities.

Since that time, the integrated circuit industry has moved from aluminium to copper conductors.

CONTD.. This required the development of an additive patterning process,

which relies on the unique abilities of CMP to remove material in a planar and uniform fashion and to stop repeatably at the interface between copper and oxide insulating layers.

Adoption of this process has made CMP processing much more widespread.

In addition to aluminum and copper, CMP processes have been developed for polishing tungsten, silicon dioxide, and (recently) carbon nanotubes.

LIMITATIONS OF CMP

There are currently several limitations of CMP that appear during the polishing process requiring optimization of a new technology.

In particular, an improvement in wafer metrology is required. In addition, it was discovered that the CMP process has several

potential defects including stress cracking, delaminating at weak interfaces, and corrosive attacks from slurry chemicals.

The oxide polishing process, which is the oldest and most used in today's industry, has one problem: a lack of end points requires blind polishing, making it hard to determine when the desired amount of material has been removed or the desired degree of planarization has been obtained.

CONTD.. If the oxide layer has not been sufficiently thinned and/or the

desired degree of planarity has not been achieved during this process, then (theoretically) the wafer can be repolished, but in a practical sense this is unattractive in production and is to be avoided if at all possible.

If the oxide thickness is too thin or too non-uniform, then the wafer must be reworked, an even less attractive process and one that is likely to fail. Obviously, this method is time-consuming and costly since technicians have to be more attentive while performing this process.

NMOS IC TECHNOLOGY Definition: N-type metal-oxide-semiconductor logic uses n-

type field effect transistors to implement logic gates and other digital circuits.

These nMOS transistors operate by creating an inversion layer in a p-type transistor body.

This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals.

The n-channel is created by applying voltage to the third terminal, called the gate.

Like other MOSFETs, nMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation.

P-N JUNCTIONS A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction.

p-type n-type

anode cathode

NMOS TRANSISTOR Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor

Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal – oxide – semiconductor (MOS) capacitor Even though gate is

no longer made of metal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

NMOS OPERATION Body is commonly tied to ground (0 V) When the gate is at a low voltage:

P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S

https://www.youtube.com/watch?v=0FwfSMxBU3s

https://www.youtube.com/watch?v=0FwfSMxBU3s

NMOS FABRICATION

CONTD.. When the gate is at a high voltage:

Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source

through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

NMOS IC TECHNOLOGY The basic n channel circuit consists of NMOS transistors. MOS transistors consists of a source, a drain a and a gate region. Each transistor is isolated form its neighbor transistors and other

devices by a thick field oxide. Usually phosphorus doped SiO2 , called P – glass is used as

insulating layer. Under this SiO2 layer, a thin layer of dopant is used, called Chan-

stop region. The Chan-stop region serves to improve isolation between

transistors.

CONTD.. When +ve charge is applied at the gate, then –ve charge starts to

move from the source to drain. Following points will be discussed. Fabrication process sequence for NMOS Special Considerations for NMOS ICs

FABRICATION PROCESS SEQUENCE FOR NMOS

1. The starting Si wafer is a lightly doped p – type substrate.

2. First step is to oxidize the Si to form a layer of SiO2 .

CONTD..3. Coat the Si with photoresist.

CONTD.. Since we have to transfer patterns in order to form source and

drain region, so the next step is lithography.

CONTD.. Now, the SiO2 regions which are not covered by hardened

photoresist can be etched away either by chemical etching or dry etching.

CONTD.. The remaining photoresist can be removes by using another solvent.

CONTD.. Now deposit a layer of thin oxide in order to form gate oxide of the

NMOS transistor.

CONTD.. Now on the top of the thin oxide layer, a layer of polysilicon is

deposited. It is used as gate electrode material for MOS to interconnect it.

CONTD.. After deposition of the polysilicon layer, it is patterned and etched to

form the interconnects and the MOS transistor gate.

CONTD.. The thin oxide not covered by polysilicon is also etched away so

that source and drain junctions may be formed.

CONTD.. The entire silicon surface is then doped with a high concentration of

impurities either by diffusion or ion implantation.

CONTD.. Once the source and drain regions are completed, the entire surface

is again covered with and insulating layer of SiO2 .

CONTD.. The insulating oxide is then patterned in order to

provide contact window for drain and source junctions.

CONTD.. The surface is now covered with evaporated aluminium which will

form the interconnections.

CONTD.. Finally the metal layer is patterned and etched, completing the

interconnections of the MOS transistor on the surface.

CONTD.. MOS transistors must be electrically isolated from each other during

fabrication. Isolation is required to prevent unwanted conduction path between

devices.

ADVANTAGES OF NMOS TECHNOLOGY

Since electron mobility is twice (say) that of hole mobility, an n-channel device will have one-half the on-resistance or impedance of an equivalent p-channel device with the same geometry and under the same operating conditions.

Thus n-channel transistors need only halt the size of p-channel devices to achieve the same impedance. Therefore, n-channel ICs can be smaller for the same complexity or, even more important, they can be more complex with no increase in silicon area.

NMOS circuits offer a speed advantage over PMOS due to smaller junction areas. Since the operating speed of an MOS IC is largely limited by internal RC time constants and capacitance of diode is directly proportional to its size, an n-channel junction can have smaller capacitance. This, in turn, improves its speed.

DISADVANTAGES The n-channel device has following problems in the device

processing. Most of the mobile contaminants are positively charged. Since

NMOS operates with the gate positively based with respect to the substrate, these ions collect along the oxide-silicon interface. This charge causes a shift in VTh.

Also, there is fixed positive charge at the Si-SiO2 interface resulting from various steps of the manufacturing process.

This also shifts the threshold voltage. Both these charges have tendency to make the device normally on.

These two charges exist in PMOS device too, but the positive ions are pulled to the AI-S1O2 interlace by the negative bias applied to gate. There, they cannot affect the device threshold severely.

CONTD.. Another problem with NMOS device occurs during the oxidation of

silicon which takes place at the Si-SiO2 interface. No real abrupt change occurs between silicon and Si02; rather there

is a transition zone. This transition zone contains positively charged Silicon atoms

which increase the absolute magnitude of the threshold voltage for a p-channel device and decrease the absolute magnitude of the threshold voltage for an n-channel device.

This means it is difficult to make an n-channel device that is off at zero gate voltage. This is why it is more difficult to make an n-channel device than a p-channel device.

WHAT IS THE ADVANTAGE OF CMOS OVER NMOS ?

CMOS is preffered over NMOS: As CMOS propogates both logic '1', and '0', without a voltage drop when using NMOS only, logic '1' (i.e Vdd) suffers a thresold drop

and the output after passing through one NMOS gate would be Vdd-Vt(thresold voltage of the NMOS gate).

Hence signal margin is very important in NMOS causing possible SI(signal integrity) issues.

Hence CMOS is preferred. By the way CMOS and NMOS and also PMOS are all low powered. Static power consumption is the same, dynamic power consumption depends on signal swing (i.e number of times data line varies)

CMOS IC TECHNOLOGY A CMOS inverter is realized by the series combination of a

PMOS and NMOS transistors. Transfer characteristic of the CMOS inverter is output

voltage as a function of input voltage. The circuit diagram of a CMOS inverter is shown on next

slide. The cross section of the inverter structure shows the n-

channel transistor formed in a p-region called tub or well. The gates of the transistors are connected to from the input. In order to understand the operation of the CMOS inverter,

define the threshold voltages of NMOS and PMOS transistors. Let VTn = 1 V & VTp = -1 V and VDD = 5V.

https://www.youtube.com/watch?v=OBiu2agne_U

https://www.youtube.com/watch?v=OBiu2agne_U

CMOS FABRICATION

CONTD.. The operation of the CMOS inverter can be divided into 5 regions.

NMOS (OFF) will be in cutoff region. PMOS (ON) will be in linear region. So, V0 = VDD.

NMOS (ON) Saturation region. PMOS (ON) Linear region

100 :A Regions intnin VVV

5.212

V:BRegion tn inDD

in VVV

CONTD..

NMOS (ON) Saturation region. PMOS (ON) Saturation region.

PMOS (ON) saturation region. NMOS (ON) Linear region.

5.22

V:CRegion in inDD VV

5.35.222

V:DRegion DD intpDD

in VVVV

CONTD..

PMOS (OFF) cutoff region. NMOS (ON) linear region.

55.32

V:ERegion DD inDDintp VVVV

ADVANTAGES OF CMOS TECHNOLOGY

1. High input impedance. The input signal is driving electrodes with a layer of insulation (the metal oxide) between them and what they are controlling. This gives them a small amount of capacitance, but virtually infinite resistance. The current into or out of CMOS input held at one level is just leakage, usually 1 nanoAmpere or less

2. The outputs actively drive both ways3. The outputs are pretty much rail-to-rail4. CMOS logic takes very little power when held in a fixed state. The

current consumption comes from switching as those capacitors are charged and discharged. Even then, it has good speed to power ratio compared to other logic types.

5. CMOS gates are very simple. The basic gate is an inverter, which is only two transistors. This together with the low power consumption means it lends itself well to dense integration. Or conversely, you get a lot of logic for the size, cost and power.

DISADVANTAGES1. No bipolar2. Some circuits are not practicable3. Difficult to implement

BIPOLAR IC FABRICATION It is high speed technology. Speed of operation of Bipolar IC is determined by base width of the

devices. Base width is determined by difference between two impurity

diffusion profiles. Devices with very thin base width has high speed of operation. Bipolar ICs requires buried layer of dopant by growing an epitaxial

layer on silicon.

https://www.youtube.com/watch?v=2fOtOp4KXbM

https://www.youtube.com/watch?v=2fOtOp4KXbM

BIPOLAR IC FABRICATION

BIPOLAR INTEGRATED CIRCUITS. FABRICATION

If EDP is used, a bipolar npn transistor can be formed by a sequence of such steps:

Step 1. n-type epilayer growth. Step 2. Oxidation. Step 3. Photolithography forming windows for isolation diffusion.

Step 4. Isolation (separation) diffusion.

CONTD.. Step 5: Oxidation. Step 6: Photolithography forming windows for base diffusion. Step 7: Base diffusion

CONTD.. Step 8. Oxidation. Step 9. Photolithography – window formation for

emitter diffusion. Step 10. Emitter diffusion.

CONTD.. Step 11. Oxidation. Step 12. Photolithography forming windows for contact areas. Step 13. Metallization (deposition of a thin aluminium layer by

vacuum evaporation). Step 14. Photolithography (selective etching of the metal layer).

Interconnections are formed at this step.

CONTD.. Step 15. Anneal in hydrogen to form ohmic contacts where the

aluminium meets n silicon region. Step 16. Passivation, i.e. deposition of silicon dioxide or silicon

nitride by lowtemperature CVD (chemical vapour deposition). Step 17. Photolithography exposing bonding pads.

ADVANTAGES/DISADVANTAGES OF BIPOLAR IC TECHNOLOGY

Bipolar devices can switch signals at high speeds

Can be manufactured to handle large currents so that they can serve as high-power amplifiers in audio equipment and in wireless transmitters.

Bipolar devices are not especially effective for weak-signal amplification, or for applications requiring high circuit impedance

FAULT DIAGNOSIS Definition: A unit under test (UUT) fails when its observed

behavior is different from its expected behavior. Diagnosis consists of locating the physical fault(s) in a structural model of the UUT. The degree of accuracy to which faults can be located is called diagnostic resolution.

Definition: Functionally equivalent faults (FEF) cannot be distinguished. The partition of all faults into distinct subsets of FEF defines the maximal fault resolution. A test that achieves the maximal fault resolution is said to be a complete fault-location test.

BASIC CONCEPTS Repairing the UUT often consists of substituting one of

its replaceable units (RU) referred as a faulty RU, rather than in an accurate identification of the real fault inside an RU.

We characterize this process by RU resolution. Suppose that the results of the test do not allow to distinguish between two suspected RUs U1 and U2.

We could replace now one of these RUs, say U1 with a good RU, and return to the test experiment.

If the new results are correct, the faulty RU was the replaced one; otherwise, it is the remaining one U2.

This type of procedure we call sequential diagnosis procedure.

TYPE OF DIAGNOSIS PROCESS The diagnosis process is often hierarchical:1. Top-down approach (system boards ICs) first-level diagnosis

may deal with "large" RUs like boards called also field-replaceable units. The faulty board is then tested in a maintenance center to locate the faulty component (IC) on the board. Accurate location of faults inside a faulty IC may be also useful for improving its manufacturing process.

2. Bottom-up approach (ICs boards system) a higher level is assembled only from components already tested at a lower level. This is done to minimize the cost of diagnosis and repair, which increases significally with the level at which the faults are detected.

COMBINATIONAL FAULT DIAGNOSIS METHODS

This approach does most of the work before the testing experiment. It uses fault simulation to determine the possible responses to a given test in the presence of faults.

The database constructed in this step is called a fault table or a fault dictionary.

To locate faults, one tries to match the actual results of test experiments with one of the precomputed expected results stored in the database. The result of the test experiment represents a combination of effects of the fault to each test pattern.

That's why we call this approach combinational fault diagnosis method. If this look-up process is successful, the fault table indicates the corresponding fault(s).

FAULT TABLE Definition: A fault table is a matrix where

columns Fj represent faults, rows Ti represent test patterns, and aij = 1 if the test pattern Ti detects the fault Fj, otherwise if the test pattern Ti does not detect the fault Fj, aij = 0.

Denote the actual result of a given test pattern by 1 if it differs from the precomputed expected one, otherwise denote it by 0.

The result of a test experiment is represented by a vector where ei = 1 if the actual result of the test patterns does not match with the expected result, otherwise ei = 0.

Each column vector fj corresponding to a fault Fj represents a possible result of the test experiment in the case of the fault Fj.

CONTD.. Three cases are now possible depending on the quality of the test

patterns used for carrying out the test experiment:

1. The test result E matches with a single column vector fj in FT. This result corresponds to the case where a single fault Fj has been located. In other words, the maximum diagnostic resolution has been obtained.

2. The test result E matches with a subset of column vectors {fi, fj … fk} in FT. This result corresponds to the case where a subset of indistinguishable faults {Fi, Fj … Fk} has been located.

3. No match for E with column vectors in FT is obtained. This result corresponds to the case where the given set of vectors does not allow to carry out fault diagnosis. The set of faults described in the fault table must be incomplete (in other words, the real existing fault is missing in the fault list considered in FT).

CONTD..

In the example the results of three test experiments E1, E2, E3 are demonstrated. E1 corresponds to the first case where a single fault is located, E2 corresponds to the second case where a subset of two indistinguishable faults is located, and E3 corresponds to the third case where no fault can be located because of the mismatch of E3 with the column vectors in the fault table.

FAULT DICTIONARY Definition: Fault dictionaries (FD) contain the same data as the

fault tables with the difference that the data is reorganized. In FD a mapping between the potential results of test experiments and the faults is represented in a more compressed and ordered form.

For example, the column bit vectors can be represented by ordered decimal codes (see the example) or by some kind of compressed signature.

MINIMIZATION OF DIAGNOSTIC DATA

To reduce large computational effort involved in building a fault dictionary, in fault simulation the detected faults are dropped from the set of simulated faults.

Hence, all the faults detected for the first time by the same vector will produce the same column vector (signature) in the fault table, and will be included in the same equivalence class of faults.

In this case the testing experiment can stop after the first failing test, because the information provided by the following tests is not used. Such a testing experiment achieves a lower diagnostic resolution.

A tradeoff between computing time and diagnostic resolution can be achieved by dropping faults after k>1 detections.

CONTD.. Example: In the fault table produced by fault simulation with fault dropping,

only 19 faults need to be simulated compared to the case of 42 faults when simulation without fault dropping is carried out (the simulated faults in the fault table are shown in shadowed boxes). As the result of the fault dropping, however, the following faults remain not distinguishable: {F2, F3},{F1, F4},{F2, F6}.

FAULT LOCATION BY STRUCTURAL ANALYSIS

Assume a single fault in the circuit. Then there should exist a path from the site of the fault to each of the outputs where errors have been detected. Hence the fault site should belong to the intersection of cones of all failing outputs. A simple structural analysis can help to find faults that can explain all the observed errors.

SEQUENTIAL FAULT DIAGNOSIS METHODS

Definition: In sequential fault diagnosis the process of fault location is carried out step by step, where each step depends on the result of the diagnostic experiment at the previous step. Such a test experiment is called adaptive testing.

Definition: Sequential experiments can be carried out either by observing only output responses of the UUT or by pinpointing by a special probe also internal control points of the UUT (guided probing). Sequential diagnosis procedure can be graphically represented as diagnostic tree.

1. Fault location by edge-pin testing2. Generating tests to distinguish faults3. Guided-probe testing4. Fault location by UUT reduction

1. FAULT LOCATION BY EDGE-PIN TESTING

In fault diagnosis test patterns are applied to the UUT step by step. In each step, only output signals at edge-pins of the UUT are observed and their values are compared to the expected ones.

The next test pattern to be applied in adaptive testing depends on the result of the previous step. The diagnostic tree of this process consists of the fault nodes FN (rectangles) and test nodes TN (circles).

A FN is labeled by a set of not yet distinguished faults. The starting fault node is labeled by the set of all faults. To each FN k a TN is linked labeled by a test pattern Tk to be applied as the next.

CONTD.. Every test pattern distinguishes between the faults it detects and the

ones it does not. The task of the test pattern Tk is to divide the faults in FN k into two groups - detected and not detected by Tk faults.

Each test node has two outgoing edges corresponding to the results of the experiment of this test pattern.

The results are indicated as passed (P) or failed (F). The set of faults shown in a current fault node (rectangle) are equivalent (not distinguished) under the currently applied test set.

CONTD.. Example: We can see that most of the faults are uniquely identified, two faults

F1,F4 remain indistinguishable. Not all test patterns used in the fault table are needed. Different faults need for identifying test sequences with different lengths. The shortest test contains two patterns the longest four patterns.

CONTD.. Rather than applying the entire test sequence in a fixed order as in

combinational fault diagnosis, adaptive testing determines the next vector to be applied based on the results obtained by the preceding vectors.

In our example, if T1 fails, the possible faults are {F2,F3}. At this point applying T2 would be wasteful, because T2 does not distinguish among these faults. The use of adaptive testing may substantially decrease the average number of tests required to locate a fault.

GENERATING TESTS TO DISTINGUISH FAULTS

To improve the fault resolution of a given test set T, it is necessary to generate tests to distinguish among faults equivalent under T.

Consider the problem of generating a test to distinguish between faults F1 and F2. Such a test must detect one of these faults but not the other, or vice versa. The following cases are possible.

1. F1 and F2 do not influence the same set of outputs. Let OUT(Fk) be the set of outputs influenced by the fault Fk. A test should be generated for F1 using only the circuit feeding the outputs OUT(F1), or for F2 using only the circuit feeding the outputs OUT(F2).

2. F1 and F2 influence the same set of outputs. A test should be generated for F1 without activating F2, or vice versa, for F2 without activating F1.

CONTD.. Three possibilities can be mentioned to keep a fault F2: xk=e not

activated, where xk denotes a line in the circuit, and e{0,1}:

1. The value e should be assigned to the line xk.

2. If this is not possible then the activated path from F2 should be blocked, so that the fault F2 could not propagate and influence the activated path from F1.

3. If the 2nd case is also not possible then the values propagated from the sites F1 and F2 and reaching the same gate G should be opposite on the inputs of G.

CONTD.. Example:

1. There are two faults in the circuit: F1: x3,10, and F2: x41. The fault F1 may influence both outputs, the fault F2 may influence only the output x8. A test pattern 0010 activates F1 up to the both outputs, and F2 only to x8. If both outputs will be wrong, F1 is present, and if only the output x8 will be wrong, F2 is present.

2. There are two faults in the circuit: F1: x3,20, and F2: x5,21. Both of them influence the same output of the circuit. A test pattern 0100 activates the fault F2. The fault F1 is not activated, because the line x3,2 has the same value as it would have had if F1 were present.

CONTD..3. There are the same two faults in the circuit: F1: x3,20, and F2:

x5,21. Both of them influence the same output of the circuit. A test pattern 0110 activates the fault F2. The fault F1 is activated at its site but not propagated through the AND gate, because of the value x4 = 0 at its input.

4. There are two faults in the circuit: F1: x3,11, and F2: x3,21. A test pattern 1001 consists the value x11 which creates the condition where both of the faults may influence only the same output x8. On the other hand, the test pattern 1001 activates both of the faults to the same OR gate (i.e. none of them is blocked).

5. However, the faults produce different values at the inputs of the gate, hence they are distinguished. If the output value on x8 will be 0, F1 is present. Otherwise, if the output value on x8 will be 1, either F2 is present or none of the faults F1 and F2 are present.

GUIDED-PROBE TESTING Guided-probe testing extends edge-pin testing process by monitoring

internal signals in the UUT via a probe which is moved (usually by an operator) following the guidance provided by the test equipment.

The principle of guided-probe testing is to backtrace an error from the primary output where it has been observed during edge-pin testing to its physical location in the UUT.

Probing is carried out step-by-step. In each step an internal signal is probed and compared to the expected value. The next probing depends on the result of the previous step.

A diagnostic tree can be created for the given test pattern to control the process of probing. The tree consists of internal nodes (circles) to mark the internal lines to be probed, and of terminal nodes (rectangles) to show the possible result of diagnosis.

The results of probing are indicated as passed (P) or failed (F).

CONTD.. Typical faults located are opens and defective components. An open

between two points A and B in a connection line is identified by a mismatch between the error observed at B and the correct value measured at A.

A faulty device is identified by detecting an error at one of its outputs, while only correct values are measured at its inputs.

The most time-consuming part of guided-probe testing is moving the probe. To speed-up the fault location process, we need to reduce the number of probed lines. A lot of methods to minimize the number of probings are available.

CONTD.. Example:

Let have a test pattern 1010 applied to the inputs of the circuit. The diagnostic tree created for this particular test pattern is shown. On the output x8 , instead of the expected value 0, an erroneous signal 1 is detected. By back tracing (indicated by bold arrows in the diagnostic tree) the faulty component NOR- x5 is located.

CONTD..

Diagnostic tree allows to carry out optimization of the fault location procedure, for example to generate a procedure with minimum average number of probes.

FAULT LOCATION BY UUT REDUCTION

Initially the UUT is the entire circuit and the process starts when its test fails. While the failing UUT can be partitioned, half of the UUT is disabled and the remaining half is tested. If the test passes, the fault must be in the disabled part, which then becomes the UUT. If the test fails, the tested part becomes the UUT.

CHARACTERIZATION TECHNIQUE

CHARACTERIZATION PROCEDURE :An outline of factors that should be considered when establishing a characterization procedure is provided here for every supplier to establish a characterization procedure.

Device Characterization Plan: The characterization plan should include the following major activities for the device to be characterized:

1. Review the Characterization Checklist. 2. Determination of if a matrix lot is necessary for the device

characterization.3. Determination of the characterization method to be used. 4. Establishment of the parameters and conditions to be

characterized. 5. Define format of the characterization report.

CONTD.. Matrix Lot Characterization: When characterizing a matrix lot,

the number of split cells, samples per cell and the data analysis methods should also be defined in the plan.

Sample Sizes :When deciding on sample sizes for characterization, two important factors are to be considered: confidence interval and confidence level.

CONTD.. Characterization Report :The characterization report should include

the following: 1. A copy of the characterization plan.2. A detailed discussion of the characterization methods used 3. A listing of parameters and conditions used in characterization. 4. Characterization data analysis and conclusions.5. Document simulation results including brief explanations on

methods applied – for parameters that are not measurable and/or tested in production and covered by design simulation only.

6. Identify part weaknesses and reliability concerns and define corrective actions.

CONCLUSIONS FDI: a mature field

Huge literature SAFEPROCESS European projects like MONET

Further research focuses on: New class of systems (e.g. Hybrid systems) Applications Fault tolerance issues

REFERENCES www.web.stanford.edu/class/ee311/NOTES/Isolation.pdf https://en.wikipedia.org/wiki/LOCOS www.textofvideo.nptel.iitm.ac.in/117106093/lec33.pdf www.iue.tuwien.ac.at/phd/filipovic/node77.html www.iue.tuwien.ac.at/phd/hollauer/node7.html www.https://en.wikipedia.org/wiki/Shallow_trench_isolation https://en.wikipedia.org/wiki/Silicon_on_insulator www.sctest.cse.ucsc.edu/lavo/Fault_Diagnosis

_Overview.ppt https://www.edgefx.in/understanding-cmos-fabrication-

technology/ www.iaa.ncku.edu.tw/~aeromems/MEMSDesign/Ch2.pdf www.circuitstoday.com/bipolar-ic-manufacturing-processBook: The Science and Engineering of Microelectronic

Fabrication, Stephen A. Campbell, Oxford University Press, 2001

http://www.web.stanford.edu/class/ee311/NOTES/Isolation.pdf



https://en.wikipedia.org/wiki/LOCOS

http://www.textofvideo.nptel.iitm.ac.in/117106093/lec33.pdf

http://www.iue.tuwien.ac.at/phd/filipovic/node77.html

http://www.iue.tuwien.ac.at/phd/hollauer/node7.html

http://www.https/en.wikipedia.org/wiki/Shallow_trench_isolation




https://en.wikipedia.org/wiki/Silicon_on_insulator

http://www.sctest.cse.ucsc.edu/lavo/Fault_Diagnosis_Overview.ppt





https://www.edgefx.in/understanding-cmos-fabrication-technology/





http://www.iaa.ncku.edu.tw/~aeromems/MEMSDesign/Ch2.pdf

http://www.circuitstoday.com/bipolar-ic-manufacturing-process





THANK YOU