ECE 523 Project – Fully Differential two Stage Amplifier

by

Karthikvel Rathinavel Chien-Chun, Yao

In partial fulfillment of the requirements for the course of CMOS Integrated Circuits II

Department of Electrical Engineering and Computer Science Oregon State University

Corvallis March, 2016

Introduction: This report describes a fully differential two stage amplifier design and its layout in cadence. Typically a two stage amplifier has advantages of higher gain but it comes at the expense of poor phase margin (without compensation). For our project we had to meet the specifications shown in table 1, for the three corner cases (slow, typical and fast). Parameters inside MOSFETS like mobility, threshold voltage etc., change with temperature. But appropriately sizing the MOSFETs and biasing them such that they are comfortably in saturation would ensure that there are not abrupt changes to the operating points. In the report we also discuss and compare the simulation results between the layout extracted netlist and the schematic netlist. Simulated Specifications:

Parameters Required Typical For 27 C

Slow For 100 C

Fast For -40 C

Differential Loop Gain >65 68.147 dB 65.153 dB 62.61 dB Loop Unity Gain Bandwidth >100 MHz 212.18 MHz 100.36 MHz 413.43 MHz

Loop Phase Margin >60 60.59 67.52 51.44 Common Mode Phase Margin >60 71.1 73.8 64.38

Common Mode Accuracy <±0.05 V 0.043 V 0.047 V 0.022 V Differential Output Swing >2 V 2.888 V 2.33327 V 2.8997 V

Power consumption <12 mW 10.6005 mW 5.5660 mW 18.965 mW Table 1: Simulated Specifications

Design Approach: Since our gain requirement was a higher order magnitude than gm*ro, we designed a two stage op-amp with the first stage being a telescopic amplifier and the second stage being a common source amplifier. Miller compensation was incorporated in our design to get a better phase margin, implying less peaking in closed loop. Once our initial design, was established for our differential loop, we had to take other constraints into consideration like power consumption, unity gain bandwidth, common mode phase margin, common mode accuracy. Our Initial design consumed very less power for a typical case but in order to increase bandwidth we had to burn more power. Once we found an estimate of the amount of current required to meet the bandwidth requirements, we appropriately sized the bias network. Initially we used a 100 uA current source as our 1x current and used PMOS mirrors to get the current in all the branches. The central challenge of this project was to get all the required measurements by iteratively changing the controllable parameters such as device sizes. Once we fix our final biasing current we replace it with a resistor that drops the same amount of voltage across it. The downside of replacing the current source is that the power consumption increase. In addition we were having small phase margin initially. But in order to improve this we simply reduce the gain of the common mode stage such that the common mode phase margin significantly improved.

Temperature varying Components:

Parameters Typical For 27 C

Slow For 100 C

Fast For -40 C

Load Capacitor, Cl 3p F 3.9p F 2.1p F Power Supply, Vdd 2.5 V 2.25 V 2.75 V

Biasing Resistor, Rbias 19.152K ohms 24.897K Ohms 13.406K Ohms Common Mode Capacitors 1p F 1.3p F 0.7p F Common Mode Resistors 5K 6.5 K 3.5 K Compensation Capacitor 1p 1.3p F 0.7p F

Table 2: Temperature Varying Components

Differential Loop Characteristics: Testbench for measuring Differential Loop Characteristics:

Differential Loop Characteristics: T= 27 degree

Differential Loop Characteristics: T= 100 degree

Differential Loop Characteristics: T= -40 degree

Phase margin could be improved in fast case by increasing the compensation capacitor but that comes at the expense of reducing the bandwidth of the amplifier.

Power Consumption: T= 27 degree

Power Consumption: T= 100 degree

Power Consumption: T= -40 degree

We were not able to meet the required specification for power consumption in the fast case. But this could be improved by reducing the current through our main biasing branch. Also we replaced our current source with an equivalent resistor such that the voltage across it remains the same. By eliminating the resistor we could have significantly reduced our power consumption for fast case.

Common-Mode Accuracy: The Common mode accuracy is the difference in the output node voltage and the common mode reference voltage. In our op-amp it was noticed that the op-amp outputs (2nd stage) were at: nodes nets 18 and net 27 T= 27 Degree

Common-Mode Accuracy: T= 100 Degree

Common-Mode Accuracy: T= -40 Degree

Common Mode Phase Margin: CMFB Phase Margin: T= 27 Degree

CMFB Phase Margin: T= 100 Degree

CMFB Phase Margin: T= -40 Degree

Differential Output Swing: T= 27 Degree

T= 100 Degree

T= -40 Degree

Single our second stage was a common source amplifier, we were able to get an excellent output swing. Our amplifier was biased in such a way that the DC output voltage was close to 1.25 V. The amplifier was highly linear over a wide range of output voltage. Single-Ended Output Swing T= 27 Degree

T= 100 Degree

T= -40 Degree

Single-Ended Vout voltage swing T= 27 Degree

T= 100 Degree

T= -40 Degree

Layout The second part of the project required us to layout our schematic for typical case (27 degrees). The layout is then extracted and after passing DRC and LVS, we generate the netlist. Below is a screenshot of the layout in Cadence Virtuoso:

The DRC and LVS successful running screenshots are shown in the next two figures below.

In the figure above we show that we passed LVS. The netlist that is extracted is put back into the test bench in order to observe the various specifications and compare them with the specifications we observed for the schematic. Due to grid errors we saw some minute difference between the layout extracted netlist specifications and the schematic specifications simulated in Hspice.

Layout Extracted Netlist Results: Once the LVS and DRC passed, we were able to generate a netlist from the extracted cell view and run analysis on the op-amp. The following were the simulation results we obtained from the layout extracted netlist:

Parameters for extracted netlist simulation Simulated Results

Differential Loop Gain 68.444 dB Loop Unity Gain Bandwidth 198 MHz

Loop Phase Margin 71.07 Common Mode Accuracy 0.1542V Differential Output Swing 3.4228 V

Power consumption 10.776 mW Table 3: Extracted Netlist from Layout Specifications

Differential Loop Specification: Phase Margin, Unity Gain Bandwidth and Gain at T =27 C

Power Consumption:

Differential Output Swing:

Single Ended Output Swing

Single Ended Output Voltage:

Common Mode Accuracy: T =27 C

The extracted netlist gave slightly different results from our initial, this can be attribute to the grid errors while doing layout and the inaccuracy of precisely laying out capacitors and resistors. In practical purposes there will always be some small change in the performance from the designed modelled op-amp to the model extracted.

Butterworth Filter: Design Approach: The 3dB bandwidth of the filter was required to be at 100 KHz. For this requirement we used a Tow- Thomas Biquad and a buffer stage to design our filter using our op-amp model. The topology for Tow-Thomas Biquad was obtained from Network Theory Class (ECE580) at Oregon State University. In order to find the values of components (Rs and Cs we used in the simulation of the Butterworth filter), a transfer function was computed by MATLAB. In this case, since stopband frequency is not specified, we used 500 kHz as the stopband frequency. The Denominator of the transfer function is separated into two sections. The first part will be the transfer function of the buffer stage. The other section will be the transfer function of the tow-Thomas Biquad. The transfer function of a tow-Thomas Biquad would be expressed in the form of

= + + By comparing with the transfer function obtained from Matlab, = 9.936 × 10 Hz, and Q is equal to 1. The value of Rs and Cs in this simulation is selected by using the equation, = × . We fixed R at 1KΩ and C is found to be approximately equal to 1nF. When we were designing the Butterworth filter, we noticed that there’s current flowing from input of the op-amp into the output of the op-amp. In order to eliminate this non-ideality, a pair of 1GΩ resistors is added to the output of each op-amp. Initially, the corner frequency of the filter is around 12KHz. To bring the corner frequency up, we decreased all the capacitors. Butterworth Schematic using the op-amp:

Frequency Response of Filter:

Matlab Code for finding transfer function of butterworth filter