7
V. R. GAIKWAD Dual Slope Analog to Digital Converter Jun 14, 2022 1 RC1130_007

Dual slope for DVM PPT

Embed Size (px)

Citation preview

Page 1: Dual slope for DVM PPT

V. R. GAIKWAD

Dual Slope Analog to Digital Converter

May 1, 2023

1

RC1130_007

Page 2: Dual slope for DVM PPT

Block Diagram

May 1, 2023RC1130_007

2

Page 3: Dual slope for DVM PPT

Circuit Diagram

May 1, 2023RC1130_007

3

Page 4: Dual slope for DVM PPT

Time Domain Analysis

tV

TV

RCTV

RCtVtv

RCTV

RCtV

tv

VvTvvRCTVTv

TtVvv

vdvRC

tv

inref

inref

o

inrefo

refio

ino

ini

t

io

0)(

)(

;);()0(

)(

;;0)0(

)0(1)(0

May 1, 2023

4

RC1130_007

Page 5: Dual slope for DVM PPT

Reflection Spot

What is the resolution of 3 ½ digit DVM which can measure input voltage from 0 V to 2 V

May 1, 2023

5

RC1130_007

Page 6: Dual slope for DVM PPT

Example

Specifications Maximum input voltage

Vin =2 V 3 ½ digit display Measurement Cycles per

second (Sampling frequency) fs=25 Hz

Design Measurement interval

Ts =1/ fs=40 ms Integration duration of

Vin T = Ts / 2=20 ms Integration duration of

Vref ; tmax = T / 2=10 ms Vref= -VinmaxT/ tmax=-4 V For N clock cycles in

time interval tmax; clock required is fclk=N/ tmax=200 kHz

May 1, 2023RC1130_007

6

Page 7: Dual slope for DVM PPT

Reference

Design with Operational Amplifier and Analog Integrated Circuit By Sergio Franco

Modern Digital Electronics By R. P. Jain

Introduction to System design using Integrated Circuit By B. S. Sonde

May 1, 2023

7

RC1130_007