Design and implementation of uart on soc

International Journal For Research & Development in Technology

Volume: 2, Issue: 1, JULY-2014 ISSN (Online):- 2349-3585

7

Copyright 2014- IJRDT www.ijrdt.org

DESIGN AND IMPLEMENTATION OF

UART ON SOC

A.Dasthagiraiah1,N.Subramanyam

2,

E.Supraja3,Dr.H.K.P.Prasad

4,K.V.Goutham

5

1,2,3,5 Assistant Professors in Priyadarshini Institute Of Technology ,Nellore

4,Pricipal at Priyadarshini Institute Of Technology ,Nellore

Abstract – Security is primary concern in our day-to-day life.

Everyone wants to be as much as secure as possible. The

UART (universal asynchronous receiver and transmitter)

module provides asynchronous serial communication with

external devices such as modems and other computers. The

UART can be used to control the process of breaking

parallel data from the PC down into serial data that can be

transmitted and vice versa for receiving data. The UART

allows the devices to communicate without the need to be

synchronized. UART is a popular method of serial

asynchronous communication. Typically, the UART is

connected between a processor and a peripheral. To the

processor, the UART appears as an 8-bit read-write parallel

port that performs serial-to-parallel conversions for the

processor, and vice versa for the peripheral. With the

implementation of UART the serial communication is done

in high data rate and no interrupts. Baud rate generator

provides high data rate and interrupt controller handles all

the interrupts. The UART serial communication interface

device receives data and converts data from serial to parallel,

where as the transmitter performs parallel to serial

conversion.

Key word:- SOC,UART

I.INTRODUCTION

The UART (universal asynchronous receiver and transmitter)

module provides asynchronous serial communication with

external devices such as modems and other computers. The

UART can be used to control the process of breaking parallel

data from the PC down into serial data that can be transmitted

and vice versa for receiving data. The UART allows the

devices to communicate without the need to be synchronized.

UART is a popular method of serial asynchronous

communication. Typically, the UART is connected between a

processor and a peripheral. To the processor, the UART

appears as an 8-bit read-write parallel port that performs serial-

to-parallel conversions for the processor, and vice versa for the

peripheral. The UART allows reliable data transfer at high

speeds with its 16-byte first in, first out (FIFO) input register.

The FIFO feature can buffer up to 16 bytes at a time, which

improves serial communications by preventing data overruns

in applications. The implementation of UART the serial

communication is done with high data rate and no interrupts.

The UART 16550 serial communication interface device

receives data and converts data from serial to parallel, where

as the transmitter performs parallel to serial conversion.

This thesis portrays a novel architecture of Universal

Asynchronous Receiver Transmitter. UARTs are used for

asynchronous serial data communication between remote

embedded systems. The UART is for interfacing computers or

microprocessors to an asynchronous serial data channel. The

receiver converts serial start, data, parity and stop bits. The

transmitter converts parallel data into serial form and

automatically adds start, parity and stop bits. The data word

length can be 5, 6, 7 or 8 bits. Parity may be odd or even.

Parity checking and generation can be inhibited. The stop bits

may be one or two or one and one-half when transmitting 5-bit

code.

The UART can be used in a wide range of applications

including modems, printers, peripherals and remote data

acquisition systems. Utilizing the advanced scaled SAJI IV

CMOS process permits operation clock frequencies up to

8.0MHz (500K Baud).

Power requirements, by comparison, are reduced from

300mW to 10mW. Status logic increases flexibility and

simplifies the user interface. The basic application of UART is

shown in Figure 1.1.

Figure 1.1 Basic Application of UART

This design can also be instantiated many times to get multiple

UARTs in the same device. For easily embedding the design

into a larger implementation, instead of using tri-state buffers,

the bi-directional data bus is separated into two buses, DIN

and DOUT. The transmitter and receiver both share a common

internal Clk16X clock. This internal clock which needs to be

16 times of the desired baud rate clock frequency is obtained

from the on-board clock through the MCLK input directly.


Paper Title:- DESIGN AND IMPLEMENTATION OF UART ON SOC (Vol.2,Issue-1) ISSN(O):- 2349-3585

8


1.1 SYNCHRONOUS SERIAL TRANSMISSION

Synchronous serial transmission requires that the

sender and receiver share a clock with one another, or that the

sender provide a strobe or other timing signal so that the

receiver knows when to “read” the next bit of the data. In most

forms of serial Synchronous communication, if there is no

data available at a given instant to transmit, a fill character

must be sent instead so that data is always being transmitted.

Synchronous communication is usually more efficient because

only data bits are transmitted between sender and receiver, and

synchronous communication can be more costly if extra

wiring and circuits are required to share a clock signal

between the sender and receiver.

A form of Synchronous transmission is used with

printers and fixed disk devices in that the data is sent on one

set of wires while a clock or strobe is sent on a different wire.

Printers and fixed disk devices are not normally serial devices

because most fixed disk interface standards send an entire

word of data for each clock or strobe signal by using a

separate wire for each bit of the word. In the PC industry,

these are known as Parallel devices.

1.2 ASYNCHRONOUS SERIAL TRANSMISSION

Asynchronous transmission allows data to be

transmitted without the sender having to send a clock signal to

the receiver. Instead, the sender and receiver must agree on

timing parameters in advance and special bits are added to

each word which are used to synchronize the sending and

receiving units.

When a word is given to the UART for

Asynchronous transmissions, a bit called the "Start Bit" is

added to the beginning of each word that is to be transmitted.

The Start Bit is used to alert the receiver that a word of data is

about to be sent, and to force the clock in the receiver into

synchronization with the clock in the transmitter. These two

clocks must be accurate enough to not have the frequency drift

by more than 10% during the transmission of the remaining

bits in the word. (This requirement was set in the days of

mechanical tele-printers and is easily met by modern

electronic equipment.)

After the Start Bit, the individual bits of the word of

data are sent, with the Least Significant Bit (LSB) being sent

first. Each bit in the transmission is transmitted for exactly the

same amount of time as all of the other bits, and the receiver

“looks” at the wire at approximately halfway through the

period assigned to each bit to determine if the bit is a 1 or a 0.

For example, if it takes two seconds to send each bit, the

receiver will examine the signal to determine if it is a 1 or a 0

after one second has passed, then it will wait two seconds and

then examine the value of the next bit, and so on.

The sender does not know when the receiver has

“looked” at the value of the bit. The sender only knows when

the clock says to begin transmitting the next bit of the word.

When the entire data word has been sent, the transmitter may

add a Parity Bit that the transmitter generates. The Parity Bit

may be used by the receiver to perform simple error checking.

Then at least one Stop Bit is sent by the transmitter.

When the receiver has received all of the bits in the

data word, it may check for the Parity Bits (both sender and

receiver must agree on whether a Parity Bit is to be used), and

then the receiver looks for a Stop Bit. If the Stop Bit does not

appear when it is supposed to, the UART considers the entire

word to be garbled and will report a Framing Error to the host

processor when the data word is read. The usual cause of a

Framing Error is that the sender and receiver clocks were not

running at the same speed, or that the signal was interrupted.

II.BLOCK DIAGRAM OF UART

Block diagram of UART is shown in Figure 2.1.

Figure:2.1 Block Diagram of UART

2.1TRANSMITTER

A component, uart_tx is designed for transferring data

using serial communication. Figure 2.2 shows the block

diagram for the module uart_tx, which has clr and clk inputs

used to reset and synchronize communication. A byte of data

is input using tx_data[7:0]. When ready is asserted the byte of

data is transmitted on the TxD output starting with the least

significant bit first. After the transmission has completed, the

transmit data ready pin, tdre, goes high.

Figure 2.2 Block diagram of Transmitter module

Transmission begins with the TxD line transitioning

from high to low for one bit time. This leading bit is called the

start bit. The bit time depends on the baud rate. Immediately

following the start bit, the first data bit, the least significant

bit, transferred followed by the next, more significant bit until

all eight bits of data have been transferred.

Each bit remains on the TxD line for one bit time. After

the most significant bit has been transferred, TxD goes high

for one bit time. This trailing bit is called the stop bit. The

state diagram for transmitting serial data is shown in Figure.

2.3



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.

Figure 2.3 State diagram of UART transmitter

The state machine starts in the mark state until the

ready signal goes high. This state resets a signal for counting

the number of bits transmitted, bit_count, to zero and asserts

the tdre output high indicating that the component is not

currently transmitting data. When the ready input goes high

the state machine transitions to the start state for transmitting

the start bit. Since the start bit is a logic low, TxD is set to

zero, and must be held low for one bit time. A counter

baud_count is used to count clock cycles until the bit time is

reached, baud_count is reset to zero in start and tdre is brought

low indicating that a transmission is in progress.

On the rising edge of the clock, the next state is

delay. The bit time counter, baud_count is incremented in the

delay state and the state machine remains in the delay state

while the baud_count is less than the bit_time. Bit_time is a

constant number of cycles required for 0.104 milliseconds to

Pass. Once the baud_count has counted up to a bit_time,

execution continues to the shift state to transfer a data bit. The

byte to transferred is stored in a buffer signal,txbuff[7:0]. In

this case, the first data bit or least significant bit of the buffer,

txbuff[0], is assigned to TxD in the shift state. Additionally,

tdre remains low, txbuff is shifted one bit to the right,

bit_count is incremented to count the number of bits

transmitted, and baud_count is reset to zero. By shifting txbuff

one bit to the right, txbuff[0] always contains the next bit to be

transferred until all the eight bits have been transferred. On the

next rising edge of the clock, the state machine transitions

back to delay. Once again, baud_count is increment on each

rising clock edge remaining in delay until one bit time has

passed, when baud_count becomes equal to bit_time.

Execution continues to shift, outputting the next bit and

shifting the transfer buffer, txbuff. After TxD has been set to

the next data bit in the shift state, the output remains the same

while the state machine remains in the delay state for one bit

time.

Using a 25MHz clock to drive uart_tx, the bit_time is

computed as follows.

25x106x0.104x10

-3=2600(0xA28 in hex)

Parameters involved:

Baud_count: A counter parameter that increments at every

positive edge of clock.

Bit_time: The time for which each data bit must stay on the

line.

Bit_count: A parameter that keeps count of the no. of bits

transmitted.

2.2 RECEIVER MODULE

Receiving data is similar to transmitting data. Figure 2.4

shows the block diagram of the receiver. Eight bits of

asynchronous data are input into RxD. Bits are shifted into the

8-bit shift register, rx_data[7:0], least-significant bit first.

When rx_data[7:0] is full, the received-data ready flag rdrf, is

set to 0 to signify that rx_data[7:0] contains a complete byte.

The output rdrf is set to 0 by setting rdrf_clr to high. The

framing error flag, FE, is set to 1 if the stop bit is not 1. This is

one indication that the data on rx_data[7:0] may not be

accurate. Fig shows the state diagram for the serial

receiver.The state diagram in Figure 2.5 has the same states

as the state machine developed for transmitting data. The

transitions between these states are also the same. There is,

however, one subtle, important difference. Instead of

remaining in the start state for a whole bit time, the state

machine transitions to the delay state after a half-bit time. Bit

time is determined by the baud rate in the same way it was

used in the transmitter.

Figure 2.4 Block diagram of Receiver module

Figure 2.5 State diagram of UART receiver

Figure 2.6 illustrates the difference in timing between serially

transmitting and receiving 8 bits of data.



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Figure 2.6 Timing differences between transmitting and

receiving

As stated earlier , the parameters used in design of

an Rx module remains the same. A new parameter namely

„half_bit_time‟ which represents half of the bit time. Due to

the delay in transmission of data , the start bit appears only

after half the bit time has elapsed.

During transmission, the start bit is transmitted for an

entire bit time just like the data bits and the stop bit. When

receiving, by waiting only a half bit time after the start bit has

been initiated, the data shifted into the shift register during the

shift state is farthest away from the time the signal changes.

That is, half way between the beginning and the ending time

during which the bit is valid.

The state diagram in Figure 2.5 starts in the mark

state. The state resets a signal for counting the number of bits

transmitted, bit_count, to zero and asserts the rdrf output low

indicating that the data in rx_data[7:0] is not complete. When

RxD goes low, signifying a start bit, the state diagram

transitions to the start state it remains in the start state for one-

half of a bit time, then transitions to the delay state. The bit

time counter, baud_count is incremented in the delay state and

the state diagram remains in the delay state while the

baud_count is less than the bit_time.

III.DEVELOPMENT OF CODE FOR UART IN

ARDUINO The other end of the SOC model is an

embedded core. In this project it is taken as an ARDUINO

controller. Arduino is an open source single board

microcontroller, descendant of the open source wiring

platform, designed to make the process of using electronics in

multidisciplinary projects more accessible. The hardware

consists of a simple open hardware design for the Arduino

board with an Atmel AVR processor and on-board

input/output support. The software consists of a standard

programming language compiler and the boot loader that runs

on the board.The code dumped into the microcontroller

performs to and fro serial communication from the board. The

algorithm for the corresponding code is given below:

START

INITIALIZE LCD

READ_DATA (INPUT_PIN)

PRINT_LCD(INPUT_PIN)

WRITE_DATA(INPUT_PIN)

STOP

3.1 FPGA IMPLEMENTATION FLOW DIAGRAM

Figure 4.1 Flow chart for FPGA

Flow chart for FPGA is shown Figure 4.1. Initially the market

research should be carried out which covers the previous

version of the design and the current requirements on the

design. Based on this survey, the specification and the

architecture must be identified. Then the RTL modeling

should be carried out in VHDL with respect to the identified

architecture. Once the RTL modeling is done, it should be

simulated and verified for all the cases. The functional

verification should meet the intended architecture and should

pass all the test cases. Once the functional verification is clear,

the RTL model will be taken to the synthesis process. Three

operations will be carried out in the synthesis process such as

Translate

Map

Place and Route

The developed RTL model will be translated to the

mathematical equation format which will be in the

understandable format of the tool. These translated equations

will be then mapped to the library that is, mapped to the

hardware. Once the mapping is done, the gates were placed

and routed. Before these processes, the constraints can be

given in order to optimize the design. Finally the BIT MAP

file will be generated that has the design information in the

binary format which will be dumped in the FPGA board.

3.2 SIMULATION RESULT OF UART

Figure 5.1 shows the simulation result of UART top

level module. UART top module contains both transmitter

module and receiver module..



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3.3 HARDWARE RESULT:

COMMUNICATION BETWEEN TWO

PROCESSORS USING UART PROTOCOL

Figure . Communication between FPGA based processor

and Embedded processor

IV.FUTURE SCOPE

By using UART protocol we can communicate

between only two processors. Hence to avoid this limitation

we have introduced Modus protocol to operate various devices

at a time.

REFERENCE [1] "Universal asynchronous receiver/transmitter", located on:

http://en.wikipedia.org/wiki/Universal_asynchronous_receiver

/transmitter

[2] "Developing Multifunctional Serial-Parallel Data

Communication Interface for PC-Based Control System",

locatedon:http://journal.uii.ac.id/index.php/Snati/article/viewF

ile/1583/1358

[3] "Verilog design of input/output processor with

built-in-self-test",locatedon:

http://eprints.utm.my/5959/1/GohKengHooMFKE2007TTT.p

df

[4] "Embedded Monitoring Server", located on:

http://www.doria.fi/bitstream/handle/10024/29686/nbnfi-

fe20071990.pdf?sequence=1

[5] "AND THE COMMITTEE ON GRADUATE STUDIES",

located on:

http://eil.stanford.edu/publications/yang_wang/yw_thesis.pdf

[6] "Computer numerical controlled drilling machine

interfaced to a computer aided design package", located on:

http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1058&context

=td_ptech

Mr. A.Dasthagiraiah- He completed

his Master of Technology in Electronics and communication

Engineering from Hindustan University in the year 2011 with

specialization in Embedded Systems. He has given guidance

to many students in their thesis work of M.Tech. He has also

contributed in the research work on Embedded Systems with

his papers. He has four years teaching Experience and

presently working as Asst. Professor in Priyadarshini Institute

of Technology,SPSR Nellore. He has done Bachelor's of

Technology from JNTUA University in the year 2009 in

Electronics and Communication Engineering

Mr. N.Subramanyam- He completed

his Master of Technology in Electronics and communication

Engineering from JNTUA in the year 2011 with specialization

in Embedded Systems. He has given guidance to many

students in their thesis work of M.Tech. He has also





Technology from ANNA University in the year 2009 in


Mr. K.V.Goutham- He completed his

Master of Technology in Electronics and communication

http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter

http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter

http://eprints.utm.my/5959/1/GohKengHooMFKE2007TTT.pdf

http://eprints.utm.my/5959/1/GohKengHooMFKE2007TTT.pdf

http://eil.stanford.edu/publications/yang_wang/yw_thesis.pdf



12


Engineering from JNTUA in the year 2012 with specialization

in Embedded Systems. He has given guidance to many

students in their thesis work of M.Tech. He has also





Technology from JNTUA University in the year 2010 in


Mrs. E.Supraja:- She completed her

Master of Technology in Electronics and communication

Engineering fromPBRVITS,Kavali in the year 2013 with

specialization in VLSI Systems. She has given guidance to

many students in their thesis work of M.Tech She has 6 years

teaching Experience and presently working as Asst. Professor

in Priyadarshini Institute of Technology,SPSR Nellore. She

has done Bachelor's of Technology from JNTUA University in

the year 2006 in Electronics and Communication Engineering.