CMOS Analog Multiplier in Deep Sub-Micron Technology

Simulation & Analysis of Wideband and Low Power

CMOS Analog Multiplier in DSM Technology

Electronics & Communication Engineering Department Laljibhai Chaturbhai Institute of Technology

Bhandu - 384120

Guided by:

Prof. Gireeja D. Amin

Asst. Prof., E.C. Dept.,

LCIT, Bhandu

Prepared by:

Dhrumil S. Patel

Enroll No. : 120290742014

PG Student

A Dissertation Phase II (740002)

Contents

• Introduction

• Classification

• Application

• Different Architectures of Analog Multiplier

• Simulation Results

• Summary & Future Scope

• References

2 CMOS Analog Multiplier 120290742014 03-July-14

Introduction

What is Analog multiplier?

• Analog Multiplier is a device which takes two analog

signals and produces an output which is their product.

3 CMOS Analog Multiplier 120290742014

Fig. 1 Basic idea of multiplier[13]

03-July-14

Multiplier Classification

Depending on the Input/output Mode

Voltage Mode Multiplier

Current Mode Multiplier

Quadrant based classification

One-quadrant multipliers:

Inputs are of the same phase.

Two quadrant multipliers:

Opposite voltage can be added to either of the input

Four quadrant multipliers:

Opposite voltage can be added to both the inputs.


Depending on the circuit configuration

Single ended multiplier

Double ended multiplier

Multiplier Classification


Analog Multiplier Application

Modulator

Divider

Squaring

Root mean square value

Mixer


Architectures of Four Quadrant

Analog Multiplier And

Simulation


Four Quadrant Multiplying Quad


Fig. 2: Multiplying Quad

03-July-14

TSMC 0.18µm Technology

in

Mentor Graphics

Eldo Simulator Tool


Simulation Result Transient Waveforms

10 CMOS Analog Multiplier 120290742014 Fig. 3: transient response

03-July-14

a) V12 sinusoidal carrier signal

b) V34 sinusoidal modulating signal

c) Output waveforms of Analog multiplier

d) Output waveforms of Analog multiplier

Simulation Result DC Analysis


Fig. 4: DC response

03-July-14

Simulation Result Freq Response


Fig. 5: Frequency response

03-July-14

331.991MHz

20.013dB

Simulation Result

Technology 0.18µm(TSMC) 0.35µm(TSMC)

Power Supply 1.5V 2.0V

Bandwidth 331.99MHz 304.336MHz

Power

Dissipation 3.35mW 17.188mW

Gain 20.013 dB 10.8 dB


Table 1: Simulated result for 180nm & 350nm technology

03-July-14

Analog Multiplier Based On Square

Rooting Circuit


Fig. 6: Analog multiplier based on square rooting circuit[3]


in

Mentor Graphics

Eldo Simulator Tool


Simulation Result


Transient Response

03-July-14





Fig. 7: Transient response

Simulation Result

CMOS Analog Multiplier 120290742014 17

Frequency Response

Fig. 8: Frequency Response

03-July-14

27.880dB

493.14MHz

Simulation Result


DC Analysis Response

Fig. 9: DC response

03-July-14

Simulation Result


Technology

0.18µm(TSMC)

0.35µm(TSMC)

Power Supply 1.5V 2V

Bandwidth 493.14MHz 229.70MHz

Power

Dissipation 160.49µW 423.25µW

Gain 27.88 dB 18.36dB

Table 2: Simulated result for 180nm & 350nm technology

03-July-14

Analog Multiplier Using Square Rooting

Circuit (Modified)


Fig. 10: Analog Multiplier Using Square Rooting Circuit

03-July-14


in

Mentor Graphics

Eldo Simulator Tool


Simulation Result Transient Waveforms

22 CMOS Analog Multiplier 120290742014 Fig. 11: Transient response

03-July-14







Fig. 12: DC response

03-July-14

Simulation Result Frequency Response



03-July-14

36.293dB

679.67MHz

Simulation Result


Table 3: Simulated result Analog Multiplier in CMOS technology

03-July-14

Parameters Ref [6]

This Work

Based on

Square rooting

circuit Modified

Power Supply(V) 1.8 1.5 1.3

Bandwidth(MHz) 110 331.99 679.67

Power Dissipation(μW) 165 160.49 145.55

Gain - 20.013dB 36.2938dB

Analog Multiplier Using Combiner and

Subtractor Circuit


Fig. 14: Analog multiplier based on subtractor and combiner circuit [6]


in

Mentor Graphics

Eldo Simulator Tool


Simulation Result


Transient Response

03-July-14 Fig. 15: Transient response








03-July-14




03-July-14

37.725dB

719.68MHz

Analog Multiplier Using Combiner and

Subtractor Circuit (Modified)


Fig. 18: Analog multiplier based on subtractor and combiner circuit


in

Mentor Graphics

Eldo Simulator Tool


Simulation Result


Transient Response

03-July-14 Fig. 19: Transient response








03-July-14




03-July-14

39.26dB

754.96MHz

Simulation Result


Table 4: Simulated Result Analog Multiplier in CMOS technology

03-July-14

Parameters Ref [23]

This Work

Based on

Combiner and

Subtractor Circuit Modified

Power Supply(V) 1.8 1.5 1.2

Bandwidth(MHz) 64 719.68 754.96

Power Dissipation(µW) 22 17.21 13.59

Gain(dB) - 37.72 39.26

Summary & Future Scope


Multiplier quad architecture has more power dissipation

and moderate bandwidth due to the biasing circuit.

Multiplier based on the square rooting circuit have the low

power dissipation and the higher bandwidth compared to

the multiplying quad due to not extra voltage references &

biasing network.

Multiplier using combiner and subtractor circuit improves

power dissipation and bandwidth due to the novel

cancellation of the non-linear terms in circuit.

Modified structure uses MOS transistor instead of resistor

so its power consumption and linearity error are less.

03-July-14

Summary & Future Scope


The future scope is use the adder circuit instead of the

subtractor circuit with the combiner cell and makes the

novel topology of four quadrant analog multiplier. So,

performance of the circuit is improved.

03-July-14

References


1. Smail Hassouni, Hassan Qjidaa, Mohamed Latrach, “A DESIGN OF

ANALOG VOLTAGE-MODE MULTIPLIER FOR UHF RFID

PASSIVE IN 0.18UM CMOS PROCESS”, Journal of Theoretical and

Applied Information Technology, 20th July 2013. Vol. 53 No.2

2. Priyanka Mandavgade, Rupali Balpande, “VlSI Implementation Of

An Analog Multiplier”, IRNet Transactions on Electrical and

Electronics Engineering (ITEEE) ISSN 2319 – 2577, Vol-1, Iss-2,

2012

3. N. Kiatwarin, W. Ngamkham and W. Kiranon, “A Compact Low

Voltage CMOS Four Quadrant Analog Multiplier”, ECTI

International Conference,2007

4. Sanjay Tembhurne, L. P. Thakare, “VLSI DESIGN OF FOUR

QUADRANT ANALOG MULTIPLIER FOR ISM BAND”, The

International Journal of Computer Science & Applications, Volume 1,

No. 3, May 2012

03-July-14

References


5. Nandini A.S, Sowmya Madhavan and Dr Chirag Sharma, “DESIGN

AND IMPLEMENTATION OF ANALOG MULTIPLIER WITH

IMPROVED LINEARITY”, International Journal of VLSI design &

Communication Systems, Vol.3, No.5, October 2012

6. P. Mohan Kumar, “Low Voltage CMOS Analog Multiplier”, Major

Project report, Thapar University, July-2011

7. Ami Patel, “Design and Simulation of Different architectures of

analog multiplier using sub-micron technology”, Nirma University,

Department of Electronics and Communication, May 2009

8. Soliman A. Mahmoud, “Low Voltage Low Power Wide Range Fully

Differential CMOS Four-Quadrant Analog Multiplier”, 978-1-4244-

4480-9/09/$25.00 ©2009 IEEE

03-July-14

References


9. Yuan Gao, Kaizhi Cai, Yuanjin Zheng and Ban-Leong Ooi, “A

Wideband CMOS Multiplier for UWB Application” 1-4244-0521l-

1/07/$20.00 ©2007 IEEE

10. Chutham Sawigun, Andreas Demosthenous, and Dipankar Pal, “A

Low-Voltage, Low-Power, High-Linearity CMOS Four-Quadrant

Analog Multiplier” 1-4244-1342-7/07/$25.00 ©2007 IEEE

11. Chunhong Chen, Zheng Li, “A Low-Power CMOS Analog

Multiplier”1057- 7130/$20.00 © 2006 IEEE

12. Boonchai Boonchu, Wanlop Surakampontorn, “A New NMOS Four-

Quadrant Analog Multiplier”, 0-7803-8834-8/05/$20.00 ©2005 IEEE.

13. R. Jacob Baker, Harry W. Li and David E. Boyce, “CMOS Circuit

Design, Layout, and Simulation”, TK 7871.99 .M44B335 1998 C.1

03-July-14

References


14. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, ISBN

0-07-238032-2, TK7874.654.R39 2001

15. http://nptel.ac.in/courses/117106088/32, NPTEL >> Electronics &

Communication Engineering >> Electronics for Analog Signal

Processing - II (Video) >> Multipliers

16. http://nptel.ac.in/courses/117106088/33, NPTEL >> Electronics &

Communication Engineering >> Electronics for Analog Signal

Processing - II (Video) >> Multipliers

03-July-14

CMOS Analog Multiplier 120290742014 43 03-July-14