8085 Microprocessor Page 1

1.8085 MICROPROCESSOR 1.1 8085 Microprocessor features:

It is invented in 1976.

It is an 8-bit microprocessor.

8085 microprocessor provides 16 address lines, therefore it can access 2^16 = 64K

bytes of memory.

It has 8 Data lines and 16 address lines, out of which 8 address lines are multiplexed

with 8 data lines. Hence it requires external hardware to separate data lines from

address lines (this is one of the disadvantage of 8085).

It generates 8 bit I/O address, hence it can access 2^8 = 256 input ports and 256

output ports.

8085 microprocessor provides one Accumulator, one Flag register, 6 General

Purpose Registers (B, C, D, E, H and L) and two special purpose registers (PC, SP).

The maximum clock frequency of 8085 microprocessor is 3MHz where as minimum

clock frequency is 500 KHz.

8085 microprocessor provides on chip clock generator, therefore there is no need of

external clock generator, but it requires external tuned circuit like LC, RC or crystal.

It is manufactured in NMOS technology

It is available in 40 pin dual in line (DIP) package.

It requires a +5volts of power supply.

8085 microprocessor has five hardware interrupts: TRAP, RST 5.5, RST 6.5, RST 7.5,

and INTR. The hardware interrupt capability of 8085 microprocessor can be

increased by providing external hardware.

8085 microprocessor has capability to share its bus with external bus controller

(Direct Memory Access controller); for transferring large amount of data from

memory to I/O and vice versa.

8085 microprocessor provides two serial I/O lines which are SOD and SID; it means,

serial peripherals can be interfaced with 8085 microprocessor directly.

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1.2 Pin diagram and Signal Description:

Fig:-Pin diagram of 8085 Microprocessor Fig: - Functional Diagram of 8085

Address & data lines:

Address bus: 8085 has 16-bit address bus AD0-AD7 and A8-A15. In this lower address bus is

multiplexed with data bus. A8-A15 lines are unidirectional and AD0-AD7 lines are

bidirectional.

Data bus: AD7-AD0 is 8-bit bidirectional data bus. It is multiplexed with lower order address bus.

ALE:

Address latch enable. It is used to de-multiplex AD0-AD7. It is connected to strobe input

of latch which is used to separate address and data bus lines. It is issued in first T-state.

Control & Status Signals:

RD: Read control signal is issued to memory or IO device to read data from it.

WR: Write control signal is issued to memory or IO device to write data into it.

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IO/M: It is a signal which is used to distinguish

between IO operation and memory operation. It is

also used in generating memory and IO, read and

write control signals.

S1, S0: These are status signals. Depending on the

value on these lines, the type of operation being

performed by the processor can be determined.

Below table shows that information.

Power Supply and clock signals:

Vcc: +5v power supply line

Vss: Electrical ground signal.

X1, X2: Crystal is connected between these pins. The frequency is internally divided by 2.

The systems operates generally at 3MHz. Hence 6 MHz clock signal needs to be connected

between X1, X2 lines.

CLK (out): It is the clock output signal from processor, which can be used to clock other

peripherals in the microprocessor based system.

READY: This is used when the processor is reading or writing data to a slow peripheral.

When this signal goes low processor inserts wait states, until it goes high.

Reset Signals:

RESET IN: When low signal is applied on this pin, 8085 resets and the microprocessor

boots from 0000h location in memory i.e. PC is loaded with 0000h location.

RESET OUT: When processor is reset, this signal goes high. This pin is connected to reset

input of other peripherals. So when processor is reset, other peripherals are also reset.

Serial IO lines:

SID: serial input data, used to receive serial data.

SOD: serial output data, used to send serial data

Interrupt Signals:

INTR: interrupt request is general purpose interrupt signal. The interrupting device needs

to send the vector address also.

INTA: is interrupt acknowledging signal. This signal indicates that processor has accepted

the interrupt.

RST7.5, RST6.5, RST5.5: These are external vectored interrupts. When these interrupt

occurs, processor vectors to a specific location.

TRAP: It is a non-mask able interrupt.

DMA signals:

HOLD: This line is used by DMA controller to request microprocessor for system bus.

When this line goes high microprocessor completes its current bus cycle and issues system

bus to DMA controller.

HLDA: HOLD acknowledging signal. Processor acknowledges DMA request using this signal.

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1.3 Architecture of 8085 Microprocessor Below figure shows the architecture of 8085 microprocessor.

Fig:- Architecture of 8085 microprocessor

The following are the different blocks in the 8085 processor. ALU:

It is 8-bit ALU. It can perform arithmetic and logical operations on 8-bit data. If an operation needs to be performed on 16-bit data, it needs to be broken into two 8-bit parts and each 8-bit operation should be performed on each 8-bit data. It takes operand inputs from accumulator and a temporary register. Result of the operation is stored in accumulator. Depending on the result of operation, flags in flag register values will be changed. Acumulator

It is a 8-bit register which is used to perform airthmetical and logical operation. It stores the output of any operation. It also works as registers for i/o accesses. Temporary Register

It is a 8-bit register which is used to hold the data on which the acumulator is computing operation. It is also called as operand register because it provides operands to ALU.

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Register Array:

8085 has six general purpose registers B, C, D, E, H, L. They can be used as pairs to hold 16-bit data as BC, DE, HL. Accumulator is 8-bit register which holds the results of operations as well as operand on which some operation needs to be performed. Flag register contains five flags, namely S, Z, CY, AC, P flags. 8085 has two 16- bit register PC and SP. PC always consists of address of next instruction to be executed. SP always points to top of stack. i.e. address of top memory location of stack. Stack is a data structure. It is used to store return addresses whenever call to subprograms or an interrupt occurs.

Two temporary registers W, Z are also present. These are used to hold temporary results during execution. But these are not accessible to the user.

Incrementer and decrementer address latch is for incrementing the PC content for every fetch cycle.

Flag register:

As already explained contents of flag register will be changed according to the result of ALU operation. Below figure shows the flag register format of 8085.

Sign flag (S): when the result of ALU operation is negative sign flag is set. If the result is positive, then sign flag is reset. i. e. the D7 bit of accumulator is copied into the sign flag, as D7 anyhow contains sign. Zero flag (Z): when the result of ALU operation is zero, Zero flag is set. If the result is non-zero then flag is reset. Auxiliary carry (AC): If an ALU operation results in carry from lower nibble to upper nibble (or) bit D3 to bit D4, Auxiliary flag is set. Else it is reset. This flag is used in BCD arithmetic. Parity flag (P): If the result contains even number of ones, the flag is set else it is reset. So the parity flag is odd parity bit. Carry flag (CY): If the arithmetic operation results in carry, CY flag is set, else it is reset.

Instruction Register and Decoding: Instruction register holds instruction that is fetched from memory. Instruction decoder decodes the opcode (which is part of fetched instruction present in instruction register). Instruction register is not accessible to the programmer.

Interrupt Controller: 8085 has 5 external interrupts. TRAP, INTR, RST 5.5, RST 6.5, and RST 7.5. Whenever processor gets interrupt it finishes current instruction execution and issues INTA (interrupt acknowledge) signal to the peripheral which raised the interrupt and goes to execute interrupt service routine. Interrupt controller controls the interrupts.

Serial I/O control: Serial data can be sent out using SOD pin and serial data can be read from SID pin. It controls serial IO related operations.

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Program Counter It is a 16 bit register used as memory pointer. It stores the memory address of the next

instruction to be executed. So we can say that this register is used to sequencing the program. Generally the memory have 16 bit addresses so that it has 16 bit memory. The program counter is set to 0000H. Stack Pointer

It is also a 16 bit register used as memory pointer. It points to the memory location called stack. Generally stack is a reserved portion of memory where information can be stores or taken back together.

Timing and Control Unit It provides timing and control signal to the microprocessor to perform the various

operation.It has three control signal. It controls all external and internal circuits. It operates with reference to clock signal.It synchronizes all the data transfers. There are three control signal:

1. ALE-Airthmetic Latch Enable, It provides control signal to synchronize the components of microprocessor.

2. RD- This is active low used for reading operation. 3. WR-This is active low used for writing operation. There are three status signal used in microprocessor S0, S1 and IO/M. It changes its

status according the provided input to these pins.

1.4 Bus Structure in 8085 There are three buses in Microprocessor: 1. Address Bus 2. Data Bus 3. Control Bus

Address Bus Genearlly, Microprocessor has 16 bit address bus. The bus over which the CPU sends

out the address of the memory location is known as Address bus. The address bus carries the address of memory location to be written or to be read from.

The address bus is unidirectional. It means bits flowing occurs only in one direction, only from microprocessor to peripheral devices. We can find that how much memory location it can using the formula 2^N. where N is the number of bits used for address lines. Q. If a processor has 4 GB memory then how many address lines are required to access this memory? Ans: 4GB= 4 * 1GB, 4 =22, 1GB = 230, 4GB = 22 X 230 = 232

So 32 address lines are required to access the 4 GB memory.

Data Bus 8085 Microprocessor has 8 bit data bus. So it can be used to carry the 8 bit data

starting from 00000000H(00H) to 11111111H(FFH). Here 'H' tells the Hexadecimal Number. It is bidirectional. These lines are used for data flowing in both direction means data can be transferred or can be received through these lines. The data bus also connects the I/O ports and CPU. The largest number that can appear on the data bus is 11111111.

It has 8 parallel lines of data bus. So it can access upto 2^8 = 256 data bus lines.

Control Bus The control bus is used for sending control signals to the memory and I/O devices. The CPU sends control signal on the control bus to enable the outputs of addressed memory devices or I/O port devices. Some of the control bus signals are as follows:

1. Memory read 2. Memory write 3. I/O read 4. I/O write

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1.5 8085 bus timings and machine cycles Before continuing with bus timings and various machine cycles, Let us concentrate

on what an instruction is and what are machine cycles and what is T-state. An instruction is a command given to processor to perform some data processing

task. An instruction consists of Opcode and operand information (may be immediate data, or reference to operand). Opcode describes what operation needs to be performed by processor. To execute each instruction processor requires some machine cycles. These machine cycles are some basic processing steps to finish an instruction execution. For example to execute an instruction opcode needs to be fetched from memory and then data need to be read from memory. These kinds of operations are called machine cycles. To perform each machine cycle processor requires some no. of T-states. In each T-state microprocessor perform some micro operation of each machine cycle. For example to fetch opcode, processor needs to issue address to memory, and issue read signal, and opcode needs to be stored in instruction register from data bus, All these are some micro operations To perform these operations processor requires some T-states.

8085 microprocessor performs following machine cycles as a whole. All the instructions may not require all the machine cycles.

1. Opcode fetch 2. Memory read 3. Memory write 4. I/O read 5. I/O write 6. Interrupt acknowledge 7. Halt 8. Hold 9. Reset

1. Opcode Fetch Machine Cycle:

Opcode fetch cycle is part of any instruction execution. In this machine cycle 8085 fetches opcode of instruction. The following are the sequence of actions that are performed by 8085 to fetch an opcode from memory. This machine cycle consists of 4 T-states. 8085 places 16-bit address from PC on to

the address bus (of course lower order address bus is multiplexed with data bus) and issues ALE pulse in first T-state (T1). This is used to de-multiplex the address and data bus. It also issues IO/M’ signal to ‘0’. This indicates that processor is performing memory related operation.

In second T-state (T2) processor issues RD’ control signal to memory. This enables memory to put data present at the address location given in previous T-state on to data bus. RD’ control signal is active for two clock pulses.

In T3 state memory places opcode on Data bus. Processor reads opcode present on data bus and de-asserts RD’ signal. Thus data bus goes into high impedance state.

In T4 state processor decodes instruction and necessary actions are performed.

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2. Memory Read machine cycle: This machine cycle is required when an operand is present in memory. This machine

cycle requires three T-states. The following are the sequence of actions performed by microprocessor during this machine cycle.

In the first T-state (T1) 8085 places

address on address bus and issues ALE signal. And also IO/M’ signal is made low, since it is memory related operation.

In the second T-state (T2), processor

issues RD’ control signal to memory. In response to this memory places data on data bus.

In the third T-state (T3), processor

reads data from data bus, and de-asserts RD’ signal.

3.Memory Write Machine cycle:

This machine cycle is required when the results of operation needs to store in memory. This machine cycle requires three T-states. The following are sequence of actions performed by processor in this machine cycle. In first T-state (T1), 8085

processor places 16- bit address on address bus and issues ALE signal. And also it makes IO/M’ signal to low, indicating it is memory related operation.

In second T-state (T2), processor places data to be written on data bus and asserts WR’ signal to the memory.

In the third T-state (T3), memory stores the data and processor de-asserts WR’ signal.

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4.IO read machine cycle: This machine cycle is required, when data needs to be read from an input device. This machine cycle requires three T-states. The following are the sequence of actions performed by processor during this machine cycle.

In the first T-state (T1) 8085 places port address(for IO mapped addresses port address is 8-bit, but for memory mapped addresses IO device address is 16-bit, but reading from such is performed by memory read machine cycle) on address bus and issues ALE signal. And also IO/M’ signal is made high, since it is IO related operation. In the second T-state (T2),

processor issues RD’ control signal to IO peripheral. In response to this input device places data on data bus.

In the third T-state (T3), processor reads data from data bus, and de-asserts RD’ signal.

5. IO write Machine cycle:

This machine cycle is required when data needs to be output to an output device. This machine cycle requires three T-states. The following are the sequence of actions performed by processor during this machine cycle. In first T-state (T1), 8085 processor

places 8-bit port address on address bus (for IO mapped addresses port address is 8-bit, but for memory mapped addresses, IO device address is 16-bit, but writing to such is performed by memory write machine cycle) and issues ALE signal. And also it makes IO/M’ signal to high, indicating it is IO related operation.

In second T-state (T2), processor places data to be written on data bus and asserts WR’ signal to the peripheral.

In the third T-state (T3), peripheral accepts the data and processor de-asserts WR’ signal.

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1.6. Addressing Modes of 8085 Microprocessor:

Addressing modes define the way operands are specified in the instruction.

In 8085 Microprocessor there are four addressing modes.

1. Immediate addressing mode

2. Register addressing mode

3. Direct addressing mode

4. Indirect addressing mode

5. Implied/Implicit addressing mode

1. Immediate addressing mode:

In this operand is specified in the instruction itself./ An immediate is transferred

directly to the register.

Example: MVI A, 30H (30H is copied into the register A)

MVI B,40H(40H is copied into the register B).

2. Register addressing mode:

In this addressing mode operand is stored in a register. And that register is

specified in the instruction./ Data is copied from one register to another register.

Example: MOV B, A (the content of A is copied into the register B)

MOV A, C (the content of C is copied into the register A).

3. Direct addressing mode:

Operand is stored in the memory. The address of operand is specified in the

instruction./ Data is directly copied from the given address to the register.

Example:LDA 3000H (The content at the location 3000H is copied to the register

A).

4. Indirect addressing mode:

Operand is stored in the memory. The address of operand is held in a register and

the register is specified in the instruction./ The data is transferred from the

address pointed by the data in a register to other register.

Example: LXI H,1020H

MOV A,M ; indirect addressing mode

Here M points to(contains) address 1020H, At his address operand is stored.

By executing this instruction, the content of 1020H is loaded into accumulator A.

5. Implied Addressing Mode

This mode doesn't require any operand. The data is specified by opcode itself.

Example: - CMP

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1.7 Instruction Set of 8085 Microprocessor:- An instruction is a binary pattern designed inside a microprocessor to perform a

specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. These instructions can be classified into the following five functional categories:

1. Data Transfer (Copy) Operations, 2. Arithmetic Operations, 3. Logical Operations, 4. Branching Operations, 5. Machine-Control Operations.

1. Data transfer instructions:

This group of instructions copy data from a location called a source to another location called a destination, without modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. However, the term transfer is misleading; it creates the impression that the contents of the source are destroyed when, in fact, the contents are retained without any modification. The various types of data transfer (copy) are listed below together with examples of each type:

S.No Type Example

1 Between Registers. Copy the contents of the register B into register D.

2 Specific data byte to a register or a Memory location.

Loads register B with the data byte 32H.

3 Between a memory location and a Register.

From a memory location 2000H to register B.

4 Between an I/O device and the Accumulator.

From an input keyboard to the accumulator.

The various types of data transfer (copy) are listed below together with examples of each type: 1. Move immediate

MVI Rd, data -Transfers 'data' value into register Rd. Ex: MVI A,50H

2. Move instruction

MOV Rd,Rs -Here Rd is destination register, Rs is source register. Transfers data in Rs into Rd. Rs content will not be changed. Ex: MOV B,A

3.IN instruction

IN port_address -This instructions reads data from IO device connected at specified port address and loads accumulator with that data. Ex: IN 10H

4.OUT instruction OUT port_address -This instruction sends content of accumulator to IO device connected at specified port address. Ex: OUT 05H

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5.LXI instruction

LXI Rp,data -This instruction loads 16-bit immediate data into specified register pair(Rp) LXI B,16-bit data ; loads BC with 16-bit data LXI D, 16-bit data; loads DE with 16-bit data LXI H,16-bit data; loads HL with 16-bit data LXI SP, 16-bit data; loads stack pointer with immediate data Ex: LXI H,2050H LXI SP,1090H

6.LDAX instruction-Load accumulator indirect LDAX B/D This instruction loads Accumulator with memory location pointed by content of B or D LDAX B; loads accumulator with content of memory location pointed by BC pair LDAX D; loads accumulator with content of memory location pointed by DE pair

7.LDA instruction-Load accumulator direct LDA 16-bit address This instruction loads accumulator with the content of memory location specified in the instruction. Ex: LDA 2005H -This instruction loads accumulator with content of [2005H]

8.STAX instruction-Store accumulator indirect STAX B/D -This instruction stores the content of accumulator into memory location pointed by B or D register pair. Example: STAX B; stores accumulator content in memory location pointed by BC pair

STAX D; stores accumulator content in memory location pointed by DE pair 9.STA instruction-Store accumulator direct

STA 16-bit address -This instruction stores accumulator content in 16-bit address location specified in the instruction Ex: STA 1020H; stores accumulator content in 1020H address

2. Arithmetic Instructions 1.ADD instruction-Addition instruction

ADD R; A=A+R ADD M; A=A+[HL] This instruction performs addition of content of specified register or memory location pointed by register pair HL and stores the result in accumulator Ex: ADD B; A=A+B

2.ADI instruction- Add immediate data ADI data This instruction adds 8-bit “data” to accumulator and places the result in accumulator

3.SUB instruction – subtract SUB R; A=A-R SUB M; A=A-[HL] This instruction subtracts content of register R or content of memory location pointed by HL register pair from accumulator and stores the result in accumulator.

4. SUI instruction- subtract immediate data SUI data This instruction subtracts 8-bit “data” from accumulator and stores the result in accumulator

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5.INR instruction- increments 8-bit data INR R; increments register R content by 1. INR M; increments content of memory location pointed by HL register pair by 1 This instruction operates on 8-bit data

6.DCR instruction- decrements 8-bit data DCR R; decrements register R content by 1 DCR M; decrements content of memory location pointed by HL register pair by 1 This instruction operates on 8-bit data

7.INX instruction- increments 16-bit data INX Rp; increments register pair Rp INX B; increments register pair BC INX D; increments register pair DE INX H; increments register pair HL INX SP; increments stack pointer SP by 1 This instruction increments 16-bit data by 1

8.DCX instruction- decrements 16-bit data DCX Rp; decrements register pair Rp DCX B; decrements register pair BC DCX D; decrements register pair DE DCX H; decrements register pair HL DCX SP; decrements stack pointer SP by 1 This instruction decrements 16-bit data by 1

3. Logical instructions These instructions perform various logical operations with the contents of the

accumulator. Flags affected: After performing these instructions carry flag will reset(except CMA) and sign, zero, parity flags are affected and these flags status depends on the result present in accumulator. 1.ANA instruction-logical And with accumulator

ANA R -This instructions performs bit wise AND operation between content of specified register and the accumulator and stores the result in accumulator.

2.ANI instruction-logical AND immediate data with accumulator ANI 8-bit data -This instruction performs bit wise AND operation between 8-bit immediate data and accumulator content and stores the result in accumulator

3.ORA instruction-logical OR with accumulator ORA R -This instruction performs bit wise OR operation between content of accumulator and specified register and stores result in accumulator.

4.ORI instruction-logical OR with immediate data ORI 8-bit data -This instruction performs bit wise OR operation between content of accumulator and 8-bit immediate data specified in the instruction and stores the result in accumulator.

5.XRA instruction-logical exclusive OR operation with accumulator XRA R -This instruction performs bit wise exclusive OR operation between content of accumulator and specified register in the instruction and stores the result in accumulator.

6.XRI instruction-Logical exclusive OR with 8-bit data XRI 8-bit data -This instruction performs bit wise logical exclusive OR between immediate data and accumulator and stores the result in accumulator.

7.CMA instruction-complement accumulator This instruction performs bit wise inversion of content of accumulator and result will be stored in accumulator.

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8.RLC instruction-rotate accumulator left This instruction rotates left the content of accumulator by one bit. The MSB of accumulator is shifted out and copied into LSB. Copy of MSB is kept in carry flag also.

9.RAL instruction-rotate accumulator left through carry

This instruction rotates left the content of accumulator along with carry by one bit. This instruction shifts the MSB of accumulator out and copies it into carry flag and content of carry flag is stored in LSB.

10.RRC instruction- rotate accumulator right

This instruction rotates the content of accumulator right by one bit. This instruction shifts the LSB of accumulator out and copies that into MSB. Copy of LSB is also stored in the carry flag

11.RAR instruction- rotate accumulator right through carry

This instruction rotates the content of accumulator through carry right by one bit. This instruction shifts the LSB of accumulator out and copies it into carry and content of carry is stored in the MSB.

12.CMP instruction- compare with accumulator

CMP R ; compare the content of specified register R with accumulator CMP M ; compare content of memory location pointed by HL register pair with accumulator. Depending on the content of R or M carry flag and zero flag are affected. This in turn subtracts content of R/M from accumulator but result is not stored anywhere, only flags are affected ACC < R/M – CY flag is set, Z flag is reset ACC = R/M - CY flag is reset, Z flag is set ACC > R/M – CY is reset, Z flag is reset

13.CPI instruction- compare immediate data with accumulator CPI 8-bit data This instruction compares 8-bit data with the content of accumulator( this in turn subtracts 8-bit data from accumulator but result is not stored any where, only flags are affected). Depending on the content Carry flag and Zero flag are affected. ACC < 8-bit data – CY flag is set, Z flag is reset ACC = 8-bit data - CY flag is reset, Z flag is set ACC > 8-bit data – CY is reset, Z flag is reset

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4. Branch and Stack related instructions Branch operations:

Unconditional branch JMP 16-bit This instruction causes PC to load with the 16-bit address specified in the instruction unconditionally. So the Processor jumps for executing from the address location specified in the instruction.

Conditional jump instructions:

This instructions jumps to the specified location in the instruction depending on the certain conditions indicated by flags. Except AC(auxiliary carry) remaining flags are used for decision making in these conditional branch instructions

1. JC 16-bit ; jump if carry(if CY=1) 2. JNC 16-bit ; jump if no carry(if CY=0) 3. JZ 16-bit ;jump if zero(if Z=1) 4. JNZ 16-bit ; jump if no zero(if Z=0) 5. JP 16-bit ; jump if positive(if S=0) 6. JM 16-bit ; jump if minus(if S=1) 7. JPE 16-bit ; jump on even parity(if P=1) 8. JPO 16-bit ; jump on odd parity(if P=0)

Unconditional CALL instruction: Subroutines can be implemented using CALL instruction. Subroutines are a way for code reuse. When it is required to perform certain operations more frequently then those operations can be written as a subroutine. Whenever those operations are required simply call the subroutine.

CALL 16-bit This instruction causes processor to start executing from the specified location in the instruction. When this instruction is executed processor stores the PC content on the stack and decrements the stack pointer by 2. It loads PC with 16-bit address specified in the instruction.

Unconditional RET instruction: This instruction is used to return from the subroutine. When this instruction is executed by the processor it copies the top of stack into PC and increments the stack pointer by 2.

Conditional CALL instruction: This instruction calls the subroutine depending on the certain conditions indicated by flags.

CC – call subroutine if CY=1(Call if carry) CNC – call subroutine if CY=0(call if no carry) CZ – call subroutine if Z=1(call if zero) CNZ – call subroutine if Z=0(call if no zero) CM – call subroutine if S=1(call if minus) CP – call subroutine if S=0(call if plus) CPE – call subroutine if P=1(call if even parity) CPO – call subroutine if P=0(call if odd parity)

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Conditional RET instruction: This instruction returns from the subroutine depending certain conditions indicated by flags.

RC – return if CY=1(Return on carry) RNC – return if CY=0(return on no carry) RZ – return if Z=0(return on zero) RNZ - return if Z=1(return on no zero) RM – return if S=1(return on minus) RP – return if S=0(return on plus) RPE – return if P=1(return on even parity) RPO – return if P=0(return on odd parity)

Restart instructions: RST n These instructions are like software interrupts to 8085. When these instructions are executed processor vectors(jumps) to a specific location called restart location. The following list gives restart location for different RST instructions. 'n' value -- Vector location RST 0 -- 0000H RST 1 -- 0008H RST 2 -- 0010H RST 3 -- 0018H RST 4 -- 0020H RST 5 -- 0028H RST 6 -- 0030H RST 7 -- 0038H

To get the vector location 'n' value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 3 instruction, multiply 3*8=24. 24 in hexadecimal notation is 18H. So vector address is 0018H.

Stack related instructions: PUSH instruction:

PUSH Rp This instruction stores the content of register pair Rp(16-bit) into stack. Stack is Last in first out data structure. Example: PUSH B; push BC pair on to stack PUSH D; push DE pair on to stack PUSH H; push HL pair on to stack PUSH PSW; push PSW(Accumulator+Flag register) on to stack

When this instruction is executed by the processor first it decrements SP by 1

and stores higher byte of the specified register pair, Then it again decrements SP by 1 and stores lower byte of the specified register pair. SP always points to top of stack. 8085 Maintains a stack which grows downwards .i.e. Higher address to lower address. And SP points to already stored location.

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POP instruction:

POP Rp This instruction is used to retrieve data from stack. i.e. Is 16-bit data from top of stack is stored in the specified register pair. Example:

POP B; store data from top of stack in BC pair POP D; store data from top of stack in DE pair POP H; store data from top of stack in HL pair POP PSW; store data from top of stack in Accumulator and Flag register

When this instruction is executed by the processor, it copies a byte from top of stack into lower byte of register pair and increments SP by 1, Then it again copies a byte from top of stack into higher byte of the register pair specified in the instruction and increments SP by 1.

5. Machine-Control Operations. HLT instruction – Halt

When this instruction is executed by the processor it stops executing

and enters into wait state. Address and data bus of the processor are

kept in high impedance state.

NOP instruction – No operation

This instructions performs nothing except wasting processor time. This

instruction is used for writing delays.

EI instruction- Enable interrupts

This instruction is used to enable the interrupts

DI instruction- disable interrupts

This instruction is used to disable the interrupts

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1.8 Interrupts In 8085 Microprocessor An interrupt is a signal or condition that causes processor to stop its normal execution

flow and makes it to jump to some other location for processing the interrupt. Interrupt is a mechanism by which an I/O or an instruction can suspend the normal

execution of processor and get itself serviced. Generally, a particular task is assigned to that interrupt signal. In the microprocessor based system the interrupts are used for data transfer between the peripheral devices and the microprocessor.

8085 has 5 external interrupts. In this 4 are vectored interrupts and 1 is non-vectored interrupt. RST 5.5, RST 6.5, RST 7.5, TRAP are vectored interrupts. INTR is non-vectored interrupt. TRAP is a non mask able interrupt.

Interrupt Service Routine(ISR) A small program or a routine that when executed services the corresponding

interrupting source is called as an ISR.

Maskable/Non-Maskable Interrupt An interrupt that can be disabled by writing some instruction is known as

Maskable Interrupt otherwise it is called Non-Maskable Interrupt.

There are 6 pins available in 8085 for interrupt: 1. TRAP 2. RST 7.5 3. RST6.5 4. RST5.5 5. INTR 6. INTA

8085 interrupt response process: Interrupts should be enabled by using EI instruction, then only processor responds to all

mask able interrupts. When microprocessor is executing a program, it checks for INTR line during

execution of each instruction. If INTR is high then processor completes executing the current instruction, disables

the interrupts and sends a INTA signal INTA is used by the external hardware to specify the restart instruction to processor(

since INTR is a non-vectored interrupt). When microprocessor receives the RST instruction, it saves PC content on stack and

PC is loaded with the vector address. Microprocessor executes the instructions at vector address. The interrupts should be enabled if required in the ISR(interrupt service routine) At the end of interrupt service routine, RET instruction loads the PC from the stack.

So processor comes back to the instruction where it was interrupted previously. Interrupt Priority: When more than one interrupts occur at the same time, then processor responds to them according to the following priority

TRAP(highest) RST 7.5 RST 6.5 RST 5.5 INTR (lowest)