Track h tools for improving design productivity - altera

© 2011 Altera Corporation—Public© 2011 Altera Corporation—© 2011 Altera Corporation—Public May 4, 2011 1

Tools for Improving design productivity

Elhanan Sharon Embedded Technology Specialist

ALTERA Department


Agenda

FPGA Design challenges Improving Productivity – What it Means? Introduction to QSys – ALTERA System Integration tool

© 2011 Altera Corporation—Public© 2011 Altera Corporation—© 2011 Altera Corporation—Public May 4, 2011 3May 4, 2011 3

System Design Challenges with FPGAs

Time

Number of system componentsin an FPGA

Number of system components in an FPGA

Time spent on system integration

• Increasing FPGA density• Growing FPGA I/O capabilities• FPGA becoming the heart

of the system

• The time spent integratingeach additional componentincreases exponentially


Productivity Challenge for FPGA Designers

Spend significant amount of time on system integration Core competency is innovation and product differentiation

InnovationProduct differentiation

System integration


Improving Productivity - What It Means ?

Do more with less—more complex products with same or less resources

Reuse across projects—avoid obsolescence Reuse across locations Lower risk—avoid “throw-away”

- Reduce risk of design errors- Reduce risk of market changes- Reduce risk of schedule slips

Allow customers to focus on their value-added core competencies


Tools to Improve Customer Productivity

As FPGAs move to the heart of the system, design software plays a key role in defining customer productivity

ALTERA Design Suite software tools leads the industry in several important areas

- Compilation time- Timing analysis and Timing closure- Power optimization and Power closure - Team-based design methodology- System-level design tools- System Integration tools


Introduction to Qsys:System Integration Made Easy


Why Use System Integration Tools like Qsys?

Simplifies complex system development Provides a standard platform supporting many IP cores Enables design re-use Raises the level of abstraction Allows developers to focus on “value add” instead of glue

logic and system interconnect Scales easily to meet the needs of the end product Reduces time to market

- Reduces design development time- Less error-prone- Eases verification


Qsys Foundation: SOPC Builder

SOPC Builder’s track record- Enjoyed ~10 years of success- Used by 10,000+ users worldwide

Trends in customer requirements:- Higher system bandwidth and increasing usage of high-

performance IP cores- Growing system size requiring very scalable development tool- Shorter time to market and limited resources demanding a system

re-use flow


System

Qsys Raises the Level of Design Abstraction

Schematic Entry Tool

SOPC Builder Tool

Qsys System Integration Tool

SoC Integration• Design a system with systems• System re-use• System verification

IP Integration• Design a system with IP cores• IP re-use• IP verification

Design Block Integration

Higher Abstraction and Improved Productivity Level

Low Medium High

Block

Block

Block

Block

IPIP

IP IP

SystemSystem

System System


Qsys: Moving To The Next Level

=

• High performance interconnect• Hierarchy• Industry-standard interfaces• IP management capabilities• Real-time system debug

AMBA AXI, AHB, ASP, …

OCP OCP

OC Wishbone

Avalon® interfaces

Industry-standard Interfaces

High Performance Interconnect

Based on Network-on-chip Architecture

Hierarchy

IP Management

DesignSystem

Add toLibrary

(Design Reuse)

Package as IP

Real-time System Debug

SOPCBuilder

+


Qsys Features

High performance: New interconnect based on network-on-chip architecture

Scalable systems: Hierarchical system design

Industry-standard interfaces: Connect IP cores of different interfaces together (Avalon, AXI, AHB, etc.)

Design re-use: IP management capabilities

Faster board bring-up: Real-time system debug


Easy-to-Use System Integration UI

IP 1IP 2

IP 3System 1System 2

Connect IP and systems

Design at a Higher Level of Abstraction byIntegrating IPs and Systems

Library ofavailable IP

• Interface protocols

• Memory• DSP• Embedded• Bridges• PLL• Your Systems


low

med

high

off

High Performance Interconnect

SOPC Builder

Qsys

System Interconnect Fabric

Manual Pipelining Manual Pipelining

Higher Performance

Qsys Interconnect(Based on Network-on-chip

Architecture)


SOPC Builder

Qsys

High Efficiency Interconnect

Master32

Wid

th A

dap

tor

Slave128

Master32

Slave128

Wid

th A

dap

tor

Burst count = 8

Burst Count = 8 Burst Count = 1

Burst Count = 1

Bur

st A

dapt

or

Bur

st A

dapt

or

Bandwidth Available for Other Masters

25% Efficiency at Slave

100% Efficiency at Slave

Higher Efficiency = Higher Throughput


Network-on-Chip (NoC) Architecture Packet transactions and transport

- Each command encapsulated in a packet to be sent to a slave- Each response encapsulated in a packet to be sent back to a master

MasterNetworkInterface

MasterNetworkInterface

Avalon-STAvalon-MM Avalon-MM

MasterInterface

MasterInterface

Avalon STNetwork

(Response)

Avalon STNetwork

(Command)

SlaveNetworkInterface

SlaveNetworkInterface

SlaveInterface

SlaveInterface

Transaction Layer Transport Layer Transaction Layer


Scalable System Design: Hierarchy

SOPC Builder

Impacts on large systems: • GUI response• System management

QsysSub-system 1

Sub-system 2

Sub-system 3

Qsys advantage: hierarchy support• Fewer components = fast GUI• Fewer components = manageable• Enables system to scale


Industry-standard Interfaces Mix industry-standard interfaces together

Developer Standard Interface Protocol

AHB, AXI, ASP, APB, ATB

OCP

Wishbone

Avalon interfaces

Qsys: Avalon (10.1), AXI (2011)

AXI

OCP

Avalon

OCP

AXI

Avalon

Master 1

Master 2

Master 3

Slave 1

Slave 2

Slave 3

Qsys Interconnect

P

A

C

K

E

T

P

A

C

K

E

T

P

A

C

K

E

T

P

A

C

K

E

T

P

A

C

K

E

T

P

A

C

K

E

T

AMBA

OCP

OC


Qsys enables re-use of IP and systems with IP management capabilities

Design Re-use

Package as IP• System Top• IP GUI wizardAdd to Library

Qsys

Project A

Top

Project B

Top

Project C

Top

Top Top


Faster Board Bring-up

Access the system in real time by sending read/write transactions through a bridge IP

CB D

BridgeIP

A

• JTAG Bridge IP• SPI Bridge IP• TCP/IP Bridge IP

View Datain Real Time

Read/Write Transactions

FPGA Design

Faster Board Bring-up with Real-TimeSystem Debug


Vision: Target Qsys Applications

Qsys can be used in every FPGA design Control plane

- Reading and writing to control status registers Data plane

- Data switching (muxing, demuxing), aggregation, bridges


Summary

Qsys increases design productivity through automated interconnect generation

- Faster design cycles- Less design errors- Easier verification- Shorter time to market

Qsys new features include:- High performance interconnect with pipelined Network-On-Chip

architecture- Scalable system design with hierarchy support- Broad IP portfolio availability with industry-standard interfaces- Design re-use with IP management capabilites- Faster board bring-up with real-time debug capabilities

Education

Track h tools for improving design productivity - altera