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Notes: Verilog Part 4 Prepared By: Jay Baxi

Notes: Verilog Part 4

7 CHAPTER 7:

7.1 STRUCTURED PROCEDURES:

7.1.1 initial statement

An initial block starts at time 0 and executes only once.

If there are more than one initial blocks, they all begin at the

same time (“0”). Each block independently finishes its

execution. They must be grouped between begin and end.

They are mainly used for initialization, monitoring waveforms

and other processes that do not require simulation for more

than one time.

There are various short hand syntaxes.

For example, when variables are declared they can be initialized.

The combined port/data declaration can also be combined with

an initialization.

They can be initialized while declaring them in the port

declaration of the module statement.

INITIAL

7.1.2 always statement

For programming level always works as infinite loop, but for

hardware designers this can be used as continuous activity from

the power on.

This can be used to generate the clock generator.

ALWAYS

7.2 PROCEDURAL ASSIGNMENTS The Syntax for the procedural assignment is as follows

assignment ::= variable_lvalue = [ delay_or_event_control ]

expression

The difference between the assignment here and that in

dataflow is that in dataflow, the value of LHS operand changes

immediately with the change in the RHS value, whereas in this

case, the value of the LHS operand does not change until

another procedural assignment is observed.

7.2.1 Blocking Assignment

Blocking assignments are executed in the order in which they

are assigned. They follow sequential flow.

The ‘=’ operator indicates sequential blocking.

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In the Blocking Assignment Example following things are to be

noted.

All statements x = 0 through reg_b = reg_a are executed

sequentially at time = 0.

The statements reg_a[2] = 0 at time = 15.

The statement reg_b[15:13] = {x,y,z} at time = 25.

Statement count = count + 1 at time = 25 is executed last

because of delays of 15 and 10 time units in the preceding

statements .

Note that if the RHS as more bits as compared to the LHS, the

RHS is truncated to match the width of the LHS, the MSBs are

truncated and LSBs are kept as it is. However, if they have RHS

has fewer bits, zeroes are filled in the vacant places.

7.2.2 Non-Blocking Assignment:

Nonblocking assignments allow scheduling of assignments

without blocking the execution of the statements in the

sequential block.

‘<=’ operator indicated Nonblocking assignment

In the nonblocking assignment example, following things should

be noted.

All statements x = 0 through reg_b = reg_a are executed

sequentially at time = 0.

The statements reg_a[2] = 0 at time = 15.

The statement reg_b[15:13] = {x,y,z} at time = 10.

Statement count = count + 1 at time = 0 (without any delay) is

executed last despite of delays of 15 and 10 time units in the

preceding statements.

The nonblocking assingments are used to eliminate the race

condition and in order to understand that, we illustrate the

example of SWAP.

7.3 TIMING CONTROLS

7.3.1 Delay Based Timing Control.

It is an expression that specifies the time duration between

when the statement is encountered and executed. There are

three different types of Delay based timing control.

1.) Regular Delay Control

2.) Intra-Assignment Delay Control

3.) Zero Delay Control

7.3.2 Event-Based Timing Control

An event is the change in the value of a register or a net. Events

can be used to trigger the execution of a statement or a block of

statements. There are four types of event based timing control

1.) Regular Event Control

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2.) Named Event Control: Verilog provides the capability to

declare an event and recognize the occurrence of the event.

The event cannot hold any data.

A named event can be declared using the keyword event.

The event is triggered by the symbol -> and recognized by ‘@’

3.) Event OR Control (Use of @(*) Operator)

4.) Level-Sensitive Timing Control:

Verilog provides ability to wait for certain condition to be true in

order for a block of statement to be executed.

The keyword used is wait.

always

wait (count_enable) #20 count = count + 1;

In the above example, the value of count_enable is continuously

monitored. If it is 0, the statement is not entered. If it is logical

1, the value of count is incremented after 20 time units.

7.4 CONDITIONAL STATEMENTS: The conditional statements are nothing but same as if..else as

observed in the C language.

//Type 1:

if (condition) true_statement;

//Type 2:

if(condition) true_statement; else false_statement;

//Type 3:

if(condition1) true_statement1;

else if (condition2) true_statement2;

else if (conditionN) true_statementN;

else false_statement;

7.5 MULTIWAY BRANCHING: The nested if-else-if becomes cumbersome if there are too

many alternatives. Hence, case comes to the rescue.

case, default and endcase are the commonly used keywords for

the case syntax.

case(condition)

alternative1: statement1;

alternative2: statement2;

alternative3: statement3;

alternativeN: statementN;

default: default_statement;

endcase

The case syntax is self-explanatory.

It compares 0,1,x or z values in the expression bit by bit.

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7.5.1 casex, casez keywords

casez treats all the z valyes in the case alternatives as don’t

cares. All bit positions with z can also be represented by ? in that

postion.

casex treats all x and z values in the case as don’t cares.

7.6 LOOPS

7.6.1 For and While Loops

The use of while and for loop in Verilog is same as that in C

language.

The while loop continues until the condition in the while

statement is not true.

For loops provides a more compact loops structure, the

initialization and increment assignment is included in the for

loop.

While Loop

For Loop

7.6.2 Repeat Loop

The keyword repeat is used in a repeat loop.

This loop iterates a statement for a fixed number of times. It

cannot be used to iterate a general logical expression.

A repeat construct must contain a number, which can be a

variable, constant or a value. However, if the number is a

constant or a signal value, it is evaluated only when the loop

starts and not during the loop execution.

Repeat Loop

7.6.3 Forever Loop

The keyword forever is used to express this loop.

The loops does not contain any expression and executes forever

until $finish is encountered.

This loop is equivalent to a while loop which always has a true

condition.

The loop can be disables by the use of disable statement.

This is generally used in conjunction with timing constructs, if

they are not the loop runs for infinite amount of time and no

further simulation will happen.

Forever Loop

7.7 SEQUENTIAL BLOCK AND PARALLEL BLOCKS

7.7.1 Types of Blocks

7.7.1.1 Sequential Blocks

They keywords begin and end are used to group sentences into

sequential block.

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They are processed in the order they are specified.

If a delay or event control is specified, it is relative to the

simulation time when the previous statement in the block

completed the execution.

7.7.1.2 Parallel Blocks

They are specified by keywords fork and join.

The statements are processed concurrently.

Ordering of the statements is controlled by delay or event

control assigned to each statement.

If delay or even control is assigned it is relative to time the block

was entered.

RACE CONDITION:

Race condition comes into picture when two statements that

use same variables are executed at the same time.

In simulation time, all fork-join statements are executed at once.

Different simulators execute statements in different order. Thus

the race condition is a limitation in today’s simulators.

7.7.2 Features

NESTING: A sequential and parallel blocks can be nested in the

same program.

NAMED BLOCKS: Blocks can be given names

local variables can be declared for the named block.

Named blocks are a part of design hierarchy.

They can be disabled.

DISABLING NAMED BLOCKS: The disable keyword is used to

terminate the execution of a named block.

It is used to handle error conditions, get out of the loop or

control execution of the pieces of code, based on control signal.

It is similar to break in C. The difference is break just comes out

of the loop, whereas disable can disable the entire block.

7.8 GENERATE Generate statements allow Verilog code to be generated

dynamically before the simulation time begins.

This is particularly useful when same operation is to be

performed for multiple bits of vector.

All the instructions are coded within generate – endgenerate

keywords.

Generated instantiations are one or more of the following types

Modules

User Defined Primitives

Verilog Gate Primitives

Continuous Assignments

initial and always blocks.

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Various data types allowed in a generate statement to support

interconnections between structural elements and/or

procedural blocks.

net, reg

integer, real, time, realtime,

event

Tasks and Functions are allowed within a Generate Scope, but

not in a generate loop.

Some module declarations and module items are not permitted

in a generate statement are

parameter, local parameter

input, output and inout declarations

specify blocks.

There are three methods to create generate statements:

7.8.1 Generate Loop

A generate loop allows one or more of the aforementioned to

be instantiated multiple times using a FOR loop.

Generate Loop.

In the above example, before the actual simulation, the code is

elaborated to create a flat representation without the generate

block. The elaborated code is simulated.

Thus generate blocks are a simply a convenient way of replacing

multiple repetitive Verilog blocks.

genvar is a keyword to declare a variable that is used only to

evaluate the generate block.

Its value can be defined only by the generate loop.

Two generate loops can be nested, provided they have different

genvars.

7.8.2 Generate Conditional

A generate conditional is just like an if-else-if.

Parameterized Multiplier.

7.8.3 Generate Case

A generate case is just like a case statement

N-bit Adder

7.9 EXAMPLES: 4-Bit Counter

Traffic Signal Controller