By StudentsArchana College of Engineering

Pandalam

Consists of 8 bit-bytes. Any 3 consecutive bytes fi\orm a word. Addresses are byte addresses. Words are addressed by the location of

their lowest numbered byte. total :: 32,768 bytes

INTERGER:stored as 24 bit bibary no:s (-)ve nos: 2’s complement represention. Characters :stored using 8-bit ASCII

code. No floating point no:

24 bit format8bit 1bit 15bit opcode x address

Instructions:LOAD & STORE REG Integer arithematic

operations :ADD,SUB,MUL,DIV Instruction (COMP):compare the value in

register A & word in m/y. Contain conditional codes.

Performed by transfering 1 byte at a time or from the rightmost 8 bits of reg A.

Each device is assigned a unique 8 bit code.

Contain 3 I/O instructions: TD(Test Device) WD(Write Data) RD(Read Data)

Memory Registers Data formats Instruction Formats Addressing modes Instruction Set Input and Output

Memory structure is same as that of SIC.

Maximum memory available is 1 megabyte

Additional registers provided by SIC/XE are:

Mnemonic Number

Special use

B 3 Base register , used for addressing

S 4 General working register_no special use

T 5 General working register_no special use

F 6 Floating-point accumulator(48 bits)

• SIC/XE provides the same data formats as SIC• There is an additional 48 bit floating point

data type • Floating point data format is:

o The fraction is interpreted as a value between 0 and 1

o Exponent is interpreted as an unsigned binary number between 0 and 2047

o Sign of the number is indicated by the value of s(0=positive,1=negative)

s exponent fraction

1 11 36

• Because of the large memory address will no longer fit into 15 bit field

• The new set of instruction formats is as follows:

I. Format 1(1 byte):

II.Format 2(2 byte):

III.Format 3(3bytes):

IV.Format 4(4 byte):

opcode8

opcode r1 r2

8 4 4r1 and r2 are operands

opcode

n i x b p e disp

6 1 11 11 1 12

opcode

n i x b p e address

6 1 1 1 1 1 1 20

Two new relative addressing modes are available for use with instructions assembled using Format 3:

Mode Indication Target address calculation

Base relative b=1,p=0 TA=(B)+disp

Program –counter relative

b=0,p=1 TA=(PC)+disp

SIC/XE provides all of the instructions that are available on the standard version

There are instructions to load and store new registers-LDB,STB ,etc

Floating point arithmetic instructions are: ADDF,SUBF,MULF,DIVF,etc

A special supervisor call instruction( SVC) is provided to communicate with the operating system

I/O instructions are similar to that of SIC There are I/O channels that can be used

to perform I/O while the CPU is executing other instructions

This improves system performance The instructions SIO ,TIO , and HIO are

used to start ,test , and halt the operations of I/O channels

Introduced by Digital Equipment Corporation in 1978

VAX architecture was designed for

compatibility with the earlier PDP-11

VAX memory consist of 8 bit bytes All addresses used are byte addresses Two consecutive bytes form a word Four bytes form a longword Eight bytes form a quadword Sixteen bytes form an octaword All VAX programs operate in a virtual

address space One half of VAX virtual address space is

called system space Other half of the address space is called

process space

There are 16 general purpose registers on VAX , denoted by R0 to R15

All general registers are 32 bits in length

Register Function

R15 Program Counter (PC)

Updated during instruction execution to point to the next instruction to be fetched

R14 Stack Pointer(SP)

Points to the current top of the stack in the program’s process space

R13 Frame Pointer(FP)

VAX procedure call conventions build a data structure called s stack frame and place its address in FP

R12 Argument Pointer(AP)

The procedure call convention uses AP to pass a list of arguments associated with the call

R6-R11 No special function

Available for general use

R0-R5 General use Used by some machine instructions

Integers are stored as binary numbers in byte , word, longword, quadword, or octaword

Negative values are represented using 2’s complement representation

Characters are stored using their 8-bit ASCII codes Four different floating point data formats on the

VAX VAX processors provide packed decimal data

format Each byte represent two decimal digits Sign is encoded in last 4 bits There is a numerical format for numerical values

Variable length instruction format

Instruction consist of opcode and operand specifiers

Operand specifiers designates addressing modes and gives additional information to locate the operand

Large number of addressing modes

Addressing mode

Register mode Operand itself may be a register

Register differed mode Operand address is in register

Auto increment mode Increment register count

Auto decrement mode Decrement register count

Base relative mode TA=(B)+disp

Program counter relative mode

TA=(PC)+disp

Indirect addressing mode TA=value contained in a word

Many instruction mnemonics are formed by combining the following elements

I. A prefix that specifies the type of operation

II. A suffix that specifies the data type of the operation

III. A modifier that gives the number of operands involved

o Provides instruction to computation, data movement ,conversion , comparison ,and branching

o There are complex instructions

I/O is accomplished by I/O device controller

Device controller has set of control and data registers

Address space of registers is called I/O space

No special instruction is required to access I/O space

•Introduced at the end of 1995•Latest X86 family

•Used in majority of PC

Memory are described into 2 different ways At physical level memory consist of 8bits/byte 2byte-word 4byte-double word Programmer view memory- collection of

segment Address *segment number * offset

Segments are of different size & have different purposes

Segments are divided into pages Some of pages are stored in physical

memory & other are stored in disk At the time of execution the bytes is

loaded into physical memory

8 general purpose register EAX, EBX, ECX, EDX, ESI, EDI, EBP,ESP Size 32 bit long EAX,EBX, ECX,EDX –data manipulation Other registers are used to store both data &

address Special purpose register *EIP-32 bit long -> contain pointer to the next instruction

to be executed

* FLAG-32 bit long -> contain many different flag bits.16bit segment register used to locateSegments in memory-> segment register contain CS-address of currently executed code SS-address of current stack segment DS-used to indicate data segment ES-used to indicate data segment FS-used to indicate data segment GS-used to indicate data segment. 80bitdata register &several control & status

register

Provides data storage for integer, floating point, char, string

2’s complement for negative numbers Integer are represent 8,16,32bit binary

numbers Integer is stored in BCD

Unpacked BCD

Each byte-1decimal digit

The value of this digit is encoded in low order 4bit of byte

Higher order bit are normally zero

Packed BCD

Each byte represent 2decimal digit

Each digit is encoded in 4bit of byte

3different floating point data formatSingle precision*32 bit long*24 bit-floating point value*7 bit-exponents*remaining bit sign of floating point valueDouble precision*64 bit long*53-significant bit*10-exponent

Extended precision* 80 bit long*64 –significant bit*15-exponent• Character represent ASCII code

Use variations of same basic format Format begin with optional prefix Following prefix is an opcode Following opcodes are number of bytes

Immediate addressing Register modeTA=(base register)+(index

register)*(scale factor)+displacement

-> base register-general purpose register-> index register-general purpose register

except ESP

Scale factor-1,2,4,8 Displacement-8bit, 16bit, 32bit Direct mode-address of an operand be

specified as an absolute value Relative mode-address of an operand is

specified as a location relative to EIP register

Contain large & complex instruction More than 400different machine register Register to register instruction Register to memory instruction Memory to memory instruction Data movement instruction Integer arithmetic instruction

String manipulation instruction deals with bytes, word, double word

Use instruction to do operation in HLPL Contain instruction that perform-> logical operation-> bit manipulation-> support control of processor-> memory management

Input I/O port EAX register Output Register I/O port Prefix allows instruction to transfer to an

entire string in a single operation

The Ultra SPARC processor introduced by Sun Microsystems in 1995.The name SPARC stands for scalable processor architecture.This architecture is implemented from microcomputers to supercomputers.SPARC ,Super SPARC, and Ultra SPARC.

Memory Registers Data Formats Instruction Formats Addressing Modes Instruction Set Input and Output

8 bits-bytes 2 consecutive bytes-half word 4 bytes-1 word 8 bytes-double word Half word stored in multiple of 2. Word stored in multiple of 4. Double word stored in multiple of 8. The virtual address space – 2^64 bytes. Virtual address space is divided into pages. Program is stored in pages. At the time of execution program containing

pages is loaded into physical memory. Virtual address is translated into physical address

by the Memory Management Unit (MMU).

Contain more than 100 general -purpose registers. Program can access 32 registers(r0-r31). First 8 are global(r0-r7),accessed by all procedures on

the system.(r0 –> always ‘zero’). SPARC – general purpose register 32 bit long. Ultra SPARC – general purpose register 64 bit long. Floating-point computations – handled by floating

point unit(FPU). Floating-point unit contains – floating-point registers

and control & status registers. Besides these register files, there are:- :- program counter(pc) :- control registers :- condition code registers

Provides strong for integers, floating-point value, and characters.

Integers are stored as 8,16,32 or 64 bit binary numbers.

2’S complement:- Negative values. Support “ big-endian” & “little-endian”. 3 different floating-point data formats. single precision 32 bit long ;23 bit significant bits(floating-point

values);8 bit exponent ; remaining-sign of floating-point ;char –ASCII Code.

Double presision 64 bit long;52 bit significant bit ; 11 bit exponent. Quad precision 63 significant bit ; 15 bit exponent.

3 basic instruction formats. 32 bit long First 2 bit – identify format of instruction->format 1:-call instruction->format 2:-branch instruction->format 3:-register load & store Fixed length arithmetic – similar to RISC Intended to speed up fetching and decoding.

Immediate mode Register mode Operand in memory are addressed by :-Mode TA->PC-relative TA=(pc)

+displacement->Register indirect TA=(register)

+displacement With displacement->Register indirect TA=(register-

1)+(register-2) Indexed

Load and store instruction access memory. All other are register-to-register operation. Instruction execution is pipelined. To make pipeline efficient SPARC branch

instruction are “delayed branches”. Example: SUB %L0, 11, %L1 BA NEXT MOV %L1, %O3 Instruction immediately following the branch is

executed before the branch is taken MOV is executed before the branch BA MOV is said to be “delay slot”. Also include special purpose instruction to provide

support to ‘OS’ and compilers.

I/O communication is done through memory. Each i/o device has a unique identification(ID). A range of memory location is logically replaced

by device register. Load and store instruction refers to a device

register ,the particular device is activated. i/o is performed with register instruction set . No special i/o instruction is needed.

*introduced by IBM

*POWER-Performance Optimization With Enhanced RISC

*powerful & low cost microprocessor

Memory Register Data format Instruction format Addressing mode Instruction set Input output

* 8bit – byte* 2byte – half word* 4byte – 1word• 8byte – double word• 16byte – quad word• Virtual address space -2^64 byte• Address space is divided into fixed length

segment (256 byte long)• Segments are divided into pages (4096 byte

long)• For execution load pages into physical memory• Convert virtual address into physical address

32 general purpose register GPR 0-GPR 31 Each register is 64 bit long GPR is used & to store & manipulate

integer data & address Floating point computation performed

by floating point units Floating point units contain 64 bit

floating point register & status & control register

Conditional register – 32 bit long

Sub divided into eight 4bit subfield, CR 0-CR 7

Power PC contain linkage register (LR) & counter register (CR)

LR & CR are used by branch instruction Power PC also contain machine status

register (MSR) control register , status register

Provide storage for integers ,floating point value ,characters

Integers is represented as 8,16,32,64 bit binary numbers

2 different floating point format Single precision 32 bit long32 bit long 23 bit significant value (store floating 23 bit significant value (store floating

point value)point value)

8 bit exponent value Remaining bit represent sign of floating point

value Double precision 64 bit long 52 bit significant value (store floating point

value) 11 bit-exponent Character as 8bit ASCII code

7 basic instruction format 32 bit long First 6 bit specify the opcode. Same instruction have “extended

opcode” field Fixed length instruction-decoding-

simple&faster

Immediate mode Register mode Memory is accessed by load , store &

branch instruction

Mode

Register indirect Register indirect

with index Register indirect

with immediate mode

T A

TA=(register) TA=(register-1)+

(register-2) TA=(register)

+displacement

Mode

Absolute Relative

Linkage register Count register

TA

TA=actual address TA=current

instruction address + displacement

TA=(LR) TA=(CR)

Contain machine instruction Floating point “multiply & add” take 3

input & perform * and + in single step Can use powerful instruction So faster instruction are needed to

perform task Instruction are pipelined “delayed branch” techniques are not

used

2 methods for performing in the I/O operation

Segments are mapped to I/O bus A refers to an address that is pot in

direct store segment represent virtual memory address

Use virtual memory management hardware & software