io-esd

I/O & ESD Design

Byron Krauter, IBMMark McDermott

Outline

I/O Signaling Requirements Basic CMOS I/O and Receiver Design Real-world CMOS I/O and Receiver Design

– Impedance Matching & Slew Rate Control– Mixed Voltages– ESD and other extreme conditions

Increasing Bandwidth– Source Synchronous I/O or Co-transmitted Clock– Pipelined Bus or Bus Pumping– Dual Data Rate– Simultaneous Bi-Directional– Pattern Based Driver Compensation

Transmission Lines

204/13/23

I/O Signaling

There are basically two forms of signaling used for input/output applications– Single Ended– Differential

In single-ended signaling one wire carries a varying voltage that represents the signal, while the other wire is connected to a reference voltage, usually ground. – Single ended signaling is less expensive to implement than differential, but

its main limitations are that it lacks the ability to reject noise caused by differences in ground voltage level between transmitting and receiving circuits.

Differential signaling uses two complementary signals sent on two separate wires. – Able to reject common-mode noise– More expensive to implement from both a wire perspective as well as the

transmit & receive logic.

304/13/23

Single Ended vs. Differential Signaling

Single Ended

Differential

404/13/23

Single-ended Bus Signaling Standards

504/13/23

Courtesy Mike Morrow, UW

Differential Bus Signaling Standards

604/13/23

Courtesy Mike Morrow, UW

Complications

Pin Count Limitations – Bi-directional signaling– Simultaneous switching noise

Transmission Line Behavior– Limited net topologies work– Terminations required– Skin effect– Dielectric loss

Other Noises– Reflections – Discontinuity noise– Crosstalk and connector noise

Mixed Voltages ESD and Other Handling Complications

704/13/23

Basic CMOS I/O and Receiver Design

Bidirectional CMOS I/O Buffer

data

enable_b Pad

0 1

0

1data

enable

Hi Z

Hi Z0

1

904/13/23

CMOS Input Receiver

Any two input gate that– Has good noise immunity– Provides on-chip control when off-chip inputs float

Example: two input NAND

0 1

0

1data

enable

X

11

1 0

X1

data

enablePad

out

1004/13/23

Real-world CMOS I/O Design

Real-world CMOS I/O Design

Output Impedance Control Slew Rate Control Mixed Voltage Designs

– Input Design for Higher Voltages– Output Design for Higher Voltages

• Dual Power Supplies• Floating Well Designs• Open Source Signaling

Other Circuits– Differential I/O Circuits– Hysteresis Receivers

ESD Circuits

1204/13/23

Output Impedance Control

Device “resistances” are too variable for source termination– Devices are non-linear – Variations due to VDD, Temp, and process variations alone are >2X in linear

region!

Output stages must be designed to reduce this variation– On-chip resistors designs – Logically tunable designs

04/13/23

Impedance Control Using On-Chip Resistors

Given a precise on-chip resistor, this design provides the best impedance control

data

enable_b

Pad

1404/13/23

Tunable Impedance Control

Stacked device settings can be preset or dynamically controlled

n1 n2 n3

data

enable_b Pad

p3p2p1

1504/13/23

Slew Rate Control

Output stage slew rate is controlled to reduce noise– Cross talk noise– Simultaneous switching noise– Reflections at discontinuities

Slew rate control is accomplished by controlling the pre-driver delay and/or pre-driver strength

1604/13/23

Output stage is divided and pre-drive signal is designed to sequentially arrive at the different sections

Slew Rate Control

data

enable_b Pad

1704/13/23

Slew Rate Control & Impedance Control

Pre-driver design might even permit crossover currents to guarantee impedance even during switching

data

enable_b Pad

04/13/23

Feedback Slew Rate Control I/O Buffer

data

enable_b

Pad

1904/13/23

Feedback Slew Rate Control I/O Buffer (Patents)

2004/13/23

Mixed Voltage Designs

Needed when chips have different supply voltages Low voltage circuits can be damaged by high voltage inputs High voltage circuits suffer delay & noise problems when receiving

low voltage signals

VDD_1

newer technology

VDD_2Bi-directionalI/O Buffers

older technology

VDD_1 < VDD_2

04/13/23

Input Design for Higher Voltages

Modifications for gate oxide & ESD protection

ESD Diodes

Pad

ESD Diodes

Pad

Receiving Same Level Receiving Higher Level

change beta ratio

04/13/23

Dual Supply Designs

Separately power I/O circuits at a lower voltage– No additional process steps required– Extra design to avoid performance penalty – ESD & simultaneous switching noise compromised

VDD_1

newer technology

VDD_2Bi-directionalI/O Buffers

older technology

VDD_1

04/13/23

Output Stage at a Lower Voltage

Slow rising delay due to low overdrive on PMOS Reduced drive = reduced noise immunity on NAND receiver

ESD Diodes

data

inhibit

Vdd1

Pad

Vdd1 or Vdd2

enable_b

Vdd2

2404/13/23

Output Stage at a Lower Voltage

Improve rising delay with NMOS pull up Change p/n beta ratio on NAND to lower switch point

ESD Diodes

data

Inhibit_b

1.2 Volts

Pad

1.2 or 1.8 Volts

enable_b

1.8 Volts

change beta ratio

2504/13/23

Dual Supply Designs

Separately power the I/O circuits at a higher voltage– More complicated circuits– ESD & simultaneous switching noise compromised

1.8 Volts

older technology

1.2 Volts Bi-directionalI/O Buffers

newer technology

1.8 Volts

2604/13/23

Output Stage at a Higher Voltage

Slow rising delay due to low overdrive on PMOS Reduced drive = reduced noise immunity on NAND receiver

04/13/23

data

enable_b

Vdd1

Pad

Vdd2

Vdd2

Vdd1

LevelShifter

Vbias

Floating Well Designs

Enabled output stage outputs a lower voltage -> Vdd1 Disabled output stage tolerates higher voltage -> Vdd2

04/13/23

data

enablePad

Vdd1

Vdd1

Vdd1

Vdd1

Open Drain Signaling

Avoids complexity of multiple chip power supplies– Off-chip termination resistors pull net up– On-chip NMOS devices pull net down

Increases transmission line design complexity Wired OR functionality

CL CL CL CL

VttVtt

CL

Driving Chip

2904/13/23

Other Circuits

Differential I/O Circuits– Reduces simultaneous switching noise– Improves receiver common mode noise immunity– Receives smaller signal levels– “Pseudo” to full differential possible

Hysteresis Receivers– High noise immunity– Excellent for low-speed asynchronous test & control signals

Hold Clamps

3004/13/23

Differential Output Buffers

Pseudo Differential Outputs

Differential Outputs

out

out

out out

Vbias

VDD

3104/13/23

Differential Transmission Lines

Pseudo = two lines

Zo

ZoDifferential = coupled pair

coupled

Zeff < Zo

Zeff < Zo

3204/13/23

Differential Far End Termination

Pseudo Differential Termination

Vtt

R = Zo Vtt

R = ZoDifferential Termination

R = 2 Zo

3304/13/23

Differential Receivers

Pseudo Differential Receiver

Differential Receiver

out

out

out out

Vbias

VDD

3404/13/23

Self Biased Differential Receiver

Combines best of NMOS and PMOS differential receivers

out out

Nbias

VDD

out out

Pbias

VDD

3504/13/23

Self Biased Differential Receiver

Combines best of NMOS and PMOS differential receivers– Rail to rail output swing– Excellent common mode noise rejection

out

VDD

(Bazes, JSSC 91)

or reference

3604/13/23

Hysteresis Input Receivers

Separates rising & fall edge dc transfer curves

inhibit

Pad

weak feedback inverter

Vin

Vout

Vout

Vin

risingfalling

AND only

Pad Vin Vout

3704/13/23

Hold Clamps

Weak clamps hold tri-stated source terminated nets

Stronger clamps will actively terminate the net– Can be slower than passive termination schemes

Padweak feedback inverter

VDD

I/O

3804/13/23

ESD Design

Pins subjected to ESD (electrostatic discharge) events during test & handling

Over-voltages can also occur during functional operation– System power-on– Hot-plugging

ESD discharge can occur between any two pins – I/O to I/O– I/O to VDD or Gnd

Pins are measured against standard ESD tests– Human body model– Machine model– Charged Device Model

ESD performance depends on many parameters other circuits don’t care about

3904/13/23

ESD Circuits

Non-breakdown based circuits– Diodes– Bipolar Junction Transistor– MOSFET

Breakdown based circuits– Thick Field Oxide Device – SCR (silicon controlled rectifier)

04/13/23

Dual Diode ESD Circuits

ESD Diodes

Pad

ESD Diodes

Pad

Single Supply Design Mixed voltage design

4104/13/23

FET ESD Circuits: non-breakdown mode

ESD Diodes

Pad

NMOS in “diode”configuration

4204/13/23

FET ESD Circuits: breakdown mode

ESD Diodes

Pad

NMOS protectsby clamping voltage

after device snapback V

I

snapback

secondbreakdown

Vgs > Vt

4304/13/23

Diode ESD Circuits

FET devices are parasitic npn & pnp bipolar circuits

ESD Diodes

Pad

ESD bipolar devices

Pad

• vertical pnp device to substrate

• horizontal npn device to guard rings (before trench isolation)

• low vdd to gnd impedance to due on-chip capacitance provide additional discharge paths

4404/13/23

Parasitic Bipolar Circuits

FET devices are parasitic npn & pnp bipolar circuits

04/13/23

• vertical pnp device to substrate

ESD Test Models

Human Body Model – Requirements 2 - 4 kVolts– Positive or negative discharge between any two pins

04/13/23

VHBM DUT

C = 100 pF

R = 1.5 K

i(t)

timet = 2-10 nsec

ipeak = VHBM/1500

ESD Test Models

Machine Model– Requirements 200 - 400 Volts– Positive or negative discharge between any two pins

04/13/23

VMM DUT

C = 200 pF

R < 8.5

L = 0.5 - 0.75 H

ESD Performance Factors

Diode symmetry is important– Bipolar conduction increases with temperature– Hot spots conduct more, heat up more, conduct more, … and finally burn

out Layout corners are rounded to reduce electric fields Decoupling capacitance needed between all supplies Functional performance requirements impose ESD size & load

capacitance constraints Parasitic bipolar effects abound Breakdown clamps don’t scale Virtual supply node needed for multi-VDD designs

04/13/23

Increasing Bandwidth

04/13/23

Common Clock Transfers

Chip to chip transfers controlled by common bus clock Equal length card routes to each chip & on-chip PLL’s minimize

clock skew

clocksource

PLL

Chip A

PLL Chip B

5004/13/23

Common Clock Transfers

clocksource

PLL

Chip A

PLL

Chip BTclk - A

TtofTdrive

TAclk

Tclk - B

TBclk

Treceive Tsetup

max(Tclk - A+TAclk +Tdrive+ Ttof+ Treceive + Tsetup ) - min(TBclk - Tclk - B) < Tcycle

Cycle time to meet setup time

5104/13/23

Source Synchronous I/O

Send source clock with source data Resolve clock phase differences with 1, 2, & 3

clocksource

PLL

Chip A

PLL

Chip B

3

21

5204/13/23

Bus Pumping

With Ttof > Tcycle, multiple bits are present on the wire

clocksource

PLL

Chip A

PLL

Chip B

3

21

5304/13/23

Dual Data Rate

Conventional source synchronous design– Data launched & captured on single clock edge – Clock switches at f– Maximium data rate = 1/2 * f

Dual data rate - if clock can switch at f, why not data?– Data is launched & captured on both clock edges – Clock switches f– Maximum data rate = f

Conventional Dual Data Rate

Data

Clock

5404/13/23

Simultaneous Bidirectional Signaling

Two chips send & receive data simultaneously on a point to point net

Waveforms superimpose on the transmission line Each chip selects it’s receiver reference voltage based on the data

it sent Sending data is subtracted from total waveform

Chip A

3/4 VDD1/4 VDD

Chip B

3/4 VDD1/4 VDD

5504/13/23

Pattern Based Driver Compensation

Incident waveforms along a long-lossy lines attenuate Slow “RC” like response to final level

(1- e-R*length/2Zo)

1/2

Vs

Rs = Zo

f

wheref = length / velocity

With complex impedance and propagation constanthigh speed wavefront decays exponentially

5604/13/23

Pattern Based Driver Compensation

Adjust driver strength based on bits sent in earlier cycles Example: When driving low to high

– Drive harder if previous bits sent = 00– Drive weaker if previous bits sent = 10

1 0 0 1 0 0

Without Compensation

1 0 0 1 0 0

Drive harder

With Compensation

ReceiverSwitch Point

5704/13/23

Increasing Bandwidth

Preceding techniques cannot be achieved through clever circuit design alone

Requires good packaging technology & net design– Good termination– Minimal capacitive & inductive discontinuities– Low cross-talk– Low simultaneous switching noise

5804/13/23

Backup

Transmission Line Behavior

But First A Few Words onCommon Ground Interconnect Models

Example - Two Wires & One Source

Twin lead transmission line modeled as a single section and driven by a Thevenin source

0.5*Cwire0.5*Cwire

Rwire

Rwire

Rsource

L22

L11

M12

6204/13/23

Example - Two Wires & One Source

Being concerned with local potentials only (i.e. capacitor potentials) inductances and resistances can be combined

0.5*Cwire0.5*Cwire

Rwire RwireRsource L22L11

M12

0.5*Cwire0.5*Cwire 2*Rwire

Rsource L11+ L22 - 2*M12

6304/13/23

Example - Three Wires & Two Sources

When multiple wires form a cutset, treat one wire as a reference lead and fold it into the other wires*.

* Brian Young, “Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages”

Rg

Lgg

0.5*C1g

R1Rs1 L11

M1g

0.5*C2g

R2Rs2 L22

M2g

0.5*C12

0.5*C12

0.5*C1g

0.5*C2g

M12

Cutset

6404/13/23

Example - Three Wires & Two Sources

Resulting loop impedance model for three parallel wires driven by two Thevenin sources

0.5*C12

0.5*C2g

0.5*C1g

R1+RgRs1L11+Lgg-2M1g

0.5*C12

M12-M1g-M2g+Lgg

i2Rg

R2+RgRs2L22+Lgg-2M1g

0.5*C1g

i1Rg

0.5*C1g

v1

v2

mutual resistances

6504/13/23


On and off chip signals can always be modeled with lumped RLC circuits

Wire segments are modeled with or t segments

L, R, C, and G can be frequency dependent

But inductance is not always important

6604/13/23


Inductance is important when– Driver source impedance Rs is low

Rs < Zo where Zo = characteristic impedance of line

– Driver rise time r is fast

r < 2.5 f

wheref = time of flight

– Line loss is lowR << jL or (R / 2Zo) << 1

Can be restated for point to point nets asRsCtot < 1/2 RlineCline < f

Wave frontdecays exponentially

with this constant

6704/13/23

When Inductance is Important

Nets ring and net delays become unpredictable unless:– Net topologies are constrained

• Point to point nets• Periodically loaded nets • Near and far end clusters

– Nets are driven appropriately• Not to strong and not to weak• Not to fast and not to slow

– Nets are terminated appropriately• Source termination• Far end termination

– Resistance to VDD or Gnd or any Thevenin Voltage • AC termination = RC circuit• Active hold clamps• Diode or Schottky diode clamps

6804/13/23


Perfectly source terminated point to point, loss-less net

V(t)

Rs = Zof

time

far end

near end

Zo = LC

f = LC

f

6904/13/23


Under driven point to point, loss-less net

Rs = 3Zof Zo =

LC

f = LC

V(t)

time

far end

near end

ApproximatesRC step response

7004/13/23


Over driven point to point, loss-less net

Rs = 1/3 Zof Zo =

LC

f = LC

V(t)

time

far end

near end

7104/13/23

Reflection and Transmission

v = ZL - Zo

ZL+ Zo

v = 1, ZL=0, ZL= Zo

-1, ZL= 0{

v = 1 + v = 2ZL

ZL+ Zo

With incident wave Vinc traveling down the line

Voltage reflection coefficient

Voltage transmission coefficient

7204/13/23

Equivalent Circuits Along Line

Rs

ZoVs

near end

Zo2Vinc

Zo along line

ZL2Vinc

Zo far end

Vinc

+

-

Zdiscontinuity

7304/13/23

Discontinuities Along Line

C

L

Vs

Rs = Zo

Vs

Rs = Zo

Vs=11

1/21/2 (1- e-2t/ZoC)

Vs=11

1/21- 1/2(1- e-2Zot/L)

7404/13/23

Well Behaved Net Topologies

Point to Point Nets

Rs = Zof

Source terminated

Rs << Zof

Far end terminated

Rterm ZoVterm

04/13/23


Periodically Loaded Nets

Source terminated: Near end switches last

Rs = Zeff

CL CL CL CL

With periodic loadingZeff =

LC + nCL

f = L(C+nCL)

04/13/23


Periodically Loaded Nets

Far end terminated: Near end switches first

Rs << Zeff

CL CL CL CL

With periodic loadingZeff =

LC + nCL

f = L(C+nCL)

Rterm Zeff

Vterm

04/13/23


Near end (or Star) cluster

Rs = Zo/N

04/13/23


Far-end cluster

Rs = Zo/N Zo/N

04/13/23


Double far-end terminated bus

CL CL CL CL

Vterm

Rs << Zo

Vterm

CL

04/13/23

Ideal Transmission Lines

=Z = L

C LC

I(z)

V(z)

t

iL

z

Vt

VC

z

i

2

2

2

2

t

VLC

z

V

Steady State Solution:

])VV[1

(ReI

]VV[ReV

)()(

)()(

ee

eetzjtzj

tzjtzj

Z

where

IdealTelegrapher’s Equation

8104/13/23

Transmission Lines with Loss

j = (jL + R) jCZ() = jL + RjC

LC

(1 - j R/2L) (1 - j R/2L)jLC

02)(

Z

RLC

00 2

)(ZC

RjZZ

8204/13/23

Waveforms Along a Low Loss Line

(1- e-R*length/2Zo)

1

Vs

Rs << Zo

f


With complex impedance & complex propagation constanthigh speed wavefront decays exponentially & distorts

8304/13/23

Distortionless Transmission Line

j = (jL + R)(jC + G)Z() = jL + RjC + G

LC

( jRL) LC

Oliver Heaviside (1887)

LRCG //

8404/13/23

Waveforms Along a Distortionless Line

(1- e-R*length/Zo)

1

Vs

Rs << Zo

f


With real impedance and complex propagation constanthigh speed wavefront decays exponentially but without distortion

8504/13/23

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