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TERM PAPER
on
Integrated circuits
Submittedto
Amity School Of Engineering
SubmittedBy
Chundru Raga Sumanth BTech-EEEEEE2 EnrollA12424611007
Under the supervisionOf
Ms Rashmi swarnakar
(Asst Professor) ASET
Amity University Uttar Pradesh
ACKNOWLEDGMENT
Any work visible is not the effort of the presenter onlybut there are many others behind the camera and my report is not an exception to thisSoin process of recognizing the effort of those behind the scenewe would like to sincerely-thank the teachers of AMITY UNIVERSITY for sharing thier valuable views and time in completion of this project
Above all Iam highly grateful to Ms Rashmi Swarnkarwhose continuous motivationguidance and suggestions backed us in completing the project most productivelyFinallynot to forget the cooperation made by our classmate in providing any relevant data they came across
FROM-
Chundru Raga Sumanth
Btech-EEE
A12424611007
Declaration
I Chundru Raga Sumanth of Amity School of Engineering declare that the
work embedded in this term paper entitled Integrated Circuits It is an
authentic record of the work carried out by the author under the supervision of
Assistant Professor Ms Rashmi Swarnkar of Amity School Of Engineering
Noida The matter presented in this term paper is original and has not been
submitted in parts or in full for diploma or degree for this or any other
institution
Chundru Raga Sumanth
A12424611007
Certificate
This is to certify that MrChundru Raga Sumanth student of BTech in
Electrical and Electronics Engineering (2011-2015) has carried out the work
presented in the project of the Term paper entitle INTEGRATED
CIRCUITSrdquo as a part of First year programme of Bachelor of Technology in
2012 from Amity School of Engineering Amity University Noida Uttar
Pradesh under my supervision
Ms Rashmi Swarnakar
(AsstProfessor)
ASET
Amity University
Noida UP
INDEX
Srno Topic
1 INTEGRATE CIRCUITS
2 HISTORY
3 EVOLUTION OF MICROELECTRONICS
4 VACUUM-TUBE EQUIPMENT
5 SOLID-STATE DEVICES
6 PRINTED CIRCUIT BOARD
7 DIFFERENCE BETWEEN DISCRETE AND INTEGRATED CIRCUITS
8 RELIABILITY
9 CLASSIFICATION OF INTEGRATED CIRCUITS
10 GENERATIONS OF INTEGRATED CIRCUITS
11 MANFACTURING OF INTEGRATED CIRCUITS
12 ThE 555 TIMER
13 3-D INTEGRATED CIRCUITS
TERM PAPER ON INTEGRATED CIRCUITS
INTEGRATED CIRCUITS
An integrated circuit (IC) can be the equivalent of dozens hundreds or thousands of separate electronic parts
Digital ICs such as microprocessors can equal millions of parts Now digital and mixedsignal ICs are finding more applications in analog systems
A mixed-signal printed circuit board containing both analog and digital components
HISTORYThe integrated circuit was introduced in 1958
It has been called the most significant technological development of the twentieth century
Integrated circuits have allowed electronics to expand at an amazing rate Much of the growth has been in the area of digital electronics
Lately analog ICs have received more attention and the designation ldquomixed-signalrdquo is now applied to ICs that combine digital and analog functions
JACK KILBYrsquoS ORIGINAL INTEGRATED CIRCUITS
Kilby won the 2000 Nobel Prize in Physics for his part of the invention of the integrated circuit Evaluation of integrated circuithistory of integrated circuit
EVOLUTION OF MICROELECTRONICS
The earliest electronic circuits were fairly simple They were composed of a few tubes transformers resistors
capacitors and wiring As more was learned by designers they began to increase both the size
and complexity of circuits Component limitations were soon identified as this technology developed
VACUUM-TUBE EQUIPMENT
Vacuum tubes were found to have several built-in problems Although the tubes were lightweight
associated components and chassis were quite heavy It was not uncommon for such chassis to weigh 40 to 50 pounds In addition the tubes generated a lot of heat required a warm-up time from 1 to 2 minutes and required hefty power supply voltages of 300 volts dc and more
No two tubes of the same type were exactly alike in output characteristics Therefore designers were
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
ACKNOWLEDGMENT
Any work visible is not the effort of the presenter onlybut there are many others behind the camera and my report is not an exception to thisSoin process of recognizing the effort of those behind the scenewe would like to sincerely-thank the teachers of AMITY UNIVERSITY for sharing thier valuable views and time in completion of this project
Above all Iam highly grateful to Ms Rashmi Swarnkarwhose continuous motivationguidance and suggestions backed us in completing the project most productivelyFinallynot to forget the cooperation made by our classmate in providing any relevant data they came across
FROM-
Chundru Raga Sumanth
Btech-EEE
A12424611007
Declaration
I Chundru Raga Sumanth of Amity School of Engineering declare that the
work embedded in this term paper entitled Integrated Circuits It is an
authentic record of the work carried out by the author under the supervision of
Assistant Professor Ms Rashmi Swarnkar of Amity School Of Engineering
Noida The matter presented in this term paper is original and has not been
submitted in parts or in full for diploma or degree for this or any other
institution
Chundru Raga Sumanth
A12424611007
Certificate
This is to certify that MrChundru Raga Sumanth student of BTech in
Electrical and Electronics Engineering (2011-2015) has carried out the work
presented in the project of the Term paper entitle INTEGRATED
CIRCUITSrdquo as a part of First year programme of Bachelor of Technology in
2012 from Amity School of Engineering Amity University Noida Uttar
Pradesh under my supervision
Ms Rashmi Swarnakar
(AsstProfessor)
ASET
Amity University
Noida UP
INDEX
Srno Topic
1 INTEGRATE CIRCUITS
2 HISTORY
3 EVOLUTION OF MICROELECTRONICS
4 VACUUM-TUBE EQUIPMENT
5 SOLID-STATE DEVICES
6 PRINTED CIRCUIT BOARD
7 DIFFERENCE BETWEEN DISCRETE AND INTEGRATED CIRCUITS
8 RELIABILITY
9 CLASSIFICATION OF INTEGRATED CIRCUITS
10 GENERATIONS OF INTEGRATED CIRCUITS
11 MANFACTURING OF INTEGRATED CIRCUITS
12 ThE 555 TIMER
13 3-D INTEGRATED CIRCUITS
TERM PAPER ON INTEGRATED CIRCUITS
INTEGRATED CIRCUITS
An integrated circuit (IC) can be the equivalent of dozens hundreds or thousands of separate electronic parts
Digital ICs such as microprocessors can equal millions of parts Now digital and mixedsignal ICs are finding more applications in analog systems
A mixed-signal printed circuit board containing both analog and digital components
HISTORYThe integrated circuit was introduced in 1958
It has been called the most significant technological development of the twentieth century
Integrated circuits have allowed electronics to expand at an amazing rate Much of the growth has been in the area of digital electronics
Lately analog ICs have received more attention and the designation ldquomixed-signalrdquo is now applied to ICs that combine digital and analog functions
JACK KILBYrsquoS ORIGINAL INTEGRATED CIRCUITS
Kilby won the 2000 Nobel Prize in Physics for his part of the invention of the integrated circuit Evaluation of integrated circuithistory of integrated circuit
EVOLUTION OF MICROELECTRONICS
The earliest electronic circuits were fairly simple They were composed of a few tubes transformers resistors
capacitors and wiring As more was learned by designers they began to increase both the size
and complexity of circuits Component limitations were soon identified as this technology developed
VACUUM-TUBE EQUIPMENT
Vacuum tubes were found to have several built-in problems Although the tubes were lightweight
associated components and chassis were quite heavy It was not uncommon for such chassis to weigh 40 to 50 pounds In addition the tubes generated a lot of heat required a warm-up time from 1 to 2 minutes and required hefty power supply voltages of 300 volts dc and more
No two tubes of the same type were exactly alike in output characteristics Therefore designers were
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Declaration
I Chundru Raga Sumanth of Amity School of Engineering declare that the
work embedded in this term paper entitled Integrated Circuits It is an
authentic record of the work carried out by the author under the supervision of
Assistant Professor Ms Rashmi Swarnkar of Amity School Of Engineering
Noida The matter presented in this term paper is original and has not been
submitted in parts or in full for diploma or degree for this or any other
institution
Chundru Raga Sumanth
A12424611007
Certificate
This is to certify that MrChundru Raga Sumanth student of BTech in
Electrical and Electronics Engineering (2011-2015) has carried out the work
presented in the project of the Term paper entitle INTEGRATED
CIRCUITSrdquo as a part of First year programme of Bachelor of Technology in
2012 from Amity School of Engineering Amity University Noida Uttar
Pradesh under my supervision
Ms Rashmi Swarnakar
(AsstProfessor)
ASET
Amity University
Noida UP
INDEX
Srno Topic
1 INTEGRATE CIRCUITS
2 HISTORY
3 EVOLUTION OF MICROELECTRONICS
4 VACUUM-TUBE EQUIPMENT
5 SOLID-STATE DEVICES
6 PRINTED CIRCUIT BOARD
7 DIFFERENCE BETWEEN DISCRETE AND INTEGRATED CIRCUITS
8 RELIABILITY
9 CLASSIFICATION OF INTEGRATED CIRCUITS
10 GENERATIONS OF INTEGRATED CIRCUITS
11 MANFACTURING OF INTEGRATED CIRCUITS
12 ThE 555 TIMER
13 3-D INTEGRATED CIRCUITS
TERM PAPER ON INTEGRATED CIRCUITS
INTEGRATED CIRCUITS
An integrated circuit (IC) can be the equivalent of dozens hundreds or thousands of separate electronic parts
Digital ICs such as microprocessors can equal millions of parts Now digital and mixedsignal ICs are finding more applications in analog systems
A mixed-signal printed circuit board containing both analog and digital components
HISTORYThe integrated circuit was introduced in 1958
It has been called the most significant technological development of the twentieth century
Integrated circuits have allowed electronics to expand at an amazing rate Much of the growth has been in the area of digital electronics
Lately analog ICs have received more attention and the designation ldquomixed-signalrdquo is now applied to ICs that combine digital and analog functions
JACK KILBYrsquoS ORIGINAL INTEGRATED CIRCUITS
Kilby won the 2000 Nobel Prize in Physics for his part of the invention of the integrated circuit Evaluation of integrated circuithistory of integrated circuit
EVOLUTION OF MICROELECTRONICS
The earliest electronic circuits were fairly simple They were composed of a few tubes transformers resistors
capacitors and wiring As more was learned by designers they began to increase both the size
and complexity of circuits Component limitations were soon identified as this technology developed
VACUUM-TUBE EQUIPMENT
Vacuum tubes were found to have several built-in problems Although the tubes were lightweight
associated components and chassis were quite heavy It was not uncommon for such chassis to weigh 40 to 50 pounds In addition the tubes generated a lot of heat required a warm-up time from 1 to 2 minutes and required hefty power supply voltages of 300 volts dc and more
No two tubes of the same type were exactly alike in output characteristics Therefore designers were
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Certificate
This is to certify that MrChundru Raga Sumanth student of BTech in
Electrical and Electronics Engineering (2011-2015) has carried out the work
presented in the project of the Term paper entitle INTEGRATED
CIRCUITSrdquo as a part of First year programme of Bachelor of Technology in
2012 from Amity School of Engineering Amity University Noida Uttar
Pradesh under my supervision
Ms Rashmi Swarnakar
(AsstProfessor)
ASET
Amity University
Noida UP
INDEX
Srno Topic
1 INTEGRATE CIRCUITS
2 HISTORY
3 EVOLUTION OF MICROELECTRONICS
4 VACUUM-TUBE EQUIPMENT
5 SOLID-STATE DEVICES
6 PRINTED CIRCUIT BOARD
7 DIFFERENCE BETWEEN DISCRETE AND INTEGRATED CIRCUITS
8 RELIABILITY
9 CLASSIFICATION OF INTEGRATED CIRCUITS
10 GENERATIONS OF INTEGRATED CIRCUITS
11 MANFACTURING OF INTEGRATED CIRCUITS
12 ThE 555 TIMER
13 3-D INTEGRATED CIRCUITS
TERM PAPER ON INTEGRATED CIRCUITS
INTEGRATED CIRCUITS
An integrated circuit (IC) can be the equivalent of dozens hundreds or thousands of separate electronic parts
Digital ICs such as microprocessors can equal millions of parts Now digital and mixedsignal ICs are finding more applications in analog systems
A mixed-signal printed circuit board containing both analog and digital components
HISTORYThe integrated circuit was introduced in 1958
It has been called the most significant technological development of the twentieth century
Integrated circuits have allowed electronics to expand at an amazing rate Much of the growth has been in the area of digital electronics
Lately analog ICs have received more attention and the designation ldquomixed-signalrdquo is now applied to ICs that combine digital and analog functions
JACK KILBYrsquoS ORIGINAL INTEGRATED CIRCUITS
Kilby won the 2000 Nobel Prize in Physics for his part of the invention of the integrated circuit Evaluation of integrated circuithistory of integrated circuit
EVOLUTION OF MICROELECTRONICS
The earliest electronic circuits were fairly simple They were composed of a few tubes transformers resistors
capacitors and wiring As more was learned by designers they began to increase both the size
and complexity of circuits Component limitations were soon identified as this technology developed
VACUUM-TUBE EQUIPMENT
Vacuum tubes were found to have several built-in problems Although the tubes were lightweight
associated components and chassis were quite heavy It was not uncommon for such chassis to weigh 40 to 50 pounds In addition the tubes generated a lot of heat required a warm-up time from 1 to 2 minutes and required hefty power supply voltages of 300 volts dc and more
No two tubes of the same type were exactly alike in output characteristics Therefore designers were
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
INDEX
Srno Topic
1 INTEGRATE CIRCUITS
2 HISTORY
3 EVOLUTION OF MICROELECTRONICS
4 VACUUM-TUBE EQUIPMENT
5 SOLID-STATE DEVICES
6 PRINTED CIRCUIT BOARD
7 DIFFERENCE BETWEEN DISCRETE AND INTEGRATED CIRCUITS
8 RELIABILITY
9 CLASSIFICATION OF INTEGRATED CIRCUITS
10 GENERATIONS OF INTEGRATED CIRCUITS
11 MANFACTURING OF INTEGRATED CIRCUITS
12 ThE 555 TIMER
13 3-D INTEGRATED CIRCUITS
TERM PAPER ON INTEGRATED CIRCUITS
INTEGRATED CIRCUITS
An integrated circuit (IC) can be the equivalent of dozens hundreds or thousands of separate electronic parts
Digital ICs such as microprocessors can equal millions of parts Now digital and mixedsignal ICs are finding more applications in analog systems
A mixed-signal printed circuit board containing both analog and digital components
HISTORYThe integrated circuit was introduced in 1958
It has been called the most significant technological development of the twentieth century
Integrated circuits have allowed electronics to expand at an amazing rate Much of the growth has been in the area of digital electronics
Lately analog ICs have received more attention and the designation ldquomixed-signalrdquo is now applied to ICs that combine digital and analog functions
JACK KILBYrsquoS ORIGINAL INTEGRATED CIRCUITS
Kilby won the 2000 Nobel Prize in Physics for his part of the invention of the integrated circuit Evaluation of integrated circuithistory of integrated circuit
EVOLUTION OF MICROELECTRONICS
The earliest electronic circuits were fairly simple They were composed of a few tubes transformers resistors
capacitors and wiring As more was learned by designers they began to increase both the size
and complexity of circuits Component limitations were soon identified as this technology developed
VACUUM-TUBE EQUIPMENT
Vacuum tubes were found to have several built-in problems Although the tubes were lightweight
associated components and chassis were quite heavy It was not uncommon for such chassis to weigh 40 to 50 pounds In addition the tubes generated a lot of heat required a warm-up time from 1 to 2 minutes and required hefty power supply voltages of 300 volts dc and more
No two tubes of the same type were exactly alike in output characteristics Therefore designers were
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
TERM PAPER ON INTEGRATED CIRCUITS
INTEGRATED CIRCUITS
An integrated circuit (IC) can be the equivalent of dozens hundreds or thousands of separate electronic parts
Digital ICs such as microprocessors can equal millions of parts Now digital and mixedsignal ICs are finding more applications in analog systems
A mixed-signal printed circuit board containing both analog and digital components
HISTORYThe integrated circuit was introduced in 1958
It has been called the most significant technological development of the twentieth century
Integrated circuits have allowed electronics to expand at an amazing rate Much of the growth has been in the area of digital electronics
Lately analog ICs have received more attention and the designation ldquomixed-signalrdquo is now applied to ICs that combine digital and analog functions
JACK KILBYrsquoS ORIGINAL INTEGRATED CIRCUITS
Kilby won the 2000 Nobel Prize in Physics for his part of the invention of the integrated circuit Evaluation of integrated circuithistory of integrated circuit
EVOLUTION OF MICROELECTRONICS
The earliest electronic circuits were fairly simple They were composed of a few tubes transformers resistors
capacitors and wiring As more was learned by designers they began to increase both the size
and complexity of circuits Component limitations were soon identified as this technology developed
VACUUM-TUBE EQUIPMENT
Vacuum tubes were found to have several built-in problems Although the tubes were lightweight
associated components and chassis were quite heavy It was not uncommon for such chassis to weigh 40 to 50 pounds In addition the tubes generated a lot of heat required a warm-up time from 1 to 2 minutes and required hefty power supply voltages of 300 volts dc and more
No two tubes of the same type were exactly alike in output characteristics Therefore designers were
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
JACK KILBYrsquoS ORIGINAL INTEGRATED CIRCUITS
Kilby won the 2000 Nobel Prize in Physics for his part of the invention of the integrated circuit Evaluation of integrated circuithistory of integrated circuit
EVOLUTION OF MICROELECTRONICS
The earliest electronic circuits were fairly simple They were composed of a few tubes transformers resistors
capacitors and wiring As more was learned by designers they began to increase both the size
and complexity of circuits Component limitations were soon identified as this technology developed
VACUUM-TUBE EQUIPMENT
Vacuum tubes were found to have several built-in problems Although the tubes were lightweight
associated components and chassis were quite heavy It was not uncommon for such chassis to weigh 40 to 50 pounds In addition the tubes generated a lot of heat required a warm-up time from 1 to 2 minutes and required hefty power supply voltages of 300 volts dc and more
No two tubes of the same type were exactly alike in output characteristics Therefore designers were
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
required to produce circuits that could work with any tube of a particular type This meant that additional components were often required to tune the circuit to the output characteristics required for the tube used Figure 1-1 shows a typical vacuum-tube chassis The actual size of the transformer is approximately 4 times 4 times 3 inches Capacitors are approximately 1 times 3 inches The components in the figure are very large when compare to modern microelectronics
Typical vacuum tube circuit
A circuit could be designed either as a complete system or as a functional part of a larger system In
complex systems such as radar many separate circuits were needed to accomplish the desired tasks
Multiple-function tubes such as dual diodes dual triodes tetrodes and others helped considerably to
reduce the size of circuits However weight heat and power consumption continued to be problems that plagued designersAnother major problem with vacuum-tube circuits was the method of wiring components referred toas POINT-TO-POINT WIRING Figure 1-2 is an excellent example of point-to-point wiring Not only
did this wiring look like a rats nest but it often caused unwanted interactions between components For example it was not at all unusual to have inductive or capacitive effects between wires Also point-topoint wiring posed a safety hazard when troubleshooting was performed on energized circuits because of exposed wiring and test points Point-to-point wiring was usually repaired with general purpose test equipment and common hand tools
SOLID-STATE DEVICES
The transition from vacuum tubes to solid-state devices took place rapidly As new types of transistors and diodes were created they were adapted to circuits The reductions in size weight and power use were impressive Circuits that earlier weighed as much as 50 pounds were reduce in weight to just a few ounces by replacing bulky components with the much lighter solid-state devices The earliest solid-state circuits still relied on point-to-point wiring which caused many of the disadvantages mentioned earlier A metal chassis similar to the
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
type used with tubes was required to provide physical support for the components The solid-state chassis was still considerably smaller and lighter than the older tube chassis Still greater improvements in component mounting methods were yet to come One of the most significant developments in circuit packaging has been the PRINTED CIRCUIT BOARD (pcb) as shown in figure 1-3 The pcb is usually an epoxy board on which the circuit leads have been added by the PHOTOETCHING process This process is similar to photography in that copper-clad boards are exposed to controlled light in the desired circuit pattern and then etched to remove the unwanted copper This process leaves copper strips (LANDS) that are used to connect the components In general printed circuit boards eliminate both the heavy metal chassis and the point-to-point wiring
Printed circuit board (pcb)
Although printed circuit boards represent a major improvement over tube technology they are not
without fault For example the number of components on each board is limited by the sizes and shapes of components Also while vacuum tubes are easily removed for testing or replacement pcb components are soldered into place and are not as easily removed Normally each pcb contains a single circuit or a subassembly of a system All printed circuit boards within the system are routinely interconnected through CABLING HARNESSES (groups of wiring orribbons of wiring) You may be confronted with problems in faulty harness connections that affect system reliability Such problems are often caused by wiring errors because of the large numbers of wires in a harness and by damage to those wires and connectors
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Another mounting form that has been used to increase the number of components in a given space is the cord word module perpendicular to the end plates The components are packed very closely together appearing to be stacked like cordwood for a fireplace The end plates are usually small printed circuit boards but may beinsulators and solid wire as shown in the figure Cordwood modules may or may not be
ENCAPSULATED (totally imbedded in solid material) but in either case they are difficult to repair
DIFFERENCE BETWEEN DISCRETE CIRCUITS AND INTEGRATED CIRCUITS
Discrete circuits use individual resistors capacitors diodes transistors and other devices to achieve the circuit function These individual or discrete parts must be interconnected The usual approach is to use a circuit board This method however increases the cost of the circuit The board assembly soldering and testing all make up a part of the cost
Integrated circuits do not eliminate the need for circuit boards assembly soldering and testingHowever with ICs the number of discrete parts can be reduced This means that the circuitboards can be smaller often use less power and Integrated Circuits that they will cost less to produce It may also be possible to reduce the overall size of the equipment using integrated circuits which can reduce costs in the chassis and cabinet
RELIABILITY Integrated circuits may lead to circuits that require fewer alignment steps at the factory This is especially true with digital devices
Reliability is related indirectly to the number of parts in the equipment As the number of parts goes up the reliability comes down Integrated circuits make it possible to reduce the number of discrete parts in a piece of equipment Thus electronic equipment can be made more reliable by the use of more ICs and fewer discrete components
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
CLASSIFICATION OF INTEGRATED CIRCUITSINTEGRATED CIRCUITS CAN BE CLASSIFIED INTO THREE CATEGORIES
1) ANALOG IC
2) DIGITAL IC
3) MIXED SIGNAL(both analog and on digital on one chip)
ANALOG ICrsquoS
Analog ICs such as sensors power management circuits and operational amplifiers work by processing continuous signals They perform functions like amplification active filtering demodulation and mixing Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Kit to make a analog integrated circuit
DIGITAL ICrsquoS
Digital integrated circuits can contain anything from one to millions of logic gates flip-flops multiplexers and other circuits in a few square millimeters The small size of these circuits allows high speed low power dissipation and reduced manufacturing cost compared with board-level integration These digital ICs typically microprocessors DSPs and micro controllers work using binary mathematics to process one and zero signals
MIXED SIGNAL
ICs can also combine analog and digital circuits on a single chip to create functions such as AD converters and DA converters Such circuits offer smaller size and lower cost but must carefully account for signal interference
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
GENERATIONS OF INTEGRATED CIRCUITS
SMALL SCALE INTEGRATION The first integrated circuits contained only a few transistors Called small-scale integration (SSI) digital circuits containing transistors numbering in the tens provided a few logic gates
MEDIUM SCALE INTEGRATION
The next step in the development of integrated circuits taken in the late 1960s introduced devices which contained hundreds of transistors on each chip called medium-scale integration (MSI)
VERY LARGE SCALE INTEGRATION
The final step in the development process starting in the 1980s and continuing through the present was very large-scale integration (VLSI) The development started with hundreds of thousands of transistors in the early 1980s and continues beyond several billion transistors as of 2009
Manfacturing of integrated circuit
Fabrication
Placing over 1 million transistors on a piece ofsilicon the size of a fingertip is intricate work
The current precision is less than one micronwith one-tenth of a micron now being used A
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
micron is only about one-hundredth the diameter of a human hairThe fabrication process is applied to thinwafers of silicon There are eight basic stepsSome of these steps arerepeated many timesmaking the total number of steps one hundredor more The entire process usually takes from10 to 30 days The eight basic steps are
bull Deposition (forming an insulating layerof SiO2 on the silicon wafer)
bull Photolithography (light-sensitive layerexposed through a patterned photomask)
bull Etching (removal of patterned areas usingplasma gas or chemicals)
bull Doping (placing donor and acceptor impuritiesinto the wafer by diffusion or by using ion implantation)
bull Metallization (formation of interconnectsand connection pads by depositing metal)
bull Passivation (application of a protective layer)
bull Testing (probes check each circuit for proper electrical function)
bull Packaging (wafers are separated into chips the chips are mounted bonded wired and the packages are sealed) Sand is the base material for making the wafers It is melted purified and then melted again in a radio frequency (RF) furnace Figure
13-4 shows the molten silicon in a quartz crucible A seed crystal is lowered into the furnace until it touches the melt After a little of the molten silicon freezes around the seed
crystal the seed begins to rotate and is slowly retracted from the furnace A large single crystal of silicon forms as the silicon moves away from the melt and cools Pulled crystals are also called ingots Ingotsn are ground to a cylindrical shape and then sliced
into thin wafers with a diamond saw The wafers then ground flat and polished to a mirror finishn The polished wafers are sent on to the wafer fabrication area or clean room where temperature humidity and dust are all tightly controlled After a thorough cleaning the wafers are exposed to ultra pure oxygen to form a layer of silicon dioxide (SiO2) Next the wafers are coated with photoresist which is a material that hardens when exposed to light The exposure is
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
made through a photomask Each mask has a pattern that will be transferred to the wafer The unhardened areas of the photoresist caused by the opaque areas of the photomask wash away during the developing step The wafer is then etched to remove the silicon dioxide and expose the patterned areas of the substrate The exposed areas act as windows to allow penetration by impurity atoms The remains of the photoresist are removed with chemicals or plasma gas Figure 13-5 shows the major steps in this mostly photolithographic process The wafer is reoxidized and the photolithographic sequence is repeated from 8 to 20 times depending on the complexity of the IC being manufactured Thus photolithography is considered the core process in IC fabrication When the basic circuit has finally been completed the surface is passivated using a silicon nitride coating This coating acts as an insulator and also serves to protect the surface from damage and contamination
The wafer size back in 1971 was about 2 inches in diameter Now wafers as large as
12 inches in diameter are being processed This means that ICs are being manufactured in everincreasing batch sizes and thatrsquos one of the reasons costs are decreasing A large wafer will yield hundreds or thousands of individual chips (Figure 13-6 on page 390) Some of the individual chips might be defective Figure 13-7 on page 390 shows that needle sharp probes are used to electrically test each chip The defective ones are marked with a dot of ink for later disposal The wafer is cut apart with a diamond saw and the good circuits now called chips are mounted onto metal headers as shown in Figure13-8 on page 390 The chip pads and header tabs are connected with very fine wire Ball bonding or more likely ultrasonic bonding is used to make the connections The package is
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
then sealed Plastic packages are most
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
common and ceramic or metal packages a
been presented so far and more detail about transistor diode resistor and capacitor circuit
functions will now be offered Figure 13-9 shows one way to fabricate an NPN junction
transistor A P type substrate is shown An N_ layer is diffused into the substrate to form the
collector of the transistor N_ means that more than the average number of impurity atoms enter the crystal This is called heavy doping and it serves to lower the resistance of the collector An N layer is then formed over the substrateusing an epitaxial process Epitaxy is the controlled growth on a crystalline substrate of a crystalline layer called an epilayer The epilayer exactly duplicates the properties and crystal structure of the substrate The epilayer is oxidized and exposed through a photomask After developing a P type impurity such as boron is diffused into the windows until the substrate is reached This electrically isolates an entire region on the N type epilayer This is called the isolation diffusion and allows separate electrical functions to exist in a single layer Refer again to Fig 13-9 Again photolithography opens up a window and a P-type impurity can be diffused in to form the base of the transistor Later an N-type diffusion will form the emitter Polarity reversals by repeated diffusions would eventually saturate the crystal so their number is usually limited to three Since emitters are normally heavily doped in any case the process is designed so that the emitter diffusion is the last one The transistor has now been electrically isolated
and its three regions have been formed To be useful it must be connected Once again the wafer is oxidized and photolithography is used to open up windows as shown in Figure 13-10 on page 392 These expose the connection points for the emitter base and the collector Aluminum is evaporated and then deposited onto the surface of the wafer to make contact through the windows Photolithography is used to pattern the metal layer Etching removes the unwanted aluminum and Fig 13-10(c) and (d) shows what remains Complex ICs can have two or even three separate aluminum layers separated by dielectric layers While the transistors are being formed diodes are also being formed
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Figure 13-12 shows how a capacitor might be formed The N type region acts as one plate
an aluminum layer as the other and silicon dioxide serves as the insulator Another approach is to use a reverse-biased P-N junction as a capacitor Both methods are used
Figure 13-13 illustrates resistor formation Different values of resistance are realized by
controlling the size of the N channel and the level of doping Once again heavy doping produces less resistance An MOS transistor is shown in Figure 13-14 Notice the insulating (SiO2) layer between the gate and the channel MOS transistors take up less space than BJTs and are often preferred for that reason IC components have certain limitations when compared with discrete components
bull Resistor accuracy is limited However resistors in hybrid ICs can be laser trimmed to overcome this
bull Very low and very high resistor values are not practical
bull Inductors are usually not practical
bull Only small values of capacitance arepractical
bull PNP transistors tend to not perform as well as discrete types
The 555 Timer
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
The NE555 IC timer offers low cost and versatility
It is available in the 8-pin mini-DIP and in the miniature molded small outline package (MSOP)
The 555 provides stable time delays or free running oscillation The time-delay mode is RC-controlled by two external components
Timing from microseconds to hours is possible The oscillator mode requires three or more external components depending on the desired output waveform Frequencies from less than 1 Hz to 500 kHz with duty cycles from 1 to 99 percent can be attained
Advances in integrated circuits
Among the most advanced integrated circuits are the microprocessors or cores which control everything fromcomputers and cellular phones to digital microwave ovens Digital memory chips and ASICs are examples ofother families of integrated circuits that are important to the modern information society While the cost ofdesigning and developing a complex integrated circuit is quite high when spread across typically millions ofproduction
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
units the individual IC cost is minimized The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speedsICs have consistently migrated to smaller feature sizes over the years allowing more circuitry to be packed oneach chip This increased capacity per unit area can be used to decrease cost andor increase functionalitymdashsee Moores law which in its modern interpretation states that the number of transistors in an integrated circuitdoubles every two years In general as the feature size shrinks almost everything improvesmdashthe cost per unit and the switching power consumption go down and the speed goes up However ICs with nanometer-scaledevices are not without their problems principal among which is leakage current (see subthreshold leakage for adiscussion of this) although these problems are not insurmountable and will likely be solved or at leastameliorated by the introduction of high-k dielectrics Since these speed and power consumption gains areapparent to the end user there is fierce competition among the manufacturers to use finer geometries This process and the expected progress over the next few years is well described by the International Technology Roadmap for Semiconductors (ITRS)In current research projects integrated circuits are also developed for sensoric applications in medical implants or other bioelectronic devicesParticular sealing strategies have to be taken in such biogenic environments to avoid corrosion or biodegradation of the exposed semiconductormaterials[17] As one of the few materials well established in CMOS technology titaniumnitride (TiN) turned out as exceptionally stable and well suited for electrode applications in medical implants
Three-dimensional integrated circuit
From Wikipedia the free encyclopediaIn electronics a three-dimensional integrated circuit (3D IC 3D-IC or 3-D IC) is a chip in which two or morelayers of active electronic components are integrated both vertically and horizontally into a single circuit The semiconductor industry is pursuing this promising technology in many different forms but it is not yet widely usedconsequently the definition is still somewhat fluid
3D ICs vs 3D packaging
3D packaging saves space by stacking separate chips in a single package This packaging known as System inPackage (SiP) or Chip Stack MCM does not integrate the chips into a single circuit The chips in the packagecommunicate using off-chip signaling much as if they were mounted in separate packages on a normal circuit board In contrast a 3D IC is a single chip All components on the layers communicate using on-chip signaling whether vertically or horizontally A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Notable 3D chips
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory Due to the high demand for memory bandwidth a traditional IO approach would consume 10 to 25W[1] To improveupon that Intel designers implemented a TSV-based memory bus Each core is connected to one memory tile in theSRAM die with a link that provides 12 GBs bandwidth resulting in a total bandwidth of 1 TBs while consumingonly 22WIn 2004 Intel presented a 3D version of the Pentium 4 CPU[2] The chip was manufactured with two dies using faceto-face stacking which allowed a dense via structure Backside TSVs are used for IO and power supply For the 3D floorplan designers manually arranged functional blocks in each die aiming for power reduction and performanceimprovement Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspotsThe 3D design provides 15 performance improvement (due to eliminated pipeline stages) and 15 power saving(due to eliminated repeaters and reduced wiring) compared to the 2D PentiumAn academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students The chip runs at a 14 GHz and it was designed for optimized vertical processingbetween the stacked chips which gives the 3D processor abilities that the traditional one layered chip could notreach[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in
harmony without any obstacles that would interfere with a piece ofinformation traveling from one layer to another [4]In ISSCC 2012 two 3D-IC-based multi-core designs using GlobalFoundries 130 nm process and Tezzazons FaStack technology were presented and demonstrated 3D-MAPS[5] a 64 custom core implementation with twologic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology The second prototype was from the Department of Electrical Engineering andComputer Science at University of Michigan called Centip3De a near-threshold design based on ARM Cortex-M3
Types of integrated circuit packages
CBGA - Ceramic Ball GridArrayCCGA - Ceramic ColumnGrid ArrayCerDIP - Ceramic Dual-in-Line PackageCerPack - CeramicPackageCLCC - Ceramic LeadlessChip CarrierCPGA - Ceramic
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Pin GridArrayCQFP - Ceramic QuadFlat PackD2PAK or DDPAK - DoubleDecawatt PackageD3PAK - DecawattPackage 3DFN - Dual Flat No LeadsPackageDPAK - DecawattPackageFBGA - Fine-Pitch BallGrid ArrayJLCC - J-Leaded CeramicChip Carrie PQFP - Plastic Quad Flat Pack
PQFP - Plastic Quad FlatPackPSOP - Power SmallOutline PackageQFN - Quad Flat NoLeads PackageQSOP - Quarter SizeOutline PackageSBDIP - Sidebraze Dualin-Line PackageSC-70 - Small OutlineTransistorSIP - Single-In-LinePackageSOIC - Small Outline ICPackageSOJ - Small Outline JLead PackageSOT-23 - Small OutlineTransistorSPDIP - Shrink PlasticDual-in-Line PackageSSOP - Shrink SmallOutline PackageTDFN - Thin Dual Flat NoLeads Package
Moores law
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Constructing Gates
1048708 A transistor has three terminals
1048708 A source (feed with 5 volts)
+5 volts
1048708 A base
1048708 An emitter typically connected to
a ground wire
1048708 If the base signal is high (close to+5 volts) the source signal is grounded and the output signal is low (0) If the base signal is low(close to 0 volts) the source signalstays high and the output signal is high (1) It turns out that because the way a transistor works the easiest gates to
create are the NOT NAND and NOR gate
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
Vin vout v1 v2 vout v1 v2 vout
0 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
1 0 1 1 1 0
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
REFERENCES
1) Jacob Millmanrsquos
ldquoMillmans Integrated Electronicsrdquo
2) DRoy Choudhary
ldquoLinear Integrated Circuits
