ABSTRACT

Many image processing operations such as scaling and rotation require re-

sampling or convolution filtering for each pixel in the image. Convolutions on

digital images are important since they represent operations that are more general

than the operations that can be performed on analog images. Convolution has

many applications which have great significance in discrete signal processing. It is

usually difficult to deal with analog signals. Hence signals are converted to digital

state. Filtering of signals is very important in order to determine which one to

accept and which one to reject, and all of that is done by convolution.

This paper presents a direct method of reducing convolution processing

time using hardware computing and implementations of discrete linear

convolution of two finite length sequences (NXN). This implementation method is

realized by simplifying the convolution building blocks. The purpose of this

research is to prove the feasibility of an FPGA that performs a convolution on an

acquired image in real time.

The proposed implementation uses a modified hierarchical design

approach, which efficiently and accurately speeds up computation; reduces power,

hardware resources, and area significantly. The efficiency of the proposed

convolution circuit is tested by embedding it in a top level FPGA. In addition, the

presented circuit uses less power consumption and delay from input to output. It

also provides the necessary modularity, expandability, and regularity to form

different convolutions for any number of bits.

1

CHAPTER 1CHAPTER 1INTRODUCTION

1.1 INTRODUCTION

Convolution provides the mathematical framework for DSP. It is the single

most important technique in Digital Signal Processing. Convolution is a

mathematical way of combining two signals to form a third signal. Using the

strategy of impulse decomposition, systems are described by a signal called the

impulse response. In signal processing, the impulse response, or impulse response

function (IRF), of a dynamic system is its output when presented with a brief

input signal, called an impulse. More generally, an impulse response refers to the

reaction of any dynamic system in response to some external change. It has

applications that include statistics, computer vision, image and signal processing,

electrical engineering, and differential equations.

1.2 INTRODUCTION TO CONVOLUTION

One of the most important concepts in Fourier theory, and in

crystallography, is that of a convolution. Convolutions arise in many guises, as

will be shown below. Because of a mathematical property of the Fourier

transform, referred to as the convolution theorem, it is convenient to carry out

calculations involving convolutions.

1.2.1 Convolution Definition

The convolution of ƒ and g is written ƒ∗g, using an asterisk or star. It is

defined as the integral of the product of the two functions after one is reversed and

shifted. As such, it is a particular kind of integral transform:

2

 

     

While the symbol t is used above, it need not represent the time domain.

But in that context, the convolution formula can be described as a weighted

average of the function ƒ(τ) at the moment t where the weighting is given by g(−τ)

simply shifted by amount t. As t changes, the weighting function emphasizes

different parts of the input function.

More generally, if f and g are complex-valued functions on Rd, then their

convolution may be defined as the integral:

1.3 TYPES OF CONVOLUTION

There are two types of convolution. They are:

Linear convolution

Circular convolution

1.3.1 Linear convolution

Convolution is an integral concatenation of two signals. It has many

applications in numerous areas of signal processing. The convolution described

above is nothing but linear convolution. The most popular application is the

determination of the output signal of a linear time-invariant system by convolving

the input signal with the impulse response of the system. Convolving two signals

is equivalent to multiplying the Fourier transform of the two signals.

3

1.3.1.1 Mathematical Formulae:

The linear convolution of two continuous time signals and is defined by,

For discrete time signals x(n) and h(n) , the integration is replaced by a summation

1.3.2 Circular Convolution

The circular convolution of two aperiodic functions occurs when one of

them is convolved in the normal way with a periodic summation of the other

function. It occurs naturally in digital signal processing when DTFTs and inverse

DTFTs are replaced by DFTs and inverse DFTs. Equivalently, the continuous

frequency domain is replaced by a discrete one. (See Circular convolution

theorem.)

The Circular convolution theorem states that :

For a periodic function xT(t) , with period T, the convolution with another

function, h(t), is also periodic, and can be expressed in terms of integration over a

finite interval as follows:

Where, to is an arbitrary parameter, and hT(t) is a periodic summation of h,

defined by:

4

When xT(t) is expressed as the periodic summation of another function x, this

convolution is sometimes referred to as circular convolution of functions h and

x.

1.4 PROPERTIES OF CONVOLUTION

This section describes the properties of convolution. The properties of

convolution are:

Commutative

Associative

Distributive

1.4.1 Commutative property:

The commutative property for convolution is expressed in mathematical

form:

a[n] * b[n] = b[n] * a[n]

In words, the order in which two signals are convolved makes no difference, the

results are identical.

1.4.2 Associative property:

The associative property describes the way to convolve more than two

signals. Convolve two of the signals to produce an intermediate signal, then

convolve the intermediate signal with the third signal. The associative property

provides that the order of the convolutions doesn't matter. As an equation:

5

(a[n] * b[n] ) * c[n] = a[n] * ( b[n] * c[n] )

The associative property is used in system theory to describe how

cascaded systems behave. Two or more systems are said to be in a cascade if the

output of one system is used as the input for the next system. From the associative

property, the order of the systems can be rearranged without changing the overall

response of the cascade. Further, any number of cascaded systems can be replaced

with a single system. The impulse response of the replacement system is found by

convolving the impulse responses of all of the original systems.

1.4.3 Distributive property:

In equation form, the distributive property is written as:

a[n] * b[n] + a[n] * c[n] = a[n] * (b[n] + c [n] )

The distributive property describes the operation of parallel systems with

added outputs. Two or more systems can share the same input, x[n] , and have

their outputs added to produce y[n] . The distributive property allows this

combination of systems to be replaced with a single system, having an impulse

response equal to the sum of the impulse responses of the original systems.

1.5 APPLICATIONS OF CONVOLUTION

Convolution and related operations are found in many applications of

engineering and mathematics. The following are the areas where convolution is

being applied :

In statistics, as noted above, a weighted moving average is a convolution.

In probability theory, the probability distribution of the sum of two

independent random variables is the convolution of their individual

distributions.

6

In optics, many kinds of "blur" are described by convolutions. A shadow (e.g.

the shadow on the table when you hold your hand between the table and a

light source) is the convolution of the shape of the light source that is casting

the shadow and the object whose shadow is being cast. An out-of-focus

photograph is the convolution of the sharp image with the shape of the iris

diaphragm. The photographic term for this is “bokeh”.

Similarly, in digital image processing, convolutional filtering plays an

important role in many important algorithms in edge detection and related

processes.

In linear acoustics, an echo is the convolution of the original sound with a

function representing the various objects that are reflecting it.

In artificial reverberation (digital signal processing, pro audio), convolution is

used to map the impulse response of a real room on a digital audio signal (see

previous and next point for additional information).

In electrical engineering and other disciplines, the output (response) of a

(stationary, or time- or space-invariant) linear system is the convolution of the

input (excitation) with the system's response to an impulse or Dirac delta

function. See LTI system theory and digital signal processing.

In time-resolved fluorescence spectroscopy, the excitation signal can be

treated as a chain of delta pulses, and the measured fluorescence is a sum of

exponential decays from each delta pulse.

In physics, wherever there is a linear system with a "superposition principle",

a convolution operation makes an appearance.

In digital signal processing, frequency filtering can be simplified by

convolving two functions (data with a filter) in the time domain, which is

analogous to multiplying the data with a filter in the frequency domain

CHAPTER 2CHAPTER 2

7

LITERATURE REVIEW

2.1 INTRODUCTION TO CONVOLUTION

The most important operation performed on signals is linear filtering,

which can be performed by convolution. The reason that linear filtering is so

important to signal processing is that it solves many problems and is relatively

simple to describe mathematically. In this chapter we will be looking at

convolution. Convolution helps to determine the effect a system has on an input

signal. It can be shown that a linear, time-invariant system is completely

characterized by its impulse response. Using the sampling property of the delta

function for continuous time signals and the unit sample for discrete time signals

we can decompose a signal into an infinite sum / integral of scaled and shifted

impulses. By knowing how a system affects a single impulse, and by

understanding the way a signal is comprised of scaled and summed impulses, it

seems reasonable that it should be possible to scale and sum the impulse responses

of a system in order to determine what output signal will results from a particular

input. This is precisely what convolution does - convolution determines the

system's output from knowledge of the input and the system's impulse response.

2.2 CONVOLUTION - DISCRETE TIME

The idea of discrete-time convolution is exactly the same as that of

continuous-time convolution. For this reason, it may be useful to look at both

versions to help your understanding of this extremely important concept.

Convolution is a very powerful tool in determining a system's output from

knowledge of an arbitrary input and the system's impulse response.

We know that any discrete-time signal can be represented by a summation

of scaled and shifted discrete-time impulses. Since we are assuming the system to

be linear and time-invariant, it would seem to reason that an input signal

8

comprised of the sum of scaled and shifted impulses would give rise to an output

comprised of a sum of scaled and shifted impulse responses. This is exactly what

occurs in convolution.

For discrete time signals and , the convolution equation is given by:

2.2.1 Graphical Interpretation:

Reflection of resulting in

Shifting of resulting in

Element-wise multiplication of the sequences and

Summation of the product sequence resulting in the convolution

value for

2.2.2 Graphical illustration of convolution properties (Discrete -

time):

A quick graphical example may help in demonstrating why convolution

works.

FIGURE 2.1: Impulse Response.

A single impulse input yields the system's impulse response.

9

FIGURE 2.2: Scaled Response.

A scaled impulse input yields a scaled response, due to the scaling

property of the systems linearity .

FIGURE 2.3: Time-invariance property.

We now use the time-invariance property of the system to show that a

delayed input results in an output of the same shape, only delayed by the same

amount as the input.

FIGURE 2.4: Additive portion of the Linearity property.

10

We now use the additively portion of the linearity property of the system to

complete the picture. Since any discrete-time signal is just a sum of scaled and

shifted discrete-time impulses, we can find the output from knowing the input and

the impulse response.

2.3 CONVOLUTION – ANALOG

In this module we examine convolution for continuous time signals. This

will result in the convolution integral and its properties. These concepts are very

important in Engineering and will make any engineer's life a lot easier if the time

is spent now to truly understand what is going on.

2.3.1 Derivation of the convolution integral

To begin this, it is necessary to state the assumptions we will be making.

In this instance, the only constraints on our system are that it be linear and time-

invariant.

2.3.1.1 Brief Overview of Derivation Steps:

1. An impulse input leads to an impulse response output.

2. A shifted impulse input leads to a shifted impulse response output. This is due

to the time-invariance of the system.

3. We now scale the impulse input to get a scaled impulse output. This is using

the scalar multiplication property of linearity.

4. We can now "sum up" an infinite number of these scaled impulses to get a sum

of an infinite number of scaled impulse responses. This is using the additively

attribute of linearity.

5. Now we recognize that this infinite sum is nothing more than an integral, so we

convert both sides into integrals.

11

6. Recognizing that the input is the function f(t), we also recognize that the output

is exactly the convolution integral.

FIGURE 2.5: Impulse Response of the system.

We begin with a system defined by its impulse response, h(t).

FIGURE 2.6: Shifted version of the input impulse.

We then consider a shifted version of the input impulse. Due to the time

invariance of the system, we obtain a shifted version of the output impulse

response.

FIGURE 2.7: Scaling aspect of linearity of the system.

Now we use the scaling part of linearity by scaling the system by a value,

f(τ), that is constant with respect to the system variable, t.

12

FIGURE 2.8: Additive aspect of linearity of the system.

We can now use the additively aspect of linearity to add an infinite number

of these, one for each possible τ. Since an infinite sum is exactly an integral, we

end up with the integration known as the Convolution Integral. Using the

sampling property, we recognize the left-hand side simply as the input f(t).

2.3.2 Convolution Integral

As mentioned above, the convolution integral provides an easy

mathematical way to express the output of an LTI system based on an arbitrary

signal, x (t), and the system's impulse response, h(t) . The convolution integral is

expressed as

Convolution is such an important tool that it is represented by the symbol

*, and can be written as

y (t) = x(t) * h(t)

By making a simple change of variables into the convolution integral, τ =

t−τ, we can easily show that convolution is commutative:

x (t) * h(t) = h(t) * x(t)

13

2.3.3 Implementation of Convolution

Taking a closer look at the convolution integral, we find that we are

multiplying the input signal by the time-reversed impulse response and

integrating. This will give us the value of the output at one given value of t. If we

then shift the time-reversed impulse response by a small amount, we get the

output for another value of t. Repeating this for every possible value of t, yields

the total output function. While we would never actually do this computation by

hand in this fashion, it does provide us with some insight into what is actually

happening. We find that we are essentially reversing the impulse response

function and sliding it across the input function, integrating as we go. This

method, referred to as the graphical method, provides us with a much simpler way

to solve for the output for simple (contrived) signals, while improving our

intuition for the more complex cases where we rely on computers. In fact Texas

Instruments develops Digital Signal Processors which have special instruction sets

for computations such as convolution.

2.4 SYMMETRIC CONVOLUTION

In mathematics, symmetric convolution is a special subset of convolution

operations in which the convolution kernel is symmetric across its zero point.

Many common convolution-based processes such as Gaussian blur and taking the

derivative of a signal in frequency-space are symmetric and this property can be

exploited to make these convolutions easier to evaluate.

The convolution theorem states that a convolution in the real domain can

be represented as a point-wise multiplication across the frequency domain of a

Fourier transform. Since sine and cosine transforms are related transforms a

modified version of the convolution theorem can be applied, in which the concept

of circular convolution is replaced with symmetric convolution. Using these

transforms to compute discrete symmetric convolutions is non-trivial since

discrete sine transforms (DSTs) and discrete cosine transforms (DCTs) can be

14

counter-intuitively incompatible for computing symmetric convolution, i.e.

symmetric convolution can only be computed between a fixed set of compatible

transforms.

2.4.1 Advantages of symmetric convolutions

There are a number of advantages to computing symmetric convolutions in

DSTs and DCTs in comparison with the more common circular convolution with

the Fourier transform. Most notably the implicit symmetry of the transforms

involved is such that only data unable to be inferred through symmetry is required.

For instance using a DCT-II, a symmetric signal need only have the positive half

DCT-II transformed, since the frequency domain will implicitly construct the

mirrored data comprising the other half. This enables larger convolution kernels to

be used with the same cost as smaller kernels circularly convolved on the DFT.

Also the boundary conditions implicit in DSTs and DCTs create edge

effects that are often more in keeping with neighboring data than the periodic

effects introduced by using the Fourier transform.

15

CHAPTER 3 VHDL BASICS

3.1 DESIGN ENTITIES AND CONFIGURATIONS

The design entity is the primary hardware abstraction in VHDL. It

represents a portion of a hardware designthat has well-defined inputs and outputs

and performs a well-defined function. A design entity may representan entire

system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of

abstraction in between.A configuration can be used to describe how design entities

are put together to form a complete design.

A design entity may be described in terms of a hierarchy of blocks, each

of which represents a portion of the whole design. The top-level block in such a

hierarchy is the design entity itself; such a block is an external block that resides

in a library and may be used as a component of other designs. Nested blocks in the

hierarchy are internal blocks, defined by block statements

3.1.1 Entity declarations:

An entity declaration defines the interface between a given design entity

and the environment in which it issued. It may also specify declarations and

statements that are part of the design entity. A given entity declaration may be

shared by many design entities, each of which has a different architecture. Thus,

an entity declaration can potentially represent a class of design entities, each with

the same interface.

entity_declaration ::=

entity identifier is

entity_header

entity_declarative_part

[ begin

16

entity_statement_part ]

end [ entity ] [ entity_simple_name ] ;

3.1.1.1 Generics:

Generics provide a channel for static information to be communicated to

a block from its environment. The following applies to both external blocks

defined by design entities and to internal blocks defined by block

statements.

generic_list ::= generic_interface_list

The generics of a block are defined by a generic interface list. Each

interface element in such a generic interface list declares a formal generic.

3.1.1.2 Ports:

Ports provide channels for dynamic communication between a block and

its environment.

port_list ::= port_interface_list

3. 2 Architecture bodies:

An architecture body defines the body of a design entity. It specifies the

relationships between the inputs and outputs of a design entity and may be

expressed in terms of structure, dataflow, or behavior. Such specifications may be

partial or complete.

architecture_body ::=

architecture identifier of entity_name is

architecture_declarative_part

begin

architecture_statement_part

end [ architecture ] [ architecture_simple_name ] ;

17

3.3 Subprograms And Packages:

3.3.1 Subprogram declarations:

A subprogram declaration declares a procedure or a function, as indicated

by the appropriate reserved word.

subprogram_declaration ::=

subprogram_specification ;

subprogram_specification ::=

procedure designator [ ( formal_parameter_list ) ]

| [ pure | impure ] function designator

[ ( formal_parameter_list ) ]

return type_mark

The specification of a procedure specifies its designator and its formal

parameters (if any). The specification of a function specifies its designator, its

formal parameters (if any), the subtype of the returned value (the result subtype),

and whether or not the function is pure. A function is impure if its specification

contains the reserved word impure; otherwise, it is said to be pure. A procedure

designator is always an identifier. A function designator is either an identifier or

an operator symbol

3.3.2 Subprogram bodies:

A subprogram body specifies the execution of a subprogram.

subprogram_body ::=

subprogram_specification is

subprogram_declarative_part

begin

subprogram_statement_part

end [ subprogram_kind ] [ designator ] ;

18

3.3.3 Package declarations:

A package declaration defines the interface to a package. The scope of a

declaration within a package can be extended to other design units.

package_declaration ::=

package identifier is

package_declarative_part

end [ package ] [ package_simple_name ] ;

3.3.4 Package bodies

A package body defines the bodies of subprograms and the value of

deferred constants declared in the interface to the package.

package_body ::=

package body package_simple_name is

package_body_declarative_part

end [ package body ] [ package_simple_name ] ;

3.4 Data Types:

3.4.1 Scalar Types:

Scalar type can be classified into four types.They are :

a) Enumeration

b) Integer

c) Physical

d) Floating Point

19

a) Enumeration types:

An enumeration type definition defines an enumeration type.

enumeration_type_definition ::=

( enumeration_literal { , enumeration_literal } )

enumeration_literal ::= identifier | character_literal

b) Integer types:

An integer type definition defines an integer type whose set of values

includes those of the specified range.

integer_type_definition ::= range_constraint.

c) Physical types:

Values of a physical type represent measurements of some quantity. Any

value of a physical type is an integral multiple of the primary unit of measurement

for that type.

physical_type_definition ::=

range_constraint

units

primary_unit_declaration

{ secondary_unit_declaration }

end units [ physical_type_simple_name ]

d) Floating point types:

20

Floating point types provide approximations to the real numbers. Floating

point types are useful for models in which the precise characterization of a

floating point calculation is not important or not determined.

floating_type_definition ::= range_constraint

3.4.2 Composite types:

Composite types are used to define collections of values. These include

both arrays of values (collections of values of a homogeneous type) and records of

values (collections of values of potentially heterogeneous types) i.e., they are of

two types:

a) Array types

b) Record types

a) Array types:

An array object is a composite object consisting of elements that have the

same subtype. The name for an element of an array uses one or more index values

belonging to specified discrete types. The value of an array object is a composite

value consisting of the values of its elements

unconstrained_array_definition ::=

array ( index_subtype_definition { ,

index_subtype_definition } )

of element_subtype_indication

constrained_array_definition ::=

array index_constraint of

element_subtype_indication

b) Record types:

21

A record type is a composite type, objects of which consist of named

elements. The value of a record object is a composite value consisting of the

values of its elements.

record_type_definition ::=

record

element_declaration

{ element_declaration }

end record [ record_type_simple_name ]

3.4.3 Access types:

An object declared by an object declaration is created by the elaboration of

the object declaration and is denoted by a simple name or by some other form of

name. In contrast, objects that are created by the evaluation of allocators (see

7.3.6) have no simple name. Access to such an object is achieved by an access

value returned by an allocator; the access value is said to designate the object.

access_type_definition ::= access subtype_indication

3.4.4 File types:

A file type definition defines a file type. File types are used to define

objects representing files in the hostsystem environment. The value of a file object

is the sequence of values contained in the host system file.

file_type_definition ::= file of type_mark

3.5 Data Objects:3.5.1 Object declarations

22

An object declaration declares an object of a specified type. Such an

object is called an explicitly declared object.

3.5.2 Constant declarations

A constant declaration declares a constant of the specified type. Such a

constant is an explicitly declared constant.

constant_declaration ::=

constant identifier_list : subtype_indication [ := expression ] ;

If the assignment symbol ":=" followed by an expression is present in a

constant declaration, the expression specifies the value of the constant; the type of

the expression must be that of the constant. The value of a constant cannot be

modified after the declaration is elaborated.

3.5.3 Signal declarations

A signal declaration declares a signal of the specified type. Such a signal is

an explicitly declared signal.

signal_declaration ::=

signal identifier_list : subtype_indication [ signal_kind ] [ := expression ] ;

signal_kind ::= register | bus

3.5.4 Variable declarations

A variable declaration declares a variable of the specified type. Such a

variable is an explicitly declared variable.

variable_declaration ::=

[ shared ] variable identifier_list : subtype_indication [ := expression ] ;

3.5.5 File declarations

23

A file declaration declares a file of the specified type. Such a file is an

“explicitly declared file”.

file_declaration ::= file identifier_list : subtype_indication

[ file_open_information ] ;

3.6 Operators:

3.6.1 Logical Operators:

The logical operators and, or, nand, nor, xor, xnor, and not are defined

for predefined types BIT and BOOLEAN. They are also defined for any one-

dimensional array type whose element type is BIT or BOOLEAN. For the binary

operators and, or, nand, nor, xor, and xnor, the operands must be of the same

base type.

Moreover, for the binary operators and, or, nand, nor, xor, and xnor

defined on one-dimensional array types, the operands must be arrays of the same

length, the operation is performed on matching elements of the arrays, and the

result is an array with the same index range as the left operand.

3.6.2 Relational Operators:

Relational operators include tests for equality, inequality, and ordering of

operands. The operands of each relational operator must be of the same type. The

result type of each relational operator is the predefined type BOOLEAN.

The table of Relational operators is as follows,

24

TABLE 3.1: Relational Operators.

Operator Operation Operand Type

Result

Type

= Equality Any Type Boolean

/= Inequality Any Type Boolean

< Less Than Any ScalarType

or Descrete type Boolean

<= Less Than or

Equal

Any ScalarType

or Descrete type

Boolean

>

GreaterThan

Any ScalarType

or Descrete type

Boolean

>= Greater Than or

Equal

Any ScalarType

or Descrete type

Boolean

3.6.3.Shift Operators:

The shift operators sll, srl, sla, sra, rol, and ror are defined for any one-

dimensional array type whose element type is either of the predefined types

BIT or BOOLEAN.

The table of Shift Operators is as follows,

25

TABLE 3.2: Shift Operators.

Operation

Left

operand

type

Right operand

type

Result

type

Sll Shift left

Logical

Any one-dimensional

array type whose element

type is BIT or

BOOLEAN

INTEGER Same as left

srl Shift right

Logical

Any one-dimensional

array type whose element

type is BIT or

BOOLEAN

INTEGER Same as left

sla Shift left

arithmetic

Any one-dimensional

array type whose element

type is BIT or

BOOLEAN

INTEGER Same as left

sra Shift right

arithmetic

Any one-dimensional

array type whose element

type is BIT or

BOOLEAN

INTEGER

Same as left

rol Rotate left

logical

Any one-dimensional

array type whose element

type is BIT or

BOOLEAN

INTEGER

Same as left

rorRotate right

Logical

Any one-dimensional

array type whose element

type is BIT or

BOOLEAN

INTEGER Same as left

3.6.4. Adding Operators:

26

The adding operators + and Ð are predefined for any numeric type and

have their conventional mathematical meaning. The concatenation operator & is

predefined for any one-dimensional array type.

TABLE 3.3: Addition Operators.

Operator Operation

Left operand

type

Right operand

Type

Result

Type

+ Addition Any numeric

type Same type

Same type

- Subtraction Any numeric

type Same type

Same type

&

Concatenation

Any array type

Same array type

Same array

type

Any array

type

Same element

type

Same array

type

The element

type

Any array type Same array

type

The element

type

Any element

type

Any array

type

3.6.5. Multiplying Operators:

The operators * and / are predefined for any integer and any floating point

type and have their conventional mathematical meaning; the operators mod and

rem are predefined for any integer type. For each of these operators, the operands

and the result are of the same type.

TABLE 3.4: Multiplying Operators.

Left operand Right Result

27

Operator Operation type operand

Type

Type

* Multiplication

Any integertype Same type Same

type

Any floating point

type

Same type Same

type

/ Division

Any integer type Same type Same

type

Any floating point

type

Same type Same

type

Mod Modulus Any integer type Same type Same

type

Rem Remainde Any integer type Same type Same

type

3.6.6. Miscellaneous operators:

The unary operator abs is predefined for any numeric type.

TABLE 3.5: Unary Operator.

Operator Operation Operand type Result type

Abs Absolute value Any numeric type Same numeric type

The exponentiating operator ** is predefined for each integer type and for

each floating point type. In either case the right operand, called the exponent, is of

the predefined type INTEGER.

TABLE 6: Miscellaneous Operators.

28

Operator Operation

Left operand

type

Right

operand

Type

Result

Type

** Exponentiation

Any integer type INTEGER Same as left

Any floating pt INTEGER Same as left

In VHDL mainly there are three types modeling styles.These are :

1. Behaviorial Modeling.

2. Data Flow Modeling.

3. Structural Modeling.

3.7 Behaviorial Modeling:

3.7 .1 Process statement

A process statement defines an independent sequential process

representing the behavior of some portion of thedesign.

process_statement ::=

[ process_label : ]

[ postponed ] process [ ( sensitivity_list ) ] [ is ]

process_declarative_part

begin

process_statement_part

end [ postponed ] process [ process_label ] ;

where the sensitivity list of the wait statement is that following the reserved word

process. Such a process statement must not contain an explicit wait statement.

Similarly, if such a process statement is a parent of a procedure, then that

procedure may not contain a wait statement.

3.7.2 Sequential statements:

29

The various forms of sequential statements are described in this section.

Sequential statements are used to define algorithms for the execution of a

subprogram or process; they execute in the order in which they appear.

a)Wait statement

The wait statement causes the suspension of a process statement or a

procedure.

wait_statement ::=

[ label : ] wait [ sensitivity_clause ] [ condition_clause ]

[ timeout_clause ] ;

sensitivity_clause ::= on sensitivity_list

sensitivity_list ::= signal_name { , signal_name }

condition_clause ::= until condition

condition ::= boolean_expression

timeout_clause ::= for time_expression

b) Assertion statement:

An assertion statement checks that a specified condition is true and reports

an error if it is not.

assertion_statement ::= [ label : ] assertion ;

assertion ::=

assert condition

[ report expression ]

[ severity expression ]

c) Report statement:

30

A report statement displays a message.

report_statement ::=

[ label : ]

report expression

[ severity expression ] ;

d) If statement:

An if statement selects for execution one or none of the enclosed

sequences of statements, depending on the value of one or more corresponding

conditions.

if_statement ::=

[ if_label : ]

if condition then

sequence_of_statements

{ elsif condition then

sequence_of_statements }

[ else

sequence_of_statements ]

end if [ if_label ] ;

If a label appears at the end of an if statement, it must repeat the if label.

For the execution of an if statement, the condition specified after if, and any

conditions specified after elsif, are evaluated in succession (treating a final else as

elsif TRUE then) until one evaluates to TRUE or all conditions are evaluated and

yield FALSE. If one condition evaluates to TRUE, then the corresponding

sequence of statements is executed; otherwise, none of the sequences of

statements is executed.

e) Case statement:

A case statement selects for execution one of a number of alternative

sequences of statements; the chosen alternative is defined by the value of an

expression.

31

case_statement ::=

[ case_label : ]

case expression is

case_statement_alternative

{ case_statement_alternative }

end case [ case_label ] ;

case_statement_alternative ::=

when choices =>

sequence_of_statements

The expression must be of a discrete type, or of a one-dimensional array

type whose element base type is a character type. This type must be determinable

independently of the context in which the expression occurs, but using the fact

that the expression must be of a discrete type or a one-dimensional character array

type. Each choice in a case statement alternative must be of the same type as the

expression; the list of choices specifies for which values of the expression the

alternative is chosen.

f) Loop statement:

A loop statement includes a sequence of statements that is to be executed

repeatedly, zero or more times.

loop_statement ::=

[ loop_label : ]

[ iteration_scheme ] loop

sequence_of_statements

end loop [ loop_label ] ;

iteration_scheme ::=

while condition

| for loop_parameter_specification

parameter_specification ::=

32

identifier in discrete_range

g) Next statement:

A next statement is used to complete the execution of one of the iterations

of an enclosing loop statement (called loop in the following text). The completion

is conditional if the statement includes a condition.

next_statement ::=

[ label : ] next [ loop_label ] [ when condition ] ;

h) Exit statement:

An exit statement is used to complete the execution of an enclosing loop

statement (called loop in the following text). The completion is conditional if the

statement includes a condition.

exit_statement ::=

[ label : ] exit [ loop_label ] [ when condition ] ;

i) Return statement:

A return statement is used to complete the execution of the innermost

enclosing function or procedure body

.return_statement ::=

[ label : ] return [ expression ] ;

j) Null statement:

A null statement performs no action.

null_statement ::=

[ label : ] null ;

33

3.8 Data Flow Modeling:

The various forms of concurrent statements are described in this section.

Concurrent statements are used to define interconnected blocks and processes

that jointly describe the overall behavior or structure of a design. Concurrent

statements execute asynchronously with respect to each other.

3.8.1 Block statement:

A block statement defines an internal block representing a portion of a

design. Blocks may be hierarchically nested to support design decomposition.

block_statement ::=

block_label :

block [ ( guard_expression ) ] [ is ]

block_header

block_declarative_part

begin

block_statement_part

end block [ block_label ] ;

If a guard expression appears after the reserved word block, then a signal

with the simple name GUARD of predefined type BOOLEAN is implicitly

declared at the beginning of the declarative part of the block, and the guard

expression defines the value of that signal at any given time (see 12.6.4). The type

of the guard expression must be type BOOLEAN. Signal GUARD may be used to

control the operation of certain statements within the block (see 9.5).

3.8.2 Concurrent procedure call statements:

A concurrent procedure call statement represents a process containing the

corresponding sequential procedure call statement.

34

concurrent_procedure_call_statement ::=

[ label : ] [ postponed ] procedure_call ;

For any concurrent procedure call statement, there is an equivalent process

statement. The equivalent process statement is a postponed process if and only if

the concurrent procedure call statement includes the reserved word postponed.

3.8.3 Concurrent assertion statements:

A concurrent assertion statement represents a passive process statement

containing the specified assertion statement.

concurrent_assertion_statement ::=

[ label : ] [ postponed ] assertion ;

3.8.4 Concurrent signal assignment statements

A concurrent signal assignment statement represents an equivalent process

statement that assigns values to signals.

concurrent_signal_assignment_statement ::=

[ label : ] [ postponed ] conditional_signal_assignment

| [ label : ] [ postponed ] selected_signal_assignment

3.8.5 Conditional signal assignments:

The conditional signal assignment represents a process statement in which

the signal transform is an if statement.

target <= options waveform1 when condition1 else

waveform2 when condition2 else

waveform3 when condition3 else

--------------

35

---------------

waveformN-1 when condition-1 else

waveformN when conditionN;

3.8.6 Selected signal assignments:

The selected signal assignment represents a process statement in which the

signal transform is a case statement.

with expression select

target <= options waveform1 when choice_list1 ,

waveform2 when choice_list2 ,

waveform3 when choice_list3,

--------------

---------------

waveformN-1 when choice_listN-1,

waveformN when choice_listN ;

3.9 Structural Modeling:

3.9.1 Component declarations:

A component declaration declares a virtual design entity interface that may

be used in a component instantiation statement. A component configuration or a

configuration specification can be used to associate a component instance with a

design entity that resides in a library.

component_declaration ::=

component identifier [ is ]

[ local_generic_clause ]

[ local_port_clause ]

end component [ component_simple_name ] ;

Each interface object in the local generic clause declares a local generic.

Each interface object in the local port clause declares a local port.If a simple name

36

appears at the end of a component declaration, it must repeat the identifier of the

component declaration.

3.9.2 Component instantiation statements:

A component instantiation statement defines a subcomponent of the design

entity in which it appears, associates signals or values with the ports of that

subcomponent, and associates values with generics of that subcomponent. This

subcomponent is one instance of a class of components defined by a

corresponding component declaration, design entity, or configuration declaration.

component_instantiation_statement ::=

instantiation_label :

instantiated_unit

[ generic_map_aspect ]

[ port_map_aspect ] ;

instantiated_unit ::=

[ component ] component_name

| entity entity_name [ ( architecture_identifier ) ]

| configuration configuration_name

CHAPTER 4CHAPTER 4DESIGN OF HARDWARE MODEL

4.1 CONVOLUTION

Convolution is an important tool in data processing, in particular in digital

signal and image processing. Many image processing operations such as scaling

and rotation require re-sampling or convolution filtering for each pixel in the

37

image Digital images can be modified (through convolution) by neighborhood

operations; these operations go beyond point wise operations, and include

smoothing, sharpening, and edge detection. Convolution has many applications

which have great significance in discrete signal processing. It is usually difficult

to deal with analog signals. Hence signals are converted to digital state.

Many approaches have been attempted to reduce the convolution

processing time using hardware and software algorithms but they are restricted to

specific applications. The main problem in implementing and computing

convolution is speed, area and power which affect any DSP system. Speeding up

convolution using a Hardware Description Language for design entry not only

increases (improves) the level of abstraction, but also opens new possibilities for

using programmable devices.

Today, most DSPs suffer from limitations in available address space, or

the ability to interface with surrounding systems. The use of high speed field

programmable gate arrays i.e. FPGAs, together with DSPs, can often increase the

system bandwidth, by providing additional functionality to the general purpose

DSPs .In this project, a novel method for computing the linear convolution of two

finite length sequences is presented. A 4x4 convolution circuit can be instantiated

for larger ones. This method is similar to the multiplication of two decimal

numbers, this similarity that makes this method easy to learn and quick to

computes.

4.2 CONVOLUTION IN TIME DOMAIN

When two signals convolution is carried out in time domain it is referred

to as convolution in time domain. We are dealing with convolution in time domain

in this project. In time domain also the convolution can be continuous or discrete.

When the convolution is in time domain is discrete then it is called as convolution

in discrete time and when the convolution is performed with respect to continuous

38

time it is called as convolution as convolution in continuous time. Convolution in

discrete and continuous time are described in previous chapter.

4.3 CONVOLUTION IN FREQUENCY DOMAIN

When two signals are convolved in frequency domain then it is called as

convolution in frequency domain. It is proved that the convolution in time domain

is equivalent to multiplication in frequency domain.

Proof:

Let f, g belong to L1 (Rn). Let F be the Fourier transform of f and G be the Fourier

transform of g:

Where the dot between x and ν indicates the inner product of Rn . Let h be the

convolution of f and g

Now notice that,

Hence by Fubini's theorem we have that so its Fourier transform H

is defined by the integral formula

39

Observe that and hence by the

argument above we may apply Fubini's theorem again:

Substitute y = z − x; then dy = dz, so:

These two integrals are the definitions of F(ν) and G(ν), so:

Hence, it is proved that the convolution in time domain is equivalent to

multiplication in frequency domain.

4.4 GENERAL IMPLEMENTATION FLOW

The generalized implementation flow diagram of the project is represented

as follows:

40

FIGURE 4.1: GENERAL IMPLEMENTATION FLOW DIAGRAM.

Initially the market research should be carried out which covers the

previous version of the design and the current requirements on the design. Based

on this survey, the specification and the architecture must be identified. Then the

RTL modelling should be carried out in VERILOG HDL with respect to the

identified architecture. Once the RTL modelling is done, it should be simulated

and verified for all the cases. The functional verification should meet the intended

architecture and should pass all the test cases.

41

Once the functional verification is clear, the RTL model will be taken to

the synthesis process. Three operations will be carried out in the synthesis process

such as

Translate

Map

Place and Route

The developed RTL model will be translated to the mathematical equation

format which will be in the understandable format of the tool. These translated

equations will be then mapped to the library that is, mapped to the hardware. Once

the mapping is done, the gates were placed and routed. Before these processes, the

constraints can be given in order to optimize the design. Finally the BIT MAP file

will be generated that has the design information in the binary format which will

be dumped in the FPGA board.

4.5 IMPLEMENTATION

In this project the implementation is carried out by first designed the

individual blocks and then these are combined to the final architecture. The

individual blocks are shown in block diagram given in the next page.

4.5.1 Block diagramThe block diagram of the proposed architecture is shown below:

42

FIGURE 4.2: Block Diagram Of Architecture.

4.5.1.1 Multiplexer 4*1 and 8*1:

A multiplexer, sometimes referred to as a "multiplexor" or simply "mux",

is a device that selects between a number of input signals. In its simplest form, a

multiplexer will have two signal inputs, one control input, and one output.

A multiplexer is a device which selects any one of the inputs from 2n

inputs and directed to output depending on n-select lines.

FIGURE 4.3: 4*1 Multiplexer

43

FIGURE 4.4: 8*1 Mutiplexer.

The higher order multiplexers can be implemented using the lower order

multiplexers. The 4*1 multiplexer can be implemented using two 2*1

multiplexers and so on. Similarly an 8*1 multiplexer can be implemented using

two 4*1 multiplexers.

4.5.1.2 Serial in parallel out block:

A serial-in/parallel-out shift register is similar to the serial-in/ serial-out

shift register in that it shifts data into internal storage elements and shifts data out

at the serial-out, data-out, pin . It is different in that it makes all the internal stages

available as outputs. Therefore, a serial in/parallel-out shift register converts data

from serial format to parallel format. If four data bits are shifted in by four clock

pulses via a single wire at data-in, below, the data becomes available

simultaneously on the four Outputs QA to QD after the fourth clock pulse.

44

FIGURE 4.5: SIPO Shift Register block.

The practical application of the serial-in/parallel-out shift register is to

convert data from serial format on a single wire to parallel format on multiple

wires. Perhaps, we will illuminate four LEDs (Light Emitting Diodes) with the

four outputs (QA QB QC QD ).

FIGURE 4.6: SIPO inner architecture.

The above details of the serial-in/parallel-out shift register are fairly

simple. It looks like a serial-in/ serial-out shift register with taps added to each

45

stage output. Serial data shifts in at SI (Serial Input). After a number of clocks

equal to the number of stages, the first data bit in appears at SO (QD) in the above

figure. In general, there is no SO pin. The last stage (QD above) serves as SO and

is cascaded to the next package if it exists.

FIGURE 4.7: SIPO Waveforms.

The shift register has been cleared prior to any data by CLR', an active

low signal, which clears all type D Flip-Flops within the shift register. Note the

serial data 1011 pattern presented at the SI input. This data is synchronized with

the clock CLK. This would be the case if it is being shifted in from something

like another shift register, for example, a parallel-in/ serial-out shift register (not

shown here). On the first clock at t1, the data 1 at SI is shifted from D to Q of the

first shift register stage. After t2 this first data bit is at QB. After t3 it is at QC.

After t4 it is at QD. Four clock pulses have shifted the first data bit all the way to

the last stage QD. The second data bit a 0 is at QC after the 4th clock. The third

data bit a 1 is at QB. The fourth data bit another 1 is at QA. Thus, the serial data

input pattern 1011 is contained in (QD QC QB QA). It is now available on the four

outputs.

46

It will available on the four outputs from just after clock t4 to just before t5.

This parallel data must be used or stored between these two times, or it will be lost

due to shifting out the QD stage on following clocks t5 to t8 as shown above.

4.5.1.3 Binary multiplier:

The binary multiplier used here is a 4-bit multiplier which takes two four

bit inputs and gives an 8-bit output.

FIGURE 4.8: Binary Multiplier.

The binary multiplier which is employed in convolution here

in the present project has a special characteristic that the internal carry will not be

forwarded to next stage. So the number of outputs obtained here is seven only

because in binary multiplier the MSB part is nothing but the carry obtained from

the second MSB so as carry is not forwarded only seven bits will be obtained as

output.

47

4.5.1.4 Register:

A circuit with flip-flops is considered a sequential circuit even in the

absence of Combinational logic. Circuits that include flip-flops are usually

classified by the function they perform. Two such circuits are registers and

counters.

A Register is a group of flip-flops. Its basic function is to hold

information within a digital system so as to make it available to the logic units

during the computing process. However, a register may also have additional

capabilities associated with it. It may have combinational gates that perform

certain data-processing tasks.

FIGURE 4.9: An 8-bit Register.

Various types of registers are available on the market. A simple 4-bit

register is shown below. The common clock input triggers all flip-flops and the

48

binary data available at the four inputs are transferred into the register. The clear

input is useful for clearing the register to all 0’s output.

Registers capable of shifting their binary contents in one or both

directions.A unidirectional 4-bit shift register that uses only flip-flops is as

follows:

FIGURE 4.10: Shift Register.

49

CHAPTER 5CHAPTER 5RESULTS AND DISCUSSIONS

5.1 INTRODUCTION TO MODEL SIMULATOR:

5.1.1 Basic Simulation Flow

The following diagram shows the basic steps for simulating a design in

ModelSim.

FIGURE 5.1: Basic Simulation Flow - Overview Lab.

In ModelSim, all designs are compiled into a library. You typically start a

new simulation in ModelSim by creating a working library called "work". "Work"

is the library name used by the compiler as the default destination for compiled

design units.

Compiling Your Design:

After creating the working library, you compile your design units into it.

The ModelSim library format is compatible across all supported platforms. You

can simulate your design on any platform without having to recompile your

design.

50

Loading the Simulator with Your Design and Running the Simulation With

the design compiled, you load the simulator with your design by invoking the

simulator on a top-level module (Verilog) or a configuration or entity/architecture

pair (VHDL). Assuming the design loads successfully, the simulation time is set

to zero, and you enter a run command to begin simulation.

Debugging Your Results

If you don’t get the results you expect, you can use ModelSim’s robust

debugging environment to track down the cause of the problem.

5.1.2 Project FlowA project is a collection mechanism for an HDL design under specification

or test. Even though you don’t have to use projects in ModelSim, they may ease

interaction with the tool and are useful for organizing files and specifying

simulation settings.

The following diagram shows the basic steps for simulating a design

within a ModelSim project.

FIGURE 5.2: Project Design Flow.

As you can see, the flow is similar to the basic simulation flow. However,

there are two important differences:

51

You do not have to create a working library in the project flow; it is done for

you automatically.

Projects are persistent. In other words, they will open every time you invoke

ModelSim unless you specifically close them.

5.1.3 Multiple Library Flow

ModelSim uses libraries in two ways:

1) As a local working library that contains the compiled version of your

design;

2) As a resource library.

The contents of your working library will change as you update your

design and recompile. A resource library is typically static and serves as a parts

source for your design. You can create your own resource libraries, or they may

be supplied by another design team or a third party (e.g., a silicon vendor).

You specify which resource libraries will be used when the design is

compiled, and there arerules to specify in which order they are searched. A

common example of using both a working library and a resource library is one

where your gate-level design and testbench are compiled into the working library,

and the design references gate-level models in a separate resource library.The

diagram below shows the basic steps for simulating with multiple libraries.

FIGURE 5.3: Multiple Library Flow.

52

5.1.3.1 Debugging Tools

ModelSim offers numerous tools for debugging and analyzing your design.

Several of these tools are covered in subsequent lessons, including:

Using projects

Working with multiple libraries

Setting breakpoints and stepping through the source code

Viewing waveforms and measuring time

Viewing and initializing memories

Creating stimulus with the Waveform Editor

Automating simulation

5.1.4 Basic Simulation

FIGURE 5.4: Basic Simulation Flow - Simulation Lab.

53

5.1.4.1 Design Files for this Lesson

The sample design for this lesson is a simple 8-bit, binary up-counter with

an associated Test bench. The pathnames are as follows:

Verilog – <install_dir>/examples/tutorials/verilog/basicSimulation/counter.v and

tcounter.v

VHDL – <install_dir>/examples/tutorials/vhdl/basicSimulation/counter.vhd and

tcounter.vhd

This lesson uses the Verilog files counter.v and tcounter.v. If you have a VHDL

license, use

counter.vhd and tcounter.vhd instead. Or, if you have a mixed license, feel free to

use the

Verilog testbench with the VHDL counter or vice versa.

5.1.5 Create the Working Design Library

Before you can simulate a design, you must first create a library and

compile the source code into that library.

1. Create a new directory and copy the design files for this lesson into it.

Start by creating a new directory for this exercise (in case other users will be

working with these lessons).

Verilog: Copy counter.v and tcounter.v files from

/<install_dir>/examples/tutorials/verilog/basicSimulation to the new directory.

VHDL: Copy counter.vhd and tcounter.vhd files from

/<install_dir>/examples/tutorials/vhdl/basicSimulation to the new directory.

2. Start ModelSim if necessary.

54

a) Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows.

Upon opening ModelSim for the first time, you will see the Welcome to

ModelSim dialog. Click Close.

b) Select File > Change Directory and change to directory you created in step 1.

3. Create the working library.

a) Select File > New > Library.

This opens a dialog where you specify physical and logical names for the

library (Figure 5.5). You can create a new library or map to an existing library.

We’ll be doing the former.

FIGURE 5.5: The Create a New Library Dialog.

b) Type work in the Library Name field (if it isn’t already entered automatically).

c) Click OK.

ModelSim creates a directory called work and writes a specially-formatted

file named _info into that directory. The _info file must remain in the directory to

distinguish it as a ModelSim library. Do not edit the folder contents from your

operating system; all changes should be made from within ModelSim. ModelSim

also adds the library to the list in the Workspace (Figure 5.6) and records the

library mapping for future reference in the ModelSim initialization file

(modelsim.ini).

55

FIGURE 5.6: Work Library in the Workspace.

When you pressed OK in step 3c above, the following was printed to the

Transcript:

vlib work

vmap work work

These two lines are the command-line equivalents of the menu selections you

made. Many

command-line equivalents will echo their menu-driven functions in this fashion.

5.1.6 Compile the Design

With the working library created, you are ready to compile your source

files.You can compile by using the menus and dialogs of the graphic interface, as

in the Verilog example below, or by entering a command at the ModelSim>

prompt.

1. Compile counter.v and tcounter.v.

a) Select Compile > Compile. This opens the Compile Source Files dialog

(Figure 5.7).

56

If the Compile menu option is not available, you probably have a project

open. If so, close the project by making the Workspace pane active and selecting

File > Close from the menus.

b) Select both counter.v and tcounter.v modules from the Compile Source Files

dialog and click Compile. The files are compiled into the work library. c. When

compile is finished, click Done.

FIGURE 5.7: Compile Source Files Dialog.

2. View the compiled design units.

a) On the Library tab, click the ’+’ icon next to the work library and you will see

two design units (Figure 3-5). You can also see their types (Modules, Entities,

etc.) and the path to the underlying source files (scroll to the right if necessary).

b) Double-click test_counter to load the design.

You can also load the design by selecting Simulate > Start Simulation in

the menu bar. This opens the Start Simulation dialog.

With the Design tab selected, click the ’+’ sign next to the work library to

see the counter and test_counter modules.

Select the test_counter module and click OK (Figure 5.8).

57

FIGURE 5.8: Loading Design with Start Simulation Dialog.

When the design is loaded, you will see a new tab in the Workspace

named sim that displays the hierarchical structure of the design (Figure 4-8). You

can navigate within the hierarchy by clicking on any line with a ’+’ (expand) or ’-’

(contract) icon. You will also see a tab named Files that displays all files included

in the design.

FIGURE 5.9: VHDL Modules Compiled into work Library.

58

5.1.7 Load the Design

1. Load the test_counter module into the simulator.

a) In the Workspace, click the ‘+’ sign next to the work library to show the files

contained there.

FIGURE 5.10: Workspace sim Tab Displays Design Hierarchy.

2. View design objects in the Objects pane.

a) Open the View menu and select Objects. The command line equivalent is: view

objects

The Objects pane (Figure 3-8) shows the names and current values of data

objects in the current region (selected in the Workspace). Data objects include

signals, nets, registers, constants and variables not declared in a process, generics,

parameters.

FIGURE 5.11: Object Pane Displays Design Objects.

59

You may open other windows and panes with the View menu or with the

view command. See Navigating the Interface.

5.1.8 Run the Simulation

Now you will open the Wave window, add signals to it, then run the

simulation.

1. Open the Wave debugging window.

a) Enter view wave at the command line

You can also use the View > Wave menu selection to open a Wave

window. The Wave window is one of several windows available for debugging.

To see a list of the other debugging windows, select the View menu. You may

need to move or resize the windows to your liking. Window panes within the

Main window can be zoomed to occupy the entire Main window or undocked to

stand alone. For details, see Navigating the Interface.

2. Add signals to the Wave window.

a) In the Workspace pane, select the sim tab.

b) Right-click test_counter to open a popup context menu.

c) Select Add > To Wave > All items in region (Figure 3-9).

All signals in the design are added to the Wave window.

FIGURE 5.12: Using the Popup Menu to Add Signals to Wave Window.

60

3. Run the simulation.

a) Click the Run icon in the Main or Wave window toolbar.

The simulation runs for 100 ns (the default simulation length) and waves

are

drawn in the Wave window.

b) Enter run 500 at the VSIM> prompt in the Main window.

The simulation advances another 500 ns for a total of 600 ns .

FIGURE 5.13: Waves Drawn in Wave Window.

c) Click the Run -All icon on the Main or Wave window toolbar.

The simulation continues running until you execute a break command or it

hits a statement in your code (e.g., a Verilog $stop statement) that halts the

simulation.

d) Click the Break icon. The simulation stops running.

61

5.2 INTRODUCTION TO SIMULATION:

The Convolution process and the developed architecture for the required

functionality were discussed in the previous chapters. Now this chapter deals with

the simulation and synthesis results of the Convolution process. Here Modelsim

tool is used in order to simulate the design and checks the functionality of the

design. Once the functional verification is done, the design will be taken to the

Xilinx tool for Synthesis process and the netlist generation.

The Appropriate test cases have been identified in order to test this

modelled Convolution process architecture. Based on the identified values, the

simulation results which describes the operation of the process has been achieved.

This proves that the modelled design works properly as per its functionality.

5.3 SIMULATION RESULTS:

5.3.1 Convolution toplevel:

FIGURE 5.14: Convolution Waveform on Wave Window.

62

5.4 INDIVIDUAL MODULES:

5.4.1 Multiplexers:

FIG 5.15: 4*1 MUX Waveform on Wave Window.

5.4.2 SIPO’s:

FIGURE 5.16: SIPO Waveform on Wave Window.

63

5.4.3 Binary Multiplier:

FIGURE 5.17: Binary Multiplier waveform on Wave Window.

5.4.4 Multiplexer 8*1:

FIGURE 5.18: 8*1 MUX Waveform on Wave Window.

64

5.4.5 Register:

FIGURE 5.19: Register Waveform on Wave Window.

5.5 INTRODUCTION TO FPGA:

FPGA stands for Field Programmable Gate Array which has the array of

logic module, I /O module and routing tracks (programmable interconnect). FPGA

can be configured by end user to implement specific circuitry. Speed is up to 100

MHz but at present speed is in GHz.

Main applications are DSP, FPGA based computers, logic emulation,

ASIC and ASSP. FPGA can be programmed mainly on SRAM (Static Random

Access Memory). It is Volatile and main advantage of using SRAM programming

technology is re-configurability. Issues in FPGA technology are complexity of

logic element, clock support, IO support and interconnections (Routing).

In this work, design of a DWT and IDWT is made using Verilog HDL and

is synthesized on FPGA family of Spartan 3E through XILINX ISE Tool. This

process includes following:

Translate

Map

Place and Route

5.5.1 FPGA FlowThe basic implementation of design on FPGA has the following steps.

Design Entry

Logic Optimization

Technology Mapping

65

Placement

Routing

Programming Unit

Configured FPGA

Above shows the basic steps involved in implementation. The initial

design entry of may be Verilog HDL, schematic or Boolean expression. The

optimization of the Boolean expression will be carried out by considering area or

speed.

FIGURE 5.20: Logic Block

In technology mapping, the transformation of optimized Boolean

expression to FPGA logic blocks, that is said to be as Slices. Here area and delay

optimization will be taken place. During placement the algorithms are used to

place each block in FPGA array. Assigning the FPGA wire segments, which are

programmable, to establish connections among FPGA blocks through routing. The

configuration of final chip is made in programming unit.

5.6 XILINX DESIGN FLOW

The first step involved in implementation of a design on FPGA involves

System Specifications. Specifications refer to kind of inputs and kind of outputs

and the range of values that the kit can take in based on these Specifications.

After the first step system specifications the next step is the Architecture.

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Architecture describes the interconnections between all the blocks involved in our

design. Each and every block in the Architecture along with their interconnections

is modeled in either VHDL or Verilog depending on the ease. All these blocks are

then simulated and the outputs are verified for correct functioning.

FIGURE 5.21: Xilinx Implementation Design Flow-Chart.

After the simulation step the next steps i.e., Synthesis. This is a very

important step in knowing whether our design can be implemented on a FPGA kit

or not. Synthesis converts our VHDL code into its functional components which

are vendor specific. After performing synthesis RTL schematic, Technology

Schematic and generated and the timing delays are generated. The timing delays

will be present in the FPGA if the design is implemented on it. Place & Route is

the next step in which the tool places all the components on a FPGA die for

optimum performance both in terms of areas and speed. We also see the

interconnections which will be made in this part of the implementation flow.

In post place and route simulation step the delays which will be involved

on the FPGA kit are considered by the tool and simulation is performed taking

into consideration these delays which will be present in the implementations on

the kit. Delays here mean electrical loading effect, wiring delays, stray

capacitances.

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After post place and route, comes generating the bit-map file, which means

converting the VHDL code into bit streams which is useful to configure the FPGA

kit. A bit file is generated this step is performed. After this comes final step of

downloading the bit map file on to the FPGA board which is done by connecting

the computer to FPGA board with the help of JTAG cable (Joint Test Action

Group) which is an IEEE standard. The bit map file consist the whole design

which is placed on the FPGA die, the outputs can now be observed from the

FPGA LEDs. This step completes the whole process of implementing our design

on an FPGA.

5.7 XILINX ISE 10.1 SOFTWARE 5.7.1 Introduction

Xilinx ISE (Integrated Software Environment) 9.2i software is from

XILINX company, which is used to design any digital circuit and implement onto

a Spartan-3E FPGA device. XILINX ISE 9.2i software is used to design the

application, verify the functionality and finally download the design on to a

Spartan-3E FPGA device.

5.7.2 Xilinx ISE 10.1 software tools SIMULATION : ISE (Integrated Software Environment) Simulator

SYNTHESIS, PLACE & POUTE : XST (Xilinx Synthesis Technology)

Synthesizer

5.7.3 Design steps using Xilinx ISE 10.1

1 Create an ISE PROJECT for particular embedded system application.

2 Write the assembly code in notepad or write pad and generate the verilog or

vhdl module by making use of assembler.

3 Check syntax for the design.

4 Create verilog test fixture of the design.

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5 Simulate the test bench waveform (BEHAVIORAL SIMULATION) for

functional verification of the design using ISE simulator.

6 Synthesize and implement the top level module using XST synthesizer.

5.8 SYNTHESIS RESULT

The developed convolution project is simulated and verified their

functionality. Once the functional verification is done, the RTL model is taken to

the synthesis process using the Xilinx ISE tool. In synthesis process, the RTL

model will be converted to the gate level net-list mapped to a specific technology

library. Here in this Spartan 3E family, many different devices were available in

the Xilinx ISE tool.The target device is SPARTAN 2 FPGA kit.In order to

synthesis this design the device named as “XC3S100E” has been chosen and the

package as “TQ144” with the device speed such as “5”.

5.8.1 Synthesis Results

The developed convolution project is simulated and verified their

functionality. Once the functional verification is done, the RTL model is taken to

the synthesis process using the Xilinx ISE tool. In synthesis process, the RTL

model will be converted to the gate level netlist mapped to a specific technology

library. Here in this Spartan 3E family, many different devices were available in

the Xilinx ISE tool. In order to synthesis this design the device named as

“XC3S500E” has been chosen and the package as “FG320” with the device speed

such as “-4”.

This design is synthesized and its results were analyzed as follows.

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FIGURE 5.22 :Design or pin diagram.

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FIGURE 5.23: Synthesis Result 1.

FIGURE 5.24: Synthesis Result 2.

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PROGRAM CODES FOR INDIVIDUAL MODULES

Program for 4*1 Mux:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;

entity MUX41 is port(CLK,RST:in std_logic; LOAD:BUFFER std_logic; S1:in std_logic_vector(1 downto 0); IN0,IN1,IN2,IN3:in std_logic_vector (3 downto 0); PO:out std_logic_vector(3 downto 0));end entity;

Program for SIPO:

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;

entity SIPO is port(CLK,L:in std_logic; SIN:in std_logic_vector(3 downto 0); POUT0,POUT1,POUT2,POUT3:buffer std_logic_vector(3 downto 0));end entity;

architecture SIPO of SIPO is type ARR is array(3 downto 0)of std_logic_vector(3 downto 0); signal MEM:ARR; signal COUNT: integer range 0 to 4;

begin process(CLK,L,SIN)is --variable COUNT: integer range 0 to 4; begin if(L='0')then COUNT<=0; POUT0<=(others=>'0'); POUT1<=(others=>'0'); POUT2<=(others=>'0');

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POUT3<=(others=>'0'); MEM<=(others=>(others=>'0')); else if(CLK'EVENT and CLK='1')then if(COUNT<=3)then MEM(COUNT)<=SIN; COUNT<=COUNT + 1; else POUT0<=MEM(0); POUT1<=MEM(1); POUT2<=MEM(2); POUT3<=MEM(3); end if; end if; end if; end process; end SIPO;

Program for Binary Multiplier:

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;

entity MUL IS PORT(CLK,RST:in std_logic; LD:buffer std_logic; A0,A1,A2,A3,B0,B1,B2,B3:in std_logic_vector(3 downto 0); S0,S1,S2,S3,S4,S5,S6:out std_logic_vector(7 downto 0));end entity;

architecture M of MUL isSignal S11,S12,S13,S14,S21,S22,S23,S24,S31,S32,S33,S34,S41,S42,S43,S44:std_logic_vector(7 downto 0);--signal SX0,SX1,SX2,SX3,SX4,SX5,SX6: signed(7 downto 0);Begin S11<=A0*B0; S12<=A1*B0; S13<=A2*B0; S14<=A3*B0; S21<=A0*B1; S22<=A1*B1; S23<=A2*B1; S24<=A3*B1

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S31<=A0*B2; S32<=A1*B2; S33<=A2*B2; S34<=A3*B2; S41<=A0*B3; S42<=A1*B3; S43<=A2*B3; S44<=A3*B3; process(CLK,RST,A0,A1,A2,A3,B0,B1,B2,B3)is begin if(CLK'EVENT and CLK='1')then if(RST='0')then S0<="00000000"; S1<="00000000"; S2<="00000000"; S3<="00000000"; S4<="00000000"; S5<="00000000"; S6<="00000000"; LD<='0'; else S0<=S11; S1<=S12 + S21; S2<=S13 + S22 + S31; S3<=S14 + S23 + S32 + S41; S4<=S24 + S33 + S42; S5<=S34 + S43; S6<=S44; LD<='1'; end if; end if; end process; --SX0<=S11; --SX1<=S12 + S21; --SX2<=S13 + S22 + S31; --SX3<=S14 + S23 + S32 + S41; --SX4<=S24 + S33 + S42; --SX5<=S34 + S43; --SX6<=S44; END;

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Program for 8*1 Mux:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;

entity MUX81 is port(CLK,RST:in std_logic; S2:in std_logic_vector(2 downto 0); I0,I1,I2,I3,I4,I5,I6:in std_logic_vector (7 downto 0); YO:out std_logic_vector(7 downto 0));end entity;

architecture MUX2 of MUX81 isbegin process(CLK,RST,S2)is begin if(CLK'EVENT and CLK='1')then if(RST='0')then YO<="00000000"; else case S2 is when "000"=>YO<=I0; when "001"=>YO<=I1; when "010"=>YO<=I2; when "011"=>YO<=I3; when "100"=>YO<=I4; when "101"=>YO<=I5; when "110"=>YO<=I6; when others=>YO<="ZZZZZZZZ"; end case; end if; end if; end process; end MUX2;

Program for Register:

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;

entity REG8 is port(CLK,RST:in std_logic; RIN:in std_logic_vector(7 downto 0);

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RO:out std_logic_vector(7 downto 0));end entity;

architecture REG of REG8 isbegin process(CLK,RST,RIN)is begin if(CLK'EVENT and CLK='1')then if(RST='0')then RO<="00000000"; else RO<=RIN; end if; end if; end process; end REG;

Program for Convolution:

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;

entity CONVOLUTION4 IS port(CLK,RST:in std_logic; SE1:in std_logic_vector(1 downto 0); SE2:in std_logic_vector(2 downto 0); A0,A1,A2,A3,B0,B1,B2,B3:in std_logic_vector(3 downto 0); CONVOLUTION_OUT:out std_logic_vector(7 downto 0));end entity;

architecture CONVOLUTION of CONVOLUTION4 is

component MUX41 is port(CLK,RST:in std_logic; LOAD:BUFFER std_logic; S1:in std_logic_vector(1 downto 0); IN0,IN1,IN2,IN3:in std_logic_vector (3 downto 0); PO:out std_logic_vector(3 downto 0)); end component; component SIPO is port(CLK,L:in std_logic; SIN:in std_logic_vector(3 downto 0); POUT0,POUT1,POUT2,POUT3:buffer std_logic_vector(3 downto 0)); end component;

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component MUL IS PORT(CLK,RST:in std_logic; LD:buffer std_logic; A0,A1,A2,A3,B0,B1,B2,B3:in std_logic_vector(3 downto 0); S0,S1,S2,S3,S4,S5,S6:out std_logic_vector(7 downto 0)); end component;

component MUX81 is port(CLK,RST:in std_logic; S2:in std_logic_vector(2 downto 0); I0,I1,I2,I3,I4,I5,I6:in std_logic_vector (7 downto 0); YO:out std_logic_vector(7 downto 0)); end component; component REG8 is port(CLK,RST:in std_logic; RIN:in std_logic_vector(7 downto 0); RO:out std_logic_vector(7 downto 0)); end component; signal MX1,MX2,P01,P02,P03,P04,P11,P12,P13,P14:std_logic_vector(3downto 0); signal SM0,SM1,SM2,SM3,SM4,SM5,SM6,MO:std_logic_vector(7 downto 0); SIGNAL L1,L2,LD1:std_logic; begin M1:MUX41 port map (CLK=>CLK, RST=>RST, LOAD=>L1, S1=>SE1, IN0=>A0, IN1=>A1, IN2=>A2, IN3=>A3, PO=>MX1); M2:MUX41 port map (CLK=>CLK, RST=>RST, LOAD=>L2, S1=>SE1, IN0=>B0, IN1=>B1, IN2=>B2, IN3=>B3, PO=>MX2);

SIPO1:SIPO port map(CLK=>CLK,

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L=>L1, SIN=>MX1, POUT0=>P01, POUT1=>P02, POUT2=>P03, POUT3=>P04); SIPO2:SIPO port map(CLK=>CLK, L=>L2, SIN=>MX2, POUT0=>P11, POUT1=>P12, POUT2=>P13, POUT3=>P14); MULT:MUL port map(CLK=>CLK, RST=>RST, LD=>LD1, A0=>P01, A1=>P02, A2=>P03, A3=>P04, B0=>P11, B1=>P12, B2=>P13, B3=>P14, S0=>SM0, S1=>SM1, S2=>SM2, S3=>SM3, S4=>SM4, S5=>SM5, S6=>SM6); MUX8:MUX81 port map (CLK=>CLK, RST=>LD1, S2=>SE2, I0=>SM0, I1=>SM1, I2=>SM2, I3=>SM3, I4=>SM4, I5=>SM5, I6=>SM6, YO=>MO); REG1:REG8 port map (CLK=>CLK, RST=>RST,

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RIN=>MO, RO=>CONVOLUTION_OUT); end CONVOLUTION;

CONCLUSION

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We presented an optimized implementation of discrete linear convolution.

This particular model has the advantage of being fine tuned for signal processing;

in this case it uses the mean squared error measurement and objective measures of

enhancement to achieve a more effective signal processing model. This

implementation has the advantage of being optimized based on operation, power

and area. To accurately analyze our proposed system, we have coded our design

using the Verilog hardware description language and have synthesized it for

FPGA products using ISE, Modelsim and DC compiler for other processor usage.

The proposed circuit uses only 5mw and saves almost 35% area and it

takes 20ns to complete. This shows improvement of more than 50% less power.

As FPGA technology matures and much larger arrays become practical,

techniques that allow the automatic generation of highly-parallel architectures will

become central to high performance computing.

We have also described some simple techniques for generation of

convolution pipelines for image processing and other applications. Higher level

techniques and approaches are also needed. FPGAs permit restructurable

processing, and restructurable interconnects are also becoming available.

FUTURE SCOPE

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Extracting a periodic signal from noise.

Software Applications:

GUI Module.

Echo Detection in Linear acoustics.

Speech Analysis and pitch.

In time-resolved Fluorescence Spectroscopy.

In Radiotherapy treatment planning systems , most part of all modern codes

can use convolution.

In Computational fluid Dynamics.

In digital image processing , convolutional filtering plays an important role in

many important algorithms in edge detection and related processes.

In Optics, many kinds of "blur" are described by convolutions.

In Probability theory.

In kernel density estimation, a distribution is estimated from sample points by

convolution with a kernel, such as an isotropic Gaussian.

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