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All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Comprehensive Low Power Design Analysis and Optimization
An RTL to GDSII Approach
Aveek Sarkar and Ronen Stilkol
Apache Design Solutions
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Power: The Metric For Chip Success
Battery performance ~ f(operational and standby current)
Current Drawn
Operational current
~ f(switching, short-circuit current)
~ f(logic, mode, frequency, library, PVT)
Standby current
~ f(sub-threshold/gate/junction leakage)
~ f(circuit, library, PVT)
Heat dissipation ~ f(current drawn, supply voltage)
Power dissipated = voltage X current
2
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Trends in Current Draw and Power Dissipation
Both dynamic and standby (leakage
currents) increasing with process
Need to control both
Supply voltage cannot scale
sufficiently fast
Threshold voltage does not scale
3
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Po
wer
Number of RTL edits
4
Current and Voltage as Design Targets
Circuit changes to “reduce”
current increases voltage fluctuation
Reduced supply voltage +
increased fluctuation affects NM
1
1 Predict power accurately “early”
2 Predict power reduction possible
2
3 Identify achievable design changes
3
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Physical Implementation& Signoff
RTL Design & reduction
Power in the RTLGDSII Flow
Floor-planning& Synthesis
Target power reduction early in the design flow
Ensure design verification to predict
voltage drop noise from low power
techniques
Power reduction Usage Curve
Power Integrity Usage Curve
Chip-Package-System Convergence
5
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Techniques for Power ReductionAn Analysis Driven Approach
Early yet accurate analysis
Before synthesis (logic)
Before routing (cap)
Analysis driven reduction
Rapid, early identification of power
hot-spots
Power gating and voltage island
prototyping
Predictable power reduction:
clock, memory, datapath
Power vs implementation overhead
6
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Operational Power Reduction Clock Tree Optimization
7
RTL: Add and Improve Clock Enables
Non-enabledEnabled
selsel sel_1dsel_1d
11
R2R2
D
RTL reductions make clock gating more effectiveRTL reductions make clock gating more effective
EN
CLKCG
GCLK
D
EN
CLK
D
Synthesis: Clock Gating
RTL
Gates
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Operational Power Reduction Datapath Optimization
8
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Standby Power Reduction Power Gating
Power Gating Options
He
ad
er
Sw
itc
he
sF
oo
ter
Sw
itc
he
s
Block
Vdd
Vss
CTL
Block
Vss
Vdd
CTL
Dual Switches
Dual Switches
cntl1
cntl2
ExtVSS
IntVSS
ExtVDD
IntVDD
Advanced power gating modes give
significant “standby” mode saving
Requires careful design and layout
9
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Power gated domain transitions from
off- to on-state
If in a driver-receiver pair, the receiver
supply ramps up first, it causes high
crowbar current scenario
Constant activity Mode
Clock gating mode
10
Power gating Clock gating
Clock mode transitions generate transient event causing Ldi/dt noise
Impact of Low Power Design Techniques on Power Integrity
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Impact of Design and Process Changes on Silicon Integrity
11
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Change in ESC/ESR for a decap cellNormalized against 130nm
Low Power Design Verification Challenges
12
Impact of package
Connection to die
Package routing and layers
Impact of decap
Decreasing efficiency
Leakage current trade-off
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Power Integrity Analysis for Low Power Designs
13
DC (IR):
Static IR, power/signal EM
Transient (Ldi/dt + iR)
Functional mode
Test-mode (L/MBIST, scan)
Clock gating transition
Ramp-up and mixed-mode
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
Case StudiesBump Placement and Package Issues Highlighted
High drop area
High switching activity
Insufficient number of bumps
Incorrect package routing
Cluster of high power cells
Driving high load
Firing at same time
Insufficient package layers
Routing congestion
Fragmented routing ~ high L
L di / dt ~ high DvD
14
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
RTL to GDS CPS Convergence
Chip Package System ConvergenceAn RTL to GDSII Focus
04/11/23 ,15
RTL Design & reduction
RTL Power Reduction
RTL Power Reduction
RTL Power Analysis
RTL Power Analysis
Floor-planning& Synthesis
PG, IO Planning
Early CPM
PG, IO Planning
Early CPM
Package/PCBplanning
Package/PCBplanning
Physical Implementation
& Signoff
IP ValidationSoC AnalysisTiming Impact
IP ValidationSoC AnalysisTiming Impact
CPS sign-off+ cost downCPS sign-off+ cost down
15
All you need to know about chip design, testing & manufacturing
Israel, May 4, 2010
I.Calhoun, B and Chandrakasan, A, “Static Noise Margin Variation for Sub-Threshold SRAM in 65-nm CMOS”, IEEE Journal of Solid State Circuits, vol 41, no 7, July 2006.II.Cadence Design Systems, “A Practical Guide to Low-Power Design: User Experience with CPF”, Cadence Design Systems whitepaper, May 2008.III.N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M. J. Irwin, M. Kandemir and V. Narayanan, “Leakage Current: Moore's Law Meets Static Power”, IEEE Transactions on Computers, Vol. 36, No. 12, December 2003, pp. 68-77.IV.L. K. Yong, F. Tan and C. S. Lee, “Power Noise Mitigation Strategy from RTL Perspective on MTCMOS Design”, DAC User Track presentation, DAC 2010, to appear.V.A. Sarkar, “Power Noise Analysis for Next Generation ICs”, Apache Design Solutions whitepaper, June 2009.
Selected References
16