Basics electronics microprocessor

BASICS OF ELECTRONICS

AND

MICROPROCESSOR

CHAPTER 1

DIGITAL ELECTRONICS

1.1 Introduction

One of the first things we have to know is that electronics can be broadly classified into two

groups, viz. analog electronics and digital electronics. Analog electronics deals with things that

are continuous in nature and digital electronics deals with things that are discrete in nature. But

they are very much interlinked. For example, if we consider a bucket of water, then it is analog

in terms of the content i.e., water, but it is discrete in terms of the container, i.e., bucket. Now

though in nature most things are analog, still we very often require digital concepts. It is because

it has some specific advantages over analog, which we will discuss in due course of time.

Many of us are accustomed with the working of electronic amplifiers. Generally they are

used to amplify electronic signals. Now these signals usually have a continuous value and hence

can take up any value within a given range, and are known as analog signals. The electronic

circuits which are used to process such signals are called analog circuits and the circuits based

on such operation are called analog systems.

On the other side, in a computer, the input is given with the help of the switches. Then

this is converted into electronic signals, which have two distinct discrete levels or values. One of

them is called HIGH level whereas the other is called LOW level. The signal must always be in

either of the two levels. As long as the signal is within a prespecified range of HIGH and LOW,

the actual value of the signal is not that important. Such signals are called digital signals and the

circuit within the device is called a digital circuit. The system based on such a concept is an

example of a digital system.

Since Claude Shannon systemized and adapted the theoretical work of George Boole in 1938,

digital techniques saw a tremendous growth. Together with developments in semiconductor

technology, and with the progress in digital technology, a revolution in digital electronics

happened when the microprocessor was introduced in 1971 by Intel Corporation of America. At

present, digital technology has progressed much from the era of vacuum tube circuits to

integrated circuits. Digital circuits find applications in computers, telephony, radar navigation,

data processing, and many other applications. The general properties of number systems,

methods of their interconversions, and arithmetic operations are discussed in this chapter.

1.2 Number System

There are several number systems which we normally use, such as decimal, binary, octal,

hexadecimal, etc. Amongst them we are most familiar with the decimal number system. These

systems are classified according to the values of the base of the number system. The number

system having the value of the base as 10 is called a decimal number system, whereas that with a

base of 2 is called a binary number system. Likewise, the number systems having base 8 and 16

are called octal and hexadecimal number systems respectively.

With a decimal system we have 10 different digits, which are 0, 1, 2, 3, 4, 5, 6, 7, 8, and

9. But a binary system has only 2 different digits—0 and 1. Hence, a binary number cannot have

any digit other than 0 or 1. So to deal with a binary number system is quite easier than a decimal

system. Now, in a digital world, we can think in binary nature, e.g., a light can be either off or

on. There is no state in between these two. So we generally use the binary system when we deal

with the digital world. Here comes the utility of a binary system. We can express everything in

the world with the help of only two digits i.e., 0 and 1. For example, if we want to express 2510 in

binary we may write 110012. The right most digit in a number system is called the ‗Least

Significant Bit‘ (LSB) or ‗Least Significant Digit‘ (LSD). And the left most digit in a number

system is called the ‗Most Significant Bit‘ (MSB) or ‗Most Significant Digit‘ (MSD). Now

normally when we deal with different number systems we specify the base as the subscript to

make it clear which number system is being used.

In an octal number system there are 8 digits—0, 1, 2, 3, 4, 5, 6, and 7. Hence, any octal

number cannot have any digit greater than 7. Similarly, a hexadecimal number system has 16

digits—0 to 9— and the rest of the six digits are specified by letter symbols as A, B, C, D, E, and

F. Here A, B, C, D, E, and F represent decimal 10, 11, 12, 13, 14, and 15 respectively. Octal and

hexadecimal codes are useful to write assembly level language.

In general, we can express any number in any base or radix ―X.‖ Any number with base

X, having n digits to the left and m digits to the right of the decimal point can be expressed as:

anXn-1

+ an-1Xn-2

+ an-2Xn-3

+ …. + a2X1 + a1X

0 + b1X

-1 + b2X

-2 + …. + bmX

-m

where an is the digit in the nth position. The coefficient an is termed as the MSD or Most

Significant Digit and bm is termed as the LSD or the Least Significant Digit.

1.2.1 Conversion between Number System

It is often required to convert a number in a particular number system to any other number

system, e.g., it may be required to convert a decimal number to binary or octal or hexadecimal.

The reverse is also true, i.e., a binary number may be converted into decimal and so on. The

methods of interconversions are now discussed.

1.2.1.1 Decimal-to-Binary Conversion

Now to convert a number in decimal to a number in binary we have to divide the decimal

number by 2 repeatedly, until the quotient of zero is obtained. This method of repeated division

by 2 is called the ‗double-dabble‘ method. The remainders are noted down for each

of the division steps. Then the column of the remainder is read in reverse order i.e., from bottom

to top order. We try to show the method with an example shown in Example 1.1.

Example 1.1. Convert 2610 into a binary number.

Solution. Division Quotient Generated remainder

26/2 13 0

13/2 6 1

6/2 3 0

3/2 1 1

1/2 0 1

Hence the converted binary number is 110102.

1.2.1.2 Decimal-to-Octal Conversion

Similarly, to convert a number in decimal to a number in octal we have to divide the decimal

number by 8 repeatedly, until the quotient of zero is obtained. This method of repeated division

by 8 is called ‗octal-dabble.‘ The remainders are noted down for each of the division steps. Then

the column of the remainder is read from bottom to top order, just as in the case of the double-

dabble method. We try to illustrate the method with an example shown in Example 1.2.

Example 1.2. Convert 42610 into an octal number.


426/8 53 2

53/8 6 5

6/8 0 6

Hence the converted octal number is 6528.

1.2.1.3 Decimal-to-Hexadecimal Conversion

The same steps are repeated to convert a number in decimal to a number in hexadecimal. Only

here we have to divide the decimal number by 16 repeatedly, until the quotient of zero is

obtained. This method of repeated division by 16 is called ‗hex-dabble.‘ The remainders are

noted down for each of the division steps. Then the column of the remainder is read from bottom

to top order as in the two previous cases. We try to discuss the method with an example shown in

Example 1.3.

Example 1.3. Convert 34810 into a hexadecimal number.


348/16 21 12

21/16 1 5

1/16 0 1

Hence the converted hexadecimal number is 15C16.

1.2.1.4 Binary-to-Decimal Conversion

Now we discuss the reverse method, i.e., the method of conversion of binary, octal, or

hexadecimal numbers to decimal numbers. Now we have to keep in mind that each of the binary,

octal, or hexadecimal number system is a positional number system, i.e., each of the digits in the

number systems discussed above has a positional weight as in the case of the decimal system.

We illustrate the process with the help of examples.

Example 1.4. Convert 101102 into a decimal number.

Solution. The binary number given is 1 0 1 1 0

Positional weights 4 3 2 1 0

The positional weights for each of the digits are written in italics below each digit. Hence

the decimal equivalent number is given as:

1*24 + 0*2

3 + 1*2

2 + 1*2

1 + 0*2

0

= 16 + 0 + 4 + 2 + 0

= 2210

Hence we find that here, for the sake of conversion, we have to multiply each bit with its

positional weights depending on the base of the number system.

1.2.1.5 Octal-to-Decimal Conversion

Example 1.5. Convert 34628 into a decimal number.

Solution. The octal number given is 3 4 6 2

Positional weights 3 2 1 0

The positional weights for each of the digits are written in italics below each digit. Hence the

decimal equivalent number is given as:

= 3*83 + 4*8

2 + 6*8

1 + 2*8

0

= 1536 + 256 + 48 + 2

= 184210

1.2.1.6 Hexadecimal-to-Decimal Conversion

Example 1.6. Convert 42AD16 into a decimal number.

Solution. The hexadecimal number given is 4 2 A D

Positional weights 3 2 1 0



= 4*163 + 2*16

2 + 10*16

1 + 13*16

0

= 16384 + 512 + 160 + 13

= 1706910

1.2.1.7 Fractional Conversion

So far we have dealt with the conversion of integer numbers only. Now if the number contains

the fractional part we have to deal in a different way when converting the number from a

different number system (i.e., binary, octal, or hexadecimal) to a decimal number system or vice

versa. We illustrate this with examples.

Example 1.7. Convert 1010.0112 into a decimal number.

Solution. The binary number given is 1 0 1 0. 0 1 1

Positional weights 3 2 1 0 -1-2-3



= 1*23 + 0*2

2 + 1*2

1 + 0*2

0 + 0*2

-1 + 1*2

-2 + 1*2

-3

= 8 + 0 + 2 + 0 + 0 + .25 + .125

= 10.37510

Example 1.8. Convert 362.358 into a decimal number.

Solution. The octal number given is 3 6 2. 3 5

Positional weights 2 1 0 -1-2



= 3*82 + 6*8

1 + 2*8

0 + 3*8

-1 + 5*8

-2

= 192 + 48 + 2 + .37 + .078125

= 242.45212510

Example 1.9. Convert 42A.1216 into a decimal number.

Solution. The hexadecimal number given is 4 2 A. 1 2

Positional weights 2 1 0 -1-2



= 4*162 + 2*16

1 + 10*16

0 + 1*16

-1 + 2*16

-2

= 1024 + 32 + 10 + .0625 + .00393625

= 1066.06640621510

Example 1.10. Convert 25.62510 into a binary number.


25/2 12 1

12/2 6 0

6/2 3 0

3/2 1 1

1/2 0 1

Therefore, (25)10 = (11001)2

Fractional Part

.625 * 2 = 1.250 1

.250 * 2 = .500 0

.500 * 2 = 1.000 1

i.e., (0.625)10 = (0.101)2

Therefore, (25.625)10 = (11001.101)2

Example 1.11. Convert 34.52510 into an octal number.


34/8 4 2

4/8 0 4

Therefore, (34)10 = (42)8

Fractional Part

.525 * 8 = 4.200 4

.200 * 8 = 1.600 1

.600 * 8 = 4.800 4

i.e., (0.525)10 = (0.414)8

Therefore, (34.525)10 = (42.411)8

Example 1.12. Convert 92.8510 into a hexadecimal number.


92/16 5 12

5/16 0 5

Therefore, (92)10 = (5C)16

Fractional Part

.85 * 16 = 13.60 13

.60 * 16 = 9.60 9

i.e., (0.85)10 = (0.D9)16

Therefore, (92.85)10 = (5C.D9)16

1.2.1.8 Conversion from a Binary to Octal Number and Vice Versa

We know that the maximum digit in an octal number system is 7, which can be represented as

1112 in a binary system. Hence, starting from the LSB, we group three digits at a time and

replace them by the decimal equivalent of those groups and we get the final octal number.

Example 1.13. Convert 1011010102 into an equivalent octal number.

Solution. The binary number given is 101101010

Starting with LSB and grouping 3 bits 101 101 010

Octal equivalent 5 5 2

Hence the octal equivalent number is (552)8.

Example 1.14. Convert 10111102 into an equivalent octal number.



Octal equivalent 1 3 6

Hence the octal equivalent number is (176)8.

Since at the time of grouping the three digits in Example 1.14 starting from the LSB, we find that

the third group cannot be completed, since only one 1 is left out in the third group, so we

complete the group by adding two 0s in the MSB side. This is called left padding of the number

with 0. Now if the number has a fractional part then there will be two different classes of

groups—one for the integer part starting from the left of the decimal point and proceeding

toward the left and the second one starting from the right of the decimal point and proceeding

toward the right. If, for the second class, any 1 is left out, we complete the group by adding two

0s on the right side. This is called right-padding.

Example 1.15. Convert 1101.01112 into an equivalent octal number.

Solution. The binary number given is 1101.0111

Grouping 3 bits 001 101. 011 100

Octal equivalent: 1 5 3 4

Hence the octal number is (15.34)8.

Now if the octal number is given and you're asked to convert it into its binary equivalent,

then each octal digit is converted into a 3-bit-equivalent binary number and—combining all

those digits we get the final binary equivalent.

Example 1.16. Convert 2358 into an equivalent binary number.

Solution. The octal number given is 2 3 5

3-bit binary equivalent 010 011 101

Hence the binary number is (010011101)2.

Example 1.17. Convert 47.3218 into an equivalent binary number.

Solution. The octal number given is 4 7 3 2 1

3-bit binary equivalent 100 111 011 010 001

Hence the binary number is (100111.011010001)2.

1.2.1.9 Conversion from a Binary to Hexadecimal Number and Vice Versa

We know that the maximum digit in a hexadecimal system is 15, which can be represented by

11112 in a binary system. Hence, starting from the LSB, we group four digits at a time and

replace them with the hexadecimal equivalent of those groups and we get the final hexadecimal

number.

Example 1.18. Convert 110101102 into an equivalent hexadecimal number.


Starting with LSB and grouping 4 bits 1101 0110

Hexadecimal equivalent D 6

Hence the hexadecimal equivalent number is (D6)16.

Example 1.19. Convert 1100111102 into an equivalent hexadecimal number.



Hexadecimal equivalent 1 9 E

Hence the hexadecimal equivalent number is (19E)16.

Since at the time of grouping of four digits starting from the LSB, in Example 1.19 we

find that the third group cannot be completed, since only one 1 is left out, so we complete the

group by adding three 0s to the MSB side. Now if the number has a fractional part, as in the case

of octal numbers, then there will be two different classes of groups—one for the integer part

starting from the left of the decimal point and proceeding toward the left and the second one

starting from the right of the decimal point and proceeding toward the right. If, for the second

class, any uncompleted group is left out, we complete the group by adding 0s on the right side.

Example 1.20. Convert 111011.0112 into an equivalent hexadecimal number.

Solution. The binary number given is 111011.011

Grouping 4 bits 0011 1011. 0110

Hexadecimal equivalent 3 B 6

Hence the hexadecimal equivalent number is (3B.6)16.

Now if the hexadecimal number is given and you're asked to convert it into its binary

equivalent, then each hexadecimal digit is converted into a 4-bit-equivalent binary number and

by combining all those digits we get the final binary equivalent.

Example 1.21. Convert 29C16 into an equivalent binary number.

Solution. The hexadecimal number given is 2 9 C

4-bit binary equivalent 0010 1001 1100

Hence the equivalent binary number is (001010011100)2.

Example 1.22. Convert 9E.AF216 into an equivalent binary number.

Solution. The hexadecimal number given is 9 E.A F 2

4-bit binary equivalent 1001 1110 1010 1111 0010

Hence the equivalent binary number is (10011110.101011110010)2.

1.2.1.10 Conversion from an Octal to Hexadecimal Number and Vice Versa

Conversion from octal to hexadecimal and vice versa is sometimes required. To convert an octal

number into a hexadecimal number the following steps are to be followed:

i. First convert the octal number to its binary equivalent (as already discussed above).

ii. Then form groups of 4 bits, starting from the LSB.

iii. Then write the equivalent hexadecimal number for each group of 4 bits.

Similarly, for converting a hexadecimal number into an octal number the following steps are to

be followed:

i. First convert the hexadecimal number to its binary equivalent.

ii. Then form groups of 3 bits, starting from the LSB.

iii. Then write the equivalent octal number for each group of 3 bits.

Example 1.23. Convert the following hexadecimal numbers into equivalent octal numbers.

(a) A72E (b) 4.BF85

Solution.

(a) Given hexadecimal number is A 7 2 E

Binary equivalent is 1010 0111 0010 1110

= 1010011100101110

Forming groups of 3 bits from the LSB 001 010 011 100 101 110

Octal equivalent 1 2 3 4 5 6

Hence the octal equivalent of (A72E)16 is (123456)8.

(b) Given hexadecimal number is 4 B F 8 5

Binary equivalent is 0100 1011 1111 1000 0101

= 0100.1011111110000101

Forming groups of 3 bits 100. 101 111 111 000 010 100

Octal equivalent 4 5 7 7 0 2 4

Hence the octal equivalent of (4.BF85)16 is (4.577024)8.

Example 1.24. Convert (247)8 into an equivalent hexadecimal number.

Solution. Given octal number is 2 4 7

Binary equivalent is 010 100 111

= 010100111

Forming groups of 4 bits from the LSB 1010 0111

Hexadecimal equivalent A 7

Hence the hexadecimal equivalent of (247)8 is (A7)16.

Example 1.25. Convert (36.532)8 into an equivalent hexadecimal number.

Solution. Given octal number is 3 6 5 3 2

Binary equivalent is 011 110 101 011 010

= 011110.101011010

Forming groups of 4 bits 0001 1110. 1010 1101

Hexadecimal equivalent 1 E. A D

Hence the hexadecimal equivalent of (36.532)8 is (1E.AD)16.

1.2.2 Complements

Complements are used in digital computers for simplifying the subtraction operation and for

logical manipulations. There are two types of complements for each number system of base-r:

the r‘s complement and the (r – 1)‘s complement. When we deal with a binary system the value

of r is 2 and hence the complements are 2‘s and 1‘s complements. Similarly for a decimal system

the value of r is 10 and we get 10‘s and 9‘s complements. With the same logic if the number

system is octal we get 8‘s and 7‘s complement, while it is 16‘s and 15‘s complements for

hexadecimal system.

1.2.2.1 The r’s Complement

If a positive number N is given in base r with an integer part of n digits, the r‘s complement of N

is given as rn–N for N != 0 and 0 for N = 0. The following examples will clarify the definition.

The 10‘s complement of (23450)10 is 105 – 23450 = 76550.

The number of digits in the number is n = 5.

The 10‘s complement of (0.3245)10 is 100 – 0.3245 = 0.6755.

Since the number of digits in the integer part of the number is n = 0, we have 100 = 1.

The 10‘s complement of (23.324)10 is 102 – 23.324 = 76.676.

The number of digits in the integer part of the number is n = 2.

Now if we consider a binary system, then r = 2.

The 2‘s complement of (10110)2 is (25)10–(10110)2 = (100000 – 10110)2 = 01010.

The 2‘s complement of (0.1011)2 is (20)10–(0.1011)2 = (1 – 0.1011)2 = 0.0101.

Now if we consider an octal system, then r = 8.

The 8‘s complement of (2450)8 is (84)10 – (2450)8.

= (409610 – 24508)

= (409610 – 132010)

= 277610.

= 53308.

Now if we consider a hexadecimal system, then r = 16.

The 16‘s complement of (4A30)16 is (164)10 – (4A30)16

= (6553610 – 4A3016)

= (6553610 – 1899210)

= 4654410

= B5D016.

From the above examples, it is clear that to find the 10‘s complement of a decimal number all of

the bits until the first significant 0 is left unchanged and the first nonzero least-significant digit is

subtracted from 10 and the rest of the higher significant digits are subtracted from 9. With a

similar reasoning, the 2‘s complement of a binary number can be obtained by leaving all of the

least significant zeros and the first nonzero digit unchanged, and then replacing 1‘s with 0‘s and

0‘s with 1‘s. Similarly the 8‘s complement of an octal number can be obtained by keeping all the

bits until the first significant 0 is unchanged, and the first non zero least significant digit is

subtracted from 8 and the rest of the higher significant digits are subtracted from 7. Similarly, the

16‘s complement of a hexadecimal number can be obtained by keeping all the bits until the first

significant 0 is unchanged, and the first nonzero least-significant digit is subtracted from 16 and

the rest of the higher significant digits are subtracted from 15. Since r‘s complement is a general

term, r can take any value e.g., r = 11. Then we will have 11‘s complement for r‘s complement

case and 10‘s complement for (r – 1)‘s complement case.

1.2.2.2 The (r–1)’s Complement

If a positive number N is given in base r with an integer part of n digits and a fraction part of m

digits, then the (r – 1)‘s complement of N is given as (rn – r

–m– N) for N 0 and 0 for N = 0. The

following examples will clarify the definition.

The 9‘s complement of (23450)10

is 105 – 10

0 – 23450 = 76549.

Since there is no fraction part, 10–m

= 100 = 1.

The 9‘s complement of (0.3245)10

is 100 – 10

–4 – 0.3245 = 0.6754.

Since there is no integer part, 10n = 10

0 = 1.

The 9‘s complement of (23.324)10

is 102

– 10–3

– 23.324 = 76.675.

Now if we consider a binary system, then r = 2, i.e., (r – 1) = 1.

The 1‘s complement of (10110)2 is (25–1)10 – (10110)2 = 01001.

The 1‘s complement of (0.1011)2 is (1–2–4

)10 – (0.1011)2 = 0.0100.

Now if we consider an octal system, then r = 8, i.e., (r – 1) = 7.

The 7‘s complement of (2350)8 is 84 – 8

0 – 23508

= 409510 – 125610

= 283910

= 54278.

The 15‘s complement of (A3E4)16 is 164 – 16

0 – A3E416

= 6553510 – 4195610

= 2357910

= 5C1B16.

From the above examples, it is clear that to find the 9‘s complement of a decimal number each of

the digits can be separately subtracted from 9. The 1‘s complement of a binary number can be

obtained by changing 1s into 0s and 0s into 1s. Similarly, to find the 7‘s complement of a

decimal number each of the digits can be separately subtracted from 7. Again, to find the 15‘s

complement of a decimal number each of the digits can be separately subtracted from 15.

Example 1.26. Find out the 11‘s and 10‘s complement of the number (576)11.

Solution.

The number in base is 11. So to find 11‘s complement we have to follow the r‘s complement rule

and in order to get 10‘s complement the (r – 1)‘s complement rule is to be followed.

11‘s complement:

rn – N = 11

3 – 57611

= (1331)10 – (576)11

Now, 57611 = 5 × 112 + 7 × 11

1 + 6 × 11

0

= 605 + 77 + 6

= 68810

Therefore, 11‘s complement is 133110 – 68810 = 64310

Now, the decimal number has to be changed in the number system of base 11.

Division Quotient Generated remainder

643/11 58 5

58/11 5 3

5/11 0 5

Hence the 11‘s complement number is (535)11.

10‘s complement:

rn – r

–m – N = 11

3 – 11

0 – 57611

= (1331)10 – (1)10 – (576)11

Therefore, 10‘s complement is 133110 – 110 – 68810 = 64210

Now, the decimal number has to be changed in the number system of base 11.

Division Quotient Generated remainder

642/11 58 4

58/11 5 3

5/11 0 5

Hence the 10‘s complement number is (534)11.

1.2.3 Binary Arithmetic

We are very familiar with different arithmetic operations, viz. addition, subtraction,

multiplication, and division in a decimal system. Now we want to find out how those same

operations may be performed in a binary system, where only two digits, viz. 0 and 1 exist.

1.2.3.1 Binary Addition

The rules of binary addition are given in Table 1.1.

Table 1.1

Augend Addend Sum Carry Result

0

0

1

1

0

1

0

1

0

1

1

0

0

0

0

1

0

1

1

10

The procedure of adding two binary numbers is same as that of two decimal numbers. Addition

is carried out from the LSB and it proceeds to higher significant bits, adding the carry resulting

from the addition of two previous bits each time.

1.2.3.2 Binary Subtraction

The rules of binary subtraction are given in Table 1.2.

Table 1.2

Minuend Subtrahend Difference Borrow

0

0

1

1

0

1

0

1

0

1

1

0

0

1

0

0

Binary subtraction is also carried out in a similar method to decimal subtraction. The subtraction

is carried out from the LSB and proceeds to the higher significant bits. When borrow is 1, as in

the second row, this is to be subtracted from the next higher binary bit as it is performed in

decimal subtraction.

Actually, the subtraction between two numbers can be performed in three ways, viz.

a. the direct method,

b. the r‘s complement method, and

c. the (r – 1)‘s complement method.

Subtraction Using the Direct Method

The direct method of subtraction uses the concept of borrow. In this method, we borrow a 1

from a higher significant position when the minuend digit is smaller than the corresponding

subtrahend digit.

1.2.3.3 Binary Multiplication

Binary multiplication is similar to decimal multiplication but much simpler than that. In a binary

system each partial product is either zero (multiplication by 0) or exactly the same as the

multiplicand (multiplication by 1). The rules of binary multiplication are given in Table 1.3.

Table 1.3

Multiplicand Multiplier Result

0

0

1

1

0

1

0

1

0

0

0

1

Actually, in a digital circuit, the multiplication operation is done by repeated additions of all

partial products to obtain the full product.

1.2.3.4 Binary Division

Binary division follows the same procedure as decimal division. The rules regarding binary

division are listed in Table 1.4.

Table 1.4

Dividend Divisor Result

0

0

1

1

0

1

0

1

Not Allowed

0

Not Allowed

1

1.3 Digital Logic Circuits Binary logic deals with variables that have two discrete values—1 for TRUE and 0 for FALSE.

A simple switching circuit containing active elements such as a diode and transistor can

demonstrate the binary logic, which can either be ON (switch closed) or OFF (switch open).

Electrical signals such as voltage and current exist in the digital system in either one of the two

recognized values, except during transition.

The switching functions can be expressed with Boolean equations. Complex Boolean

equations can be simplified by a new kind of algebra, which is popularly called Switching

Algebra or Boolean Algebra, invented by the mathematician George Boole in 1854. Boolean

Algebra deals with the rules by which logical operations are carried out.

1.3.1 Basic Definitions

Boolean algebra, like any other deductive mathematical system, may be defined with a set of

elements, a set of operators, and a number of assumptions and postulates. A set of elements

means any collection of objects having common properties. If S denotes a set, and X and Y are

certain objects, then X S denotes X is an object of set S, whereas Y denotes Y is not the

object of set S. A binary operator defined on a set S of elements is a rule that assigns to each pair

of elements from S a unique element from S. As an example, consider this relation X*Y = Z.

This implies that * is a binary operator if it specifies a rule for finding Z from the objects ( X, Y )

and also if all X, Y, and Z are of the same set S. On the other hand, * can not be binary operator

if X and Y are of set S and Z is not from the same set S.

The postulates of a mathematical system are based on the basic assumptions, which make

possible to deduce the rules, theorems, and properties of the system. Various algebraic structures

are formulated on the basis of the most common postulates, which are described as follows.

1. Closer: A set is closed with respect to a binary operator if, for every pair of elements of

S, the binary operator specifies a rule for obtaining a unique element of S. For example,

the set of natural numbers N = 1, 2, 3, 4, ... is said to be closed with respect to the

binary operator plus ( + ) by the rules of arithmetic addition, since for any X,Y N we

obtain a unique element Z N by the operation X + Y = Z. However, note that the set of

natural numbers is not closed with respect to the binary operator minus (–) by the rules of

arithmetic subtraction because for 1 – 2 = –1, where –1 is not of the set of naturals

numbers.

2. Associative Law: A binary operator * on a set S is said to be associated whenever

(A*B)*C = A*(B*C) for all A,B,C S.

3. Commutative Law: A binary operator * on a set S is said to be commutative whenever

A*B = B*A for all A,B S.

4. Identity Element: A set S is to have an identity element with respect to a binary

operation * on S, if there exists an element E ∈ S with the property E*A = A*X = A.

Example: The element 0 is an identity element with respect to the binary operator + on

the set of integers I = .... –4, –3, –2, –1, 0, 1, 2, 3, 4, .... as A + 0 = 0 + A = A.

Similarly, the element 1 is the identity element with respect to the binary operator × as A

× 1 = 1 × A = A.

5. Inverse: If a set S has the identity element E with respect to a binary operator *, there

exists an element B ∈ S, which is called the inverse, for every A ∈ S, such that A*B = E.

Example: In the set of integers I with E = 0, the inverse of an element A is (-A) since A +

(–A) = 0.

6. Distributive Law: If * and (.) are two binary operators on a set S, * is said to be

distributive over (.), whenever A*(B.C) = (A*B).(A*C).

If summarized, for the field of real numbers, the operators and postulates have the

following meanings:

The binary operator + defines addition.

The additive identity is 0.

The additive inverse defines subtraction.

The binary operator (.) defines multiplication.

The multiplication identity is 1.

The multiplication inverse of A is 1/A, defines division i.e., A. 1/A = 1.

The only distributive law applicable is that of (.) over +

A . (B + C) = (A . B) + (A . C)

1.3.2 DEFINITION OF BOOLEAN ALGEBRA

In 1854 George Boole introduced a systematic approach of logic and developed an algebraic

system to treat the logic functions, which is now called Boolean algebra. In 1938 C.E. Shannon

developed a two-valued Boolean algebra called Switching algebra, and demonstrated that the

properties of two-valued or bistable electrical switching circuits can be represented by this

algebra. The postulates formulated by E.V. Huntington in 1904 are employed for the formal

definition of Boolean algebra. However, Huntington postulates are not unique for defining

Boolean algebra and other postulates are also used. The following Huntington postulates are

satisfied for the definition of Boolean algebra on a set of elements S together with two binary

operators (+) and (.).

1. (a) Closer with respect to the operator (+).

(b) Closer with respect to the operator (.).

2. (a) An identity element with respect to + is designated by 0 i.e., A + 0 = 0 + A =

A.

(b) An identity element with respect to . is designated by 1 i.e., A.1 = 1. A = A.

3. (a) Commutative with respect to (+), i.e., A + B = B + A.

(b) Commutative with respect to (.), i.e., A.B = B.A.

4. (a) (.) is distributive over (+), i.e., A . (B+C) = (A . B) + (A . C).

(b) (+) is distributive over (.), i.e., A + (B .C) = (A + B) . (A + C).

5. For every element A ∈ S, there exists an element A' ∈ S (called the complement of A)

such that A + A′ = 1 and A . A′ = 0.

6. There exists at least two elements A,B ∈ S, such that A is not equal to B.

Comparing Boolean algebra with arithmetic and ordinary algebra (the field of real numbers), the

following differences are observed:

1. Huntington postulates do not include the associate law. However, Boolean algebra

follows the law and can be derived from the other postulates for both operations.

2. The distributive law of (+) over ( . ) i.e., A+ (B.C) = (A+B) . (A+C) is valid for

Boolean algebra, but not for ordinary algebra.

3. Boolean algebra does not have additive or multiplicative inverses, so there are no

subtraction or division operations.

4. Postulate 5 defines an operator called Complement, which is not available in ordinary

algebra.

5. Ordinary algebra deals with real numbers, which consist of an infinite set of elements.

Boolean algebra deals with the as yet undefined set of elements S, but in the two valued

Boolean algebra, the set S consists of only two elements—0 and 1.

Boolean algebra is very much similar to ordinary algebra in some respects. The symbols (+) and

(.) are chosen intentionally to facilitate Boolean algebraic manipulations by persons already

familiar to ordinary algebra. Although one can use some knowledge from ordinary algebra to

deal with Boolean algebra, beginners must be careful not to substitute the rules of ordinary

algebra where they are not applicable.

It is important to distinguish between the elements of the set of an algebraic structure and

the variables of an algebraic system. For example, the elements of the field of real numbers are

numbers, the variables such as X, Y, Z, etc., are the symbols that stand for real numbers, which

are used in ordinary algebra. On the other hand, in the case of Boolean algebra, the elements of a

set S are defined, and the variables A, B, C, etc., are merely symbols that represent the elements.

At this point, it is important to realize that in order to have Boolean algebra, the following must

be shown.

1. The elements of the set S.

2. The rules of operation for the two binary operators.

3. The set of elements S, together with the two operators satisfies six Huntington postulates.

One may formulate much Boolean algebra, depending on the choice of elements of set S

and the rules of operation. In the subsequent chapters, we will only deal with a two-valued

Boolean algebra i.e., one with two elements. Two-valued Boolean algebra has the applications in

set theory and propositional logic. But here, our interest is with the application of Boolean

algebra to gate-type logic circuits.

1.3.3 Basic Properties And Theorems Of Boolean Algebra

1.3.3.1 Principle of Duality

From Huntington postulates, it is evident that they are grouped in pairs as (a) and (b) and every

algebraic expression deductible from the postulates of Boolean algebra remains valid if the

operators and identity elements are interchanged. This means one expression can be obtained

from the other in each pair by interchanging every element i.e., every 0 with 1, every 1 with 0, as

well as interchanging the operators i.e., every (+) with (.) and every (.) with (+). This important

property of Boolean algebra is called principle of duality.

1.3.3.2 DeMorgan's Theorem

Two theorems that were proposed by DeMorgan play important parts in Boolean algebra.

The first theorem states that the complement of a product is equal to the sum of the

complements. That is, if the variables are A and B, then

(A.B)′ = A′ + B′

The second theorem states that the complement of a sum is equal to the product of the

complements. In equation form, this can be expressed as

(A + B)′ = A′ . B′

The complements of Boolean logic function or a logic expression may be simplified or expanded

by the following steps of DeMorgan‘s theorem.

(a) Replace the operator (+) with (.) and (.) with (+) given in the expression.

(b) Complement each of the terms or variables in the expression.

DeMorgan‘s theorems are applicable to any number of variables. For three variables A, B, and

C, the equations are

(A.B.C)′ = A′ + B′ + C′ and

(A + B + C)′ = A′.B′.C′

1.3.3.3 Other Important Theorems

Theorem 1(a): A + A = A

A + A = (A + A).1 by postulate 2(b)

= (A + A) . ( A + A′) by postulate 5

= A + A.A′

= A + 0 by postulate 4

= A by postulate 2(a)

Theorem 1(b): A . A = A

A . A = (A . A) + 0 by postulate 2(a)

= (A . A) + ( A . A′) by postulate 5

= A (A + A′)

= A . 1 by postulate 4

= A by postulate 2(b)

Theorem 2(a): A + 1 = 1

Theorem 2(b): A . 0 = 0

Theorem 3(a): A + A.B = A

A + A.B = A . 1 + A.B by postulate 2(b)

= A ( 1 + B) by postulate 4(a)

= A . 1 by postulate 2(a)

= A by postulate 2(b)

Theorem 3(b): A ( A + B ) = A by duality

The following is the complete list of postulates and theorems useful for two-valued Boolean

algebra.

Postulate 2 (a) A + 0 = A (b) A.1 = A

Postulate 5 (a) A + A′ = 1 (b) A.A′ = 0

Theorem 1 (a) A + A = A (b) A.A = A

Theorem 2 (a) A + 1 = 1 (b) A.0 = 0

Theorem 3, Involution (A′)′ = A

Theorem 3, Involution (a) A + B = B + A (b) A.B = B.A

Theorem 4, Associative (a) A + (B + C) = (A + B) + C (b) A.(B.C) = (A.B).C

Theorem 4, Distributive (a) A(B + C) = A.B + A.C (b) A + B.C = (A + B).(A + C)

Theorem 5, DeMorgan (a) (A + B)′ = A′.B′ (b) (A.B)′ = A′ + B′

Theorem 6, Absorption (a) A + A.B = A (b) A.(A + B) = A

1.3.3.4 Boolean Functions

Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with

binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses

and equal sign. The value of a function may be 0 or 1, depending on the values of variables

present in the Boolean function or expression. For example, if a Boolean function is expressed

algebraically as

F = AB′C

then the value of F will be 1, when A = 1, B = 0, and C = 1. For other values of A, B, C the value

of F is 0.

Boolean functions can also be represented by truth tables. A truth table is the tabular

form of the values of a Boolean function according to the all possible values of its variables. For

an n number of variables, 2n combinations of 1s and 0s are listed and one column represents

function values according to the different combinations. For example, for three variables the

Boolean function F = AB + C truth table can be written as below in Figure below.

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

A Boolean function from an algebraic expression can be realized to a logic diagram composed of

logic gates. Figure 3.11 is an example of a logic diagram realized by the basic gates like AND,

OR, and NOT gates. In subsequent chapters, more logic diagrams with various gates will be

shown.

1.3.3.5 Simplification Of Boolean Expressions

When a Boolean expression is implemented with logic gates, each literal in the function is

designated as input to the gate. The literal may be a primed or unprimed variable. Minimization

of the number of literals and the number of terms leads to less complex circuits as well as less

number of gates, which should be a designer‘s aim. There are several methods to minimize the

Boolean function. In this chapter, simplification or minimization of complex algebraic

expressions will be shown with the help of postulates and theorems of Boolean algebra.

Example 1. Simplify the Boolean function F=AB+ BC + B′C.

Solution. F = AB + BC + B′C

= AB + C(B + B′)

= AB + C

Example 2. Simplify the Boolean function F= A + A′B.

Solution. F = A+ A′B

= (A + A′) (A + B)

= A + B

Example 3. Simplify the Boolean function F= A′B′C + A′BC + AB′.

Solution. F = A′B′C + A′BC + AB′

= A′C (B′+B) + AB′

= A′C + AB′

Example 4. Simplify the Boolean function F = AB + (AC)′ + AB′C(AB + C).

Solution. F = AB + (AC)′ + AB′C(AB + C)

= AB + A′ + C′+ AB′C.AB + AB′C.C

= AB + A′ + C′ + 0 + AB′C (B.B′ = 0 and C.C = C)

= ABC + ABC′ + A′ + C′ + AB′C (AB = AB(C + C′) = ABC + ABC′)

= AC(B + B′) + C′(AB + 1) + A′

= AC + C′+A′ (B + B′ = 1 and AB + 1 = 1)

= AC + (AC)′

= 1

Example 5. Simplify the Boolean function F = ((XY′ + XYZ)′ + X(Y + XY′))′.

Solution. F = ((XY′ + XYZ)′ + X(Y + XY′))′

= ((X(Y′ + YZ))′ + XY + XY′)′

= ((X(Y′Z + Y′ + YZ))′ + X(Y + Y′))′ (Y′ = Y′(Z + 1) = Y′Z + Y′)

= (X(Y′ + Z))′ + X)′

= (X′ + (Y′ + Z)′ + X)′

= (1+ YZ′)′

= 1′

= 0

Example 3.6. Simplify the Boolean function F = XYZ + XY′Z + XYZ′.

Solution. F = XYZ + XY′Z + XYZ′

= XZ (Y + Y′) + XY (Z + Z′)

= XZ + XY

= X (Y + Z)

1.3.3.6 CANONICAL AND STANDARD FORMS

Logical functions are generally expressed in terms of different combinations of logical variables

with their true forms as well as the complement forms. Binary logic values obtained by the

logical functions and logic variables are in binary form. An arbitrary logic function can be

expressed in the following forms.

(i) Sum of the Products (SOP)

(ii) Product of the Sums (POS)

Product Term. In Boolean algebra, the logical product of several variables on which a function

depends is considered to be a product term. In other words, the AND function is referred to as a

product term or standard product. The variables in a product term can be either in true form or in

complemented form. For example, ABC′ is a product term.

Sum Term. An OR function is referred to as a sum term. The logical sum of several variables on

which a function depends is considered to be a sum term. Variables in a sum term can also be

either in true form or in complemented form. For example, A + B + C′ is a sum term.

Sum of Products (SOP). The logical sum of two or more logical product terms is referred to as a

sum of products expression. It is basically an OR operation on AND operated variables. For

example, Y = AB + BC + AC or Y = A′B + BC + AC′ are sum of products expressions.

Product of Sums (POS). Similarly, the logical product of two or more logical sum terms is called

a product of sums expression. It is an AND operation on OR operated variables. For example, Y

= (A + B + C)(A + B′ + C)(A + B + C′) or Y = (A + B + C)(A′ + B′ + C′) are product of sums

expressions.

Standard form. The standard form of the Boolean function is when it is expressed in sum of the

products or product of the sums fashion. The examples stated above, like Y = AB + BC + AC or

Y = (A + B + C)(A + B′ + C)(A + B + C′) are the standard forms.

However, Boolean functions are also sometimes expressed in nonstandard forms like F = (AB +

CD)(A′B′ + C′D′), which is neither a sum of products form nor a product of sums form.

However, the same expression can be converted to a standard form with help of various Boolean

properties, as

F = (AB + CD)(A′B′ + C′D′) = A′B′CD + ABC′D′

1 Minterm

A product term containing all n variables of the function in either true or complemented form is

called the minterm. Each minterm is obtained by an AND operation of the variables in their true

form or complemented form. For a two-variable function, four different combinations are

possible, such as, A′B′, A′B, AB′, and AB. These product terms are called the fundamental

products or standard products or minterms. In the minterm, a variable will possess the value 1 if

it is in true or uncomplemented form, whereas, it contains the value 0 if it is in complemented

form. For three variables function, eight minterms are possible as listed in the following table in

Figure below.

A B C Minterm

0 0 0 A′B′C′

0 0 1 A′B′C

0 1 0 A′BC′

0 1 1 A′BC

1 0 0 AB′C′

1 0 1 AB′C

1 1 0 ABC′

1 1 1 ABC

So, if the number of variables is n, then the possible number of minterms is 2n. The main

property of a minterm is that it possesses the value of 1 for only one combination of n input

variables and the rest of the 2n – 1 combinations have the logic value of 0. This means, for the

above three variables example, if A = 0, B = 1, C = 1 i.e., for input combination of 011, there is

only one combination A′BC that has the value 1, the rest of the seven combinations have the

value 0.

Canonical Sum of Product Expression. When a Boolean function is expressed as the

logical sum of all the minterms from the rows of a truth table, for which the value of the function

is 1, it is referred to as the canonical sum of product expression. The same can be expressed in a

compact form by listing the corresponding decimal-equivalent codes of the minterms containing

a function value of 1. For example, if the canonical sum of product form of a three-variable logic

function F has the minterms A′BC, AB′C, and ABC′, this can be expressed as the sum of the

decimal codes corresponding to these minterms as below.

F (A,B,C) = (3,5,6)

= m3 + m5 + m6

= A′BC + AB′C + ABC′

where Σ (3,5,6) represents the summation of minterms corresponding to decimal codes 3, 5, and

6.

The canonical sum of products form of a logic function can be obtained by using the

following procedure.

i. Check each term in the given logic function. Retain if it is a minterm,

continue to examine the next term in the same manner.

ii. Examine for the variables that are missing in each product which is not a

minterm. If the missing variable in the minterm is X, multiply that

minterm with (X+X′).

iii. Multiply all the products and discard the redundant terms. Here are some

examples to explain the above procedure.

Example 3.7. Obtain the canonical sum of product form of the following function.

F (A, B) = A + B

Solution. The given function contains two variables A and B. The variable B is missing from the

first term of the expression and the variable A is missing from the second term of the expression.

Therefore, the first term is to be multiplied by (B + B′) and the second term is to be multiplied by

(A + A′) as demonstrated below.

F (A, B) = A + B

= A.1 + B.1

= A (B + B′) + B (A + A′)

= AB + AB′ + AB + A′B

= AB + AB′ + A′B (as AB + AB = AB)

Hence the canonical sum of the product expression of the given function is

F (A, B) = AB + AB′ + A′B.


F (A, B, C) = A + BC

Solution. Here neither the first term nor the second term is minterm. The given function contains

three variables A, B, and C. The variables B and C are missing from the first term of the

expression and the variable A is missing from the second term of the expression. Therefore, the

fi rst term is to be multiplied by (B + B′) and (C + C′). The second term is to be multiplied by (A

+ A′). This is demonstrated below.

F (A, B, C) = A + BC

= A (B + B′) (C + C′) + BC (A + A′)

= (AB + AB′) (C + C′) + ABC + A′BC

= ABC + AB′C + ABC′ + AB′C′ + ABC + A′BC

= ABC + AB′C + ABC′ + AB′C′ + A′BC (as ABC + ABC = ABC)

Hence the canonical sum of the product expression of the given function is

F (A, B) = ABC + AB′C + ABC′ + AB′C′ + A′BC.


F (A, B, C, D) = AB + ACD

Solution. F (A, B, C, D) = AB + ACD

= AB (C + C′) (D + D′) + ACD (B + B′)

= (ABC + ABC′) (D + D′) + ABCD + AB′CD

= ABCD + ABCD′ + ABC′D + ABC′D′ + ABCD + AB′CD

= ABCD + ABCD′ + ABC′D + ABC′D′ + AB′CD

Hence above is the canonical sum of the product expression of the given function.

2 Maxterm

A sum term containing all n variables of the function in either true or complemented form is

called the maxterm. Each maxterm is obtained by an OR operation of the variables in their true

form or complemented form. Four different combinations are possible for a two-variable

function, such as, A′ + B′, A′ + B, A + B′, and A + B. These sum terms are called the standard

sums or maxterms. Note that, in the maxterm, a variable will possess the value 0, if it is in true or

uncomplemented form, whereas, it contains the value 1, if it is in complemented form. Like

minterms, for a three-variable function, eight maxterms are also possible as listed in the

following table in Figure below.

A B C Maxterm

0 0 0 A + B + C

0 0 1 A + B + C′

0 1 0 A + B′ + C

0 1 1 A + B′ + C′

1 0 0 A′ + B + C

1 0 1 A′ + B + C′

1 1 0 A′ + B′ + C

1 1 1 A′ + B′ + C′

So, if the number of variables is n, then the possible number of maxterms is 2n. The main

property of a maxterm is that it possesses the value of 0 for only one combination of n input

variables and the rest of the 2n –1 combinations have the logic value of 1. This means, for the

above three variables example, if A = 1, B = 1, C = 0 i.e., for input combination of 110, there is

only one combination A′ + B′ + C that has the value 0, the rest of the seven combinations have

the value 1.

Canonical Product of Sum Expression. When a Boolean function is expressed as the

logical product of all the maxterms from the rows of a truth table, for which the value of the

function is 0, it is referred to as the canonical product of sum expression. The same can be

expressed in a compact form by listing the corresponding decimal equivalent codes of the

maxterms containing a function value of 0. For example, if the canonical product of sums form

of a three-variable logic function F has the maxterms A + B + C, A + B′ + C, and A′ + B + C′,

this can be expressed as the product of the decimal codes corresponding to these maxterms as

below,

F (A,B,C = Π (0,2,5)

= M0 M2 M5

= (A + B + C) (A + B′ + C) (A′ + B + C′)

where Π (0,2,5) represents the product of maxterms corresponding to decimal codes 0, 2, and 5.

The canonical product of sums form of a logic function can be obtained by using the

following procedure.

i. Check each term in the given logic function. Retain it if it is a maxterm,

continue to examine the next term in the same manner.

ii. Examine for the variables that are missing in each sum term that is not a

maxterm. If the missing variable in the maxterm is X, multiply that

maxterm with (X.X′).

iii. Expand the expression using the properties and postulates as described

earlier and discard the redundant terms.

Some examples are given here to explain the above procedure.

Example 3.10. Obtain the canonical product of the sum form of the following function.

F (A, B, C) = (A + B′) (B + C) (A + C′)

Solution. In the above three-variable expression, C is missing from the first term, A is missing

from the second term, and B is missing from the third term. Therefore, CC′ is to be added with fi

rst term, AA′ is to be added with the second, and BB′ is to be added with the third term. This is

shown below.

F (A, B, C) = (A + B′) (B + C) (A + C′)

= (A + B′ + 0) (B + C + 0) (A + C′ + 0)

= (A + B′ + CC′) (B + C + AA′) (A + C′ + BB′)

= (A + B′ + C) (A + B′ + C′) (A + B + C) (A′ + B + C) (A + B + C′) (A + B′ + C′)

[using the distributive property, as X + YZ = (X + Y)(X + Z)]

= (A + B′ + C) (A + B′ + C′) (A + B + C) (A′ + B + C) (A + B + C′)

[as (A + B′ + C′) (A + B′ + C′) = A + B′ + C′]

Hence the canonical product of the sum expression for the given function is

F (A, B, C) = (A + B′ + C) (A + B′ + C′) (A + B + C) (A′ + B + C) (A + B + C′)

Example 3.11. Obtain the canonical product of the sum form of the following function.

F (A, B, C) = A + B′C

Solution. In the above three-variable expression, the function is given at sum of the product

form. First, the function needs to be changed to product of the sum form by applying the

distributive law as shown below.

F (A, B, C) = A + B′C

= (A + B′) (A + C)

Now, in the above expression, C is missing from the first term and B is missing from the second

term. Hence CC′ is to be added with the first term and BB′ is to be added with the second term as

shown below.

F (A, B, C) = (A + B′) (A + C)

= (A + B′ + CC′) (A + C + BB′)

= (A + B′ + C) (A + B′ + C′) (A + B + C) (A + B′ + C)

[using the distributive property, as X + YZ = (X + Y) (X + Z)]

= (A + B′ + C) (A + B′ + C′) (A + B + C)

[as (A + B′ + C) (A + B′ + C) = A + B′ + C]

Hence the canonical product of the sum expression for the given function is

F (A, B, C) = (A + B′ + C) (A + B′ + C′) (A + B + C).

3 Deriving a Sum of Products (SOP) Expression from a Truth Table

The sum of products (SOP) expression of a Boolean function can be obtained from its truth table

summing or performing OR operation of the product terms corresponding to the combinations

containing a function value of 1. In the product terms the input variables appear either in true

(uncomplemented) form if it contains the value 1, or in complemented form if it possesses the

value 0.

Now, consider the following truth table in Figure 3.14, for a three-input function Y. Here

the output Y value is 1 for the input conditions of 010, 100, 101, and 110, and their

corresponding product terms are A′BC′, AB′C′, AB′C, and ABC′ respectively.

Input Output Product Terms Sum Terms

A B C

0 0 0 0 A + B + C

0 0 1 0 A + B + C′

0 1 0 1 A′BC′

0 1 1 0 A + B′ + C′

1 0 0 1 AB′C′

1 0 1 1 AB′C

1 1 0 1 ABC′

1 1 1 0 A′ + B′ + C′

The final sum of products expression (SOP) for the output Y is derived by summing or

performing an OR operation of the four product terms as shown below.

Y = A′BC′ + AB′C′ + AB′C + ABC′

In general, the procedure of deriving the output expression in SOP form from a truth table

can be summarized as below.

i. Form a product term for each input combination in the table, containing an

output value of 1.

ii. Each product term consists of its input variables in either true form or

complemented form. If the input variable is 0, it appears in complemented

form and if the input variable is 1, it appears in true form.

iii. To obtain the fi nal SOP expression of the output, all the product terms are

OR operated.

4 Deriving a Product of Sums (POS) Expression from a Truth Table

As explained above, the product of sums (POS) expression of a Boolean function can also be

obtained from its truth table by a similar procedure. Here, an AND operation is performed on the

sum terms corresponding to the combinations containing a function value of 0. In the sum terms

the input variables appear either in true (uncomplemented) form if it contains the value 0, or in

complemented form if it possesses the value 1. Now, consider the same truth table as shown in

Figure 3.14, for a three-input function Y. Here the output Y value is 0 for the input conditions of

000, 001, 011, and 111, and their corresponding product terms are A + B + C, A + B + C′, A + B′

+ C′, and A′ + B′ + C′ respectively.

So now, the fi nal product of sums expression (POS) for the output Y is derived by

performing an AND operation of the four sum terms as shown below.

Y = (A + B + C) (A + B + C′) (A + B′ + C′) (A′ + B′ + C′)

In general, the procedure of deriving the output expression in POS form from a truth table

can be summarized as below.

i. Form a sum term for each input combination in the table, containing an

output value of 0.

ii. Each product term consists of its input variables in either true form or

complemented form. If the input variable is 1, it appears in complemented

form and if the input variable is 0, it appears in true form.

iii. To obtain the fi nal POS expression of the output, all the sum terms are

AND operated.

5 Conversion between Canonical Forms

From the above example, it may be noted that the complement of a function expressed as the

sum of products (SOP) equals to the sum of products or sum of the minterms which are missing

from the original function. This is because the original function is expressed by those minterms

that make the function equal to 1, while its complement is 1 for those minterms whose values are

0. According to the truth table given in Figure 3.14:

F (A,B,C) = ( 2,4,5,6)

= m2 + m4 + m5 + m6

= A′BC′ + AB′C′ + AB′C + ABC′.

This has the complement that can be expressed as

F′ (A,B,C) = (0,1,3,7)

= m0 + m1 + m3 + m7

Now, if we take complement of F′ by DeMorgan‘s theorem, we obtain F as

F (A,B,C) = (m0 + m1 + m3 + m7)′

= m0′m1′m3′m′7

= M0M1M3M7

= Π(0,1,3,7)

= (A + B + C)(A + B + C′) (A + B′ + C′) (A′ + B′ + C′).

The last conversion follows from the defi nition of minterms and maxterms as shown in

the tables in Figures 3.12 and 3.13. It can be clearly noted that the following relation holds true

m′j = Mj.

That is, the maxterm with subscript j is a complement of the minterm with the same

subscript j, and vice versa.

This example demonstrates the conversion between a function expressed in sum of

products (SOP) and its equivalent in product of maxterms. A similar example can show the

conversion between the product of sums (POS) and its equivalent sum of minterms. In general,

to convert from one canonical form to other canonical form, it is required to interchange the

symbols Σ and π, and list the numbers which are missing from the original form.

Note that, to fi nd the missing terms, the total 2n number of minterms or maxterms must

be realized, where n is the number of variables in the function.

1.3.4 Digital Logic Gates

As Boolean functions are expressed in terms of AND, OR, and NOT operations, it is easier to

implement the Boolean functions with these basic types of gates. However, for all practical

purposes, it is possible to construct other types of logic gates. The following factors are to be

considered for construction of other types of gates.

Name Graphic Symbol Algebraic Function Truth Table

AND

F = AB

A B F

0

0

0

1

0

0

1

1

0

1

0

1

OR

F = A + B

A B F

0

1

1

1

0

0

1

1

0

1

0

1

Inverter or

NOT

F = A′

A

0

1

F

1

0

Buffer

F = A

A

0

1

F

0

1

NAND

F = (AB)′

A B F

1

1

1

0

0

0

1

1

0

1

0

1

NOR

F = (A + B)′

A B F

1

0

0

0

0

0

1

1

0

1

0

1

Exclusive-OR

(XOR)

F = AB′ + A′B

= A B

A B F

0

1

1

0

0

0

1

1

0

1

0

1

Exclusive-

NOR (XNOR)

F = AB + A′B′

= A B

A B F

1

0

0

1

0

0

1

1

0

1

0

1

1. The feasibility and economy of producing the gate with physical parameters.

2. The possibility of extending to more than two inputs.

3. The basic properties of the binary operator such as commutability and associability.

4. The ability of the gate to implement the Boolean functions alone or in conjunction with other

gates.

Out of the 16 functions described in the table in Figure 3.15, we have seen that two are

equal to constant, and four others are repeated twice. Two functions—inhibition and implication,

are impractical to use as standard gates due to lack of commutative or associative properties. So,

there are eight functions—Transfer (or buffer), Complement, AND, OR, NAND, NOR,

Exclusive-OR (XOR), and Equivalence (XNOR) that may be considered to be standard gates in

digital design.

The graphic symbols and truth tables of eight logic gates are shown in Figure above. The

transfer or buffer and complement or inverter or NOT gates are unary gates, i.e., they have single

input, while other logic gates have two or more inputs.

1.4 Flip Flops The basic 1-bit digital memory circuit is known as a flip-flop. It can have only two states, either

the 1 state or the 0 state. A flip-flop is also known as a bistable multivibrator. Flip-flops can be

obtained by using NAND or NOR gates. The general block diagram representation of a flip-flop

is shown in Figure 7.3. It has one or more inputs and two outputs. The two outputs are

complementary to each other. If Q is 1 i.e., Set, then Q' is 0; if Q is 0 i.e., Reset, then Q' is 1.

That means Q and Q' cannot be at the same state simultaneously. If it happens by any chance, it

violates the definition of a flip-flop and hence is called an undefined condition. Normally, the

state of Q is called the state of the fl ip-fl op, whereas the state of Q' is called the complementary

state of the flip-flop. When the output Q is either 1 or 0, it remains in that state unless one or

more inputs are excited to effect a change in the output. Since the output of the flip-flop remains

in the same state until the trigger pulse is applied to change the state, it can be regarded as a

memory device to store one binary bit.

1.4.1 Types of Flip Flop

There are different types of fl ip-fl ops depending on how their inputs and clock pulses cause

transition between two states. We will discuss four different types of flip-flops in this chapter,

viz., S-R, D, J-K, and T. Basically D, J-K, and T are three different modifications of the S-R flip-

flop.

1.4.1.1 S-R (Set-Reset) Flip-flop

An S-R flip-flop has two inputs named Set (S) and Reset (R), and two outputs Q and Q'. The

outputs are complement of each other, i.e., if one of the outputs is 0 then the other should be 1.

This can be implemented using NAND or NOR gates. The block diagram of an S-R flip-flop is

shown in Figure.

S-R Flip-flop Based on NOR Gates

An S-R flip-flop can be constructed with NOR gates at ease by connecting the NOR gates back

to back as shown in Figure. The cross-coupled connections from the output of gate 1 to the input

of gate 2 constitute a feedback path. This circuit is not clocked and is classified as an

asynchronous sequential circuit. The truth table for the S-R flip-flop based on a NOR gate is

shown in the table.

To analyze the circuit shown in above Figure, we have to consider the fact that the output of a

NOR gate is 0 if any of the inputs are 1, irrespective of the other input. The output is 1 only if all

of the inputs are 0. The outputs for all the possible conditions as shown in the table in Figure 7.8

are described as follows.

Inputs Outputs Action

S R Qn+1 Q'n+1

0

0

1

1

0

0

1

0

1

0

Qn

0

1

0

-

Q'n

1

0

0

-

No change

Reset

Set

Forbidden(Undefined)

Indeterminate

Case 1. For S = 0 and R = 0, the fl ip-fl op remains in its present state (Qn). It means that the next

state of the fl ip-fl op does not change, i.e., Qn+1 = 0 if Qn = 0 and vice versa. First let us assume

that Qn = 1 and Q'n = 0. Thus the inputs of NOR gate 2 are 1 and 0, and therefore its output

Q'n+1= 0. This output Q'n+1 = 0 is fed back as the input of NOR gate 1, thereby producing a 1 at

the output, as both of the inputs of NOR gate 1 are 0 and 0; so Qn+1 = 1 as originally assumed.

Now let us assume the opposite case, i.e., Qn = 0 and Q'n = 1. Thus the inputs of NOR

gate 1 are 1 and 0, and therefore its output Qn+1 = 0. This output Qn+1 =0 is fed back as the input

of NOR gate 2, thereby producing a 1 at the output, as both of the inputs of NOR gate 2 are 0 and

0; so Q'n+1 = 1 as originally assumed. Thus we fi nd that the condition S = 0 and R = 0 do not

affect the outputs of the flip-flop, which means this is the memory condition of the S-R fl ip-fl

op.

Case 2. The second input condition is S = 0 and R = 1. The 1 at R input forces the output of

NOR gate 1 to be 0 (i.e., Qn+1 = 0). Hence both the inputs of NOR gate 2 are 0 and 0 and so its

output Q'n+1 = 1. Thus the condition S = 0 and R = 1 will always reset the flip-flop to 0. Now if

the R returns to 0 with S = 0, the flip-flop will remain in the same state.

Case 3. The third input condition is S = 1 and R = 0. The 1 at S input forces the output of NOR

gate 2 to be 0 (i.e., Q'n+1 = 0). Hence both the inputs of NOR gate 1 are 0 and 0 and so its output

Qn+1 = 1. Thus the condition S = 1 and R = 0 will always set the flip-flop to 1. Now if the S

returns to 0 with R = 0, the flip-flop will remain in the same state.

Case 4. The fourth input condition is S = 1 and R = 1. The 1 at R input and 1 at S input forces

the output of both NOR gate 1 and NOR gate 2 to be 0. Hence both the outputs of NOR gate 1

and NOR gate 2 are 0 and 0; i.e., Qn+1 = 0 and Q'n+1 = 0. Hence this condition S = 1 and R = 1

violates the fact that the outputs of a flip-flop will always be the complement of each other. Since

the condition violates the basic definition of flip-flop, it is called the undefined condition.

Generally this condition must be avoided by making sure that 1s are not applied simultaneously

to both of the inputs.

Case 5. If case 4 arises at all, then S and R both return to 0 and 0 simultaneously, and then any

one of the NOR gates acts faster than the other and assumes the state. For example, if NOR gate

1 is faster than NOR gate 2, then Qn+1 will become 1 and this will make Q'n+1 = 0. Similarly, if

NOR gate 2 is faster than NOR gate 1, then Q'n+1 will become 1 and this will make Qn+1 = 0.

Hence, this condition is determined by the flip-flop itself. Since this condition cannot be

controlled and predicted it is called the indeterminate condition.

S'-R' Flip-fl op Based on NAND Gates

An S'-R' flip-flop can be constructed with NAND gates by connecting the NAND gates back to

back as shown in Figure 7.9. The operation of the S'-R' flip-flop can be analyzed in a similar

manner as that employed for the NOR-based S-R flip-flop. This circuit is also not clocked and is

classified as an asynchronous sequential circuit. The truth table for the S'-R' flip-flop based on a

NAND gate is shown in the table in Figure below.

To analyze the circuit shown in above Figure, we have to remember that a LOW at any input of a

NAND gate forces the output to be HIGH, irrespective of the other input. The output of a NAND

gate is 0 only if all of the inputs of the NAND gate are 1. The outputs for all the possible

conditions as shown in the table are described below.

Inputs Outputs Action S' R' Qn+1 Q'n+1

1

1

0

0

1

1

0

1

0

1

Qn

0

1

1

-

Qn

1

0

1

-

No change

Reset

Set

Forbidden(Undefined)

Indeterminate

Case 1. For S' = 1 and R' = 1, the fl ip-fl op remains in its present state (Qn). It means that the

next state of the flip-flop does not change, i.e., Qn+1 = 0 if Qn = 0 and vice versa. First let us

assume that Qn =1 and Q'n = 0. Thus the inputs of NAND gate 1 are 1 and 0, and therefore its

output Qn+1 = 1. This output Qn+1 = 1 is fed back as the input of NAND gate 2, thereby producing

a 0 at the output, as both of the inputs of NAND gate 2 are 1 and 1; so Q'n+1 = 0 as originally

assumed. Now let us assume the opposite case, i.e., Qn = 0 and Q'n = 1. Thus the inputs of

NAND gate 2 are 1 and 0, and therefore its output Q'n+1 = 1. This output Q'n+1 = 1 is fed back as

the input of NAND gate 1, thereby producing a 0 at the output, as both of the inputs of NAND

gate 1 are 1 and 1; so Qn+1 = 0 as originally assumed. Thus we find that the condition S' = 1 and

R' = 1 do not affect the outputs of the flip-flop, which means this is the memory condition of the

S'-R' flip-flop.

Case 2. The second input condition is S' = 1 and R' = 0. The 0 at R' input forces the output of

NAND gate 2 to be 1 (i.e., Q'n+1 = 1). Hence both the inputs of NAND gate 1 are 1 and 1 and so

its output Qn+1 = 0. Thus the condition S' = 1 and R' = 0 will always reset the flip-flop to 0. Now

if the R' returns to 1 with S' = 1, the flip-flop will remain in the same state.

Case 3. The third input condition is S' = 0 and R' = 1. The 0 at S' input forces the output of

NAND gate 1 to be 1 (i.e., Qn+1 = 1). Hence both the inputs of NAND gate 2 are 1 and 1 and so

its output Q'n+1 = 0. Thus the condition S' = 0 and R' = 1 will always set the flip-flop to 1. Now if

the S' returns to 1 with R' = 1, the flip-flop will remain in the same state.

Case 4. The fourth input condition is S' = 0 and R' = 0. The 0 at R' input and 0 at S' input forces

the output of both NAND gate 1 and NAND gate 2 to be 1. Hence both the outputs of NAND

gate 1 and NAND gate 2 are 1 and 1; i.e., Qn+1 = 1 and Q'n+1 = 1. Hence this condition S' = 0 and

R' = 0 violates the fact that the outputs of a flip-flop will always be the complement of each

other. Since the condition violates the basic definition of a flip-flop, it is called the undefined

condition. Generally, this condition must be avoided by making sure that 0s are not applied

simultaneously to both of the inputs.

Case 5. If case 4 arises at all, then S' and R' both return to 1 and 1 simultaneously, and then any

one of the NAND gates acts faster than the other and assumes the state. For example, if NAND

gate 1 is faster than NAND gate 2, then Qn+1 will become 1 and this will make Q'n+1 = 0.

Similarly, if NAND gate 2 is faster than NAND gate 1, then Q'n+1 will become 1 and this will

make Qn+1 = 0. Hence, this condition is determined by the flip-flop itself. Since this condition

cannot be controlled and predicted it is called the indeterminate condition.

Thus, comparing the NOR flip-flop and the NAND flip-flop, we find that they basically

operate in just the complement fashion of each other. Hence, to convert a NAND-based S'-R'

flip-flop into a NOR-based S-R flip-flop, we have to place an inverter at each input of the flip-

flop. The resulting circuit is shown in Figure above, which behaves in the same manner as an S-

R flip-flop.

1.4.1.2 Clocked S-R Flip-Flop

Generally, synchronous circuits change their states only when clock pulses are present. The

operation of the basic flip-flop can be modified by including an additional input to control the

behaviour of the circuit. Such a circuit is shown in Figure below.

Block diagram of a clocked S-R flip-flop.

The circuit shown in Figure above consists of two AND gates. The clock input is

connected to both of the AND gates, resulting in LOW outputs when the clock input is LOW. In

this situation the changes in S and R inputs will not affect the state (Q) of the flip-flop. On the

other hand, if the clock input is HIGH, the changes in S and R will be passed over by the AND

gates and they will cause changes in the output (Q) of the flip-flop. This way, any information,

either 1 or 0, can be stored in the flip-flop by applying a HIGH clock input and be retained for

any desired period of time by applying a LOW at the clock input. This type of flip-flop is called

a clocked S-R flip-flop. Such a clocked S-R flip-flop made up of two AND gates and two NOR

gates is shown in Figure below.

A clocked NOR-based S-R flip-flop

Now the same S-R flip-flop can be constructed using the basic NAND latch and two other

NAND gates. The S and R inputs control the states of the flip-flop in the same way as described

earlier for the unclocked S-R flip-flop. However, the flip-flop only responds when the clock

signal occurs. The clock pulse input acts as an enable signal for the other two inputs. As long as

the clock input remains 0 the outputs of NAND gates 1 and 2 stay at logic 1. This 1 level at the

inputs of the basic NAND-based S-R flip flop retains the present state.

The logic symbol of the S-R flip-flop is shown in Figure below. It has three inputs: S, R,

and CLK. The CLK input is marked with a small triangle. The triangle is a symbol that denotes

the fact that the circuit responds to an edge or transition at CLK input.

Assuming that the inputs do not change during the presence of the clock pulse, we can express

the working of the S-R flip-flop in the form of the truth table in Figure 7.16. Here, Sn and Rn

denote the inputs and Qn the output during the bit time n . Qn+1 denotes the output after the pulse

passes, i.e., in the bit time n + 1.

Inputs Output

S R Qn+1

0

0

1

1

0

1

0

1

Qn

0

1

-

Case 1. If Sn = Rn = 0, and the clock pulse is not applied, the output of the flip-flop remains in

the present state. Even if Sn = Rn = 0, and the clock pulse is applied, the output at the end of the

clock pulse is the same as the output before the clock pulse, i.e., Qn+1 = Qn. The first row of the

table indicates that situation.

Case 2. For Sn = 0 and Rn = 1, if the clock pulse is applied (i.e., CLK = 1), the output of NAND

gate 1 becomes 1; whereas the output of NAND gate 2 will be 0. Now a 0 at the input of NAND

gate 4 forces the output to be 1, i.e., Q' = 1. This 1 goes to the input of NAND gate 3 to make

both the inputs of NAND gate 3 as 1, which forces the output of NAND gate 3 to be 0, i.e., Q =

0.

Case 3. For Sn = 1 and Rn = 0, if the clock pulse is applied (i.e., CLK = 1), the output of NAND

gate 2 becomes 1; whereas the output of NAND gate 1 will be 0. Now a 0 at the input of NAND

gate 3 forces the output to be 1, i.e., Q = 1. This 1 goes to the input of NAND gate 4 to make

both the inputs of NAND gate 4 as 1, which forces the output of NAND gate 4 to be 0, i.e., Q' =

0.

Case 4. For Sn = 1 and Rn = 1, if the clock pulse is applied (i.e., CLK = 1), the outputs of both

NAND gate 2 and NAND gate 1 becomes 0. Now a 0 at the input of both NAND gate 3 and

NAND gate 4 forces the outputs of both the gates to be 1, i.e., Q = 1 and Q' = 1. When the CLK

input goes back to 0 (while S and R remain at 1), it is not possible to determine the next state, as

it depends on whether the output of gate 1 or gate 2 goes to 1 first.

1.4.1.3 Clocked D Flip-Flop

The D flip-flop has only one input referred to as the D input, or data input, and two outputs as

usual Q and Q'. It transfers the data at the input after the delay of one clock pulse at the output Q.

So in some cases the input is referred to as a delay input and the flip-flop gets the name delay (D)

flip-flop. It can be easily constructed from an S-R flip-flop by simply incorporating an inverter

between S and R such that the input of the inverter is at the S end and the output of the inverter is

at the R end. We can get rid of the undefined condition, i.e., S = R = 1 condition, of the S-R flip-

flop in the D flip-flop. The D flip-flop is either used as a delay device or as a latch to store one

bit of binary information. The truth table of D flip flop is given in the table in Figure 7.23. The

structure of the D flip-flop is shown in Figure 7.22, which is being constructed using NAND

gates. The same structure can be constructed using only NOR gates.

Input

Dn

Output

Qn+1

0

1

0

1

Case 1. If the CLK input is low, the value of the D input has no effect, since the S and R inputs

of the basic NAND flip-flop are kept as 1.

Case 2. If the CLK = 1, and D = 1, the NAND gate 1 produces 0, which forces the output of

NAND gate 3 as 1. On the other hand, both the inputs of NAND gate 2 are 1, which gives the

output of gate 2 as 0. Hence, the output of NAND gate 4 is forced to be 1, i.e., Q = 1, whereas

both the inputs of gate 5 are 1 and the output is 0, i.e., Q' = 0. Hence, we find that when D = 1,

after one clock pulse passes Q = 1, which means the output follows D.

Case 3. If the CLK = 1, and D = 0, the NAND gate 1 produces 1. Hence both the inputs of

NAND gate 3 are 1, which gives the output of gate 3 as 0. On the other hand, D = 0 forces the

output of NAND gate 2 to be 1. Hence the output of NAND gate 5 is forced to be 1, i.e., Q' = 1,

whereas both the inputs of gate 4 are 1 and the output is 0, i.e., Q = 0. Hence, we find that when

D = 0, after one clock pulse passes Q = 0, which means the output again follows D.

1.4.1.4 J-K flip-flop

A J-K flip-flop has very similar characteristics to an S-R flip-flop. The only difference is that the

undefined condition for an S-R flip-flop, i.e., Sn = Rn = 1 condition, is also included in this case.

Inputs J and K behave like inputs S and R to set and reset the flip-flop respectively. When J = K

= 1, the flip-flop is said to be in a toggle state, which means the output switches to its

complementary state every time a clock passes.

The data inputs are J and K, which are ANDed with Q' and Q respectively to obtain the

inputs for S and R respectively. A J-K flip-flop thus obtained is shown in Figure below. The

truth table of such a flip-flop.

Inputs Output

Jn Kn Qn+1

0

0

1

1

0

1

0

1

Qn

0

1

Q'n

Case 1. When the clock is applied and J = 0, whatever the value of Q'n (0 or 1), the output of

NAND gate 1 is 1. Similarly, when K = 0, whatever the value of Qn (0 or 1), the output of gate 2

is also 1. Therefore, when J = 0 and K = 0, the inputs to the basic flip-flop are S = 1 and R = 1.

This condition forces the flip-flop to remain in the same state.

Case 2. When the clock is applied and J = 0 and K = 1 and the previous state of the flip-flop is

reset (i.e., Qn = 0 and Q'n = 1), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flip-flop

does not alter the state and remains in the reset state. But if the flip-flop is in set condition (i.e.,

Qn = 1 and Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic flip-flop changes its

state and resets.


reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic fl ip-fl op

changes its state and goes to the set state. But if the flip-flop is already in set condition (i.e., Qn =

1 and Q'n = 0), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flip-flop does not alter its

state and remains in the set state.


reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic flip-flop

changes its state and goes to the set state. But if the flip-flop is already in set condition (i.e., Qn =

1 and Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic flip-flop changes its state

and goes to the reset state. So we find that for J = 1 and K = 1, the flip-flop toggles its state from

set to reset and vice versa. Toggle means to switch to the opposite state.

1.4.1.5 T Flip Flop

With a slight modification of a J-K flip-flop, we can construct a new flip-flop called a T flip flop.

If the two inputs J and K of a J-K flip-flop are tied together it is referred to as a T flip-flop.

Hence, a T flip-flop has only one input T and two outputs Q and Q'. The name T flip-flop

actually indicates the fact that the flip-flop has the ability to toggle. It has actually only two

states—toggle state and memory state. Since there are only two states, a T flip flop is a very

good option to use in counter design and in sequential circuits design where switching an

operation is required. The truth table of a T flip-flop is given below.

T Qn Qn+1

0

0

1

1

0

1

0

1

0

1

1

0

If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change

with the clock pulse. On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock

pulse, the Q output will change to Q' with the clock pulse. In other words, we may say that, if T

= 1 and the device is clocked, then the output toggles its state.

The truth table shows that when T = 0, then Qn+1 = Qn, i.e., the next state is the same as

the present state and no change occurs. When T = 1, then Qn+1 = Q'n, i.e., the state of the flip-flop

is complemented. The circuit diagram of a T flip-flop is shown in Figure below.

1.4.2 Triggering Of Flip-Flops

Flip-flops are synchronous sequential circuits. This type of circuit works with the application of

a synchronization mechanism, which is termed as a clock. Based on the specific interval or point

in the clock during or at which triggering of the flip-flop takes place, it can be classified into two

different types—level triggering and edge triggering. A clock pulse starts from an initial value of

0, goes momentarily to 1, and after a short interval, returns to the initial value.

1.4.2.1 Level Triggering of Flip-flops

If a flip-flop gets enabled when a clock pulse goes HIGH and remains enabled throughout the

duration of the clock pulse remaining HIGH, the flip-flop is said to be a level triggered flip-flop.

If the flip-flop changes its state when the clock pulse is positive, it is termed as a positive level

triggered f ip-flop. On the other hand, if a NOT gate is introduced in the clock input terminal of

the flip-flop, then the flip-flop changes its state when the clock pulse is negative, it is termed as a

negative level triggered flip-flop.

The main drawback of level triggering is that, as long as the clock pulse is active, the

flip-flop changes its state more than once or many times for the change in inputs. If the inputs do

not change during one clock pulse, then the output remains stable. On the other hand, if the

frequency of the input change is higher than the input clock frequency, the output of the flip-flop

undergoes multiple changes as long as the clock remains active. This can be overcome by using

either master-slave flip-flops or the edge-triggered flip-flop.

1.4.2.2 Edge-triggering of Flip-flops

A clock pulse goes from 0 to 1 and then returns from 1 to 0. Figure 7.46 shows the two

transitions and they are defined as the positive edge (0 to 1 transition) and the negative edge (1 to

0 transition). The term edge-triggered means that the flip-flop changes its state only at either the

positive or negative edge of the clock pulse.

One way to make the flip-flop respond to only the edge of the clock pulse is to use capacitive

coupling. An RC circuit is shown in Figure 7.47, which is inserted in the clock input of the flip-

flop. By deliberate design, the RC time constant is made much smaller than the clock pulse

width. The capacitor can charge fully when the clock goes HIGH. This exponential charging

produces a narrow positive spike across the resistor. Later, the trailing edge of the pulse results in

a narrow negative spike. The circuit is so designed that one of the spikes (either the positive or

negative) is neglected and the edge triggering occurs due to the other spike.

1.4.2.3 Excitation Table Of a Flip-Flop

The truth table of a flip-fl op is also referred to as the characteristic table of a flip-flop, since this

table refers to the operational characteristics of the flip-flop. But in designing sequential circuits,

we often face situations where the present state and the next state of the flip-flop is specified, and

we have to find out the input conditions that must prevail for the desired output condition. By

present and next states we mean to say the conditions before and after the clock pulse

respectively. For example, the output of an S-R flip-flop before the clock pulse is Qn = 1 and it is

desired that the output does not change when the clock pulse is applied.

Now from the characteristic table of an S-R flip-flop (Figure 7.20), we obtain the

following conditions:

1. S = R = 0 (second row)

2. S = 1, R = 0 (sixth row).

We come to the conclusion from the above conditions that the R input must be 0, whereas the S

input may be 0 or 1 (i.e., don‘t-care). Similarly, for all possible situations, the input conditions

can be found out. A tabulation of these conditions is known as an excitation table. The table in

below gives the excitation table for S-R, D, J-K, and T flip-flops. These conditions are derived

from the corresponding characteristic tables of the flip-flops.

Present

State (Qn)

Next

State (Qn+1)

S-R FF D FF J-K FF T-FF

Sn Rn Dn Jn Kn Tn

0

0

1

1

0

1

0

1

0

1

0

X

X

0

1

0

0

1

0

1

0

1

X

X

X

X

1

0

0

1

1

0

Excitation table of different flip-flops

1.5 Adders Various information-processing jobs are carried out by digital computers. Arithmetic operations

are among the basic functions of a digital computer. Addition of two binary digits is the most

basic arithmetic operation. The simple addition consists of four possible elementary operations,

which are 0+0 = 0, 0+1 = 1, 1+0 = 1, and 1+1 = 10. The first three operations produce a sum of

one digit, but the fourth operation produces a sum consisting of two digits. The higher significant

bit of this result is called the carry. A combinational circuit that performs the addition of two bits

as described above is called a half-adder. When the augend and addend numbers contain more

significant digits, the carry obtained from the addition of two bits is added to the next higher-

order pair of significant bits. Here the addition operation involves three bits—the augend bit,

addend bit, and the carry bit and produces a sum result as well as carry. The combinational

circuit performing this type of addition operation is called a full-adder. In circuit development

two half-adders can be employed to form a full-adder.

1.5.1 Design of Half-adders

As described above, a half-adder has two inputs and two outputs. Let the input variables augend

and addend be designated as A and B, and output functions be designated as S for sum and C for

carry. The truth table for the functions is below.

Input Variables Output Variables

A B S C

0

0

1

1

0

1

0

1

0

1

1

0

0

0

0

1

From the truth table in Figure 5.2, it can be seen that the outputs S and C functions are similar to

Exclusive-OR and AND functions respectively, as shown in Figure below. The Boolean

expressions are

S = A′B+AB′ and

C = AB.

Figure below shows the logic diagram to implement the half-adder circuit.

1.5.2 Design of Full-adders

A combinational circuit of full-adder performs the operation of addition of three bits—the

augend, addend, and previous carry, and produces the outputs sum and carry. Let us designate

the input variables augend as A, addend as B, and previous carry as X, and outputs sum as S and

carry as C. As there are three input variables, eight different input combinations are possible. The

truth table is shown below according to its functions.

Input Variables Output Variables

X A B S C

0 0 0 0 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

1

1

0

1

0

0

1

0

0

1

0

1

1

1

To derive the simplified Boolean expression from the truth table, the Karnaugh map method is

adopted as in shown below.

A′ B′ A′B AB AB′

X′

X

Map for function S

A′ B′ A′B AB AB′

X′

X

Map for function C

The simplified Boolean expressions of the outputs are

S = X′A′B + X′AB′ + XA′B′ + XAB and

C = AB + BX + AX.

The logic diagram for the above functions is shown below. It is assumed complements of

X, A, and B are available at the input source.

1 1

1 1

1

1 1 1

Note that one type of configuration of the combinational circuit diagram for full-adder is

realized in below, with two-input and three-input AND gates, and three input and four-input OR

gates. Other configurations can also be developed where number and type of gates are reduced.

For this, the Boolean expressions of S and C are modified as follows.

S = X′A′B + X′AB′ + XA′B′ + XAB

= X′ (A′B + AB′) + X (A′B′ + AB)

= X′ (A B) + X (A B)′

= X A B

C = AB + BX + AX = AB + X (A + B)

= AB + X (AB + AB′ + AB + A′B)

= AB + X (AB + AB′ + A‘B)

= AB + XAB + X (AB′ + A‘B)

= AB + X (A B)

Logic diagram according to the modified expression is

You may notice that the full-adder developed in above Figure consists of two 2-input AND

gates, two 2-input XOR (Exclusive-OR) gates and one 2-input OR gate. This contains a reduced

number of gates as well as type of gates as compared to actual Figure. Also, if compared with a

half-adder circuit, the full-adder circuit can be formed with two half-adders and one OR gate.

1.6 Registers A register is a group of binary storage cells capable of holding binary information. A group of

flip-flops constitutes a register, since each flip-flop can work as a binary cell. An n-bit register,

has n flip-flops and is capable of holding n-bits of information. In addition to flip-flops a register

can have a combinational part that performs data-processing tasks.

Various types of registers are available in MSI circuits. The simplest possible register is

one that contains no external gates, and is constructed of only flip-flops. Figure 8.1 shows such a

type of register constructed of four S-R flip-flops, with a common clock pulse input. The clock

pulse enables all the flip-flops at the same instant so that the information available at the four

inputs can be transferred into the 4-bit register. All the flip-flops in a register should respond to

the clock pulse transition. Hence they should be either of the edge-triggered type or the master-

slave type. A group of flip-flops sensitive to the pulse duration is commonly called a gated latch.

Latches are suitable to temporarily store binary information that is to be transferred to an

external destination. They should not be used in the design of sequential circuits that have

feedback connections.

1.6.1 Shift Register

A register capable of shifting its binary contents either to the left or to the right is called a shift

register. The shift register permits the stored data to move from a particular location to some

other location within the register. Registers can be designed using discrete flip-flops (S-R, J-K,

and D-type).

The data in a shift register can be shifted in two possible ways:

(a) serial shifting and

(b) parallel shifting.

The serial shifting method shifts one bit at a time for each clock pulse in a serial manner,

beginning with either LSB or MSB. On the other hand, in parallel shifting operation, all the data

(input or output) gets shifted simultaneously during a single clock pulse. Hence, we may say that

parallel shifting operation is much faster than serial shifting operation.

There are two ways to shift data into a register (serial or parallel) and similarly two ways

to shift the data out of the register. This leads to the construction of four basic types of registers

as shown in Figures below. All of the four configurations are commercially available as TTL

MSI/LSI circuits. They are:

1. Serial in/Serial out (SISO) – 54/74L91, 8 bits

2. Serial in/Parallel out (SIPO) – 54/74164, 8 bits

3. Parallel in/Serial out (PISO) – 54/74265, 8 bits

4. Parallel in/Parallel out (PIPO) – 54/74198, 8 bits.

Serial data Serial Data

input output

(a) Serial In/Serial Out

Serial data

input

--------

MSB LSB

Parallel Data Output

(b) Serial In/Parallel Out

Parallel Data Input

MSB LSB

--------

Serial Data

output

(c) Parallel In/Serial Out

Parallel Data Input

MSB LSB

--------

--------

MSB LSB

Parallel Data Output

(d) Parallel In/Parallel Out

n- bit

n- bit

n- bit

n- bit

1.6.2 Serial-In–-Serial-Out Shift Register

From the name itself it is obvious that this type of register accepts data serially, i.e., one bit at a

time at the single input line. The output is also obtained on a single output line in a serial fashion.

The data within the register may be shifted from left to right using shift-left register, or may be

shifted from right to left using shift-right register.

1.6.2.1 Shift-right Register

A shift-right register can be constructed with either J-K or D flip-flops as shown in Figure 8.3. A

J-K flip-flop–based shift register requires connection of both J and K inputs. Input data are

connected to the J and K inputs of the left most (lowest order) flip-flop. To input a 0, one should

apply a 0 at the J input, i.e., J = 0 and K = 1 and vice versa. With the application of a clock pulse

the data will be shifted by one bit to the right. In the shift register using D fl ip-fl op, D input of

the left most flip-flop is used as a serial input line. To input 0, one should apply 0 at the D input

and vice versa.

The clock pulse is applied to all the flip-flops simultaneously. When the clock pulse is applied,

each flip-flop is either set or reset according to the data available at that point of time at the

respective inputs of the individual flip-flops. Hence the input data bit at the serial input line is

entered into flip-flop A by the first clock pulse. At the same time, the data of stage A is shifted

into stage B and so on to the following stages. For each clock pulse, data stored in the register is

shifted to the right by one stage. New data is entered into stage A, whereas the data present in

stage D are shifted out (to the right).

1.6.2.2 Shift-left Register

A shift-left register can also be constructed with either J-K or D flip-flops as shown in Figure

below. Let us now illustrate the entry of the 4-bit number 1110 into the register, beginning with

the right-most bit. A 0 is applied at the serial input line, making D = 0. As the first clock pulse is

applied, flip-flop A is RESET, thus storing the 0. Next a 1 is applied to the serial input, making

D = 1 for flip-flop A and D = 0 for flip-flop B, because the input of flip-flop B is connected to

the QA output.

When the second clock pulse occurs, the 1 on the data input is ―shifted‖ to the flip-flop

A and the 0 in the flip-flop A is ―shifted‖ to flip-flop B. The 1 in the binary number is now

applied at the serial input line, and the third clock pulse is now applied. This 1 is entered in flip-

flop A and the 1 stored in flip-flop A is now ―shifted‖ to flip-flop B and the 0 stored in flip-flop

B is now ―shifted‖ to flip-flop C. The last bit in the binary number that is the 1 is now applied at

the serial input line and the fourth clock pulse is now applied. This 1 now enters the flip-flop A

and the 1 stored in flip-flop A is now ―shifted‖ to flip-flop B and the 1 stored in flip-flop B is

now ―shifted‖ to flip-flop C and the 0 stored in flip-flop C is now ―shifted‖ to flip-flop D. Thus

the entry of the 4-bit binary number in the shift-right register is now completed.

1.6.2.3 8-bit Serial-in–Serial-out Shift Register

The pinout and logic diagram of IC 74L91 is shown in Figure 8.6. IC 74L91 is actually an

example of an 8-bit serial-in–serial-out shift register. This is an 8-bit TTL MSI chip. There are

eight S-R flip-flops connected to provide a serial input as well as a serial output. The clock input

at each flip-flop is negative edge-triggered. However, the applied clock signal is passed through

an inverter. Hence the data will be shifted on the positive edges of the input clock pulses.

An inverter is connected in between R and S on the first flip-flop. This means that this

circuit functions as a D-type flip-flop. So the input to the register is a single liner on which the

data can be shifted into the register appears serially. The data input is applied at either A (pin 12)

or B (pin 11). The data level at A (or B) is complemented by the NAND gate and then applied to

the R input of the first flip-flop. The same data level is complemented by the NAND gate and

then again complemented by the inverter before it appears at the S input. So, a 0 at input A will

reset the first flip-flop (in other words this 0 is shifted into the first flip-flop) on a positive clock

transition.

The NAND gate with A and B inputs provide a gating function for the input data stream

if required, if gating is not required, simply connect pins 11 and 12 together and apply the input

data stream to this connection.

1.6.3 Serial-In–Parallel-Out Register

In this type of register, the data is shifted in serially, but shifted out in parallel. To obtain the

output data in parallel, it is required that all the output bits are available at the same time. This

can be accomplished by connecting the output of each flip-flop to an output pin. Once the data is

stored in the flip-flop the bits are available simultaneously.

1.6.3.1 8-bit Serial-in–Parallel-out Shift Register

The pinout and logic diagram of IC 74164 is shown in Figure 8.7. IC 74164 is an example of an

8-bit serial-in–parallel-out shift register. There are eight S-R flip-flops, which are all sensitive to

negative clock transitions. The logic diagram of this is same as previous one with only two

exceptions: (1) each flip-flop has an asynchronous CLEAR input; and (2) the true side of each

flip-flop is available as an output—thus all 8 bits of any number stored in the register are

available simultaneously as an output (this is a parallel data output).

Hence, a low level at the CLR input to the chip (pin 9) is applied through an amplifier

and will reset every flip-flop. As long as the CLR input to the chip is LOW, the flip-flop outputs

will all remain low. It means that, in effect, the register will contain all zeros. Shifting of data

into the register in a serial fashion is exactly the same as the IC 74L91. Data at the serial input

may be changed while the clock is either low or high, but the usual hold and setup times must be

observed. The data sheet for this device gives hold time as 0.0 ns and setup time as 30 ns. Now

we try to analyze the gated serial inputs A and B. Suppose that the serial data is connected to B;

then A can be used as a control line. Here‘s how it works:

A is held high: The NAND gate is enabled and the serial input data passes through the NAND

gate inverted. The input data is shifted serially into the register.

A is held low: The NAND gate output is forced high, the input data steam is inhibited, and the

next clock pulse will shift a 0 into the first flip-flop. Each succeeding positive clock pulse will

shift another 0 into the register. After eight clock pulses, the register will be full of zeros.

Example 8.1. How long will it take to shift an 8-bit number into a 74164 shift register if the

clock is set at 1 MHz?

Solution. A minimum of eight clock Pulses will be required since the data is entered serially.

One clock pulse period is 1000 ns, so it will require 8000 ns minimum.

1.6.4 Parallel-In–Serial-Out Register

In the preceding two cases the data was shifted into the registers in a serial manner. We now can

develop an idea for the parallel entry of data into the register. Here the data bits are entered into

the flip-flops simultaneously, rather than a bit-by-bit basis. A 4-bit parallel-in–serial-out register

is illustrated in Figure below. A, B, C, and D are the four parallel data input lines and SHIFT /

LOAD (SH / LD) is a control input that allows the four bits of data at A, B, C, and D inputs to

enter into the register in parallel or shift the data in serial. When SHIFT / LOAD is HIGH, AND

gates G1, G3, and G5 are enabled, allowing the data bits to shift right from one stage to the next.

When SHIFT / LOAD is LOW, AND gates G2, G4, and G6 are enabled, allowing the data bits at

the parallel inputs. When a clock pulse is applied, the flip-flops with D = 1 will be set and the

flip-flops with D = 0 will be reset, thereby storing all the four bits simultaneously. The OR gates

allow either the normal shifting operation or the parallel data-entry operation, depending on

which of the AND gates are enabled by the level on the SHIFT / LOAD input.

1.6.5 Parallel-In–Parallel-Out Register

There is a fourth type of register already before, which is designed such that data can be shifted

into or out of the register in parallel. The parallel input of data has already been discussed in the

preceding section of parallel-in–serial-out shift register. Also, in this type of register there is no

interconnection between the flip-flops since no serial shifting is required. Hence, the moment the

parallel entry of the data is accomplished the data will be available at the parallel outputs of the

register. A simple parallel-in–parallel out shift register is shown below.

Here the parallel inputs to be applied at PA, PB, PC, and PD inputs are directly connected to the

D inputs of the respective flip-flops. On applying the clock transitions, these inputs are entered

into the register and are immediately available at the outputs QA, QB, QC, and QD.

1.7 Counters Counters are one of the simplest types of sequential networks. A counter is usually constructed

from one or more flip-flops that change state in a prescribed sequence when input pulses are

received. A counter driven by a clock can be used to count the number of clock cycles. Since the

clock pulses occur at known intervals, the counter can be used as an instrument for measuring

time and therefore period of frequency. Counters can be broadly classified into three categories:

(i) Asynchronous and Synchronous counters.

(ii) Single and multimode counters.

(iii) Modulus counters.

The asynchronous counter is simple and straightforward in operation and construction and

usually requires a minimum amount of hardware. In asynchronous counters, each flip flop is

triggered by the previous flip-flop, and hence the speed of operation is limited. In fact, the

settling time of the counter is the cumulative sum of the individual settling times of the flip-

flops. This type of counters is also called ripple or serial counter.

The speed limitation of asynchronous counters can be overcome by applying clock pulses

simultaneously to all of the flip-flops. This causes the settling time of the flip-flops to be equal to

the propagation delay of a single flip-flop. The increase in speed is usually attained at the price

of increased hardware. This type of counter is also known as a parallel counter.

The counters can be designed such that the contents of the counter advances by one with

each clock pulse; and is said to operate in the count-up mode. The opposite is also possible,

when the counter is said to operate in the count-down mode. In both cases the counter is said to

be a single mode counter. If the same counter circuit can be operated in both the UP and DOWN

modes, it is called a multimode counters.

Modulus counters are defined based on the number of states they are capable of counting.

This type of counter can again be classified into two types: Mod N and MOD < N. For example,

if there are n bits then the maximum number counted can be 2n or N. If the counter is so

designed that it can count up to 2n or N states, it is called MOD N or MOD 2n counter. On the

other hand, if the counter is designed to count sequences less than the maximum value attainable,

it is called a MOD < N or MOD < 2n counter.

1.7.1 ASYNCHRONOUS (SERIAL OR RIPPLE) COUNTERS

The simplest counter circuit can be built using T flip-flops because the toggle feature is naturally

suited for the implementation of the counting operation. J-K flip-fl ps can also be used with the

toggle property in hand. Other flip-flops like D or S-R can also be used, but they may lead to

more complex designs.

In this counter all the flip-flops are not driven by the same clock pulse. Here, the clock

pulse is applied to the first flip-flop; i.e., the least significant bit state of the counter, and the

successive flip-flop is triggered by the output of the previous flip-flop. Hence the counter has

cumulative settling time, which limits its speed of operation. The first stage of the counter

changes its state first with the application of the clock pulse to the flip-flop and the successive

flip-flops change their states in turn causing a ripple-through effect of the clock pluses. As the

signal propagates through the counter in a ripple fashion, it is called a ripple counter.

1.7.1.1 Asynchronous (or Ripple) Up-counter

Figure below shows a 3-bit counter capable of counting from 0 to 7. The clock inputs of the three

flip-flops are connected in cascade. The T input of each flip-flop is connected to a constant 1,

which means that the state of the flip-flop will toggle (reverse) at each negative edge of its clock.

We are assuming that the purpose of this circuit is to count the number of pulses that occur on

the primary input called CLK (Clock). Thus the clock input of the first flip-flop is connected to

the Clock line. The other two flip-flops have their clock inputs driven by the Q output of the

preceding flip-flop. Therefore, they toggle their state whenever the preceding flip-flop changes

its state from Q = 1 to Q = 0, which results in a negative edge of the Q signal.

Figure (b) shows a timing diagram for the counter. The value of Q0 toggles once each

clock cycle. The change takes place shortly after the negative edge of the Clock signal. The delay

is caused by the propagation delay through the flip-flop. Since the second flip-flop is clocked by

Q0, the value of Q1 changes shortly after the negative edge of the Q0 signal. Similarly, the value

of Q2 changes shortly after the negative edge of the Q1 signal. If we look at the values Q2 Q1 Q0

as the count, then the timing diagram indicates that the counting sequence is 0, 1, 2, 3, 4, 5, 6, 7,

0, 1, 2, and so on. This circuit is a modulo-8 counter. Since it counts in the upward direction, we

call the circuit an up-counter.

The counter in above Figure has three stages, each comprising of a single flip-flop. Only the first

stage responds directly to the Clock signal. Hence we may say that this stage is synchronized to

the clock. The other two stages respond after an additional delay. For example, when count = 3,

the next clock pulse will change the count to 4. Now this change requires all three flip-flops to

toggle their states. The change in Q0 is observed only after a propagation delay from the negative

edge of the clock pulse. The Q1 and Q2 flip-flops have not changed their states yet. Hence, for a

brief period, the count will be Q2Q1Q0 = 010.

The change in Q1 appears after a second propagation delay, and at that point the count is

Q2Q1Q0 = 000. Finally, the change in Q2 occurs after a third delay, and hence the stable state of

the circuit is reached and the count is Q2Q1Q0 = 100.

Table below shows the sequence of binary states that the flip-flops will follow as clock

pulses are applied continuously. An n-bit binary counter repeats the counting sequence for every

2n (n = number of flip-flops) clock pulses and has discrete states from 0 to 2n–1.

Counter State Q2 Q1 Q0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

Count sequence of a 3-bit binary ripple up-counter

1.7.1.2 Asynchronous (or Ripple) Counter With Modulus < 2n

The ripple counter shown in Figure 9.1 is a MOD N or MOD 2n counter, where n is the number

of flip-flops and N is the number of count sequences. This is the maximum MOD-number that is

attainable by using n flip-flops. But in practice, it is often required to have a counter which has a

MOD-number less than 2n. In such cases, it is required that the counter will skip states that are

normally a part of the counting sequences. A MOD-6 ripple counter is shown in Figure 9.4.

In the circuit shown in Figure 9.4(a), without the NAND gate, the counter functions as a

MOD-8 binary ripple counter, which can count from 000 to 111. However, when a NAND gate

is incorporated in the circuit as shown in Figure 9.4(a) the sequence is altered in the following

way:

1. The NAND gate output is connected to the clear inputs of each flip-flop. As along as

the NAND gate produces a high output, it will have no effect on the counter. But when

the NAND gate output goes low, it will clear all flip-flops, and the counter will

immediately go to the 000 state.

2. The outputs Q2, Q1, and Q′0 are given as the inputs to the NAND gate. The NAND

output occurs low whenever Q2Q1Q0 = 110. This condition will occur on the sixth clock

pulse. The low at the NAND gate output will clear the counter to the 000 state. Once the

flip-flops are cleared the NAND gate output goes back to 1.

3. Hence, again, the cycle of the required counting sequence repeats itself.

Although the counter goes to the 110 state, it remains there only for a few nanoseconds before it

recycles to the 000 state. Hence we may say that the counter counts from 000 to 101, it skips the

states 110 and 111; thus it works as a MOD-6 counter.

From the waveform shown above, it can be noted that the Q1 output contains a spike or

glitch caused by the momentary occurrence of the 110 state before the clearing operation takes

place. This glitch is essentially very narrow (owing to the propagation delay of the NAND gate).

It can be noted that the Q2 output has a frequency equal to 1/6 of the input frequency. So we may

say that the MOD-6 counter has divided the input frequency by 6.

To construct any MOD-N counter, the following general steps are to be followed.

1. Find the number of flip-flops (n) required for the desired MOD-number using the equation

2n-1 < N < 2n.

2. Then connect all the n flip-flops as a ripple counter.

3. Find the binary number for N.

4. Connect all the flip-flop outputs, for which Q = 1, as well as Q′ = 1, when the count is N, as

inputs to the NAND gate.

5. Connect the NAND gate output to the clear input of each flip-flop.

When the counter reaches the N-th state, the output of the NAND gate goes low, resetting

all flip-flops to 0. So the counter counts from 0 through N – 1, having N states.

1.7.1.3 Asynchronous (or Ripple) Down-counter

A down-counter using n flip-flops counts downward starting from a maximum count of (2n – 1)

to zero. The count sequence of such a 3-bit down-counter is given in Table below.

Counter State Q2 Q1 Q0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

Count sequence of a 3-bit binary ripple down-counter

1.7.1.4 Asynchronous (or Ripple) Up-down Counter

We have already considered up-counters and down-counters separately. But both of the units can

be combined in a single up-down counter. Such a combined unit of up-down counter can count

both upward as well as downward. Such a counter is also called a multimode counter. In the up-

counter each flip-flop is triggered by the normal output of the preceding flip-flop; whereas in a

down-counter, each flip-flop is triggered by the complement output of the preceding flip-flop.

However, in both the counters, the first flip-flop is triggered by the input pulses.

A 3-bit up-down counter is shown below. The operation of such a counter is controlled

by the up-down control input. The counting sequence of the up-down counter in the two modes

of counting is given in Table 9.3. From the circuit diagram we find that three logic gates are

required per stage to switch the individual stages from count-up to count-down mode. The logic

gates are used to allow either the non inverted output or the inverted output of one flip-flop to the

clock input of the following flip-flop, depending on the status of the control input. An inverter

has been inserted in between the count-up control line and the count-down control line to ensure

that the count-up and count-down cannot be simultaneously in the HIGH state.

COUNT-UP mode COUNT-DOWN mode

State QC QB QA State QC QB QA

0 0 0 0 7 1 1 1

1 0 0 1 6 1 1 0

2 0 1 0 5 1 0 1

3 0 1 1 4 1 0 0

4 1 0 0 3 0 1 1

5 1 0 1 2 0 1 0

6 1 1 0 1 0 0 1

7 1 1 1 0 0 0 0

When the count-up/down line is held HIGH, the lower AND gates will be disabled and their

outputs will be zero. So they will not affect the outputs of the OR gates. At the same time the

upper AND gates will be enabled. Hence, QA will pass through the OR gate and into the clock

input of the B flip-flop. Similarly, QB will be gated into the clock input of the C flip-flop. Thus,

as the input pulses are applied, the counter will count up and follow a natural binary counting

sequence from 000 to 111.

Similarly, with count-up/down line being logic 0, the upper AND gates will become

disabled and the lower AND gates are enabled, allowing Q′A and Q′B to pass through the clock

inputs of the following flip-flops. Hence, in this condition the counter will count in down mode,

as the input pulses are applied.

1.7.2 Synchronous (Parallel) Counters

The ripple or asynchronous counter is the simplest to build, but its highest operating frequency is

limited because of ripple action. Each flip-flop has a delay time. In ripple counters these delay

times are additive and the total ―settling‖ time for the counter is approximately the product of the

delay time of a single flip-flop and the total number of flip-fl ops. Again, there is the possibility

of glitches occurring at the output of decoding gates used with a ripple counter.

Both of these problems can be overcome, if all the flip-flops are clocked synchronously.

The resulting circuit is known as a synchronous counter. Synchronous counters can be designed

for any count sequence (need not be straight binary). These can be designed following a

systematic approach. Before we discuss the formal method of design for such counters, we shall

consider an intuitive method.

A 4-bit synchronous counter with parallel carry is shown above. In this circuit the clock inputs of

all the flip-flops are tied together so that the input clock signal may be applied simultaneously to

each flip-flop. Only the LSB flip-flop 0 has its J input connected permanently to logic 1 (i.e.,

VCC), while the J inputs of the other flip-flops are driven by some combination of flip-flop

outputs. The J input of flip-flop 1 is connected to the output Q0 of flip-flop 0; the J input of flip-

flop 2 is connected with the AND-operated output of Q0 and Q1. Similarly, the J input of 3 flip-

flop is connected with the AND-operated output of Q0, Q1, and Q2.

From the circuit, we can see that flip-flop 0 changes its state with the negative transition

of each clock pulse. Flip-flop 1 changes its state only when the value of Q0 is 1 and a negative

transition of the clock pulse takes place. Similarly, flip-flop 2 changes its state only when both

Q0 and Q1 are 1 and a negative edge transition of the clock pulse takes place. In the same

manner, the flip-flop 3 changes its state when Q0 = Q1 = Q2 = 1 and when there is a negative

transition at clock input. The count sequence of the counter is given below

State Q3 Q2 Q1 Q0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Count sequence of a 4-bit binary synchronous counter

1.7.2.1 Synchronous Down-Counter

A parallel down-counter can be made to count down by using the inverted outputs of flip-flops to

feed the various logic gates. Even the same circuit may be retained and the outputs may be taken

from the complement outputs of each flip-flop. The parallel counter shown in Figure 9.17 can be

converted to a down-counter by connecting the Q′A, Q′B, and Q′C outputs to the AND gates in

place of QA, QB, and QC respectively as shown in Figure below. In this case the count

sequences through which the counter proceeds will be as shown in Table below.

State Q3 Q2 Q1 Q0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.7.2.2 Synchronous Up-Down Counter

Combining both the functions of up- and down-counting in a single counter, we can make a

synchronous up-down counter as shown in Figure 9.18. Here the control input (countup/ down)

is used to allow either the normal output or the inverted output of one flip-flop to the T input of

the following flip-flop. Two separate control lines (count-Up and count-down) could have been

used but in such case we have to be careful that both of the lines cannot be simultaneously in the

high state. When the count-up/down line is high, then the upper AND gates will be active and the

lower AND gates will remain inactive and hence the normal output of each flip-flop is carried

forward to the following flip-flop. In such case, the counter will count from 000 to 111. On the

other hand, if the control line is low, then the upper AND gates remain inactive, while the lower

AND gates will become active. So the inverted output comes into operation and the counter

counts from 111 to 000.

1.8 A/D and D/A Conversion There are numerous advantages to processing signals using digital systems. And because of these

advantages, digital systems are widely used for control, communication, computers,

instrumentation, etc. In many such applications of digital systems, the signals are not available in

the digital form. Therefore, to process these analog signals using digital hardware, they have to

be converted into digital form. The process of conversion of analog signal to digital signal is

referred as analog-to-digital conversion. The system that realizes the conversion is referred to as

an analog-to-digital converter or A/D Converter or ADC.

The output of the system may be desired to be of analog form. Therefore, the output of

the digital system is required to be converted back to the analog form. The process of converting

the digital signal to analog form is called digital-to-analog conversion and the system used for

this purpose is referred to as a digital to analog converter or D/A converter or DAC.

Analog Digital Digital Analog

Signal Signal Signal Signal

In the present trend of technology, most of the signal processing is based on digital systems. But

the real-world signals are analog in nature. A/D converter and D/A converter are the bridge

Analog to

Digital

Converter

Digital

Processor

Digital to

Analog

Converter

between the analog world and digital world. They find their applications in almost every system

of signal processing. An elementary analog signal-processing system with the use of a digital

processor is illustrated with the block diagram in above Figure. In this chapter the D/A converter

will be discussed first as it also serves as a sub-system of the A/D converter.

1.8.1 Digital-To-Analog Converters (DAC)

The input of a D/A converter is an n-bit binary signal, available in parallel form. Normally,

digital signals are available at the output of latches or registers and the voltages correspond to

logic 0 and logic 1. In general, the logic levels do not have precisely fixed voltages. Therefore,

these voltages are applied directly to the converter for digital-to-analog computation, but they are

used to operate digitally controlled switches. The switch is operated to one of the two positions

depending upon the digital signal logic levels (logic 0 or logic 1) which connects precisely fi xed

voltages or voltage references V(1) or V(0) to the converter input, corresponding to logic 1 and

logic 0 respectively.

As an example, for a 4-bit D/A converter, there are 16 voltage levels and they are

tabulated below assuming the voltage step size or the proportionality factor K = 1.

Digital Input Analog O/P

D3 D2 D1 D0 V

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1.8.1.1 Specification of D/A Converters

It is very important that the designers as well as the users be aware of the governing

characteristics of D/A converters, as these characteristics play an important role to determine the

stability and accuracy in analog output. The following characteristics of D/A converters are

generally specified by the manufacturers.

1. Resolution.

2. Linearity.

3. Accuracy.

4. Settling time.

5. Temperature sensitivity.

1.8.1.2 Various Types of D/A Convertors

There are two types of commonly used D/A converters as mentioned below.

1. Weighted-resistor D/A converter, and

2. R-2R ladder D/A converter.

1.8.2 Analog-To-Digital Converters

An analog-to-digital converter, or A/D converter, is the reverse system of a D/A converter,

which converts an analog signal to its digital form. In an analog-to-digital converter, the input

analog voltage may have any value in a range and it will produce the digital output of 2N number

of discrete values for an N-bit converter. Therefore, the whole range of analog voltage is

required to be represented suitably in 2N intervals, and each of the intervals corresponds to a

digital output.

Let us consider that an analog voltage range of 0 to V is represented by 3-bits digital

output. Since a 3-bit digital system can generate 23 = 8 different digital outputs, the full analog

range will be divided into 8 intervals, and each interval of voltage of the size of V/8 is assigned

unique digital value. This process is called quantization. The interval of analog voltage and their

corresponding digital representations are tabulated below.

It may be observed from the figure that a complete voltage interval is represented by a

digital value, irrespective of any voltage value within the interval. Therefore, there involves

always some error while converting any analog voltage interval to its digital value, which is

referred to as quantization error.

Analog Voltage Equivalent

Digital Voltage

1 V

7/8 V 111

6/8 V 110

5/8 V 101

4/8 V 100

3/8 V 011

2/8 V 010

1/8 V 001

0 000

Quantization error E = 1/8 V

1.8.2.1 Specification of an A/D Converter

The A/D converters are usually specified by the following characteristics.

1. Range of input voltage. This is the factor that specifies the minimum and maximum

analog input voltage that can be accepted by an A/D converter.

2. Input impedance. This is an important design criteria that limits the maximum input

current to the A/D converter without deteriorating its performance or damage.

3. Accuracy. It is the error involved in the conversion process and is represented in %.

4. Conversion time. This characteristics specifies the maximum time required for the

conversion process and is very critical while interfacing with other devices and

synchronization with time. The output is considered only after the end of conversion.

5. Format of digital output. Digital output may be of various formats, like unipolar,

bipolar, parallel, serial, etc. The information is essential while designing and interfacing

with other networks.

1.8.2.2 Various Types of A/D Convertors

There are two types of commonly used A/D converters as mentioned below.

1. Parallel comparator A/D converter,

2. Successive Approximation A/D converter,

3. Counting A/D converter,

4. Dual Scope A/D converter,

5. A/D converter using Voltage – to – Frequency Conversion, and

6. A/D converter using Voltage – to – Time Conversion

REVIEW QUESTIONS

1. Convert the decimal number 247.8 to base 3, base 4, base 5, base 11, and base 16.

2. Convert the following decimal numbers to binary: 12.345, 103, 45.778, and 9981.

3. Convert the following binary numbers to decimal: 11110001, 00101101, 1010001, and

1001110.

4. Explain how division and multiplication can be performed in digital systems.

5. State the methods used to simplify the Boolean equations.

6. State and explain the basic Boolean logic operations.

7. What are the applications of Boolean algebra?

8. Define truth table.

9. How is the AND multiplication different from the ordinary multiplication?

10. How does OR addition differ from the ordinary addition method?

11. What are the basic laws of Boolean algebra?

12. State and prove Absorption and Simplifi cation theorems.

13. State and prove Associative and Distributive theorems.

14. What is meant by duality in Boolean algebra?

15. Describe a parallel-in–parallel-out shift register with a neat logic diagram.

16. Explain how a parallel-in–serial-out shift register works with a logic diagram.

17. What are D/A converters and A/D converters and what are their uses?

18. What is quantization and what is quantization error?

19. What is the maximum quantization error for an 8-bit A/D converter if a full-scale analog

input is 10 V?

20. A dual-slope A/D converter has a resolution of 12 bits. If the clock rate is 100 kHz, what

is the maximum rate at which samples can be converted?

CHAPTER 2

SEMICONDUCTORS & RECTIFIERS

Electronics (coined from the word ‗electron‘) is the branch of science and engineering dealing

with the theory and use of a class of devices in which electrons are transported through a

vacuum, gas or semiconductor. The motion of electrons in such devices, called electron devices,

is usually controlled by electric fields. Diodes, triodes, transistors etc. are examples of electron

devices.

Electronics can be broadly classified into two branches: physical electronics and

electronic engineering. Physical electronics treats the motion of electrons in a vacuum, gas or

semiconductor. The design, fabrication, and application of electron devices form the subject

matter of electronic engineering. Electronics has inroads into many fields of science and

technology, and has profoundly influenced the life of modern man. Modern computers and

communication systems are intimately linked with advances in electronics.

We list below some areas of application of electronics; the list is, however, far from

complete.

a. In home, we use a variety of electronic systems: radios, TVs, VCRs, CD players,

telephone answering machines, PCs, microwave ovens, pocket calculators, digital

watches, etc.

b. Round-the-globe communication via microwave or fibre-optic links and satellites,

and access to internets have been possible with advances in electronics. This has

shaped the global village.

c. Sophisticated electronic instruments are used for researches in various fields of

science and engineering.

d. The commercial and industrial sectors rely on electronic communication,

information processing, and control systems.

e. Electronic radar systems are employed for a safe flight from one airport to

another. A modern aircraft is equipped with electronic sensors and computers.

f. Electronic communication and radars play a vital role in meleorology, defence,

and military services.

g. Modern medical practice relies on precise diagonistic and monitoring electronic

systems.

For better times, and at times for worse, electronics has shaped our lives. Our living

standards have improved, but we are also at the peril of deadly weapons that would not have

appeared without the progress in electronics.

2.1 Classification of solids based on energy band theory

2.1.1 ENERGY BANDS IN CRYSTALS

A crystal is a solid consisting of a regular and repetitive arrangement of atoms or molecules

(strictly speaking, ions) in space. If the positions of the atoms in the crystal are represented by

points, called lattice points, we get a crystal lattice. The distance between the atoms in a crystal is

fixed and is termed the lattice constant of the crystal.

To discuss the behaviour of electrons in a crystal, we consider an isolated atom of the

crystal. If Z is the atomic number, the atomic nucleus has a positive charge Ze. At a distance r

from the nucleus, the electrostatic potential due to the nuclear charge is (in SI units)

V(r) = Ze / 4 r πε0

where ε0 is the permittivity of free space. Since an electron carries a negative charge, the

potential energy of an electron at a distance r from the nucleus is

Ep (r) = – eV(r) = –Ze2 / 4πε0r

V(r) is positive while Ep(r) is negative. Both V(r) and Ep(r) are zero at an infinite distance from

the nucleus.

The total energy of an electron in an atom, kinetic plus potential, is negative and has

discrete values. When a number of atoms are brought close together to form a crystal, each atom

will exert an electric force on its neighbours. As a result of this interatomic coupling, the crystal

forms a single electronic system obeying Pauli‘s exclusion principle. Therefore, each energy

level of the isolated atom splits into as many energy levels as there are atoms in the crystal, so

that Pauli‘s exclusion principle is satisfied. The separation between the split-off energy levels is

very small. This large number of discrete and closely spaced energy levels form an energy band.

The width of an energy band is determined by the parent energy level of the isolated atom

and the atomic spacing in the crystal. The lower energy levels are not greatly affected by the

interaction among the neighbouring atoms, and hence form narrow bands. The higher energy

levels are greatly affected by the interatomic interactions and produce wide bands. The

interatomic spacing, although fixed for a given crystal, is different for different crystals. The

width of an energy band thus depends on the type of the crystal, and is larger for a crystal with a

small interatomic spacing. The width of a band is independent of the number of atoms in the

crystal, but the number of energy levels in a band is equal to the number of atoms in the solid.

Consequently, as the number of atoms in the crystal increases, the separation between the energy

levels in a band decreases. As the crystal contains a large number of atoms (≈ 1029 m–3), the

spacing between the discrete levels in a band is so small that the band can be treated as

continuous.

The lower energy bands are normally completely filled by the electrons since the

electrons always tend to occupy the lowest available energy states. The higher energy bands may

be completely empty or may be partly filled by the electrons. Pauli‘s exclusion principle restricts

the number of electrons that a band can accommodate. A partly filled band appears when a partly

filled energy level produces an energy band or when a totally filled band and a totally empty

band overlap.

As the allowed energy levels of a single atom expand into energy bands in a crystal, the

electrons in a crystal cannot have energies in the region between two successive bands. In other

words, the energy bands are separated by gaps of forbidden energy.

2.1.2 Classification of Bands

The conductivity of solids can be explained by Band Theory of solids.

Band Theory of solids : A solid is a periodic arrangement of atoms. In case of isolated atom

the energy levels are discrete or well separated. For a particular atom in the solid, neighbouring

atoms influence the energies of the outer electrons. The discrete energy levels spread into band

of energy levels. The highest filled band is called valance band. The next higher unfilled band is

called conduction band. The valance band and conduction band are separated by certain

forbidden energy region called forbidden energy gap (Eg). The energy bands which are

completely filled at 0 K are called valance bands. The bands with higher energies are called

conduction bands.

On the basis of the band structure, crystals can be classified into metals, insulators, and

semiconductors.

1. Insulator : In some crystalline solids, the forbidden energy gap between the uppermost

filled band, called the valence band, and the lowermost empty band, called the

conduction band, is very large. In such solids, at ordinary temperatures only a few

electrons can acquire enough thermal energy to move from the valence band into the

conduction band. Such solids are known as insulators. Since only a few free electrons are

available in the conduction band, an insulator is a bad conductor of electricity. Diamond

having a forbidden gap of 6 eV is a good example of an insulator. The energy band

structure of an insulator is schematically shown in Fig. 2.1(a).

2. Semiconductor : A material for which the width of the forbidden energy gap between

the valence and the conduction band is relatively small (~ 1 eV) is referred to as a

semiconductor. Germanium and silicon having forbidden gaps of 0.78 and 1.2 eV,

respectively, at 0 K are typical semiconductors. As the forbidden gap is not very wide,

some of the valence electrons acquire enough thermal energy to go into the conduction

band. These electrons then become free and can move about under the action of an

applied electric field. The absence of an electron in the valence band is referred to as a

hole. The holes also serve as carriers of electricity. The electrical conductivity of a

semiconductor is less than that of a metal but greater than that of an insulator. The band

diagram of a semiconductor is given in Fig. 2.1(b).

3. Conductor : A crystalline solid is called a metal if the uppermost energy band is partly

filled [Fig. 2.1(c)] or the uppermost filled band and the next unoccupied band overlap in

energy. Here, the electrons in the uppermost band find neighbouring vacant states to

move in, and thus behave as free particles. In the presence of an applied electric field,

these electrons gain energy from the field and produce an electric current, so that a metal

is a good conductor of electricity. The partly filled band is called the conduction band.

The electrons in the conduction band are known as free electrons or conduction electrons

Fig. 2.1 Energy band structure of (a) insulator, (b) semiconductor, and (c) conductor.

2.2 Introduction to Semiconductors A semiconductor material is one whose electrical properties lie in between those of insulators

and good conductors. Semiconductor, can also be defined as solid material whose electrical

conductivity at room temperature is between that of a conductor and that of an insulator

(see conduction; insulation). At high temperatures its conductivity approaches that of a metal,

and at low temperatures it acts as an insulator. In a semiconductor there is a limited movement of

electrons, depending upon the crystal structure of the material used. The substances first used for

semiconductors were the elements germanium, silicon, and gray tin. It was found that the

incorporation of certain impurities in them enhances their conductive properties. The impurities

either add free electrons or create holes (electron deficiencies) in the crystal structures of the host

substances by attracting electrons. Thus there are two types of semiconductor: the N-type

(negative), in which the current carriers (electrons) are negative, and the P-type (positive), in

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which the positively charged holes move and carry the current. The process of adding these

impurities is called doping; the impurities themselves are called dopants. Dopants that contribute

mobile electrons are called donor impurities; those that cause holes to form are acceptor

impurities. Undoped semiconductor material is called intrinsic semiconductor material. Certain

chemical compounds, including gallium arsenide, indium antimonide, and aluminum phosphide

are semiconductors. Semiconductors are used to produce such electronic devices

as diodes, transistors, and computer memory devices. The field of solid-state physics includes the

study of semiconductors.

2.2.1 Types of Semiconductors

Semiconductor may be classified as under:

Semiconductors

intrinsic or pure extrinsic or impure

semiconductors semiconductors

N-Type P-Type

2.2.1.1 Intrinsic Semiconductor

An intrinsic semiconductor is one which is made of the semiconductor material in its extremely

pure form. Pure form of Si or Ge crystals are called intrinsic semiconductors (tetravalent). The

responsible charge carriers for conduction are both the free electrons and holes. The number of

holes and the number of free electrons are equal (ne=nh) and increase with increase of

temperature. Even though the responsible charge carriers are both the free electrons and holes the

current contributed by the electrons is more than that of holes because of their higher mobility.

Mobility of electrons is nearly twice to that of holes in Germanium and 4 times in silicon. Fermi-

energy level lies exactly at the mid point of the forbidden gap.

Examples of such semiconductors are: pure germanium and silicon which have forbidden

energy gaps of 0.72 eV and 1.1 eV respectively. The energy gap is so small that even at ordinary

room temperature; there are many electrons which possess sufficient energy to jump across the

small energy gap between the valence and the conduction bands.

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Alternatively, an intrinsic semiconductor may be defined as one in which the number of

conduction electrons is equal to the number of holes. Schematic energy band diagram of an

intrinsic semiconductor at room temperature is shown in Fig. below

Hole :

a) A hole is an unfilled covalent bond (or) A vacant energy state in the valance band of a

semiconductor is called hole.

b) The existence of energy level of a hole can be observed in valence band of a

semiconductor.

c) Hole acts like a positive charge but not a particle. Hole drifts in opposite direction to

electrons with lesser speed.

Fermi energy :

The highest energy level which an electron can occupy at 0 k is called Fermi level. For

intrinsic semiconductors this level lies in the middle of the forbidden gap. It can also taken as

average energy of charge carriers.

2.2.1.2 Extrinsic Conductor

The conductivity of intrinsic semiconductor is relatively less. To increase their conductivity pure

semiconductors are doped with trivalent or pentavalent substances. Doping is adding of selected

impurities to a semiconductor to increase its conductivity. Those intrinsic semiconductors to

which some suitable impurity or doping agent or doping has been added in extremely small

amounts (about 1 part in 108) are called extrinsic or impurity semiconductors.

Depending on the type of doping material used, extrinsic semiconductors can be sub-

divided into two classes:

(i) N-type semiconductors and

(ii)P-type semiconductors.

2.3 Types of Extrinsic Semiconductors

2.3.1 N-Type Extrinsic Semiconductor

This type of semiconductor is obtained when a pentavalent material like antimonty (Sb) is added

to pure germanium crystal. In n-type semiconductor, electrons are majority carriers and holes are

minority carriers. (ne>nh). The fermi-energy level in nearer to the conduction band. It is

electrically neutral. The energy level formed slightly below (about 0.01 eV) the conduction band

due to donor impurities is called donor energy level.

1) Conductivity of n-type > p-type > intrinsic.

2) With the increase of temperature fermi level moves down

Hence, it can be easily excited from the valence band to the conduction band by the

application of electric field or increase in thermal energy. It is seen from the above description

that in N-type semiconductors, electrons are the majority carriers while holes constitute the

minority carriers.

2.3.1 P-Type Extrinsic Semiconductor

This type of semiconductor is obtained when traces of a trivalent like boron (B) are added to a

pure germanium crystal. In this case, the three valence electrons of boron atom form covalent

bonds with four surrounding germanium atoms but one bond is left incomplete and gives rise to a

hole. Thus, boron which is called an acceptor impurity causes as many positive holes in a

germanium crystal as there are boron atoms thereby producing a P-type (P for positive) extrinsic

semiconductor.In this type of semiconductor, conduction is by the movement of holes in the

valence band.

In p-type semiconductor, holes are majority carriers and electrons are minority carriers

(nh>ne). The fermi-energy level lies nearer to the valence band. It is electrically neutral. The

energy level formed slightly above (about 0.01 eV) the valence band due to acceptor impurities

is called acceptor energy level.

Majority and Minority Carriers:

In a piece of pure germanium or silicon, no free charge carriers are available at 0ºK. However, as

its temperature is raised to room temperature, some of the covalent bonds are broken by heat

energy and as a result, electron-hole pairs are Produced. These are called thermally-generated

charge carriers. They are also known as intrinsically-available charge carriers. Ordinarily, their

number is quite small. An intrinsic of pure germanium can be converted into a P-type

semiconductor by the addition of an acceptor impurity which adds a large number of holes to it.

Hence, a P-type material contains following charge carriers:

(a) Large number of positive holes—most of them being the added impurity holes with

only a very small number of thermally generated ones.

(b) A very small number of thermally-generated electrons (the companions of the

thermally generated holes mentioned above).

Obviously, in a P-type material, the number of holes (both added and thermally

generated) is much more than that of electrons. Hence, in such a material, holes constitute

majority carriers and electrons form minority carriers as shown in Fig. below (a). Similarly, in an

N-type material, the number of electrons (both added and thermally-generated) is much larger

than the number of thermally-generated holes. Hence, in such a material, electrons are majority

carriers whereas holes are minority carriers as shown in Fig. below (b).

P-Type

Majority Carriers

(a)

Minority Carriers

N-Type

Majority Carriers

(b)

Minority Carriers

2.4 P-N Junction When a semi conducting material such as silicon or germanium is doped with impurity in such a

way that one side has a large number of acceptor impurities and the other side has a large number

of donor impurities. The resulting semiconductor is called p-n junction.

+ + + + + +

+ + + + + +

- - -

- - - - - -

- - - - - -

+ + +

2.4.1 P-N Junction Diode

A p-n junction diode cannot be obtained by simple contact of p-type and n-type semiconductor.

Near the junction, the free electrons from n-region migrate towards p-region and the holes in p-

region migrate towards n-region. This process is known as diffusion. This diffusion is due to

concentration gradient. Due to diffusion, positive ions are left over in n-region and negative ions

are left over in p-region, near the junction. These ions are immobile. Due to the immobile ions on

either side of the junction an internal electric field is formed at the junction which is directed

from n to p.

The no charge carrier region formed at p-n junction due to the combination of electrons

and holes is called depletion layer. The thickness of the depletion layer is of the order of 10–6 m.

When the depletion layer is sufficient by built up, it prevents the electrons diffusion from n to p

side and hole diffusion from p to n side i.e., it acts as a barrier. The potential difference across

the barrier which is set up to prevent diffusion of charge carriers through the junction is called

potential barrier or contact potential. The potential barrier for silicon is 0.7 volts and for

germanium is 0.3 volts. The potential barrier value lies in between 0.1 to 0.7 volts, which

depends on the nature of semiconductor, doping concentration and temperature of the junction.

It can be presumed to be equivalent to a condenser in which the depletion layer act as a

dielectric.

p-n junction diode can be used as rectifiers, detectors. In a circuit p-n junction diode is

represented as. Here arrow mark represents the direction of current in forward bias. It represents

‗p‘ side.

2.4.1.1 Construction

It is two terminal devices consisting of a P-N junction formed either in Ge or Si crystal. It‘s

circuit symbol is shown in fig. above. The P and N type regions are referred to as anode and

cathode respectively. In fig. above arrowhead indicates the conventional direction of current flow

when forward biased. It is the same direction in which hole flow takes place.

2.4.1.2 Working

A P-N junction diode is a one way device offering low resistance when forward biased and

behaving almost as an insulator when reverse biased. Hence such diodes are mostly used as

rectifiers for converting alternating current into direct current.

2.4.1.3 V/I Characteristics

Fig. below shows the static voltage current characteristics for a low power P-N junction diode.

1. Forward characteristic: When the diode is forward biased and applied voltage is increased

from zero hardly any current flows through the device in the beginning. It is so because

the external voltage is being opposed by the internal barrier voltage VB whose value is

0.7 V for Si and 0.3 V for Ge. As soon as VB is neutralized, current through the diode

increases rapidly with increasing applied battery voltage. It is found that as little a voltage

as 1.0 V produces a forward current of about 50 mA.

2. Reverse characteristic: When the diode is reverse biased majority carriers are blocked and

only a small current (due to minority carriers) flows through the diode. As the reverse

voltage is increased from zero, the reverse current very quickly reaches its maximum or

saturation value I0 which is also known as leakage current. It is of order of nano ampers

(nA) for Si and micro ampers (µA) for Ge. As seen from fig.2 when reverse voltage

VBR, the leakage current suddenly and sharply increases, the curve indicating zero

resistance at this point.

2.4.1.4 Diode Parameters

1. Bulk resistance ( rb ): It is the sum of the resistance values of the P and N type semiconductor

materials of which the diode is made of

rb = rp + rn

Usually, it is very small, it is given by

rb = (V – Vk )/ If

It is the resistance offered by the diode well above the knee voltage when current resistance is

large. Obviously, this resistance is offered in the forward direction.

2. Junction resistance ( rj ): It is value for forward biased junction depends on the magnitude of

forward dc current.

3. Dynamic or ac resistance:

rac or rd = rB + rj

For large values of forward current, rj is negligible. Hence, rac = rB for small values of IF, rB is

negligible as compared to rj

rac = rj

4. Forward voltage drop

It is given by the relation

forward voltage drop = power dissipated

forward dc current

Reverse saturation current (I0)

Reverse breakdown voltage (VBR)

Reverse dc resistance (RR)

RR = reverse voltage

reverse current

5. Equation of diode current: The analytical equation which describes both the forward and

reverse characteristics is called the Boltzmann‘s diode equation given

I = Io ( e40v

– 1 ) …….. for Ge

I = Io e40v

if V > 1volt

I = Io ( e20v

– 1 ) …….. for Si

I = Io e20v

if V > 1volt

Where I0 reverse saturation current. V voltage across the diode.

2.5 Zenor Diode It is a reverse-biased heavily-doped silicon (or germanium) P-N junction diode which is operated

in the breakdown region where current is limited by both external resistance and power

dissipation of the diode. Silicon is preferred to Ge because of its higher temperature and current

capability.

When a diode breaks down, both Zener and avalanche effects are present although

usually one or the other predominates depending on the value of reverse voltage. At reverse

voltages less than 6 V, Zener effect predominates whereas above 6 V, avalanche effect is

predominant. Strictly speaking, the first one should be called Zener diode and the second one as

avalanche diode but the general practice is to call both types as Zener diodes.

Zener breakdown occurs due to breaking of covalent bonds by the strong electric field set

up in the depletion region by the reverse voltage. It produces an extremely large number of

electrons and holes which constitute the reverse saturation current (now called Zener current, Iz)

whose value is limited only by the external resistance in the circuit. It is independent of the

applied voltage.

2.5.1 Zener Effect

The Zener effect is a type of electrical breakdown in a reverse biased p-n diode in which

the electric field enables tunneling of electrons from the valence to the conduction band of

a semiconductor, leading to a large number of free minority carriers, which suddenly increase the

reversecurrent. Zener breakdown is employed in a Zener diode.

2.5.1.1 Mechanism

Under a high reverse-bias voltage, the p-n junction's depletion regionexpands, leading to a high

strength electric field across the junction. A sufficiently strong electric field enables tunneling of

electrons from the valence to the conduction band of a semiconductor leading to a large number

of free charge carriers. This sudden generation of carriers rapidly increases the reverse current

and gives rise to the high slope resistance of the Zener diode.

http://en.wikipedia.org/wiki/P-n_junction#Reverse_bias

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http://en.wikipedia.org/wiki/Electric_field

http://en.wikipedia.org/wiki/Semiconductor

http://en.wikipedia.org/wiki/Charge_carriers_in_semiconductors

http://en.wikipedia.org/wiki/Electric_current

http://en.wikipedia.org/wiki/Zener_diode

http://en.wikipedia.org/wiki/Depletion_region

http://en.wikipedia.org/wiki/Semiconductor

http://en.wikipedia.org/wiki/Charge_carriers_in_semiconductors

2.5.1.2 Relationship to Avalanche Effect

The Zener effect is distinct from avalanche breakdown which involves minority

carrier electrons in the transition region which are accelerated by the electric field to energies

sufficient to free electron-hole pairs via collisions with bound electrons. Either the Zener or the

avalanche effect may occur independently, or both may occur simultaneously. In general, diode

junctions which break down below 5 V are caused by the Zener effect, while junctions which

experience breakdown above 5 V are caused by the avalanche effect. Intermediate breakdown

voltages (around 5V) are usually caused by a combination of the two effects. This Zener

breakdown voltage is found to occur at electric field intensity of about 3×107 V/m. Zener

breakdown occurs in heavily doped junctions (p-type semiconductor moderately doped and n-

type heavily doped), which produces a narrow depletion region. The avalanche breakdown

occurs in lightly doped junctions, which produce a wider depletion layer. Temperature increase

in the junction decreases Zener breakdown and increases the contribution of avalanche

breakdown.

2.5.2 Voltage/Current Characteristic of Zenor Diode

A typical characteristic is shown by Fig. below in the negative quadrant. The forward

characteristic is simply that of an ordinary forward-biased junction diode. The important points

on the reverse characteristic are:

Vz = Zener breakdown voltage

Iz min = minimum current to sustain breakdown

Iz max = maximum Zener current limited by maximum power dissipation

http://en.wikipedia.org/wiki/Avalanche_breakdown

http://en.wikipedia.org/wiki/Electron

http://en.wikipedia.org/wiki/Electric_field

The schematic symbol of a Zener diode and its equivalent circuit are shown in Fig. below.

2.5.3 Zener Voltages

Zener diodes are available having Zener voltages of 2.4 V to 200 V. Their power dissipation is

given by the product VzIz. Maximum ratings vary from 150 mW to 50 W.

2.5.4 Zener Biasing

For proper working of a Zener diode in any circuit, it is essential that it must

1. be reverse-biased.

2. Have voltage across it greater than Vz.

3. be in a circuit where current is less than Iz max.

2.5.5 Uses

Zener diodes find numerous applications in transistor circuitry. Some of their common uses are:

1. as voltage regulators.

2. as a fixed reference voltage in a network for biasing and comparison purposes and for

calibrating voltmeters.

3. as peak clippers or voltage limiters.

4. for meter protection against damage from accidental application of excessive voltage.

5. for reshaping a waveform.

2.5.6 Zener Applications

2.5.6.1 Zener Regulator

The constant reverse voltage of the zener diode makes it a valuable component for the

regulation of the output voltage against both variations in the input voltage from an unregulated

power supply or variations in the load resistance. The current through the zener will change to

http://hyperphysics.phy-astr.gsu.edu/hbase/solids/zener.html#c3

keep the voltage at within the limits of the threshold of zener action and the maximum power it

can dissipate.

2.5.6.2 Zener Controlled Comparators

This comparator application makes use of the properties of the zener diode to cause the output to

switch between voltages determined by the zener diodes when the input voltage

difference changes sign. The output circuit amounts to a zener regulator which switches

from one zener voltage to the other on a transition.

2.5.6.3 Zener Limiter

A single Zener diode can limit one side of a sinusoidal waveform to the zener voltage while

clamping the other side to near zero. With two opposing zeners, the waveform can be limited to

the zener voltage on both polarities.


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2.5.6.4 Zener Role in Power Supply

The zener diode is widely used as a voltage regulator because of its capacity to maintain a

constant voltage over a sizeable range of currents. It can be used as a single component across

the output of a rectifier or incorporated into one of the variety of one-chip regulators.

2.6 Rectifiers

A rectifier is an electrical device that converts alternating current (AC), which periodically

reverses direction, to direct current (DC), which flows in only one direction. The process is

known as rectification. Physically, rectifiers take a number of forms, including vacuum

tube diodes, mercury-arc valves, copper and selenium oxide rectifiers, solid-state diodes, silicon-

controlled rectifiers and other silicon-based semiconductor switches. Historically, even

synchronous electromechanical switches and motors have been used. Early radio receivers,

called crystal radios, used a "cat's whisker" of fine wire pressing on a crystal of galena (lead

sulfide) to serve as a point-contact rectifier or "crystal detector".

Rectifiers have many uses, but are often found serving as components of DC power

supplies and high-voltage direct current power transmission systems. Rectification may serve in

roles other than to generate direct current for use as a source of power. As

noted, detectors of radio signals serve as rectifiers. In gas heating systems flame rectification is

used to detect presence of flame.

The simple process of rectification produces a type of DC characterized by pulsating voltages

and currents (although still unidirectional). Depending upon the type of end-use, this type of DC

current may then be further modified into the type of relatively constant voltage DC

characteristically produced by such sources as batteries and solar cells.

2.6.1 Rectifier device

Before the development of silicon semiconductor rectifiers, vacuum tube thermionic diodes and

copper oxide- or selenium-based metal rectifier stacks were used.[1]

With the introduction of

semiconductor electronics, vacuum tube rectifiers became obsolete, except for some enthusiasts

of vacuum tube audio equipment. For power rectification from very low to very high current,

semiconductor diodes of various types (junction diodes, Schottky diodes, etc.) are widely used.

Other devices which have control electrodes as well as acting as unidirectional current valves are

used where more than simple rectification is required; e.g., where variable output voltage is

needed. High-power rectifiers, such as those used in high-voltage direct current power

transmission, employ silicon semiconductor devices of various types. These are thyristors or

other controlled switching solid-state switches which effectively function as diodes to pass

current in only one direction.


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https://en.wikipedia.org/wiki/Electric_power_conversion

https://en.wikipedia.org/wiki/Alternating_current

https://en.wikipedia.org/wiki/Direct_current

https://en.wikipedia.org/wiki/Vacuum_tube



https://en.wikipedia.org/wiki/Diode

https://en.wikipedia.org/wiki/Mercury-arc_valve

https://en.wikipedia.org/wiki/Solid-state_(electronics)

https://en.wikipedia.org/wiki/Silicon-controlled_rectifier

https://en.wikipedia.org/wiki/Silicon-controlled_rectifier

https://en.wikipedia.org/wiki/Crystal_radio

https://en.wikipedia.org/wiki/Cat%27s-whisker_detector

https://en.wikipedia.org/wiki/Galena

https://en.wikipedia.org/wiki/Power_supplies



https://en.wikipedia.org/wiki/High-voltage_direct_current

https://en.wikipedia.org/wiki/Detector_(radio)

https://en.wikipedia.org/wiki/Radio

https://en.wikipedia.org/wiki/Flame_rectification

https://en.wikipedia.org/wiki/Battery_(electrical)

https://en.wikipedia.org/wiki/Solar_cell

https://en.wikipedia.org/wiki/Thermionic_diode

https://en.wikipedia.org/wiki/Metal_rectifier

https://en.wikipedia.org/wiki/Rectifier#cite_note-1

https://en.wikipedia.org/wiki/Audio_equipment

https://en.wikipedia.org/wiki/Junction_diode

https://en.wikipedia.org/wiki/Schottky_diode


https://en.wikipedia.org/wiki/Thyristor

2.6.2 Rectifier circuits

Rectifier circuits may be single-phase or multi-phase (three being the most common number of

phases). Most low power rectifiers for domestic equipment are single-phase, but three-phase

rectification is very important for industrial applications and for the transmission of energy as

DC (HVDC).

2.6.2.1 Single-phase rectifiers

Half-wave rectification

In half wave rectification of a single-phase supply, either the positive or negative half of the AC

wave is passed, while the other half is blocked. Because only one half of the input waveform

reaches the output, mean voltage is lower. Half-wave rectification requires a single diode in

a single-phase supply, or three in a three-phase supply. Rectifiers yield a unidirectional but

pulsating direct current; half-wave rectifiers produce far more ripple than full-wave rectifiers,

and much more filtering is needed to eliminate harmonics of the AC frequency from the output.

The no-load output DC voltage of an ideal half wave rectifier is:

Where:

Vdc, Vav - the DC or average output voltage,

Vpeak, the peak value of the phase input voltages,

Vrms, the root-mean-square value of output voltage.

Full-wave rectification

A full-wave rectifier converts the whole of the input waveform to one of constant polarity

(positive or negative) at its output. Full-wave rectification converts both polarities of the input

https://en.wikipedia.org/wiki/HVDC

https://en.wikipedia.org/wiki/Single-phase_electric_power

https://en.wikipedia.org/wiki/Three-phase_electric_power

waveform to pulsating DC (direct current), and yields a higher average output voltage. Two

diodes and a center tapped transformer, or four diodes in a bridge configuration and any AC

source (including a transformer without center tap), are needed.[3]

Single semiconductor diodes,

double diodes with common cathode or common anode, and four-diode bridges, are

manufactured as single components.

For single-phase AC, if the transformer is center-tapped, then two diodes back-to-back

(cathode-to-cathode or anode-to-anode, depending upon output polarity required) can form a

full-wave rectifier. Twice as many turns are required on the transformer secondary to obtain the

same output voltage than for a bridge rectifier, but the power rating is unchanged.

The average and root-mean-square no-load output voltages of an ideal single-phase full-wave

rectifier are:

Very common double-diode rectifier vacuum tubes contained a single common cathode and

two anodes inside a single envelope, achieving full-wave rectification with positive output. The

5U4 and 5Y3 were popular examples of this configuration.

2.6.2.2 Three-phase rectifiers

Single-phase rectifiers are commonly used for power supplies for domestic equipment. However,

for most industrial and high-power applications, three-phase rectifier circuits are the norm. As

with single-phase rectifiers, three-phase rectifiers can take the form of a half-wave circuit, a full-

wave circuit using a center-tapped transformer, or a full-wave bridge circuit. Thyristors are

commonly used in place of diodes in order to allow the output voltage to be regulated. Many

devices that generate alternating current (some such devices are called alternators) generate

three-phase AC. For example, an automobile alternator has six diodes inside it to function as a

full-wave rectifier for battery charging applications.

Three-phase, half-wave circuit

An uncontrolled three-phase, half-wave circuit requires three diodes, one connected to each

phase. This is the simplest type of three-phase rectifier but suffers from relatively

high harmonic distortion on both the AC and DC connections. This type of rectifier is said to

https://en.wikipedia.org/wiki/Center_tap

https://en.wikipedia.org/wiki/Transformer

https://en.wikipedia.org/wiki/Diode_bridge

https://en.wikipedia.org/wiki/Rectifier#cite_note-3

https://en.wikipedia.org/wiki/Arithmetic_mean

https://en.wikipedia.org/wiki/Root-mean-square


https://en.wikipedia.org/wiki/Cathode

https://en.wikipedia.org/wiki/Anode

https://en.wikipedia.org/wiki/Three-phase_electric_power


https://en.wikipedia.org/wiki/Alternator

https://en.wikipedia.org/wiki/Harmonic

have a pulse-number of three, since the output voltage on the DC side contains three distinct

pulses per cycle of the grid frequency.

Three-phase, full-wave circuit using center-tapped transformer

If the AC supply is fed via a transformer on which the secondary windings contain a center tap, a

rectifier circuit with improved harmonic performance can be obtained. This rectifier now

requires six diodes, one connected to each end of each transformer secondary winding. This

circuit has a pulse-number of six, and in effect, can be thought of as a six-phase, half-wave

circuit.

Before solid state devices became available, the half-wave circuit, and the full-wave

circuit using a center-tapped transformer, were very commonly used in industrial rectifiers

using mercury-arc valves.[4]

This was because the three or six AC supply inputs could be fed to a

corresponding number of anode electrodes on a single tank, sharing a common cathode.

With the advent of diodes and thyristors, these circuits have become less popular and the

three-phase bridge circuit has become the most common circuit

Three-phase bridge rectifier

For an uncontrolled three-phase bridge rectifier, six diodes are used, and the circuit again has a

pulse number of six. For this reason, it is also commonly referred to as a six-pulse bridge.

For low-power applications, double diodes in series, with the anode of the first diode

connected to the cathode of the second, are manufactured as a single component for this purpose.

Some commercially available double diodes have all four terminals available so the user can

configure them for single-phase split supply use, half a bridge, or three-phase rectifier.

For higher-power applications, a single discrete device is usually used for each of the six

arms of the bridge. For the very highest powers, each arm of the bridge may consist of tens or

hundreds of separate devices in parallel (where very high current is needed, for example

in aluminium smelting) or in series (where very high voltages are needed, for example in high-

voltage direct current power transmission).

For a three-phase full-wave diode rectifier, the ideal, no-load average output voltage is

If thyristors are used in place of diodes, the output voltage is reduced by a factor cos(α):

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Or, expressed in terms of the line to line input voltage

Where:

VLLpeak, the peak value of the line to line input voltages,

Vpeak, the peak value of the phase (line to neutral) input voltages,

α, firing angle of the thyristor (0 if diodes are used to perform rectification)

The above equations are only valid when no current is drawn from the AC supply or in

the theoretical case when the AC supply connections have no inductance. In practice, the supply

inductance causes a reduction of DC output voltage with increasing load, typically in the range

10–20% at full load.

The effect of supply inductance is to slow down the transfer process

(called commutation) from one phase to the next. As result of this is that at each transition

between a pair of devices, there is a period of overlap during which three (rather than two)

devices in the bridge are conducting simultaneously. The overlap angle is usually referred to by

the symbol μ (or u), and may be 20 30° at full load.

2.6.3 Voltage Multiplying Rectifier

The simple half wave rectifier can be built in two electrical configurations with the diode

pointing in opposite directions, one version connects the negative terminal of the output direct to

the AC supply and the other connects the positive terminal of the output direct to the AC supply.

By combining both of these with separate output smoothing it is possible to get an output voltage

of nearly double the peak AC input voltage. This also provides a tap in the middle, which allows

use of such a circuit as a split rail power supply.

A variant of this is to use two capacitors in series for the output smoothing on a bridge

rectifier then place a switch between the midpoint of those capacitors and one of the AC input

terminals. With the switch open this circuit will act like a normal bridge rectifier. With the

switch closed it will act like a voltage doubling rectifier. In other words this makes it easy to

derive a voltage of roughly 320 V (±15%, approx.) DC from any 120 V or 230 V mains supply

in the world, this can then be fed into a relatively simple switched-mode power supply.

Cascaded diode and capacitor stages can be added to make a voltage multiplier

(Cockroft-Walton circuit). These circuits are capable of producing a DC output voltage potential

tens of times that of the peak AC input voltage, but are limited in current capacity and regulation.

Diode voltage multipliers, frequently used as a trailing boost stage or primary high voltage (HV)

source, are used in HV laser power supplies, powering devices such as cathode ray tubes (CRT)

https://en.wikipedia.org/wiki/Switched-mode_power_supply

https://en.wikipedia.org/wiki/Cockcroft-Walton_generator

https://en.wikipedia.org/wiki/Cathode_ray_tube

(like those used in CRT based television, radar and sonar displays), photon amplifying devices

found in image intensifying and photo multiplier tubes (PMT), and magnetron based radio

frequency (RF) devices used in radar transmitters and microwave ovens. Before the introduction

of semiconductor electronics, transformerless powered vacuum tube receiverspowered directly

from AC power sometimes used voltage doublers to generate about 170 VDC from a 100–120 V

power line.

2.6.4 Rectifier Losses

A real rectifier will have a characteristic which drops part of the input voltage (a voltage drop,

for silicon devices, of typically 0.7 volts plus an equivalent resistance, in general non-linear), and

at high frequencies will distort waveforms in other ways; unlike an ideal rectifier, it will dissipate

power.

An aspect of most rectification is a loss from the peak input voltage to the peak output

voltage, caused by the built-in voltage drop across the diodes (around 0.7 V for ordinary

silicon p–n junctiondiodes and 0.3 V for Schottky diodes). Half-wave rectification and full-wave

rectification using a center-tapped secondary will have a peak voltage loss of one diode drop.

Bridge rectification will have a loss of two diode drops. This reduces output voltage, and limits

the available output voltage if a very low alternating voltage must be rectified. As the diodes do

not conduct below this voltage, the circuit only passes current through for a portion of each half-

cycle, causing short segments of zero voltage (where instantaneous input voltage is below one or

two diode drops) to appear between each "hump".

Peak loss is very important for low voltage rectifiers (for example, 12 V or less) but is

insignificant in high-voltage applications such as HVDC.

2.6.5 Rectification Technologies

1. Electromechanical

Early power conversion systems were purely electro-mechanical in design, since

electronic devices were not available to handle significant power. Mechanical

rectification systems usually use some form of rotation or resonant vibration

(e.g. vibrators) in order to move quickly enough to follow the frequency of the input

power source, and cannot operate beyond several thousand cycles per second.

Due to reliance on fast-moving parts of mechanical systems, they needed a high

level of maintenance to keep operating correctly. Moving parts will have friction, which

requires lubrication and replacement due to wear. Opening mechanical contacts under

load results in electrical arcs and sparks that heat and erode the contacts.

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https://en.wikipedia.org/wiki/Schottky_diode

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2. Synchronous rectifier

To convert alternating into direct current in electric locomotives, a synchronous

rectifier may be used[citation needed]

. It consists of a synchronous motor driving a set of

heavy-duty electrical contacts. The motor spins in time with the AC frequency and

periodically reverses the connections to the load at an instant when the sinusoidal current

goes through a zero-crossing. The contacts do not have to switch a large current, but they

need to be able to carry a large current to supply the locomotive's DC traction motors.

3. Vibrator

Vibrators used to generate AC from DC in pre-semiconductor battery-to-high-voltage-

DC power supplies often contained a second set of contacts that performed

synchronous mechanical rectification of the stepped-up voltage.

4. Motor-generator set

A motor-generator set, or the similar rotary converter, is not strictly a rectifier as it does

not actually rectify current, but rather generates DC from an AC source. In an "M-G set",

the shaft of an AC motor is mechanically coupled to that of a DC generator. The DC

generator produces multiphase alternating currents in its armature windings, which

a commutator on the armature shaft converts into a direct current output; or a homopolar

generator produces a direct current without the need for a commutator. M-G sets are

useful for producing DC for railway traction motors, industrial motors and other high-

current applications, and were common in many high-power D.C. uses (for example,

carbon-arc lamp projectors for outdoor theaters) before high-power semiconductors

became widely available.

5. Electrolytic

The electrolytic rectifier was a device from the early twentieth century that is no longer

used. A home-made version is illustrated in the 1913 book The Boy Mechanic but it

would only be suitable for use at very low voltages because of the low breakdown

voltage and the risk of electric shock. A more complex device of this kind was patented

by G. W. Carpenter in 1928 (US Patent 1671970).

When two different metals are suspended in an electrolyte solution, direct current

flowing one way through the solution sees less resistance than in the other direction.

Electrolytic rectifiers most commonly used an aluminum anode and a lead or steel

cathode, suspended in a solution of tri-ammonium ortho-phosphate.

The rectification action is due to a thin coating of aluminum hydroxide on the

aluminum electrode, formed by first applying a strong current to the cell to build up the

coating. The rectification process is temperature-sensitive, and for best efficiency should

not operate above 86 °F (30 °C). There is also a breakdown voltage where the coating is

penetrated and the cell is short-circuited. Electrochemical methods are often more fragile

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https://en.wikipedia.org/wiki/Traction_motor

https://en.wikipedia.org/wiki/Vibrator_(electronic)

https://en.wikipedia.org/wiki/Mechanical_rectifier

https://en.wikipedia.org/wiki/Electrical_generator

https://en.wikipedia.org/wiki/Armature

https://en.wikipedia.org/wiki/Commutator_(electric)

https://en.wikipedia.org/wiki/Homopolar_generator



https://en.wikipedia.org/wiki/Electrolytic

https://en.wikipedia.org/wiki/Breakdown_voltage



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than mechanical methods, and can be sensitive to usage variations which can drastically

change or completely disrupt the rectification processes.

Similar electrolytic devices were used as lightning arresters around the same era

by suspending many aluminium cones in a tank of tri-ammomium ortho-phosphate

solution. Unlike the rectifier above, only aluminium electrodes were used, and used on

A.C., there was no polarization and thus no rectifier action, but the chemistry was similar.

The modern electrolytic capacitor, an essential component of most rectifier circuit

configurations was also developed from the electrolytic rectifier.

6. Plasma type

7. Mercury arc

A rectifier used in high-voltage direct current (HVDC) power transmission systems and

industrial processing between about 1909 to 1975 is a mercury arc rectifier or mercury

arc valve. The device is enclosed in a bulbous glass vessel or large metal tub. One

electrode, the cathode, is submerged in a pool of liquid mercury at the bottom of the

vessel and one or more high purity graphite electrodes, called anodes, are suspended

above the pool. There may be several auxiliary electrodes to aid in starting and

maintaining the arc. When an electric arc is established between the cathode pool and

suspended anodes, a stream of electrons flows from the cathode to the anodes through the

ionized mercury, but not the other way (in principle, this is a higher-power counterpart

to flame rectification, which uses the same one-way current transmission properties of the

plasma naturally present in a flame).

These devices can be used at power levels of hundreds of kilowatts, and may be

built to handle one to six phases of AC current. Mercury arc rectifiers have been replaced

by silicon semiconductor rectifiers and high-power thyristor circuits in the mid 1970s.

The most powerful mercury arc rectifiers ever built were installed in the Manitoba

Hydro Nelson River Bipole HVDC project, with a combined rating of more than 1 GW

and 450 kV.

8. Argon gas electron tube

The General Electric Tungar rectifier was an argon gas-filled electron tube device with a

tungsten filament cathode and a carbon button anode. It was used for battery chargers and

similar applications from the 1920s until lower-cost metal rectifiers, and later

semiconductor diodes, supplanted it. These were made up to a few hundred volts and a

few amperes rating, and in some sizes strongly resembled an incandescent lamp with an

additional electrode.

The 0Z4 was a gas-filled rectifier tube commonly used in vacuum tube car radios

in the 1940s and 1950s. It was a conventional full-wave rectifier tube with two anodes

and one cathode, but was unique in that it had no filament (thus the "0" in its type


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number). The electrodes were shaped such that the reverse breakdown voltage was much

higher than the forward breakdown voltage. Once the breakdown voltage was exceeded,

the 0Z4 switched to a low-resistance state with a forward voltage drop of about 24 V.

9. Vacuum tube (valve)

Since the discovery of the Edison effect or thermionic emission, various vacuum

tube devices were developed to rectify alternating currents. The simplest is the simple

vacuum diode (the term "valve" came into use for vacuum tubes in general due to this

unidirectional property, by analogy with a unidirectional fluid flow valve). Low-current

devices were used as signal detectors, first used in radio by Fleming in 1904. Many

vacuum-tube devices also used vacuum diode rectifiers in their power supplies, for

example the All American Five radio receiver. Vacuum rectifiers were made for very

high voltages, such as the high voltage power supply for the cathode ray

tube of television receivers, and the kenotron used for power supply in X-ray equipment.

However, vacuum rectifiers generally had current capacity rarely exceeding 250 mA

owing to the maximum current density that could be obtained by electrodes heated to

temperatures compatible with long life. Another limitation of the vacuum tube rectifier

was that the heater power supply often required special arrangements to insulate it from

the high voltages of the rectifier circuit.

10. Solid state

11. Crystal detector

The cat's-whisker detector, typically using a crystal of galena, was the earliest type of

semiconductor diode, though not recognised as such at the time.

12. Selenium and copper oxide rectifiers

Once common until replaced by more compact and less costly silicon solid-state

rectifiers, these units used stacks of metal plates and took advantage of

the semiconductor properties ofselenium or copper oxide. While selenium rectifiers were

lighter in weight and used less power than comparable vacuum tube rectifiers, they had

the disadvantage of finite life expectancy, increasing resistance with age, and were only

suitable to use at low frequencies. Both selenium and copper oxide rectifiers have

somewhat better tolerance of momentary voltage transients than silicon rectifiers.

Typically these rectifiers were made up of stacks of metal plates or washers, held

together by a central bolt, with the number of stacks determined by voltage; each cell was

rated for about 20 V. An automotive battery charger rectifier might have only one cell:

the high-voltage power supply for a vacuum tube might have dozens of stacked plates.

Current density in an air-cooled selenium stack was about 600 mA per square inch of

active area (about 90 mA per square centimeter).

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13. Silicon and germanium diodes

In the modern world, silicon diodes are the most widely used rectifiers for lower voltages

and powers, and have largely replaced earlier germanium diodes. For very high voltages

and powers, the added need for controllability has in practice caused simple silicon

diodes to be replaced by high-power thyristors (see below) and their newer actively gate-

controlled cousins.

14. High power: thyristors (SCRs) and newer silicon-based voltage sourced converters

In high-power applications, from 1975 to 2000, most mercury valve arc-rectifiers were

replaced by stacks of very high power thyristors, silicon devices with two extra layers of

semiconductor, in comparison to a simple diode.

In medium-power transmission applications, even more complex and

sophisticated voltage sourced converter (VSC) silicon semiconductor rectifier systems,

such as insulated gate bipolar transistors (IGBT) and gate turn-off thyristors (GTO), have

made smaller high voltage DC power transmission systems economical. All of these

devices function as rectifiers.

As of 2009 it was expected that these high-power silicon "self-commutating

switches," in particular IGBTs and a variant thyristor (related to the GTO) called

the integrated gate-commutated thyristor (IGCT), would be scaled-up in power rating to

the point that they would eventually replace simple thyristor-based AC rectification

systems for the highest power-transmission DC applications.

2.6.6 Applications

The primary application of rectifiers is to derive DC power from an AC supply. Virtually all

electronic devices require DC, so rectifiers are used inside the power supplies of virtually all

electronic equipment.

Converting DC power from one voltage to another is much more complicated. One

method of DC-to-DC conversion first converts power to AC (using a device called an inverter),

then uses a transformer to change the voltage, and finally rectifies power back to DC. A

frequency of typically several tens of kilohertz is used, as this requires much smaller inductance

than at lower frequencies and obviates the use of heavy, bulky, and expensive iron-cored units.

Rectifiers are also used for detection of amplitude modulated radio signals. The signal

may be amplified before detection. If not, a very low voltage drop diode or a diode biased with a

fixed voltage must be used. When using a rectifier for demodulation the capacitor and load

resistance must be carefully matched: too low a capacitance will result in the high frequency

carrier passing to the output, and too high will result in the capacitor just charging and staying

charged.

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https://en.wikipedia.org/wiki/Inverter_(electrical)

https://en.wikipedia.org/wiki/Detector_(radio)

https://en.wikipedia.org/wiki/Amplitude_modulation

Rectifiers are used to supply polarised voltage for welding. In such circuits control of the

output current is required; this is sometimes achieved by replacing some of the diodes in a bridge

rectifier with thyristors, effectively diodes whose voltage output can be regulated by switching

on and off withphase fired controllers.

Thyristors are used in various classes of railway rolling stock systems so that fine control

of the traction motors can be achieved. Gate turn-off thyristorsare used to produce alternating

current from a DC supply, for example on the Eurostar Trains to power the three-phase traction

motors.

2.7 Voltage Regulation

Voltage regulation is a measure of change in the voltage magnitude between the sending and

receiving end of a component, such as a transmission or distribution line. Voltage regulation

describes the ability of a system to provide near constant voltage over a wide range

of load conditions. The term may refer to a passive property that result in more or less voltage

drop under various load conditions, or to the active intervention with devices for the specific

purpose of adjusting voltage.

In electrical power systems it is a dimensionless quantity defined at the receiving end of a

transmission line as:

Percent VR = ( |Vnl| - |Vfl| ) * 100 / |Vfl|

where,

Vnl is voltage at no load and

Vfl is voltage at full load.

A smaller value of Voltage Regulation is usually beneficial.

The Voltage Regulation formula could be visualized with the following: "Consider power

being delivered to a load such that the voltage at the load is the load's rated voltage VRated, if then

the load disappears, the voltage at the point of the load will rise to Vnl."

Sometimes, the term voltage regulation is used to describe processes by which the

quantity VR is reduced, especially concerning special circuits and devices for this purpose

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http://en.wikipedia.org/wiki/Voltage

http://en.wikipedia.org/wiki/Transmission_line

http://en.wikipedia.org/wiki/Electrical_load

http://en.wikipedia.org/wiki/Dimensionless_quantity

2.7.1 Voltage Regulator

A voltage regulator is designed to automatically maintain a constant voltage level. A voltage

regulator may be a simple "feed-forward" design or may include negative feedback control

loops. It may use an electromechanical mechanism, or electronic components. Depending on the

design, it may be used to regulate one or more AC or DC voltages.

Electronic voltage regulators are found in devices such as computer power

supplies where they stabilize the DC voltages used by the processor and other elements. In

automobile alternators and central power station generator plants, voltage regulators control the

output of the plant. In an electric power distribution system, voltage regulators may be installed

at a substation or along distribution lines so that all customers receive steady voltage independent

of how much power is drawn from the line.

2.7.1.1 Measures of Regulator Quality

The output voltage can only be held roughly constant; the regulation is specified by two

measurements:

load regulation is the change in output voltage for a given change in load current (for

example: "typically 15 mV, maximum 100 mV for load currents between 5 mA and

1.4 A, at some specified temperature and input voltage").

line regulation or input regulation is the degree to which output voltage changes with

input (supply) voltage changes - as a ratio of output to input change (for example

"typically 13 mV/V"), or the output voltage change over the entire specified input voltage

range (for example "plus or minus 2% for input voltages between 90 V and 260 V, 50-

60 Hz").

Other important parameters are:

Temperature coefficient of the output voltage is the change with temperature (perhaps

averaged over a given temperature range).

Initial accuracy of a voltage regulator (or simply "the voltage accuracy") reflects the error

in output voltage for a fixed regulator without taking into account temperature or aging

effects on output accuracy.

Dropout voltage is the minimum difference between input voltage and output voltage for

which the regulator can still supply the specified current. A low drop-out (LDO) regulator

is designed to work well even with an input supply only a volt or so above the output

voltage. The input-output differential at which the voltage regulator will no longer

maintain regulation is the dropout voltage. Further reduction in input voltage will result

in reduced output voltage. This value is dependent on load current and junction

temperature.

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Absolute maximum ratings are defined for regulator components, specifying the

continuous and peak output currents that may be used (sometimes internally limited), the

maximum input voltage, maximum power dissipation at a given temperature, etc.

Output noise (thermal white noise) and output dynamic impedance may be specified as

graphs versus frequency, while output ripple noise (mains "hum" or switch-mode "hash"

noise) may be given as peak-to-peak or RMS voltages, or in terms of their spectra.

Quiescent current in a regulator circuit is the current drawn internally, not available to the

load, normally measured as the input current while no load is connected (and hence a

source of inefficiency; some linear regulators are, surprisingly, more efficient at very low

current loads than switch-mode designs because of this).

Transient response is the reaction of a regulator when a (sudden) change of the load

current (called the load transient) or input voltage (called the line transient) occurs. Some

regulators will tend to oscillate or have a slow response time which in some cases might

lead to undesired results. This value is different from the regulation parameters, as that is

the stable situation definition. The transient response shows the behaviour of the

regulator on a change. This data is usually provided in the technical documentation of a

regulator and is also dependent on output capacitance.

Mirror-image insertion protection means that a regulator is designed for use when a

voltage, usually not higher than the maximum input voltage of the regulator, is applied to

its output pin while its input terminal is at a low voltage, volt-free or grounded. Some

regulators can continuously withstand this situation; others might only manage it for a

limited time such as 60 seconds, as usually specified in the datasheet. This situation can

occur when a three terminal regulator is incorrectly mounted for example on a PCB, with

the output terminal connected to the unregulated DC input and the input connected to the

load. Mirror-image insertion protection is also important when a regulator circuit is used

in battery charging circuits, when external power fails or is not turned on and the output

terminal remains at battery voltage.

2.7.1.2 Electronic Voltage Regulator

A simple voltage regulator can be made from a resistor in series with a diode (or series of

diodes). Due to the logarithmic shape of diode V-I curves, the voltage across the diode changes

only slightly due to changes in current drawn or changes in the input. When precise voltage

control and efficiency are not important, this design may work fine.

Feedback voltage regulators operate by comparing the actual output voltage to some

fixed reference voltage. Any difference is amplified and used to control the regulation element in

such a way as to reduce the voltage error. This forms a negative feedback control loop;

increasing the open-loop gain tends to increase regulation accuracy but reduce stability

(avoidance of oscillation, or ringing during step changes). There will also be a trade-off between

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https://en.wikipedia.org/wiki/Open-loop_gain

stability and the speed of the response to changes. If the output voltage is too low (perhaps due to

input voltage reducing or load current increasing), the regulation element is commanded, up to a

point, to produce a higher output voltage–by dropping less of the input voltage (for linear series

regulators and buck switching regulators), or to draw input current for longer periods (boost-

type switching regulators); if the output voltage is too high, the regulation element will normally

be commanded to produce a lower voltage. However, many regulators have over-current

protection, so that they will entirely stop sourcing current (or limit the current in some way) if

the output current is too high, and some regulators may also shut down if the input voltage is

outside a given range (see also: crowbar circuits).

2.7.1.3 Electromechanical Regulators

In electromechanical regulators, voltage regulation is easily accomplished by coiling the sensing

wire to make an electromagnet. The magnetic field produced by the current attracts a moving

ferrous core held back under spring tension or gravitational pull. As voltage increases, so does

the current, strengthening the magnetic field produced by the coil and pulling the core towards

the field. The magnet is physically connected to a mechanical power switch, which opens as the

magnet moves into the field. As voltage decreases, so does the current, releasing spring tension

or the weight of the core and causing it to retract. This closes the switch and allows the power to

flow once more.

If the mechanical regulator design is sensitive to small voltage fluctuations, the motion of

the solenoid core can be used to move a selector switch across a range of resistances or

transformer windings to gradually step the output voltage up or down, or to rotate the position of

a moving-coil AC regulator.

Early automobile generators and alternators had a mechanical voltage regulator using

one, two, or three relays and various resistors to stabilize the generator's output at slightly more

than 6 or 12 V, independent of the engine's rpm or the varying load on the vehicle's electrical

system. Essentially, the relay(s) employed pulse width modulation to regulate the output of the

generator, controlling the field current reaching the generator (or alternator) and in this way

controlling the output voltage produced.

The regulators used for DC generators (but not alternators) also disconnect the generator

when it was not producing electricity, thereby preventing the battery from discharging back into

the generator and attempting to run it as a motor. The rectifier diodes in an alternator

automatically perform this function so that a specific relay is not required; this appreciably

simplified the regulator design.

More modern designs now use solid state technology (transistors) to perform the same

function that the relays perform in electromechanical regulators.

Electromechanical regulators are used for mains voltage stabilisation

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https://en.wikipedia.org/wiki/Crowbar_(circuit)

https://en.wikipedia.org/wiki/Magnetic_field

https://en.wikipedia.org/wiki/Automobile

https://en.wikipedia.org/wiki/Electrical_generator

https://en.wikipedia.org/wiki/Alternator_(auto)

https://en.wikipedia.org/wiki/Relay

https://en.wikipedia.org/wiki/Resistor

https://en.wikipedia.org/wiki/Internal_combustion_engine

https://en.wikipedia.org/wiki/Rpm

https://en.wikipedia.org/wiki/Pulse_width_modulation

https://en.wikipedia.org/wiki/Rectifier


https://en.wikipedia.org/wiki/Transistor

REVIEW QUESTIONS

1. Classify the solids based on the energy band theory?

2. What are the various categories of semiconductors?

3. Explain Intrinsic Semiconductors.

4. Explain Extrinsic Semiconductors.

5. Distinguish between P-Type and N-Type Semiconductors?

6. What do you mean by PN junction diode?

7. Define the working of Zener diode.

8. Define Rectifiers.

9. Explain the function of Half wave and Full wave Rectifier.

10. What do you mean by Voltage Regulation.

CHAPTER 3

TRANSISTORS & AMPLIFIERS

3.1 Introduction to Transistors Basically, the transistor consists of two back-to back P-N junctions manufactured in a single

piece of a semiconductor crystal. These two junctions give rise to three regions called emitter,

base and collector. As shown in Fig. 1 (a) junction transistor is simply a sandwich of one type of

semiconductor material between two layers of the other type. Fig. 1 (a) shows a layer of N-type

material sandwiched between two layers of P-type material. It is described as a PNP transistor.

Fig. 1 (b) shown an NPN – transistor consisting of a layer of P-type material sandwiched

between two layers of N-type material. The emitter, base and collector are provided with

terminals which are labelled as E, B and C. The two junctions are: emitter-base (E/B) junction

and collector-base (C/B) junction. The symbols employed for PNP and NPN transistors are also

shown in Fig. 1. For a PNP transistor, arrowhead points from emitter to base meaning that

emitter is positive with respect to base (and also with respect to collector)* For NPN transistor, it

points from base to emitter meaning that base (and collector as well)* is positive with respect to

the emitter.

(a) (b)

1. Emitter: It is more heavily doped than any of the other regions because its main function is to

supply majority charge carries (either electrons or holes) to the base.

2. Base: It forms the middle section of the transistor. It is very thin (10–6 m) as compared to

either the emitter or collector and is very lightly-doped.

3. Collector: Its main function (as indicated by its name) is to collect majority charge carriers

coming from the emitter and passing through the base.

3.2 Bipolar Junction Transistor A bipolar junction transistor is formed by joining three sections of semiconductors with

alternatively different dopings. The middle section (base) is narrow and one of the other two

regions (emitter) is heavily doped. Two variants of BJT are possible: NPN and PNP.

We will focus on NPN BJTs. Operation of a PNP transistor is analogous to that of a NPN

transistor except that the role of ―majority" charge carries reversed. In NPN transistors, electron

flow is dominant while PNP transistors rely mostly on the flow of ―holes." Therefore, to zeroth

order, NPN and PNP transistors behave similarly except the sign of current and voltages are

reversed. i.e., PNP = - NPN ! In practice, NPN transistors are much more popular than PNP

transistors because electrons move faster in a semiconductor. As a results, a NPN transistor has a

faster response time compared to a PNP transistor.

At the first glance, a BJT looks like 2 diodes placed back to back. Indeed this is the case

if we apply voltage to only two of the three terminals, letting the third terminal oat. This is also

the way that we check if a transistor is working: use an ohm-meter to ensure both diodes are in

working conditions. (One should also check the resistance between CE terminals and read a vary

high resistance as one may have a burn through the base connecting collector and emitter.)

The behavior of the BJT is different, however, when voltage sources are attached to both

BE and CE terminals. The BE junction acts like a diode. When this junction is forward biased,

electrons flow from emitter to the base (and a small current of holes from base to emitter). The

base region is narrow and when a voltage is applied between collector and emitter, most of the

electrons that were flowing from emitter to base, cross the narrow base region and are collected

at the collector region. So while the BC junction is reversed biased, a large current can flow

through that region and BC junction does not act as a diode.

The amount of the current that crosses from emitter to collector region depends strongly

on the voltage applied to the BE junction, vBE. (It also depends weakly on voltage applied

between collector and emitter, vCE.) As such, small changes in vBE or iB controls a much larger

collector current iC. Note that the transistor does not generate iC. It acts as a valve controlling the

current that can flow through it. The source of current (and power) is the power supply that feeds

the CE terminals.

A BJT has three terminals. Six parameters; iC, iB, iE, vCE, vBE, and vCB; define the state of

the transistor. However, because BJT has three terminals, KVL and KCL should hold for these

terminals, i.e.

iE = iC + iB

vBC = vBE - vCE

Several ―models" available for a BJT. These are typically divided into two general categories:

―large-signal" models that apply to the entire range of values of current and voltages, and ―small-

signal" models that apply to AC signals with small amplitudes. ―Low-frequency" and ―high-

frequency" models also exist (high-frequency models account for capacitance of each junction).

Obviously, the simpler the model, the easier the circuit calculations are. More complex models

describe the behavior of a BJT more accurately but analytical calculations become diffcult.

PSpice program uses a high-frequency, Eber-Mos large-signal model which is a quite accurate

representation of BJT.

3.3 CB, CE, CC configuration and characteristics

3.3.1 Common-Base Configuration In electronics, a common-base (also known as grounded-base) amplifier is one of three basic

single-stage bipolar junction transistor (BJT) amplifier topologies, typically used as

a current buffer or voltage amplifier. In this circuit the emitter terminal of the transistor serves as

the input, the collector the output, and the base is connected to ground, or "common," hence its

name. The analogous field-effect transistor circuit is the common-gate amplifier. The input

signal is applied between the emitter and base whereas output is taken out from the collector.

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3.3.1.1 Common-Base Output Characteristics

The CB output characteristics are plots of IC vs VCB and are shown in Fig. below. There are 4

points to note.

1) Even when IE = 0 a small current flows – this is ICBO, the reverse current through the

reverse-biased collector base junction.

2) For VCB > 0 the characteristics are essentially flat, i.e. IC is independent of VCB. Hence the

output resistance is large. (In reality, there is a finite slope on the flat sections because _ varies

with IC and VCB.) Note also that in these flat regions IC ≈ IE since _ ≈ 1.

3) At large values of VCB the characteristics turn up due to breakdown at the reverse-biased

collector-base junction.

4) The characteristics fall rapidly to zero for VCB < 0, i.e. when the collector-base junction

becomes forward biased.

3.3.1.2 Applications

This arrangement is not very common in low-frequency circuits, where it is usually employed for

amplifiers that require an unusually low input impedance, for example to act as a preamplifier for

moving-coil microphones. However, it is popular in high-frequency amplifiers, for example

for VHF and UHF, because its input capacitance does not suffer from the Miller effect, which

degrades the bandwidth of the common-emitter configuration, and because of the relatively high

isolation between the input and output. This high isolation means that there is little feedback

from the output back to the input, leading to high stability.

This configuration is also useful as a current buffer since it has a current gain of

approximately unity (see formulas below). Often a common base is used in this manner,

preceded by a common-emitter stage. The combination of these two form

the cascade configuration, which possesses several of the benefits of each configuration, such as

high input impedance and isolation.

3.3.2 Common-Emitter Configuration The input characteristics for the CE configuration (Fig. below) are again essentially those for a

forward-biased diode. The plots depend on VCE because as VCE increases, the reverse bias at

the collector-base junction increases and so the effective width of the base region decreases (the

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http://en.wikipedia.org/wiki/Common-emitter

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Early Effect again). If the base becomes narrower there will be less recombination taking place

in it so IB will decrease, since IB supplies the carriers required for recombination in the base.

The CE output characteristics (Fig. 119) are similar in shape to those for the CB

configuration. A small current flows even when IB = 0 – this is ICEO. Breakdown occurs at

large values of VCE. Notice that IB is in microamps whereas IC is in milliamps – this is because

current amplification is occurring in this configuration: IC ≈ βIB.

3.3.2.1 Common-Emitter Output Characteristics

From Fig. below it is clear that the characteristics for the CE configurations will be the plots

given below:

CE CC

Input Characteristics IB(VBE) IB(VCB)

Output Characteristics IC(VCE) IE(VCE)

3.3.2.2 Emitter Degeneration

Common- emitter amplifiers give the amplifier an inverted output and can have a very

high gain that may vary widely from one transistor to the next. The gain is a strong function of

both temperature and bias current, and so the actual gain is somewhat unpredictable. Stability is

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another problem associated with such high gain circuits due to any unintentional positive

feedback that may be present. Other problems associated with the circuit are the low

input dynamic range imposed by the small-signal limit; there is high distortion if this limit is

exceeded and the transistor ceases to behave like its small-signal model. One common way of

alleviating these issues is with the use of negative feedback, which is usually implemented

with emitter degeneration. Emitter degeneration refers to the addition of a small resistor (or

anyimpedance) between the emitter and the common signal source (e.g., the ground reference or

a power supply rail). This impedance reduces the overall transconductance of

the circuit by a factor of , which makes the voltage gain

So the voltage gain depends almost exclusively on the ratio of the resistors rather than

the transistor's intrinsic and unpredictable characteristics. The distortion and stability

characteristics of the circuit are thus improved at the expense of a reduction in gain.


1. Low frequency voltage amplifier

A typical example of the use of a common-emitter amplifier is shown in Figure below:

The input capacitor C removes any constant component of the input, and the

resistors R1 and R2 bias the transistor so that it will remain in active mode for the entire range of

the input. The output is an inverted copy of the AC-component of the input that has been

amplified by the ratio RC/RE and shifted by an amount determined by all four resistors.

Because RC is often large, the output impedance of this circuit can be prohibitively high. To

alleviate this problem, RC is kept as low as possible and the amplifier is followed by a

voltage buffer like an emitter follower.

2. Radio

Common-emitter amplifiers are also used in radio frequency circuits, for example to amplify

faint signals received by an antenna. In this case it is common to replace the load resistor with a

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tuned circuit. This may be done to limit the bandwidth to a narrow band centered around the

intended operating frequency. More importantly it also allows the circuit to operate at higher

frequencies as the tuned circuit can be used to resonate any inter-electrode and stray

capacitances, which normally limit the frequency response. Common emitters are also

commonly used as low-noise amplifiers.

3.3.3 Common Collector Configuration In electronics, a common-collector amplifier (also known as an emitter follower or BJT voltage

follower) is one of three basic single-stage bipolar junction transistor(BJT) amplifier topologies,

typically used as a voltage buffer. In this circuit the base terminal of the transistor serves as the

input, the emitter is the output, and the collector is common to both (for example, it may be tied

to ground reference or a power supply rail), hence its name. The analogous field-effect

transistor circuit is the common-drain amplifier.

3.3.3.1 Common-Collector Basic Circuit

The circuit can be explained by viewing the transistor as being under the control of negative

feedback. From this viewpoint, a common-collector stage (Fig. above) is an amplifier with full

series negative feedback. In this configuration (Fig. below with β = 1), the entire output voltage

VOUT is placed contrary and in series with the input voltage VIN. Thus the two voltages are

subtracted according to KVL (the subtractor from the function block diagram is implemented

just by the input loop) and their difference Vdiff = VIN - VOUT is applied to the base-emitter

junction. The transistor monitors continuously Vdiff and adjusts its emitter voltage almost equal

(less VBEO) to the input voltage by passing the according collector current through the emitter

resistor RE. As a result, the output voltage follows the input voltage variations from VBEO up to

V+; hence the name, emitter follower. Intuitively, this behavior can be also understood by

realizing that the base-emitter voltage in the bipolar transistor is very insensitive to bias changes,

so any change in base voltage is transmitted (to good approximation) directly to the emitter. It

depends slightly on various disturbances (transistor tolerances, temperature variations, load

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resistance, collector resistor if it is added, etc.) since the transistor reacts to these disturbances

and restores the equilibrium. It never saturates even if the input voltage reaches the positive rail.

The common collector circuit can be shown mathematically to have a voltage gain of almost

unity:

A small voltage change on the input terminal will be replicated at the output (depending slightly

on the transistor's gain and the value of the load resistance; see gain formula below). This circuit

is useful because it has a large input impedance, so it will not load down the previous circuit:

and a small output impedance, so it can drive low-resistance loads:

Typically, the emitter resistor is significantly larger and can be removed from the equation:


The low output impedance allows a source with a large output impedance to drive a small load

impedance; it functions as a voltage buffer. In other words, the circuit has current gain (which

depends largely on the hFE of the transistor) instead of voltage gain. A small change to the input

current results in much larger change in the output current supplied to the output load.

One aspect of buffer action is transformation of impedances. For example, the Thévenin

resistance of a combination of a voltage follower driven by a voltage source with high Thévenin

resistance is reduced to only the output resistance of the voltage follower (a small resistance).

That resistance reduction makes the combination a more ideal voltage source. Conversely, a


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voltage follower inserted between a small load resistance and a driving stage presents a large

load to the driving stage—an advantage in coupling a voltage signal to a small load.

This configuration is commonly used in the output stages of class-B and class-AB amplifiers.

The base circuit is modified to operate the transistor in class-B or AB mode. In class-A mode,

sometimes an active current source is used instead of RE (Fig. below) to improve linearity and/or

efficiency.

3.4 Biasing Circuit

Biasing in electronics is the method of establishing predetermined voltages or currents at various

points of an electronic circuit for the purpose of establishing proper operating conditions in

electronic components. Many electronic devices whose function is signal processing time-

varying (AC) signals also require a steady (DC) current or voltage to operate correctly. The AC

signal applied to them is superposed on this DC bias current or voltage. Other types of devices,

for example magnetic recording heads, require a time-varying (AC) signal as bias. The operating

point of a device, also known as bias point, quiescent point, or Q-point, is the steady-state

voltage or current at a specified terminal of an active device (a transistor or vacuum tube) with

no input signal applied.

For proper working of a transistor, it is essential to apply voltages of correct polarity

across its two depletion layers one with each junctions. These layers form a barrier which is need

some positional to breaking this potential is 0.7 V. for Si junction and 0.3 V. for Ge junction. For

the normal operation of the transistor ,the following should be verified:

1. emitter-base junction is always forward biased and

2. collector-base junction is always reverse- biased.

This type of biasing is known as reverse biasing. As showing in fig. (below)

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Positive terminal of VEE is connected to P-type emitter in order to repel or Push holes into the

base. The negative terminal of VCC is connected to the collector so that it may attract or pull

holes through the base. Similar considerations apply to the NPN transistor. It must be

remembered that a transistor will never conduct any current if its emitter-base junction is not

forward- biased.

3.4.1 Need For Biasing a Transistor For normal operation of a transistor amplifier circuit, it is essential that there should be a

(a) Forward bias on the emitter-base junction and

(b) Reverse bias on the collector-base junction.

In addition, amount of bias required is important for establishing the Q-point which is dictated by

the mode of operation desired. If the transistor is not biased correctly, it would

1. Work inefficiently and

2. Produce distortion in the output signal.

3.4.2 Different Methods for Transistor Biasing

Some of the methods used for providing bias for a transistor are:

1. Base bias or fixed current bias.

It is not a very satisfactory method because bias voltages and currents do not remain constant

during transistor operation.

2. Base bias with emitter feedback

This circuit achieves good stability of dc operating point against changes in β with the help of

emitter resistor which causes degeneration to take place.

3. Base bias with collector feedbac.

It is also known as collector-to-base bias or collector feedback bias. It provides better bias

stability.

4. Voltage divider bias

It is most widely used in linear discrete circuits because it provides good bias stability. It is also

called universal bias circuit or base bias with one supply.

3.5 Amplifiers

An electronic amplifier, amplifier, or (informally) amp is an electronic device that increases

the power of a signal. It does this by taking energy from a power supply and controlling the

output to match the input signal shape but with a larger amplitude. In this sense, an amplifier

modulates the output of the power supply.

Numerous types of electronic amplifiers are specialized to various applications. An

amplifier can refer to anything from an electrical circuit that uses a single active component, to a

complete system such as a packaged audio hi-fi amplifier.

3.5.1 Amplifier Characteristics

Amplifier quality is characterized by a list of specifications that includes:

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Gain, the ratio between the magnitude of output and input signals

Bandwidth, the width of the useful frequency range

Efficiency, the ratio between the power of the output and total power consumption

Linearity, the degree of proportionality between input and output

Noise, a measure of undesired noise mixed into the output

Output dynamic range, the ratio of the largest and the smallest useful output levels

Slew rate, the maximum rate of change of the output

Rise time, settling time, ringing and overshoot that characterize the step response

Stability, the ability to avoid self-oscillation

3.5.2 Amplifier Types

Amplifiers are described according to their input and output properties.[1]

They have some kind

of gain, or multiplication factor that relates the magnitude of the output signal to the input signal.

The gain may be specified as the ratio of output voltage to input voltage (voltage gain), output

power to input power (power gain), or some combination of current, voltage, and power. In

many cases, with input and output in the same unit, gain is unit less (though often expressed

in decibels). For others this is not necessarily so. For example, a transconductance amplifier has

a gain with units of conductance (output current per input voltage). The power gain of an

amplifier depends on the source and load impedances used as well as its voltage gain; while

an RF amplifier may have its impedances optimized for power transfer, audio and

instrumentation amplifiers are normally employed with amplifier input and output impedances

optimized for least loading and highest quality. So an amplifier that is said to have a gain of

20 dB might have a voltage gain of ten times and an available power gain of much more than

20 dB (100 times power ratio), yet be delivering a much lower power gain if, for example, the

input is a 600 ohm microphone and the output is a 47 kilohm power amplifier's input socket.

In most cases an amplifier should be linear; that is, the gain should be constant for any

combination of input and output signal. If the gain is not constant, e.g., by clipping the output

signal at the limits of its capabilities, the output signal is distorted. There are however cases

where variable gain is useful.

There are many types of electronic amplifiers, commonly used

in radio and television transmitters and receivers, high-fidelity ("hi-fi") stereo equipment,

microcomputers and other electronic digital equipment, and guitar and other instrument

amplifiers. Critical components include active devices, such as vacuum tubes or transistors. A

brief introduction to the many types of electronic amplifier follows.

1. Power amplifier: The term power amplifier is a relative term with respect to the amount

of power delivered to the load and/or sourced by the supply circuit. In general a power

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amplifier is designated as the last amplifier in a transmission chain (the output stage) and

is the amplifier stage that typically requires most attention to power efficiency. Efficiency

considerations lead to various classes of power amplifier based on the biasing of the

output transistors or tubes: see power amplifier classes.

i. Power amplifiers by application:

- Audio power amplifiers

- RF power amplifier, such as for transmitter final stages (see

also: Linear amplifier).

- Servo motor controllers, where linearity is not important.

- Piezoelectric audio amplifier includes a DC-to-DC converter to

generate the high voltage output required to drive piezoelectric

speakers.[2]

ii. Power amplifier circuits: Power amplifier circuits include the following types:

- Vacuum tube/valve, hybrid or transistor power amplifiers

- Push-pull output or single-ended output stages

2. Vacuum-tube (valve) amplifiers: According to Symons, while semiconductor

amplifiers have largely displaced valve amplifiers for low power applications, valve

amplifiers are much more cost effective in high power applications such as "radar,

countermeasures equipment, or communications equipment". Many microwave

amplifiers are specially designed valves, such as the klystron, gyrotron, traveling wave

tube, and crossed-field amplifier, and these microwave valves provide much greater

single-device power output at microwave frequencies than solid-state devices.

Valves/tube amplifiers also have niche uses in other areas, such as

- electric guitar amplification

- in Russian military aircraft, for their EMP tolerance

- niche audio for their sound qualities (recording, and audiophile equipment)

3. Transistor amplifiers: The essential role of this active element is to magnify an input

signal to yield a significantly larger output signal. The amount of magnification (the

"forward gain") is determined by the external circuit design as well as the active device.

Many common active devices in transistor amplifiers are bipolar junction

transistors (BJTs) and metal oxide semiconductor field-effect transistors (MOSFETs).

Applications are numerous, some common examples are audio amplifiers in a home

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stereo or PA system, RF high power generation for semiconductor equipment, to RF and

Microwave applications such as radio transmitters.

Transistor-based amplifier can be realized using various configurations: for

example with a bipolar junction transistor we can realize common base, common

collector or common emitter amplifier; using a MOSFET we can realize common

gate, common source or common drain amplifier. Each configuration has different

characteristic (gain, impedance...).

4. Operational amplifiers (op-amps): An operational amplifier is an amplifier circuit with

very high open loop gain and differential inputs that employs external feedback to control

its transfer function, or gain. Though the term today commonly applies to integrated

circuits, the original operational amplifier design used valves.

5. Fully differential amplifiers: A fully differential amplifier is a solid state integrated

circuit amplifier that uses external feedback to control its transfer function or gain. It is

similar to the operational amplifier, but also has differential output pins. These are

usually constructed using BJTs or FETs.

6. Video amplifiers: These deal with video signals and have varying bandwidths depending

on whether the video signal is for SDTV, EDTV, HDTV 720p or 1080i/p etc.. The

specification of the bandwidth itself depends on what kind of filter is used—and at which

point (-1 dB or -3 dB for example) the bandwidth is measured. Certain requirements for

step response and overshoot are necessary for an acceptable TV image.

7. Oscilloscope vertical amplifiers: These deal with video signals that drive an

oscilloscope display tube, and can have bandwidths of about 500 MHz. The

specifications on step response, rise time, overshoot, and aberrations can make designing

these amplifiers difficult. One of the pioneers in high bandwidth vertical amplifiers was

the Tektronix company.

8. Distributed amplifiers: These use transmission lines to temporally split the signal and

amplify each portion separately to achieve higher bandwidth than possible from a single

amplifier. The outputs of each stage are combined in the output transmission line. This

type of amplifier was commonly used on oscilloscopes as the final vertical amplifier. The

transmission lines were often housed inside the display tube glass envelope.

9. Switched mode amplifiers: These nonlinear amplifiers have much higher efficiencies

than linear amps, and are used where the power saving justifies the extra complexity.

10. Negative resistance devices: Negative resistances can be used as amplifiers, such as

the tunnel diode amplifier.

11. Microwave amplifiers

12. Travelling wave tube amplifiers: Traveling wave tube amplifiers (TWTAs) are used for

high power amplification at low microwave frequencies. They typically can amplify

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across a broad spectrum of frequencies; however, they are usually not as tunable as

klystrons.

13. Klystrons:Klystrons are specialized linear-beam vacuum-devices, designed to provide

high power, widely tunable amplification of millimetre and sub-millimetre waves.

Klystrons are designed for large scale operations and despite having a narrower

bandwidth than TWTAs, they have the advantage of coherently amplifying a reference

signal so its output may be precisely controlled in amplitude, frequency and phase.

14. Musical instrument amplifiers: An audio power amplifier is usually used to amplify

signals such as music or speech. Several factors are especially important in the selection

of musical instrument amplifiers (such as guitar amplifiers) and other audio amplifiers

(although the whole of the sound system – components such

as microphones to loudspeakers – affect these parameters):

i. Frequency response – not just the frequency range but the requirement that the

signal level varies so little across the audible frequency range that the human ear

notices no variation. A typical specification for audio amplifiers may be

20 Hz to 20 kHz +/- 0.5dB.

ii. Power output – the power level obtainable with little distortion, to obtain a

sufficiently loud sound pressure level from the loudspeakers.

iii. Low distortion – all amplifiers and transducers distort to some extent. They

cannot be perfectly linear, but aim to pass signals without affecting

the harmonic content of the sound more than the human ear can tolerate. That

tolerance of distortion, and indeed the possibility that some "warmth" or second

harmonic distortion (Tube sound) improves the "musicality" of the sound, are

subjects of great debate.

3.5.3 Power Amplifier Classes

Power amplifier circuits (output stages) are classified as A, B, AB and C for analog designs, and

class D and E for switching designs based on the proportion of each input cycle (conduction

angle), during which an amplifying device is passing current. The image of the conduction angle

is derived from amplifying a sinusoidal signal. If the device is always on, the conducting angle is

360°. If it is on for only half of each cycle, the angle is 180°. The angle of flow is closely related

to the amplifier power efficiency. The various classes are introduced below, followed by a more

detailed discussion under their individual headings further down.

In the illustrations below, a bipolar junction transistor is shown as the amplifying device, but the

same attributes are found if with MOSFETs or vacuum tubes.

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3.5.3.1 Conduction angle classes

Class A: 100% of the input signal is used (conduction angle Θ = 360°). The active element

remains conducting all of the time.

Class B: 50% of the input signal is used (Θ = 180°); the active element carries current half of

each cycle, and is turned off for the other half.

Class AB: Class AB is intermediate between class A and B, the two active elements conduct

more than half of the time

Class C: Less than 50% of the input signal is used (conduction angle Θ < 180°).

A "Class D" amplifier uses some form of pulse-width modulation to control the output devices;

the conduction angle of each device is no longer related directly to the input signal but instead

varies in pulse width. These are sometimes called "digital" amplifiers because the output device

is switched fully on or off, and not carrying current proportional to the signal amplitude.

Additional classes: There are several other amplifier classes, although they are mainly

variations of the previous classes. For example, class-G and class-H amplifiers are marked by

variation of the supply rails (in discrete steps or in a continuous fashion, respectively) following

the input signal. Wasted heat on the output devices can be reduced as excess voltage is kept to a

minimum. The amplifier that is fed with these rails itself can be of any class. These kinds of

amplifiers are more complex, and are mainly used for specialized applications, such as very

high-power units. Also, class-E and class-F amplifiers are commonly described in literature for

radio-frequency applications where efficiency of the traditional classes is important, yet several

aspects deviate substantially from their ideal values. These classes use harmonic tuning of their

output networks to achieve higher efficiency and can be considered a subset of class C due to

their conduction-angle characteristics.

3.5.3.1.1 Class A

Amplifying devices operating in class A conduct over the whole of the input cycle. A class-A

amplifier is distinguished by the output stage being biased into class A (see definition above).

Subclass A2 is sometimes used to refer to vacuum-tube class-A stages where the grid is allowed

to be driven slightly positive on signal peaks, resulting in slightly more power than normal class

A (A1; where the grid is always negative), but incurring more distortion.

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Advantages of class-A amplifiers

Class-A designs are simpler than other classes; for example class-AB and -B designs

require two devices (push–pull output) to handle both halves of the waveform; class

A can use a single device single-ended.

The amplifying element is biased so the device is always conducting to some extent,

normally implying the quiescent (small-signal) collector current (for transistors; drain

current for FETs or anode/plate current for vacuum tubes) is close to the most linear

portion of its transconductance curve.

Because the device is never shut off completely there is no "turn on" time, little

problem with charge storage, and generally better high frequency performance and

feedback loop stability (and usually fewer high-order harmonics).

The point at which the device comes closest to being cut off is not close to zero

signal, so the problem of crossover distortion associated with class-AB and -B

designs is avoided.

Disadvantage of class-A amplifiers

They are very inefficient. A theoretical maximum of 50% is obtainable with

inductive output coupling and only 25% with capacitive coupling, unless deliberate

use of nonlinearities is made (such as in square-law output stages). In a power

amplifier, this not only wastes power and limits battery operation, increase costs and

may restrict the output devices that can be used (for example, ruling out some audio

triodes to accommodate modern low-efficiency loudspeakers. Inefficiency comes not

just from the fact that the device is always conducting to some extent. (That happens

even with class AB, yet its efficiency can be close to class B.) It is that the standing

current is roughly half the maximum output current (though this can be less with a

square law output stage), and a large part of the power supply voltage develops

across the output device at low signal levels (as with classes AB and B, but unlike

output stages such as class D). If high output powers are needed from a class-A

circuit, the power waste (and the accompanying heat) becomes significant. For

every watt delivered to the load, the amplifier itself, at best, dissipates another watt.

For large powers this means very large and expensive power supplies and heat

sinking.

Class-A designs have largely been superseded by the more efficient designs for power

amplifiers, though they remain popular with some hobbyists, mostly for their simplicity. There is

a market for expensive high fidelity class-A amps considered a "cult item" amongst

audiophiles mainly for their absence of crossover distortion and reduced odd-harmonic and high-

order harmonic distortion.

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Class A Amplifier

Class-A amplifiers are often used in output stages of high quality op-amps (although the

accuracy of the bias in low cost op-amps such as the 741 may result in class A or class AB or

class B, varying from device to device or with temperature). They are sometimes used as

medium-power, low-efficiency, and high-cost audio power amplifiers. The power consumption

is unrelated to the output power. At idle (no input), the power consumption is essentially the

same as at high output volume. The result is low efficiency and high heat dissipation.

3.5.3.1.2 Class B

Class-B amplifiers only amplify half of the input wave cycle, thus creating a large amount of

distortion, but their efficiency is greatly improved and is much better than class A. Class-B

amplifiers are also favored in battery-operated devices, such as transistor radios. Class B has a

maximum theoretical efficiency of π/4. (i.e. 78.5%) This is because the amplifying element is

switched off altogether half of the time, and so cannot dissipate power. A single class-B element

is rarely found in practice, though it has been used for driving the loudspeaker in the early IBM

Personal Computers with beeps, and it can be used in RF power amplifier where the distortion

levels are less important. However, class C is more commonly used for this.

A practical circuit using class-B elements is the push–pull stage, such as the very simplified

complementary pair arrangement shown below. Here, complementary or quasi-complementary

devices are each used for amplifying the opposite halves of the input signal, which is then

recombined at the output. This arrangement gives excellent efficiency, but can suffer from the

drawback that there is a small mismatch in the cross-over region – at the "joins" between the two

https://en.wikipedia.org/wiki/Operational_amplifier

https://en.wikipedia.org/wiki/Transistor_radio

https://en.wikipedia.org/wiki/Loudspeaker

https://en.wikipedia.org/wiki/IBM_Personal_Computer



https://en.wikipedia.org/wiki/RF_power_amplifier

https://en.wikipedia.org/wiki/Push-pull_output

halves of the signal, as one output device has to take over supplying power exactly as the other

finishes. This is called crossover distortion. An improvement is to bias the devices so they are

not completely off when they're not in use. This approach is called class AB operation.

3.5.3.1.3 Class AB

Class AB is widely considered a good compromise for audio power amplifiers, since much of the

time the music is quiet enough that the signal stays in the "class A" region, where it is amplified

with good fidelity, and by definition if passing out of this region, is large enough that the

distortion products typical of class B are relatively small. The crossover distortion can be

reduced further by using negative feedback.

In class-AB operation, each device operates the same way as in class B over half the waveform,

but also conducts a small amount on the other half. As a result, the region where both devices

simultaneously are nearly off (the "dead zone") is reduced. The result is that when the

waveforms from the two devices are combined, the crossover is greatly minimised or eliminated

altogether. The exact choice of quiescent current, the standing current through both devices when

there is no signal, makes a large difference to the level of distortion (and to the risk of thermal

runaway, that may damage the devices); often the bias voltage applied to set this quiescent

current has to be adjusted with the temperature of the output transistors (for example in the

circuit at the beginning of the article the diodes would be mounted physically close to the output

transistors, and chosen to have a matched temperature coefficient). Another approach (often used

as well as thermally tracking bias voltages) is to include small value resistors in series with the

emitters.

Class AB sacrifices some efficiency over class B in favor of linearity, thus is less

efficient (below 78.5% for full-amplitude sinewaves in transistor amplifiers, typically; much less

is common in class-AB vacuum-tube amplifiers). It is typically much more efficient than class A.

Sometimes a numeral is added for vacuum-tube stages. If the grid voltage is always

negative with respect to the cathode the class is AB1. If the grid is allowed to go slightly positive


https://en.wikipedia.org/wiki/Audio_distortion

https://en.wikipedia.org/wiki/Thermal_runaway



https://en.wikipedia.org/wiki/Sinewave

(hence drawing grid current, adding more distortion, but giving slightly higher output power) on

signal peaks the class is AB2.

3.5.3.1.4 Class C

Class-C amplifiers conduct less than 50% of the input signal and the distortion at the output is

high, but high efficiencies (up to 90%) are possible. The usual application for class-C amplifiers

is in RF transmitters operating at a single fixed carrier frequency, where the distortion is

controlled by a tuned load on the amplifier. The input signal is used to switch the active device

causing pulses of current to flow through a tuned circuit forming part of the load.

The class-C amplifier has two modes of operation: tuned and untuned. The diagram shows a

waveform from a simple class-C circuit without the tuned load. This is called untuned operation,

and the analysis of the waveforms shows the massive distortion that appears in the signal. When

the proper load (e.g., an inductive-capacitive filter plus a load resistor) is used, two things

happen. The first is that the output's bias level is clamped with the average output voltage equal

to the supply voltage. This is why tuned operation is sometimes called a clamper. This allows the

waveform to be restored to its proper shape despite the amplifier having only a one-polarity

supply. This is directly related to the second phenomenon: the waveform on the center frequency

becomes less distorted. The residual distortion is dependent upon the bandwidth of the tuned

load, with the center frequency seeing very little distortion, but greater attenuation the farther

from the tuned frequency that the signal gets.

The tuned circuit resonates at one frequency, the fixed carrier frequency, and so the unwanted

frequencies are suppressed, and the wanted full signal (sine wave) is extracted by the tuned load.

The signal bandwidth of the amplifier is limited by the Q-factor of the tuned circuit but this is not

a serious limitation. Any residual harmonics can be removed using a further filter.

In practical class-C amplifiers a tuned load is invariably used. In one common arrangement the

resistor shown in the circuit above is replaced with a parallel-tuned circuit consisting of an

inductor and capacitor in parallel, whose components are chosen to resonate the frequency of the

https://en.wikipedia.org/wiki/Transmitter

https://en.wikipedia.org/wiki/LC_circuit


https://en.wikipedia.org/wiki/Q-factor

input signal. Power can be coupled to a load by transformer action with a secondary coil wound

on the inductor. The average voltage at the drain is then equal to the supply voltage, and the

signal voltage appearing across the tuned circuit varies from near zero to near twice the supply

voltage during the rf cycle. The input circuit is biassed so that the active element (e.g. transistor)

conducts for only a fraction of the rf cycle, usually one third (120 degrees) or less.

The active element conducts only while the drain voltage is passing through its minimum. By

this means, power dissipation in the active device is minimised, and efficiency increased. Ideally,

the active element would pass only an instantaneous current pulse while the voltage across it is

zero: it then disspates no power and 100% efficiency is achieved. However practical devices

have a limit to the peak current they can pass, and the pulse must therefore be widened, to around

120 degrees, to obtain a reasonable amount of power, and the efficiency is then 60-70%.

3.5.3.1.5 Class D

In the class-D amplifier the input signal is converted to a sequence of higher voltage output

pulses. The averaged-over-time power values of these pulses are directly proportional to the

instantaneous amplitude of the input signal. The frequency of the output pulses is typically ten or

more times the highest frequency in the input signal to be amplified. The output pulses contain

inaccurate spectral components (that is, the pulse frequency and its harmonics), which must be

removed by a low-pass passive filter. The resulting filtered signal is then an amplified replica of

the input.

These amplifiers use pulse width modulation, pulse density modulation (sometimes referred to as

pulse frequency modulation) or a more advanced form of modulation such as Delta-sigma

modulation (for example, in the Analog Devices AD1990 class-D audio power amplifier).

Output stages such as those used in pulse generators are examples of class-D amplifiers. The

term class D is usually applied to devices intended to reproduce signals with a bandwidth well

below the switching frequency.

Class-D amplifiers can be controlled by either analog or digital circuits. The digital control

introduces additional distortion called quantization errorcaused by its conversion of the input

signal to a digital value.

https://en.wikipedia.org/wiki/Class-D_amplifier

https://en.wikipedia.org/wiki/Harmonics

https://en.wikipedia.org/wiki/Electronic_filter

https://en.wikipedia.org/wiki/Pulse_width_modulation

https://en.wikipedia.org/wiki/Pulse_density_modulation

https://en.wikipedia.org/wiki/Delta-sigma_modulation

https://en.wikipedia.org/wiki/Delta-sigma_modulation

https://en.wikipedia.org/wiki/Pulse_generator

https://en.wikipedia.org/wiki/Analog_circuit

https://en.wikipedia.org/wiki/Digital_circuit

The main advantage of a class-D amplifier is power efficiency. Because the output pulses have a

fixed amplitude, the switching elements (usually MOSFETs, but valves (vacuum tubes)

and bipolar transistors were once used) are switched either completely on or completely off,

rather than operated in linear mode. A MOSFET operates with the lowest resistance when fully

on and thus (excluding when fully off) has the lowest power dissipation when in that condition.

Compared to an equivalent class-AB device, a class-D amplifier's lower losses permit the use of

a smaller heat sink for the MOSFETs while also reducing the amount of input power required,

allowing for a lower-capacity power supply design. Therefore, class-D amplifiers are typically

smaller than an equivalent class-AB amplifier.

Class-D amplifiers have been widely used to control motors, but they are now also used

as audio power amplifiers, with some extra circuitry to allow analogue to be converted to a much

higher frequency pulse width modulated signal.

3.5.3.1.6 Additional classes

Class E

The class-E/F amplifier is a highly efficient switching power amplifier, typically used at such

high frequencies that the switching time becomes comparable to the duty time. As said in the

class-D amplifier, the transistor is connected via a serial LC circuit to the load, and connected via

a large L (inductor) to the supply voltage. The supply voltage is connected to ground via a large

capacitor to prevent any RF signals leaking into the supply. The class-E amplifier adds a C

(capacitor) between the transistor and ground and uses a defined L1 to connect to the supply

voltage.

Class E uses a significant amount of second-harmonic voltage. The second harmonic can be used

to reduce the overlap with edges with finite sharpness. For this to work, energy on the second

harmonic has to flow from the load into the transistor, and no source for this is visible in the

circuit diagram. In reality, the impedance is mostly reactive and the only reason for it is that class

E is a class F (see below) amplifier with a much simplified load network and thus has to deal

with imperfections.


https://en.wikipedia.org/wiki/Bipolar_transistor

https://en.wikipedia.org/wiki/Heat_sink

https://en.wikipedia.org/wiki/Electric_motor

The class-E amplifier was invented in 1972 by Nathan O. Sokal and Alan D. Sokal, and details

were first published in 1975.[13]

Some earlier reports on this operating class have been published

in Russian.

Class F

In push–pull amplifiers and in CMOS, the even harmonics of both transistors just cancel.

Experiment shows that a square wave can be generated by those amplifiers. Theoretically square

waves consist of odd harmonics only. In a class-D amplifier, the output filter blocks all

harmonics; i.e., the harmonics see an open load. So even small currents in the harmonics suffice

to generate a voltage square wave. The current is in phase with the voltage applied to the filter,

but the voltage across the transistors is out of phase. Therefore, there is a minimal overlap

between current through the transistors and voltage across the transistors. The sharper the edges,

the lower the overlap.

Class F can be driven by sine or by a square wave, for a sine the input can be tuned by an

inductor to increase gain. If class F is implemented with a single transistor, the filter is

complicated to short the even harmonics. All previous designs use sharp edges to minimise the

overlap.

3.5.4 Implementation

Amplifiers are implemented using active elements of different kinds:

The first active elements were relays. They were for example used in transcontinental

telegraph lines: a weak current was used to switch the voltage of a battery to the outgoing

line.

For transmitting audio, carbon microphones were used as the active element. This was

used to modulate a radio-frequency source in one of the first AM audio transmissions,

by Reginald Fessenden on Dec. 24, 1906.[19]

In the 1960s, the transistor started to take over. These days, discrete transistors are still

used in high-power amplifiers and in specialist audio devices.

Up to the early 1970s, most amplifiers used vacuum tubes. Today, tubes are used for

specialist audio applications such as guitar amplifiers and audiophile amplifiers. Many

broadcast transmitters still use vacuum tubes.

Beginning in the 1970s, more and more transistors were connected on a single chip

therefore creating the integrated circuit. A large number of amplifiers commercially

available today are based on integrated circuits.

For special purposes, other active elements have been used. For example, in the early days of the

satellite communication, parametric amplifiers were used. The core circuit was a diode whose

https://en.wikipedia.org/wiki/Alan_Sokal


https://en.wikipedia.org/wiki/Carbon_microphone#Carbon_microphones_used_as_amplifiers

https://en.wikipedia.org/wiki/Reginald_Fessenden


https://en.wikipedia.org/wiki/Integrated_circuit

https://en.wikipedia.org/wiki/Parametric_amplifier

capacity was changed by an RF signal created locally. Under certain conditions, this RF signal

provided energy that was modulated by the extremely weak satellite signal received at the earth

station.

3.5.4.1 Amplifier circuit

The practical amplifier circuit to the right could be the basis for a moderate-power audio

amplifier. It features a typical (though substantially simplified) design as found in modern

amplifiers, with a class-AB push–pull output stage, and uses some overall negative feedback.

Bipolar transistors are shown, but this design would also be realizable with FETs or valves.

The input signal is coupled through capacitor C1 to the base of transistor Q1. The capacitor

allows the AC signal to pass, but blocks the DC bias voltage established by resistors R1 and R2

so that any preceding circuit is not affected by it. Q1 and Q2 form adifferential amplifier (an

amplifier that multiplies the difference between two inputs by some constant), in an arrangement

known as along-tailed pair. This arrangement is used to conveniently allow the use of negative

feedback, which is fed from the output to Q2 via R7 and R8.

The negative feedback into the difference amplifier allows the amplifier to compare the input to

the actual output. The amplified signal from Q1 is directly fed to the second stage, Q3, which is

a common emitter stage that provides further amplification of the signal and the DC bias for the

output stages, Q4 and Q5. R6 provides the load for Q3 (A better design would probably use

some form of active load here, such as a constant-current sink). So far, all of the amplifier is

operating in class A. The output pair are arranged in class-AB push–pull, also called a

complementary pair. They provide the majority of the current amplification (while consuming

low quiescent current) and directly drive the load, connected via DC-blocking capacitor C2.

The diodes D1 and D2 provide a small amount of constant voltage bias for the output pair, just

biasing them into the conducting state so that crossover distortion is minimized. That is, the

diodes push the output stage firmly into class-AB mode (assuming that the base-emitter drop of

the output transistors is reduced by heat dissipation).

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https://en.wikipedia.org/wiki/Differential_amplifier

https://en.wikipedia.org/wiki/Long-tailed_pair

https://en.wikipedia.org/wiki/Common_emitter


This design is simple, but a good basis for a practical design because it automatically stabilises

its operating point, since feedback internally operates from DC up through the audio range and

beyond. Further circuit elements would probably be found in a real design that would roll

off the frequency response above the needed range to prevent the possibility of

unwanted oscillation. Also, the use of fixed diode bias as shown here can cause problems if the

diodes are not both electrically and thermally matched to the output transistors – if the output

transistors turn on too much, they can easily overheat and destroy themselves, as the full current

from the power supply is not limited at this stage.

A common solution to help stabilise the output devices is to include some emitter

resistors, typically an ohm or so. Calculating the values of the circuit's resistors and capacitors is

done based on the components employed and the intended use of the amp. For the basics of radio

frequency amplifiers using valves, see Valved RF amplifiers.

3.6 Field Effect Transistor The field-effect transistor (FET) is a transistor that uses an electric field to control the shape and

hence the conductivity of a channel of one type ofcharge carrier in a semiconductor material.

FETs are unipolar transistors as they involve single-carrier-type operation. The concept of the

FET predates the bipolar junction transistor (BJT), though it was not physically implemented

until after BJTs due to the limitations of semiconductor materials and the relative ease of

manufacturing BJTs compared to FETs at the time.

3.6.1 Basic Operation

FETs can be majority-charge-carrier devices, in which the current is carried predominantly by

majority carriers, or minority-charge-carrier devices, in which the current is mainly due to a flow

of minority carriers.[2]

The device consists of an active channel through which charge carriers,

electrons or holes, flow from the source to the drain. Source and drain terminal conductors are

connected to the semiconductor through ohmic contacts. The conductivity of the channel is a

function of the potential applied across the gate and source terminals.

The FET's three terminals are:[3]

Source (S), through which the carriers enter the channel. Conventionally, current entering

the channel at S is designated by IS.

Drain (D), through which the carriers leave the channel. Conventionally, current entering

the channel at D is designated by ID. Drain-to-source voltage is VDS.

Gate (G), the terminal that modulates the channel conductivity. By applying voltage to G,

one can control ID.

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3.6.2 FET Operation

The FET controls the flow of electrons (or electron holes) from the source to drain by affecting

the size and shape of a "conductive channel" created and influenced by voltage (or lack of

voltage) applied across the gate and source terminals. (For simplicity, this discussion assumes

that the body and source are connected.) This conductive channel is the "stream" through which

electrons flow from source to drain.

In an n-channel depletion-mode device, a negative gate-to-source voltage causes a depletion

region to expand in width and encroach on the channel from the sides, narrowing the channel. If

the depletion region expands to completely close the channel, the resistance of the channel from

source to drain becomes large, and the FET is effectively turned off like a switch. This is

called pinch-off, and the voltage at which it occurs is called the pinch-off voltage. Conversely, a

positive gate-to-source voltage increases the channel size and allows electrons to flow easily.

In an n-channel enhancement-mode device, a conductive channel does not exist naturally within

the transistor, and a positive gate-to-source voltage is necessary to create one. The positive

voltage attracts free-floating electrons within the body towards the gate, forming a conductive

channel. But first, enough electrons must be attracted near the gate to counter the dopant ions

added to the body of the FET; this forms a region free of mobile carriers called a depletion

region, and the voltage at which this occurs is referred to as the threshold voltage of the FET.

Further gate-to-source voltage increase will attract even more electrons towards the gate which

are able to create a conductive channel from source to drain; this process is called inversion.

In a p-channel depletion-mode device, a positive voltage from gate to body creates a depletion

layer by forcing the positively charged holes away from the gate-insulator/semiconductor

interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions.

For either enhancement- or depletion-mode devices, at drain-to-source voltages much less than

gate-to-source voltages, changing the gate voltage will alter the channel resistance, and drain

current will be proportional to drain voltage (referenced to source voltage). In this mode the FET

operates like a variable resistor and the FET is said to be operating in a linear mode or ohmic

mode.

I–V characteristics and output plot of a JFET n-channel transistor

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https://en.wikipedia.org/wiki/Depletion_region



https://en.wikipedia.org/wiki/Threshold_voltage

If drain-to-source voltage is increased, this creates a significant asymmetrical change in the

shape of the channel due to a gradient of voltage potential from source to drain. The shape of the

inversion region becomes "pinched-off" near the drain end of the channel. If drain-to-source

voltage is increased further, the pinch-off point of the channel begins to move away from the

drain towards the source. The FET is said to be in saturation mode;[6]

although some authors

refer to it as active mode, for a better analogy with bipolar transistor operating regions.[7][8]

The

saturation mode, or the region between ohmic and saturation, is used when amplification is

needed. The in-between region is sometimes considered to be part of the ohmic or linear region,

even where drain current is not approximately linear with drain voltage.

Even though the conductive channel formed by gate-to-source voltage no longer connects source

to drain during saturation mode, carriers are not blocked from flowing. Considering again an n-

channel enhancement-mode device, a depletion region exists in the p-type body, surrounding the

conductive channel and drain and source regions. The electrons which comprise the channel are

free to move out of the channel through the depletion region if attracted to the drain by drain-to-

source voltage. The depletion region is free of carriers and has a resistance similar to silicon.

Any increase of the drain-to-source voltage will increase the distance from drain to the pinch-off

point, increasing the resistance of the depletion region in proportion to the drain-to-source

voltage applied. This proportional change causes the drain-to-source current to remain relatively

fixed, independent of changes to the drain-to-source voltage, quite unlike its ohmic behavior in

the linear mode of operation. Thus, in saturation mode, the FET behaves as a constant-current

source rather than as a resistor, and can effectively be used as a voltage amplifier. In this case,

the gate-to-source voltage determines the level of constant current through the channel.

3.6.3 Types of Field Effect Transistors

The channel of a FET is doped to produce either an n-type semiconductor or a p-type

semiconductor. The drain and source may be doped of opposite type to the channel, in the case

of depletion mode FETs, or doped of similar type to the channel as in enhancement mode FETs.

Field-effect transistors are also distinguished by the method of insulation between channel and

gate. Types of FETs include:

The CNTFET (carbon nanotube field-effect transistor).

The DEPFET is a FET formed in a fully depleted substrate and acts as a sensor, amplifier

and memory node at the same time. It can be used as an image (photon) sensor.

The DGMOSFET (dual-gate MOSFET) is a FET with two insulated gates.

The DNAFET (DNA field-effect transistor) is a specialized FET that acts as a biosensor,

by using a gate made of single-strand DNA molecules to detect matching DNA strands.

The FREDFET (fast-reverse or fast-recovery epitaxial diode FET) is a specialized FET

designed to provide a very fast recovery (turn-off) of the body diode.

https://en.wikipedia.org/wiki/Field_effect_transistor#cite_note-Spencer-6

https://en.wikipedia.org/wiki/Field_effect_transistor#cite_note-Sedra-7



https://en.wikipedia.org/wiki/Charge_carriers


https://en.wikipedia.org/wiki/Silicon

https://en.wikipedia.org/wiki/Current_source

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https://en.wikipedia.org/wiki/Carbon_nanotube_field-effect_transistor

https://en.wikipedia.org/w/index.php?title=DEPFET&action=edit&redlink=1

https://en.wikipedia.org/w/index.php?title=Dual-gate_MOSFET&action=edit&redlink=1

https://en.wikipedia.org/wiki/DNA_field-effect_transistor

https://en.wikipedia.org/wiki/Biosensor

https://en.wikipedia.org/wiki/FREDFET

The HEMT (high-electron-mobility transistor), also called a HFET (heterostructure FET),

can be made using bandgap engineering in a ternary semiconductor such as AlGaAs. The

fully depleted wide-band-gap material forms the isolation between gate and body.

The HIGFET (heterostructure insulated gate field-effect transisitor) is now used mainly

in research.

The IGBT (insulated-gate bipolar transistor) is a device for power control. It has a

structure akin to a MOSFET coupled with a bipolar-like main conduction channel. These

are commonly used for the 200–3000 V drain-to-source voltage range of

operation. Power MOSFETs are still the device of choice for drain-to-source voltages of

1 to 200 V.

The ISFET (ion-sensitive field-effect transistor) can be used to measure ion

concentrations in a solution; when the ion concentration (such as H+) changes, the current

through the transistor will change accordingly.

The JFET (junction field-effect transistor) uses a reverse biased p–n junction to separate

the gate from the body.

The MESFET (metal–semiconductor field-effect transistor) substitutes the p–n

junction of the JFET with a Schottky barrier; and is used in GaAs and other III-V

semiconductor materials.

The MODFET (modulation-doped field-effect transistor) uses a quantum well structure

formed by graded doping of the active region.

The MOSFET (metal–oxide–semiconductor field-effect transistor) utilizes

an insulator (typically SiO2) between the gate and the body.

The NOMFET is a nanoparticle organic memory field-effect transistor.

The OFET (organic field-effect transistor) uses an organic semiconductor in its channel.

The GNRFET (graphene nanoribbon field-effect transistor) uses a graphene

nanoribbon for its channel.

The VeSFET (vertical-slit field-effect transistor) is a square-shaped junctionless FET

with a narrow slit connecting the source and drain at opposite corners. Two gates occupy

the other corners, and control the current through the slit.

The TFET (tunnel field-effect transistor) is based on band-to-band tunneling.

3.6.4 Advantages of FET

The main advantage of the FET is its high input resistance, on the order of 100 MΩ or more.

Thus, it is a voltage-controlled device, and shows a high degree of isolation between input and

output. It is a unipolar device, depending only upon majority current flow. It is less noisy and is

thus found in FM tuners and in low-noise amplifiers for VHF and satellite receivers. It is

https://en.wikipedia.org/wiki/High-electron-mobility_transistor

https://en.wikipedia.org/wiki/Bandgap

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https://en.wikipedia.org/wiki/Power_MOSFET

https://en.wikipedia.org/wiki/ISFET

https://en.wikipedia.org/wiki/JFET

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https://en.wikipedia.org/wiki/Schottky_barrier

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https://en.wikipedia.org/wiki/Quantum_well


https://en.wikipedia.org/wiki/Electrical_insulation

https://en.wikipedia.org/wiki/Silicon_dioxide

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https://en.wikipedia.org/wiki/OFET

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https://en.wikipedia.org/wiki/Low-noise_amplifier

https://en.wikipedia.org/wiki/VHF

relatively immune to radiation. It exhibits no offset voltage at zero drain current and hence

makes an excellent signal chopper. It typically has better thermal stability than a bipolar junction

transistor (BJT).

3.6.5 Disadvantages of FET

It has a relatively low gain-bandwidth product compared to a BJT. The MOSFET has a drawback

of being very susceptible to overload voltages, thus requiring special handling during

installation. The fragile insulating layer of the MOSFET between the gate and channel makes it

vulnerable to electrostatic damage during handling. This is not usually a problem after the device

has been installed in a properly designed circuit.

3.6.6 Uses

The most commonly used FET is the MOSFET. The CMOS (complementary metal oxide

semiconductor) process technology is the basis for modern digital integrated circuits.

This process technology uses an arrangement where the (usually "enhancement-mode") p-

channel MOSFET and n-channel MOSFET are connected in series such that when one is on, the

other is off.

In FETs, electrons can flow in either direction through the channel when operated in the

linear mode. The naming convention of drain terminal and source terminal is somewhat

arbitrary, as the devices are typically (but not always) built symmetrically from source to drain.

This makes FETs suitable for switching analog signals between paths (multiplexing). With this

concept, one can construct a solid-state mixing board, for example.

A common use of the FET is as an amplifier. For example, due to its large input

resistance and low output resistance, it is effective as a buffer in common-drain (source follower)

configuration.

IGBTs see application in switching internal combustion engine ignition coils, where fast

switching and voltage blocking capabilities are important.

3.7 Silicon Controlled Rectifiers

A silicon-controlled rectifier (or semiconductor-controlled rectifier) is a four-layer solid

state current controlling device. The name "silicon controlled rectifier" or SCR is General

Electric's trade name for a type of thyristor. The SCR was developed by a team of power

engineers led by Robert N. Hall and commercialized by Frank W. "Bill" Gutzwiller in 1957.

Some sources define silicon controlled rectifiers and thyristors as synonymous, other

sources define silicon controlled rectifiers as a subset of a larger family of devices with at least

four layers of alternating N and P-type material, this entire family being referred to as thyristors.




https://en.wikipedia.org/wiki/Electrostatic_discharge


https://en.wikipedia.org/wiki/CMOS

https://en.wikipedia.org/wiki/Digital

https://en.wikipedia.org/wiki/Integrated_circuit

https://en.wikipedia.org/wiki/Semiconductor_device_fabrication

https://en.wikipedia.org/wiki/Multiplexing

https://en.wikipedia.org/wiki/Mixing_board

https://en.wikipedia.org/wiki/Common-drain




https://en.wikipedia.org/wiki/Electric_current





https://en.wikipedia.org/wiki/Power_engineering



https://en.wikipedia.org/wiki/Robert_N._Hall

SCRs are unidirectional devices (i.e. can conduct current only in one direction) as

opposed to TRIACs which are bidirectional (i.e. current can flow through them in either

direction). SCRs can be triggered normally only by currents going into the gate as opposed to

TRIACs which can be triggered normally by either a positive or a negative current applied to its

gate electrode.

SCR schematic symbol

3.7.1 Application of SCR

SCRs are mainly used in devices where the control of high power, possibly coupled with high

voltage, is demanded. Their operation makes them suitable for use in medium to high-voltage

AC power control applications, such as lamp dimming, regulators and motor control.

SCRs and similar devices are used for rectification of high power AC in high-voltage

direct current power transmission. They are also used in the control of welding machines, mainly

MTAW and GTAW processes.

3.8 DIAC

The DIAC, or "diode for alternating current", is a diode that conducts current only after its

breakover voltage, VBO, has been reached momentarily.

DIAC

When this occurs, the diode enters the region of negative dynamic resistance, leading to a

decrease in the voltage drop across the diode and, usually, a sharp increase in current through the



http://en.wikipedia.org/wiki/Diode

http://en.wikipedia.org/wiki/Alternating_current

http://en.wikipedia.org/wiki/Electrical_current


http://en.wikipedia.org/wiki/Negative_dynamic_resistance

diode. The diode remains "in conduction" until the current through it drops below a value

characteristic for the device, called the holding current, IH. Below this value, the diode switches

back to its high-resistance (non-conducting) state. This behavior is bidirectional, meaning

typically the same for both directions of current.

Most DIACs have a three-layer structure with breakover voltage around 30 V. In this way, their

behavior is somewhat similar to (but much more precisely controlled and taking place at lower

voltages than) a neon lamp.

DIACs have no gate electrode, unlike some other thyristors that they are commonly used to

trigger, such as TRIACs. Some TRIACs, like Quadrac, contain a built-in DIAC in series with the

TRIAC's "gate" terminal for this purpose.

DIACs are also called symmetrical trigger diodes due to the symmetry of their characteristic

curve. Because DIACs are bidirectional devices, their terminals are not labeled

as anode and cathode but as A1 and A2 or MT1 ("Main Terminal") and MT2.

3.9 TRIAC

TRIAC, from Triode for Alternating Current, is a genericized tradename for an electronic

component that can conduct current in either direction when it is triggered (turned on), and is

formally called a bidirectional triode thyristor or bilateral triode thyristor.

TRIACs belong to the thyristor family and are closely related to Silicon-controlled

rectifiers (SCR). However, unlike SCRs, which are unidirectional devices (i.e. can conduct

current only in one direction), TRIACs are bidirectional and so current can flow through them in

either direction. Another difference from SCRs is that TRIACs can be triggered by either a

positive or a negative current applied to its gate electrode, whereas SCRs can be triggered only

by currents going into the gate. In order to create a triggering current, a positive or negative

voltage has to be applied to the gate with respect to the MT1 terminal (otherwise known as A1).

Once triggered, the device continues to conduct until the current drops below a certain threshold,

called the holding current.

The bidirectionality makes TRIACs very convenient switches for AC circuits, also allowing

them to control very large power flows with milliampere-scale gate currents. In addition,

applying a trigger pulse at a controlled phase angle in an AC cycle allows one to control the

percentage of current that flows through the TRIAC to the load (phase control), which is

commonly used, for example, in controlling the speed of low-power induction motors, in

dimming lamps and in controlling AC heating resistors.

http://en.wikipedia.org/wiki/Neon_lamp

http://en.wikipedia.org/wiki/Electrode

http://en.wikipedia.org/wiki/Thyristor

http://en.wikipedia.org/wiki/TRIAC

http://en.wikipedia.org/wiki/Quadrac

http://en.wikipedia.org/wiki/Genericized_tradename





http://en.wikipedia.org/wiki/Thyristor

http://en.wikipedia.org/wiki/Silicon-controlled_rectifier

http://en.wikipedia.org/wiki/Silicon-controlled_rectifier

http://en.wikipedia.org/wiki/Silicon_controlled_rectifier#Modes_of_operation

http://en.wikipedia.org/wiki/Ampere

http://en.wikipedia.org/wiki/Phase_control

http://en.wikipedia.org/wiki/Induction_motors

TRIAC systematic symbol

3.9 Applications

Low power TRIACs are used in many applications such as light dimmers, speed controls

for electric fans and other electric motors, and in the modern computerized control circuits of

many household small and major appliances.

http://en.wikipedia.org/wiki/Electric_light

http://en.wikipedia.org/wiki/Dimmer

http://en.wikipedia.org/wiki/Electric_fan

http://en.wikipedia.org/wiki/Electric_motor

http://en.wikipedia.org/wiki/Small_appliance

http://en.wikipedia.org/wiki/Major_appliance

REVIEW QUESTIONS

1. Define Transistors.

2. What do you mean by Bipolar Junction Transistor?

3. What is the difference between common base, common emitter and common control

configuration?

4. What do you mean by amplifiers?

5. What are the various types of amplifiers?

6. Discuss the various classes of Amplifiers.

7. What do you mean by Field Effect Transistor?

8. Explain DIAC.

9. Explain TRIAC.

10. Explain SCR.

CHAPTER 4

8085 MICROPROCESSOR

The microprocessor, also known as the Central Processing Unit (CPU), is the brain of all

computers and many household and electronic devices. Multiple microprocessors, working

together, are the "hearts" of datacenters, super-computers, communications products, and other

digital devices.

The first microprocessor was the Intel 4004, introduced in 1971. The 4004 was not very

powerful; it was primarily used to perform simple mathematical operations in a calculator called

―Busicom.‖ Just like microwaves or telephones, devices with microprocessors have become so

integrated into our daily lives, that we cannot imagine a life without them.

It‘s sometimes hard to believe that only 60 years ago, computers were rare and were not

available for the wider public. It wasn't until the '80s that computers entered our homes and -

thanks to the microprocessor - really made an impact on the average person's life.

Nowadays, modern microprocessors can perform extremely sophisticated operations in

areas such as meteorology, aviation, nuclear physics and engineering, and take up much less

space as well as delivering superior performance.

Over the past 40 years, microprocessors have become faster and more powerful, yet

increasingly smaller and more affordable

4.1 Introduction to Microprocessor & Microcontroller

4.1.1 Microprocessor

A microprocessor (sometimes abbreviated µP) is a digital electronic component with

miniaturized transistors on a single semiconductor integrated circuit (IC). • One or more

microprocessors typically serve as a central processing unit (CPU) in a computer system or

handheld device. Microprocessors made possible the advent of the microcomputer. At the heart

of all personal computers and most working stations sits a microprocessor.

Microprocessors also control the logic of almost all digital devices, from clock radios to

fuel-injection systems for automobiles. Three basic characteristics differentiate microprocessors:

• Instruction set: The set of instructions that the microprocessor can execute.

• Bandwidth: The number of bits processed in a single instruction.

• Clock speed: Given in megahertz (MHz), the clock speed determines how many

instructions per second the processor can execute.

In both cases, the higher the value, the more powerful the CPU. For example, a 32 bit

microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at

25MHz. In addition to bandwidth and clock speed, microprocessors are classified as being either

RISC (reduced instruction set computer) or CISC (complex instruction set computer).

4.1.2 Microcontroller

A highly integrated chip that contains all the components comprising a controller. Typically this

includes a CPU, RAM, some form of ROM, I/O ports, and timers. Unlike a general-purpose

computer, which also includes all of these components, a microcontroller is designed for a very

specific task - to control a particular system. A microcontroller differs from a microprocessor,

which is a general-purpose chip that is used to create a multi-function computer or device and

requires multiple chips to handle various tasks.

A microcontroller is meant to be more self-contained and independent, and functions as a

tiny, dedicated computer. The great advantage of microcontrollers, as opposed to using larger

microprocessors, is that the parts-count and design costs of the item being controlled can be kept

to a minimum. They are typically designed using CMOS (complementary metal oxide

semiconductor) technology, an efficient fabrication technique that uses less power and is more

immune to power spikes than other techniques.

Microcontrollers are sometimes called an embedded microcontroller, which just means

that they are part of an embedded system that is, one part of a larger device or system.

Controller: A device that controls the transfer of data from a computer to a peripheral device

and vice versa. For example, disk drives, display screens, keyboards and printers all require

controllers. In personal computers, the controllers are often single chips. When you purchase a

computer, it comes with all the necessary controllers for standard components, such as the

display screen, keyboard, and disk drives. If you attach additional devices, however, you may

need to insert new controllers that come on expansion boards.

Controllers must be designed to communicate with the computer's expansion bus. There

are three standard bus architectures for PCs - the AT bus, PCI (Peripheral Component

Interconnect) and SCSI. When you purchase a controller, therefore, you must ensure that it

conforms to the bus architecture that your computer uses.

Short for Peripheral Component Interconnect, a local bus standard developed by Intel

Corporation. Most modern PCs include a PCI bus in addition to a more general IAS expansion

bus. PCI is also used on newer versions of the Macintosh computer. PCI is a 64-bit bus, though it

is usually implemented as a 32 bit bus. It can run at clock speeds of 33 or 66 MHz. At 32 bits and

33 MHz, it yields a throughput rate of 133 MBps.

Short for small computer system interface, a parallel interface standard used by Apple

Macintosh computers, PCs, and many UNIX systems for attaching peripheral devices to

computers. Nearly all Apple Macintosh computers, excluding only the earliest Macs and the

recent iMac, come with a SCSI port for attaching devices such as disk drives and printers.

SCSI interfaces provide for faster data transmission rates (up to 80 megabytes per

second) than standard serial and parallel ports. In addition, you can attach many devices to a

single SCSI port, so that SCSI is really an I/O bus rather than simply an interface. Although

SCSI is an ANSI standard, there are many variations of it, so two SCSI interfaces may be

incompatible. For example, SCSI supports several types of connectors. While SCSI has been the

standard interface for Macintoshes, the iMac comes with IDE, a less expensive interface, in

which the controller is integrated into the disk or CD-ROM drive.

The following varieties of SCSI are currently implemented:

• SCSI-1: Uses an 8-bit bus, and supports data rates of 4 MBps.

• SCSI-2: Same as SCSI-1, but uses a 50-pin connector instead of a 25-pin connector, and

supports multiple devices. This is what most people mean when they refer to plain SCSI.

• Wide SCSI: Uses a wider cable (168 cable lines to 68 pins) to support 16-bit transfers.

• Fast SCSI: Uses an 8-bit bus, but doubles the clock rate to support data rates of 10

MBps.

• Fast Wide SCSI: Uses a 16-bit bus and supports data rates of 20 MBps.

• Ultra SCSI: Uses an 8-bit bus, and supports data rates of 20 MBps.

• Wide Ultra2 SCSI: Uses a 16-bit bus and supports data rates of 80 MBps.

• SCSI-3: Uses a 16-bit bus and supports data rates of 40 MBps. Also called Ultra Wide

SCSI.

• Ultra2 SCSI: Uses an 8-bit bus and supports data rates of 40 MBps

4.2 Microcomputer System

4.2.1 General Architecture of a Microcomputer System

The hardware of a microcomputer system can be divided into four functional sections: the Input

unit, Microprocessing Unit, Memory Unit, and Output Unit as shown in fig. below:

Micro Processor Unit (MPU) is the heart of a microcomputer. A microprocessor is a

general purpose processing unit built into a single integrated circuit (IC). The

Microprocessor is the part of the microcomputer that executes instructions of the program

and processes data. It is responsible for performing all arithmetic operations and making

the logical decisions initiated by the computer‘s program. In addition to arithmetic and

logic functions, the MPU controls overall system operation.

Input and Output units are the means by which the MPU communicates with the

outside world.

Input unit: keyboard, mouse, scanner, etc.

Output unit: Monitor, printer, etc.

Memory unit:

Primary: is normally smaller in size and is used for temporary storage of

active information. Typically ROM, RAM.

Secondary: is normally larger in size and used for long-term storage of

information. Like Hard disk, Floppy, CD, etc.

Memory Unit

Primary Storage Unit

Secondary

Storage

Unit

Program

Storage

Memory

Data

Storage

Memory

Input Unit

MPU

Output Unit

4.2.2 Block diagram of Microcomputer System

If we think of the computer as an information manipulation device the basic components of a

microcomputer are:

Four Ports

1. Input Port :

Converts human code into computer code,

Provides a interface between the input device and the CPU

2. CPU (Central Processing Unit/Microprocessor):

Contains the control unit and the Arithmetic Logic Unit

Organizes the correct sequence of the processes

Performs all the mathematical and logical operations of the system

3. Memory:

Stores the instructions and data needed during processing and

execution of programs or commands

4. Output Port:

Converts computer code into human code

Provides interface between the CPU and the output devices

Three Buses

1. Address Bus:

Used by the CPU to select memory locations

Used by the input and output ports to be active at a given time

2. Data Bus:

Where all the data and instructions travel from the CPU to the

memory or any input/output port or vice versa

3. Control Bus:

Used by the CPU to inform the memory or the input/output port

that it is ready to perform data transfer may it be a read or a write

operation

4.3 Architecture of 8085 Microprocessor

4.3.1 Internal Architecture of 8085 Microprocessor

The basic architecture of 8085 Microprocessor is shown below.

Microprocessor consists of mainly following parts:

Control Unit

Arithmetic Logic Unit

Registers

Accumulator

Flags

Program Counter

Stack Pointer

Instruction Register/Decoder

Memory Address Register

Control Generator

Register Selector

General Purpose Registers

Microprogramming

1. Control Unit: Generates signals within microprocessor to carry out the instruction,

which has been decoded. In reality causes certain connections between blocks of the uP

to be opened or closed, so that data goes where it is required, and so that ALU operations

occur.

2. Arithmetic Logic Unit: The ALU performs the actual numerical and logic operation

such as ‗add‘, ‗subtract‘, ‗AND‘, ‗OR‘, etc. Uses data from memory and from

Accumulator to perform arithmetic. Always stores result of operation in Accumulator.

3. Registers: The 8085/8080A-programming model includes six registers, one accumulator,

and one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack

pointer and the program counter. They are described briefly as follows. The 8085/8080A

has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H,

and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL -

to perform some 16-bit operations. The programmer can use these registers to store or

copy data into the registers by using data copy instructions.

4. Accumulator: The accumulator is an 8-bit register that is a part of arithmetic/logic unit

(ALU). This register is used to store 8-bit data and to perform arithmetic and logical

operations. The result of an operation is stored in the accumulator. The accumulator is

also identified as register A.

5. Flags: The ALU includes five flip-flops, which are set or reset after an operation

according to data conditions of the result in the accumulator and other registers. They are

called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are

listed in the Table and their bit positions in the flag register are shown in the Figure

below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor

uses these flags to test data conditions.

For example, after an addition of two numbers, if the sum in the accumulator id larger

than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) -- is set

to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag

is set to one. The Figure shows an 8-bit register, called the flag register, adjacent to the

accumulator. However, it is not used as a register; five bit positions out of eight are used

to store the outputs of the five flip-flops. The flags are stored in the 8-bit register so that

the programmer can examine these flags (data conditions) by accessing the register

through an instruction.

These flags have critical importance in the decision-making process of the micro-

processor. The conditions (set or reset) of the flags are tested through the software

instructions. For example, the instruction JC (Jump on Carry) is implemented to change

the sequence of a program when CY flag is set. The thorough understanding of flag is

essential in writing assembly language programs.

6. Program Counter (PC): This 16-bit register deals with sequencing the execution of

instructions. This register is a memory pointer. Memory locations have 16-bit addresses,

and that is why this is a 16-bit register. The microprocessor uses this register to sequence

the execution of the instructions. The function of the program counter is to point to the

memory address from which the next byte is to be fetched. When a byte (machine code)

is being fetched, the program counter is incremented by one to point to the next memory

location

7. Stack Pointer (SP): The stack pointer is also a 16-bit register used as a memory pointer.

It points to a memory location in R/W memory, called the stack. The beginning of the

stack is defined by loading 16-bit address in the stack pointer.

8. Instruction Register/Decoder: Temporary store for the current instruction of a program.

Latest instruction sent here from memory prior to execution. Decoder then takes

instruction and ‗decodes‘ or interprets the instruction. Decoded instruction then passed to

next stage.

9. Memory Address Register: Holds address, received from PC, of next program

instruction. Feeds the address bus with addresses of location of the program under

execution.

10. Control Generator: Generates signals within uP to carry out the instruction which has

been decoded. In reality causes certain connections between blocks of the uP to be

opened or closed, so that data goes where it is required, and so that ALU operations

occur.

11. Register Selector: This block controls the use of the register stack in the example. Just a

logic circuit which switches between different registers in the set will receive instructions

from Control Unit.

12. General Purpose Registers: P requires extra registers for versatility. Can be used to

store additional data during a program. More complex processors may have a variety of

differently named registers.

13. Microprogramming: How does the µP knows what an instruction means, especially

when it is only a binary number? The micro program in a P/ C is written by the chip

designer and tells the P/ C the meaning of each instruction P/ C can then carry out

operation.

4.3.2 8085 System Bus

Typical system uses a number of busses, collection of wires, which transmit binary numbers, one

bit per wire. A typical microprocessor communicates with memory and other devices (input and

output) using three busses: Address Bus, Data Bus and Control Bus is shown below:

1. Address Bus: One wire for each bit, therefore 16 bits = 16 wires. Binary number carried

alerts memory to ‗open‘ the designated box. Data (binary) can then be put in or taken out.

The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A 16 bit

binary number allows 216

different numbers, or 32000 different numbers, i.e.

0000000000000000 up to 1111111111111111. Because memory consists of boxes, each

with a unique address, the size of the address bus determines the size of memory, which

can be used. To communicate with memory the microprocessor sends an address on the

address bus, e.g. 0000000000000011 (3 in decimal), to the memory. The memory the

selects box number 3 for reading or writing data. Address bus is unidirectional, i.e.

numbers only sent from microprocessor to memory, not other way.

Question 1: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits), how

many wires does the address bus need, in order to be able to specify an address in this

memory? Note: the memory is organized in groups of 8 bits per location, therefore, how

many locations must you be able to specify?

Question 2: If a processor has 4 GB memory then how many address lines are required

to access this memory?

Solution: 4GB= 4 * 1GB

4 = 2^2

1GB = 2^30

4GB = 2^2 * 2^30 = 2^32

So 32 address lines are required to access the 4 GB memory.

2. Data Bus: Data Bus: carries ‗data‘, in binary form, between µP and other external units,

such as memory. Typical size is 8 or 16 bits. Size determined by size of boxes in memory

and µP size helps determine performance of µP. The Data Bus typically consists of 8

wires. Therefore, 28 combinations of binary digits. Data bus used to transmit "data", i.e.

information, results of arithmetic, etc, between memory and the microprocessor. Bus is

bi-directional. Size of the data bus determines what arithmetic can be done. If only 8 bits

wide then largest number is 11111111 (255 in decimal). Therefore, larger number have to

be broken down into chunks of 255. This slows microprocessor. Data Bus also carries

instructions from memory to the microprocessor. Size of the bus therefore limits the

number of possible instructions to 256, each specified by a separate number.

3. Control Bus: Control Bus are various lines which have specific functions for

coordinating and controlling P operations. E.g.: Read/Not Write line, single binary digit.

Control whether memory is being ‗written to‘ (data stored in mem) or ‗read from‘ (data

taken out of mem) 1 = Read, 0 = Write. May also include clock line(s) for

timing/synchronizing, ‗interrupts‘, ‗reset‘ etc. Typically µP has 10 control lines. Cannot

function correctly without these vital control signals.

The Control Bus carries control signals partly unidirectional, partly bi-directional.

Controls signals are things like "read or write". This tells memory that we are reading

from a location, specified on the address bus, or writing to a location specified. Various

other signals to control and coordinate the operation of the system. Modern day

microprocessors, like 80386, 80486 have much larger busses. Typically 16 or 32 bit

busses, which allow larger number of instructions, more memory location, and faster

arithmetic. Microcontrollers organized along same lines, except: because

microcontrollers have memory etc inside the chip, the busses may all be internal. In the

microprocessor the three busses are external to the chip (except for the internal data bus).

In case of external busses, the chip connects to the busses via buffers, which are simply

an electronic connection between external bus and the internal data bus.

4.4 8085 Pin Configuration

4.4.1 Pin Properties

The main features of 8085 μp are:

It is a 8 bit microprocessor.

It is manufactured with N-MOS technology.

It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory

locations through A0 - A15

The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7

Data bus is a group of 8 lines D0 – D7

It supports external interrupt request.

A 16 bit program counter (PC)

A 16 bit stack pointer (SP)

Six 8-bit general purpose register arranged in pairs: BC, DE, HL.

It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.

It is enclosed with 40 pins DIP (Dual in line package).

4.4.2 Pin Description

The following describes the function of each pin:

A6 - A1s (Output 3 State)

Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/0

address,3 stated during Hold and Halt modes.

AD0 - 7 (Input/Output 3state)

Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/0 address)

appear on the bus during the first clock cycle of a machine state. It then becomes the data

bus during the second and third clock cycles. 3 stated during Hold and Halt modes.

ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and

enables the address to get latched into the on chip latch of peripherals. The falling edge of

ALE is set to guarantee setup and hold times for the address information. ALE can also

be used to strobe the status information. ALE is never 3stated.

SO, S1 (Output)

Data Bus Status: Encoded status of the bus cycle:

S1 S0

O O HALT

0 1 WRITE

1 0 READ

1 1 FETCH

S1 can be used as an advanced R/W status.

RD (Output 3state)

READ: indicates the selected memory or 1/0 device is to be read and that the Data Bus is

available for the data transfer.

WR (Output 3state)

WRITE: indicates the data on the Data Bus is to be written into the selected memory or

1/0 location. Data is set up at the trailing edge of WR. 3 stated during Hold and Halt

modes.

READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is

ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high

before completing the read or write cycle.

HOLD (Input)

HOLD: indicates that another Master is requesting the use of the Address and Data

Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as

soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed. When the Hold is

acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output)

HOLD ACKNOWLEDGE: indicates that the CPU has received the Hold request and

that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold

request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.

INTR (Input)

INTERRUPT REQUEST: is used as a general purpose interrupt. It is sampled only

during the next to the last clock cycle of the instruction. If it is active, the Program

Counter (PC) will be inhibited from incrementing and an INTA will be issued. During

this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt

service routine. The INTR is enabled and disabled by software. It is disabled by Reset

and immediately after an interrupt is accepted.

INTA (Output)

INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD

during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259

Interrupt chip or some other interrupt port.

RST 5.5

RST 6.5 - (Inputs)

RST 7.5

RESTART INTERRUPTS

These three inputs have the same timing as I NTR except they cause an internal

RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher

priority than the INTR.

TRAP (Input)

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as

INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any

interrupt.

RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-

flops. None of the other flags or registers (except the instruction register) are affected The

CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPU is being reset. Can be used as a system RESET. The signal is

synchronized to the processor clock.

X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be an

external clock input instead of a crystal. The input frequency is divided by 2 to give the

internal operating frequency.

CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used as an input

to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and

Halt modes.

SID (Input)

Serial input data line The data on this line is loaded into accumulator bit 7 whenever a

RIM instruction is executed.

SOD (output)

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Vcc

+5 volt supply.

Vss

Ground Reference.

4.4.3 8085 Functional Description

The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt supply. Its

basic clock speed is 3 MHz thus improving on the present 8080's performance with higher

system speed. Also it is designed to fit into a minimum system of three IC's: The CPU, a RAM/

IO, and a ROM or PROM/IO chip.

The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit

Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address is sent out.

The lower 8bits are latched into the peripherals by the Address Latch Enable (ALE). During the

rest of the machine cycle the Data Bus is used for memory or l/O data.

The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt

Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are synchronized.

The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple

serial interface.

In addition to these features, the 8085A has three maskable, restart interrupts and one

non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus control.

Status Information

Status information is directly available from the 8085A. ALE serves as a status strobe.

The status is partially encoded, and provides the user with advanced timing of the type of

bus transfer being done. IO/M cycle status signal is provided directly also. Decoded So,

S1 Carries the following status information:

HALT, WRITE, READ, FETCH

S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address are

multiplexed with the data instead of status. The ALE line is used as a strobe to enter the

lower half of the address into the memory or peripheral address latch. This also frees

extra pins for expanded interrupt capability.

Interrupt and Serial l/O

The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR is

identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5. 7.5,

has a programmable mask. TRAP is also a RESTART interrupt except it is nonmaskable.

The three RESTART interrupts cause the internal execution of RST (saving the program

counter in the stack and branching to the RESTART address) if the interrupts are enabled

and if the interrupt mask is not set. The non-maskable TRAP causes the internal

execution of a RST independent of the state of the interrupt enable or masks.

The interrupts are arranged in a fixed priority that determines which interrupt is to be

recognized if more than one is pending as follows: TRAP highest priority, RST 7.5, RST

6.5, RST 5.5, INTR lowest priority This priority scheme does not take into account the

priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt a

RST 7.5 routine if the interrupts were re-enabled before the end of the RST 7.5 routine.

The TRAP interrupt is useful for catastrophic errors such as power failure or bus error.

The TRAP input is recognized just as any other interrupt but has the highest priority. It is

not affected by any flag or mask. The TRAP input is both edge and level sensitive.

Basic System Timing

The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8bits

of address on the Data Bus. Figure 2 shows an instruction fetch, memory read and l/ O

write cycle (OUT). Note that during the l/O write and read cycle that the l/O port address

is copied on both the upper and lower half of the address. As in the 8080, the READY

line is used to extend the read and write pulse lengths so that the 8085A can be used with

slow memory. Hold causes the CPU to relingkuish the bus when it is through with it by

floating the Address and Data Buses.

System Interface

8085A family includes memory components, which are directly compatible to the 8085A

CPU. For example, a system consisting of the three chips, 8085A, 8156, and 8355 will

have the following features:

· 2K Bytes ROM

· 256 Bytes RAM

· 1 Timer/Counter

· 4 8bit l/O Ports

· 1 6bit l/O Port

· 4 Interrupt Levels

· Serial In/Serial Out Ports

In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing

technique. With this technique, an area of memory address space is assigned for l/O

address, thereby, using the memory address for I/O manipulation. The 8085A CPU can

also interface with the standard memory that does not have the multiplexed address/data

bus.

4.5 8085 Instruction Sets

An instruction is a binary pattern designed inside a microprocessor to perform a specific

function. The entire group of instructions, called the instruction set, determines what functions

the microprocessor can perform. 8085 has 246 instructions. Each instruction is represented by an

8-bit binary value. These 8-bits of binary value is called Op-Code or Instruction Byte. These

instructions can be classified into the following five functional categories:

data transfer (copy) instructions,

arithmetic instructions,

logical instructions,

branching instructions, and

machine-control instructions.

4.5.1 Classification of 8085 Instruction Set

4.5.1.1 Data Transfer Instructions

This group of instructions copy data from a location called a source to another location called a

destination, without modifying the contents of the source. In technical manuals, the term data

transfer is used for this copying function. However, the term transfer is misleading; it creates the

impression that the contents of the source are destroyed when, in fact, the contents are retained

without any modification. The various types of data transfer (copy) are listed below together

with examples of each type:

Opcode Operand Description

Copy from source to destination

MOV Rd, Rs This instruction copies the contents of the source

M, Rs register into the destination register; the contents of

Rd, M the source register are not altered. If one of the

operands is a memory location, its location is

specified by the contents of the HL registers.

Example: MOV B, C or MOV B, M

Move immediate 8-bit

MVI Rd, data The 8-bit data is stored in the destination register or

M, data memory. If the operand is a memory location, its

location is specified by the contents of the HL

registers. Example: MVI B, 57H or MVI M, 57H

Load accumulator

LDA 16-bit address The contents of a memory location, specified by a

16-bit address in the operand, are copied to the

accumulator. The contents of the source are not

altered. Example: LDA 2034H

Load accumulator indirect

LDAX B/D Reg. pair The contents of the designated register pair point to

a memory location. This instruction copies the

contents of that memory location into the

accumulator. The contents of either the register pair

or the memory location are not altered. Example:

LDAX B

Load register pair immediate

LXI Reg. pair, 16-bit data The instruction loads 16-bit data in the register pair

designated in the operand. Example: LXI H, 2034H

or LXI H, XYZ

Load H and L registers direct

LHLD 16-bit address The instruction copies the contents of the memory

location pointed out by the 16-bit address into

register L and copies the contents of the next

memory location into register H. The contents of

source memory locations are not altered. Example:

LHLD 2040H

Store accumulator direct

STA 16-bit address The contents of the accumulator are copied into the

memory location specified by the operand. This is a

3-byte instruction, the second byte specifies the

low-order address and the third byte specifies the

high-order address. Example: STA 4350H

Store accumulator indirect

STAX Reg. pair The contents of the accumulator are copied into the

memory location specified by the contents of the

operand (register pair). The contents of the

accumulator are not altered. Example: STAX B

Store H and L registers direct

SHLD 16-bit address The contents of register L are stored into the

memory location specified by the 16-bit address in

the operand and the contents of H register are stored

into the next memory location by incrementing the

operand. The contents of registers HL are not

altered. This is a 3-byte instruction, the second byte

specifies the low-order address and the third byte

specifies the high-order address. Example: SHLD

2470H

Exchange H and L with D and E

XCHG none The contents of register H are exchanged with the

contents of register D, and the contents of register L

are exchanged with the contents of register E.

Example: XCHG

Copy H and L registers to the stack pointer

SPHL none The instruction loads the contents of the H and L

registers into the stack pointer register, the contents

of the H register provide the high-order address and

the contents of the L register provide the low-order

address. The contents of the H and L registers are

not altered. Example: SPHL

Exchange H and L with top of stack

XTHL none The contents of the L register are exchanged with

the stack location pointed out by the contents of the

stack pointer register. The contents of the H register

are exchanged with the next stack location (SP+1);

however, the contents of the stack pointer register

are not altered. Example: XTHL

Push register pair onto stack

PUSH Reg. pair The contents of the register pair designated in the

operand are copied onto the stack in the following

sequence. The stack pointer register is decremented

and the contents of the high order register (B, D, H,

A) are copied into that location. The stack pointer

register is decremented again and the contents of the

low-order register (C, E, L, flags) are copied to that

location. Example: PUSH B or PUSH A

Pop off stack to register pair

POP Reg. pair The contents of the memory location pointed out by

the stack pointer register are copied to the low-order

register (C, E, L, status flags) of the operand. The

stack pointer is incremented by 1 and the contents

of that memory location are copied to the high-order

register (B, D, H, A) of the operand. The stack

pointer register is again incremented by 1. Example:

POP H or POP A

Output data from accumulator to a port with 8-bit address

OUT 8-bit port address The contents of the accumulator are copied into the

I/O port specified by the operand. Example: OUT

F8H

Input data to accumulator from a port with 8-bit address

IN 8-bit port address The contents of the input port designated in the

operand are read and loaded into the accumulator.

Example: IN 8CH

4.5.1.2 Arithmetic Instructions

These instructions perform arithmetic operations such as addition, subtraction, increment, and

decrement.


Add register or memory to accumulator

ADD R The contents of the operand (register or memory)

are M added to the contents of the accumulator and

the result is stored in the accumulator. If the

operand is a memory location, its location is

specified by the contents of the HL registers. All

flags are modified to reflect the result of the

addition. Example: ADD B or ADD M

Add register to accumulator with carry

ADC R The contents of the operand (register or memory)

and M the Carry flag are added to the contents of

the accumulator and the result is stored in the

accumulator. If the operand is a memory location,

its location is specified by the contents of the HL

registers. All flags are modified to reflect the result

of the addition. Example: ADC B or ADC M

Add immediate to accumulator

ADI 8-bit data The 8-bit data (operand) is added to the contents of

the accumulator and the result is stored in the

accumulator. All flags are modified to reflect the

result of the addition. Example: ADI 45H

Add immediate to accumulator with carry

ACI 8-bit data The 8-bit data (operand) and the Carry flag are

added to the contents of the accumulator and the

result is stored in the accumulator. All flags are

modified to reflect the result of the addition.

Example: ACI 45H

Add register pair to H and L registers

DAD Reg. pair The 16-bit contents of the specified register pair are

added to the contents of the HL register and the sum

is stored in the HL register. The contents of the

source register pair are not altered. If the result is

larger than 16 bits, the CY flag is set. No other flags

are affected. Example: DAD H

Subtract register or memory from accumulator

SUB R The contents of the operand (register or memory )

are M subtracted from the contents of the

accumulator, and the result is stored in the



registers. All flags are modified to reflect the result

of the subtraction. Example: SUB B or SUB M

Subtract source and borrow from accumulator

SBB R The contents of the operand (register or memory )

and M the Borrow flag are subtracted from the

contents of the accumulator and the result is placed

in the accumulator. If the operand is a memory

location, its location is specified by the contents of

the HL registers. All flags are modified to reflect

the result of the subtraction. Example: SBB B or

SBB M

Subtract immediate from accumulator

SUI 8-bit data The 8-bit data (operand) is subtracted from the

contents of the accumulator and the result is stored

in the accumulator. All flags are modified to reflect

the result of the subtraction. Example: SUI 45H

Subtract immediate from accumulator with borrow

SBI 8-bit data The 8-bit data (operand) and the Borrow flag are

subtracted from the contents of the accumulator and

the result is stored in the accumulator. All flags are

modified to reflect the result of the subtraction.

Example: SBI 45H

Increment register or memory by 1

INR R The contents of the designated register or memory)

are M incremented by 1 and the result is stored in

the same place. If the operand is a memory location,


registers. Example: INR B or INR M

Increments register pair by 1

INX R The contents of the designated register pair are

incremented by 1 and the result is stored in the same

place. Example: INX H

Decrement register or memory by 1

DCR R The contents of the designated register or memory

are M decremented by 1 and the result is stored in

the same place. If the operand is a memory location,


registers. Example: DCR B or DCR M

Decrement register pair by 1

DCX R The contents of the designated register pair are

decremented by 1 and the result is stored in the

same place. Example: DCX H

Decimal adjust accumulator

DAA none The contents of the accumulator are changed from a

binary value to two 4-bit binary coded decimal

(BCD) digits. This is the only instruction that uses

the auxiliary flag to perform the binary to BCD

conversion, and the conversion procedure is

described below. S, Z, AC, P, CY flags are altered

to reflect the results of the operation. If the value of

the low-order 4-bits in the accumulator is greater

than 9 or if AC flag is set, the instruction adds 6 to

the low-order four bits. If the value of the high-

order 4-bits in the accumulator is greater than 9 or if

the Carry flag is set, the instruction adds 6 to the

high-order four bits. Example: DAA

4.5.1.3 Logical Instructions

These instructions perform various logical operations with the contents of the accumulator.


Compare register or memory with accumulator

CMP R The contents of the operand (register or memory)

are M compared with the contents of the

accumulator. Both contents are preserved . The

result of the comparison is shown by setting the

flags of the PSW as follows:

if (A) < (reg/mem): carry flag is set

if (A) = (reg/mem): zero flag is set

if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M

Compare immediate with accumulator

CPI 8-bit data The second byte (8-bit data) is compared with the

contents of the accumulator. The values being

compared remain unchanged. The result of the

comparison is shown by setting the flags of the

PSW as follows:

if (A) < data: carry flag is set

if (A) = data: zero flag is set

if (A) > data: carry and zero flags are reset

Example: CPI 89H

Logical AND register or memory with accumulator

ANA R The contents of the accumulator are logically

ANDed with M the contents of the operand (register

or memory), and the result is placed in the


its address is specified by the contents of HL

registers. S, Z, P are modified to reflect the result of

the operation. CY is reset. AC is set. Example:

ANA B or ANA M

Logical AND immediate with accumulator

ANI 8-bit data The contents of the accumulator are logically

ANDed with the 8-bit data (operand) and the result

is placed in the accumulator. S, Z, P are modified to

reflect the result of the operation. CY is reset. AC is

set. Example: ANI 86H

Exclusive OR register or memory with accumulator

XRA R The contents of the accumulator are Exclusive

ORed with M the contents of the operand (register

or memory), and the result is placed in the




the operation. CY and AC are reset. Example: XRA

B or XRA M

Exclusive OR immediate with accumulator

XRI 8-bit data The contents of the accumulator are Exclusive

ORed with the 8-bit data (operand) and the result is

placed in the accumulator. S, Z, P are modified to

reflect the result of the operation. CY and AC are

reset. Example: XRI 86H

Logical OR register or memory with accumulaotr

ORA R The contents of the accumulator are logically ORed

with M the contents of the operand (register or

memory), and the result is placed in the




the operation. CY and AC are reset. Example: ORA

B or ORA M

Logical OR immediate with accumulator

ORI 8-bit data The contents of the accumulator are logically ORed

with the 8-bit data (operand) and the result is placed

in the accumulator. S, Z, P are modified to reflect

the result of the operation. CY and AC are reset.

Example: ORI 86H

Rotate accumulator left

RLC none Each binary bit of the accumulator is rotated left by

one position. Bit D7 is placed in the position of D0

as well as in the Carry flag. CY is modified

according to bit D7. S, Z, P, AC are not affected.

Example: RLC

Rotate accumulator right

RRC none Each binary bit of the accumulator is rotated right

by one position. Bit D0 is placed in the position of

D7 as well as in the Carry flag. CY is modified


Example: RRC

Rotate accumulator left through carry

RAL none Each binary bit of the accumulator is rotated left by

one position through the Carry flag. Bit D7 is

placed in the Carry flag, and the Carry flag is placed

in the least significant position D0. CY is modified


Example: RAL

Rotate accumulator right through carry

RAR none Each binary bit of the accumulator is rotated right

by one position through the Carry flag. Bit D0 is

placed in the Carry flag, and the Carry flag is placed

in the most significant position D7. CY is modified


Example: RAR

Complement accumulator

CMA none The contents of the accumulator are complemented.

No flags are affected. Example: CMA

Complement carry

CMC none The Carry flag is complemented. No other flags are

affected. Example: CMC

Set Carry

STC none The Carry flag is set to 1. No other flags are

affected. Example: STC

4.5.1.4 Branching Instructions

This group of instructions alters the sequence of program execution either conditionally or

unconditionally.


Jump unconditionally

JMP 16-bit address The program sequence is transferred to the memory

location specified by the 16-bit address given in the

operand. Example: JMP 2034H or JMP XYZ

Jump conditionally

Operand: 16-bit address

The program sequence is transferred to the memory


operand based on the specified flag of the PSW as

described below. Example: JZ 2034H or JZ XYZ

Opcode Description Flag Status

JC Jump on Carry CY = 1

JNC Jump on no Carry CY = 0

JP Jump on positive S = 0

JM Jump on minus S = 1

JZ Jump on zero Z = 1

JNZ Jump on no zero Z = 0

JPE Jump on parity even P = 1

JPO Jump on parity odd P = 0

Unconditional subroutine call

CALL 16-bit address The program sequence is transferred to the memory


operand. Before the transfer, the address of the next

instruction after CALL (the contents of the program

counter) is pushed onto the stack. Example: CALL

2034H or CALL XYZ

Call conditionally

Operand: 16-bit address

The program sequence is transferred to the memory


operand based on the specified flag of the PSW as

described below. Before the transfer, the address of

the next instruction after the call (the contents of the

program counter) is pushed onto the stack.

Example: CZ 2034H or CZ XYZ


CC Call on Carry CY = 1

CNC Call on no Carry CY = 0

CP Call on positive S = 0

CM Call on minus S = 1

CZ Call on zero Z = 1

CNZ Call on no zero Z = 0

CPE Call on parity even P = 1

CPO Call on parity odd P = 0

Return from subroutine unconditionally

RET none The program sequence is transferred from the

subroutine to the calling program. The two bytes

from the top of the stack are copied into the

program counter, and program execution begins at

the new address. Example: RET

Return from subroutine conditionally

Operand: none

The program sequence is transferred from the

subroutine to the calling program based on the

specified flag of the PSW as described below. The

two bytes from the top of the stack are copied into

the program counter, and program execution begins

at the new address. Example: RZ


RC Return on Carry CY = 1

RNC Return on no Carry CY = 0

RP Return on positive S = 0

RM Return on minus S = 1

RZ Return on zero Z = 1

RNZ Return on no zero Z = 0

RPE Return on parity even P = 1

RPO Return on parity odd P = 0

Load program counter with HL contents

PCHL none The contents of registers H and L are copied into

the program counter. The contents of H are placed

as the high-order byte and the contents of L as the

low-order byte. Example: PCHL

Restart

RST 0-7 The RST instruction is equivalent to a 1-byte call

instruction to one of eight memory locations

depending upon the number. The instructions are

generally used in conjunction with interrupts and

inserted using external hardware. However these

can be used as software instructions in a program to

transfer program execution to one of the eight

locations. The addresses are:

Instruction Restart Address

RST 0 0000H

RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

The 8085 has four additional interrupts and these

interrupts generate RST instructions internally and

thus do not require any external hardware. These

instructions and their Restart addresses are:

Interrupt Restart Address

TRAP 0024H

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

4.5.1.5 Control Instructions

These instructions control machine functions such as Halt, Interrupt, or do nothing. The

microprocessor operations related to data manipulation can be summarized in four functions:

1. copying data

2. performing arithmetic operations

3. performing logical operations

4. testing for a given condition and alerting the program sequence

Some important aspects of the instruction set are noted below:

1. In data transfer, the contents of the source are not destroyed; only the contents of the

destination are changed. The data copy instructions do not affect the flags.

2. Arithmetic and Logical operations are performed with the contents of the accumulator,

and the results are stored in the accumulator (with some expectations). The flags are

affected according to the results.

3. Any register including the memory can be used for increment and decrement.

4. A program sequence can be changed either conditionally or by testing for a given data

condition.


No operation

NOP none No operation is performed. The instruction is

fetched and decoded. However no operation is

executed. Example: NOP

Halt and enter wait state

HLT none The CPU finishes executing the current instruction

and halts any further execution. An interrupt or

reset is necessary to exit from the halt state.

Example: HLT

Disable interrupts

DI none The interrupt enable flip-flop is reset and all the

interrupts except the TRAP are disabled. No flags

are affected. Example: DI

Enable interrupts

EI none The interrupt enable flip-flop is set and all interrupts

are enabled. No flags are affected. After a system

reset or the acknowledgement of an interrupt, the

interrupt enable flipflop is reset, thus disabling the

interrupts. This instruction is necessary to reenable

the interrupts (except TRAP). Example: EI

Read interrupt mask

RIM none This is a multipurpose instruction used to read the

status of interrupts 7.5, 6.5, 5.5 and read serial data

input bit. The instruction loads eight bits in the

accumulator with the following interpretations.

Example: RIM

Set interrupt mask

SIM none This is a multipurpose instruction and used to

implement the 8085 interrupts 7.5, 6.5, 5.5, and

serial data output. The instruction interprets the

accumulator contents as follows. Example: SIM

4.5.2 Summary of 8085 Instruction Set

DATA TRANSFER INSTRUCTIONS

MOV Copy from source to destination

MVI Move immediate 8-bit

LDA Load accumulator

LDAX Load accumulator indirect

LXI Load register pair immediate

LHLD Load H and L registers direct

STA Store accumulator direct

STAX Store accumulatorindirect

SHLD Store H and L registers direct

XCHG Exchange H and L with D and E

SPHL Copy H and L registersto the stack pointer

XTHL Exchange H and L with top ofstack

PUSH Push register pair onto stack

POP Pop ofstack to register pair

OUT Output data from accumulatorto a port with 8-bit address

IN Input data to accumulatorfrom a port with 8-bit address

ARITHMETIC INSTRUCTIONS

ADD Add register or memory to accumulator

ADC Add register to accumulator with carry

ADI Add immediate to accumulator

ACI Add immediate to accumulator with carry

DAD Add register pairto H and L registers

SUB Subtract register or memory from accumulator

SBB Subtractsource and borrow from accumulator

SUI Subtract immediate from accumulator

SBI Subtract immediate from accumulator with borrow

INR Increment register or memory by 1

INX Increment register pair by 1

DCR Decrement register or memory by 1

DCX Decrement register pair by 1

DAA Decimal adjust accumulator

LOGICAL INSTRUCTIONS

CMP Compare register or memory with accumulator

CPI Compare immediate with accumulator

ANA Logical AND register or memory with accumulator

ANI Logical AND immediate with accumulator

XRA Exclusive OR register or memory with accumulator

XRI Exclusive OR immediate with accumulator

ORA Logical OR register or memory with accumulator

ORI Logical OR immediate with accumulator

RLC Rotate accumulator left

RRC Rotate accumulator right

RAL Rotate accumulator left through carry

RAR Rotate accumulator right through carry

CMA Complement accumulator

CMC Complement carry

STC Set carry

BRANCHING INSTRUCTIONS

JMP Jump unconditionally

JC Jump on carry

JNC Jump on no carry

JP Jump on positive

JM Jump on minus

JZ Jump on zero

JNZ Jump on no zero

JPE Jump on parity even

JPO Jump on parity odd

CALL Call unconditionally

CC Call on carry

CNC Call on no carry

CP Call on positive

CM Call on minus

CZ Call on zero

CNZ Call on no zero

CPE Call on parity even

CPO Call on parity odd

RET Return unconditionally

RC Return on carry

RNC Return on no carry

RP Return on positive

RM Return on minus

RZ Return on zero

RNZ Return on no zero

RPE Return on parity even

RPO Return on parity odd

PCHL Load program counter with HL contents

RST Restart

CONTROL INSTRUCTIONS

NOP No operation

HLT Halt

DI Disable interrupts

EI Enable interrupts

RIM Read interrupt mask

SIM Set interrupt mask

4.5.3 Instruction Format

An instruction is a command to the microprocessor to perform a given task on a specified data.

Each instruction has two parts: one is task to be performed, called the operation code (opcode),

and the second is the data to be operated on, called the operand. The operand (or data) can be

specified in various ways. It may include 8-bit (or 16-bit ) data, an internal register, a memory

location, or 8-bit (or 16-bit) address. In some instructions, the operand is implicit.

Instruction word size: The 8085 instruction set is classified into the following three groups

according to word size:

1. One-word or 1-byte instructions

2. Two-word or 2-byte instructions

3. Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,

instructions are commonly referred to in terms of bytes rather than words.

1. One-Byte Instructions: A 1-byte instruction includes the opcode and operand in the

same byte. Operand(s) are internal register and are coded into the instruction. For

example:

Task Opcode Operand Binary code Hex code

Copy the contents of the

accumulator in the register C.

MOV C, A 0100 1111 4FH

Add the contents of register B to the

contents of the accumulator.

ADD B 1000 0000 80H

Invert (compliment) each bit in the

accumulator.

CMA 0010 1111 2FH

These instructions are 1-byte instructions performing three different tasks. In the first instruction,

both operand registers are specified. In the second instruction, the operand B is specified and the

accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the

implicit operand. These instructions are stored in 8- bit binary format in memory; each requires

one memory location.

MOV rd,

rs rd <-- rs copies contents of rs into rd.

Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the

destination of the data, sss is the code of the source register.

Example: MOV A,B

Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction design of such

processors).

ADD r

A <-- A + r

2. Two-Byte Instructions: In a two-byte instruction, the first byte specifies the operation

code and the second byte specifies the operand. Source operand is a data byte

immediately following the opcode. For example:

Task Opcode Operand Binary

code

Hex code

Load an 8-bit data byte

in the accumulator

MVI A, DATA 0011 1110

DATA

3E

Data

First Byte

Second Byte

Assume that the data byte is 32H. The assembly language instruction is written as

Mnemonics Hex code

MVI A, 32H 3E 32H

The instruction would require two memory locations to store in memory.

MVI r,data

r <-- data

Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is an example of

immediate addressing.

ADI data

A <-- A + data

OUT port where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but

points directly to where it is located this is called direct addressing.

3. Three-Byte Instructions: In a three-byte instruction, the first byte specifies the opcode,

and the following two bytes specify the 16-bit address. Note that the second byte is the

low-order address and the third byte is the high-order address. opcode + data byte + data

byte For example:

Task Opcode Operand Binary

code

Hex code

Transfer the program

sequence to the memory

location 2085H.

JMP 2085H 1100 0011

1000 0101

0010 0000

C3

85

20

First Byte

Second Byte

Third Byte

This instruction would require three memory locations to store in memory.

Three byte instructions - opcode + data byte + data byte

LXI rp, data16

rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data bytes are 16-

bit data in L H order of significance.

rp <-- data16

Example: LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate

addressing.

LDA addr

A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H

21H. This is also an example of direct addressing.

4.6 Addressing Modes

The instructions MOV B, A or MVI A, 82H are to copy data from a source into a destination. In

these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH).

Similarly, a destination can be a register or an output port. The sources and destination are

operands. The various formats for specifying operands are called the ADDRESSING MODES.

For 8085, they are:

1. Immediate addressing.

2. Register addressing.

3. Direct addressing.

4. Indirect addressing.

5. Implied addressing

1. Immediate addressing: Data is present in the instruction. Load the immediate data to the

destination provided.

Example: MVI R, data

MVI A, 30H (30H is copied into the register A)

MVI B, 40H(40H is copied into the register B).

2. Register addressing: Data is provided through the registers.

Example: MOV Rd, Rs

MOV B, A (the content of A is copied into the register B)

MOV A, C (the content of C is copied into the register A).

3. Direct addressing: Used to accept data from outside devices to store in the accumulator

or send the data stored in the accumulator to the outside device. Accept the data from the

port 00H and store them into the accumulator or Send the data from the accumulator to

the port 01H.

Example: IN 00H or OUT 01H

LDA 3000H (The content at the location 3000H is copied to the register A).

4. Indirect Addressing: This means that the Effective Address is calculated by the

processor. And the contents of the address (and the one following) is used to form a

second address. The second address is where the data is stored. Note that this requires

several memory accesses; two accesses to retrieve the 16-bit address and a further access

(or accesses) to retrieve the data which is to be loaded into the register.

Example: MOV A, M (data is transferred from the memory location pointed by the

register to the accumulator).

5. Implied Addressing Mode: This mode doesn't require any operand. The data is specified

by opcode itself.

4.7 Simple programs using arithmetic and logical

1. Write an assembly program to add two numbers

Program

MVI D, 8BH

MVI C, 6FH

MOV A, C

1100 0011

1000 0101

0010 0000ADD D

OUT PORT1

HLT

2. Write an assembly program to multiply a number by 8

Program

MVI A, 30H

RRC

RRC

RRC

OUT PORT1

HLT

3. Write an assembly program to find greatest between two numbers

Program

MVI B, 30H

MVI C, 40H

MOV A, B

CMP C

JZ EQU

JC GRT

OUT PORT1

HLT

EQU: MVI A, 01H

OUT PORT1

HLT

GRT: MOV A, C

OUT PORT1

HLT

REVIEW QUESTIONS

1. Explain the block diagram of Microcomputer.

2. What are the function of Microprocessor?

3. Define Instruction Sets. What are the various instruction set?

4. Explain the pin description of 8085 Microprocessor.

5. Describe the various addressing mode.

6. Define the internal architecture of 8085 microprocessor.

7. What are the functions of 8085?

8. Define the 8085 system bus.

9. What do you mean by microcontroller.

10. What are the various logical instruction?

CHAPTER 5

INTERFACING AND APPLICATIONS OF

MICROPROCESSOR

5.1 Basic Interfacing Concept

Interfacing is the process of connecting devices together so that they can exchange

information. A special interface must translate between the signal that the computer uses and

those that the peripheral uses. An interface includes the physical connection, the hardware and a

set of rules or procedures, i.e., the software. The interface must provide the proper timing and

control. Formally, an interface is a device and/or set of rules to match the output of one device to

the input of another device for sending information from one to the other. For example, the

connection between a microprocessor and external memory is an interface. There are physical

connections for addressing, data flow and control signals. The software consists of instructions

that read from and/or write to an addressed location.

Any application of Microprocessor Based system Requires the transfer of data between

external circuitry to the Microprocessor and Microprocessor to the External circuitry. User can

give information (i.e. input) to the Microprocessor using keyboard and user can see the result or

output information from the Microprocessor with the help of display. Hence interfacing is used

to exchange information between two different applications/devices.

The major problems with interfacing are:

- wide variety of peripheral devices

- enormous range of peripheral speeds

- variety in signal types and signal levels in peripheral devices

- complexity of the signaling structure (strobes, handshaking, etc.)

5.2 Interfacing of Input/Output Device The process of reading input signals and sending output signals is called input/output (I/O). The

subsystems are known as I/O subsystems which are sometimes called an interface. Input and

output are similar to memory accesses. The processor can transfer data to and from the

peripherals in the same way that it transfers data to and from memory. In fact, memory is simply

another peripheral. I/O direction is relative to the MCU. Input is data read by the MCU. Output is

data sent out by the MCU.

A simple I/O section in a microcomputer system may include a temperature sensor that

provides data every 5 minutes, a modem device that transfers 56K bits every second and a floppy

disk that transfers bits in the order of megabits per second.

5.2.1 Simple Input Interface

An input operation is similar to a memory read cycle.

1. μP generates address and control signals to select the input device.

2. Input device generates data and loads data lines.

3. μP reads data from the data bus and places it in a register.

Most μPs accept data from an input device through the data bus connections and therefore

require some form of switch to connect this data to the bus at the appropriate time. One effective

digital switch available is the three-state buffer.

5.2.2 Simple Output Interface

An output operation is similar to a memory write cycle.

1. μP generates address and control signals to select the output device.

2. μP places data on the data bus.

3. μP waits for the transfer to be successfully completed.

Whenever data is sent out from the μP to an external output device, it appears on the data bus for

only a brief period of time. In almost all instances, the external output device uses some form of

latch to grab onto and hold the data bus information.

5.2.3 Input/Output Mapping

Most I/O sections consist of more than one device. Such I/O sections require bus structures that

must be combined with those required by the memory section. Almost all microprocessors use

the same bus for both memory and I/O transfers.

There are two basic input/output schemes:

1. Memory-mapped I/O; in which I/O devices (parallel I/O lines) are treated exactly the

same as memory locations

2. Isolated I/O; in which memory and I/O addresses are decoded separately.

Advantages of memory-mapped I/O are:

- Any instruction that operates on data in memory can operate on data at input and output

devices.

- No separate decoding or control system is necessary for input and output.

Drawbacks of memory-mapped I/O are:

- I/O transfers may be difficult to distinguish from other operations in software.

- I/O devices occupy some of the address space.

- The decoding system may become complex because I/O devices occupy much less than

memory chips. In order to avoid complexity the memory space has to be wasted.

Advantages of isolated I/O are:

- I/O device addresses can be short.

- Programs are clearer because I/O transfers are distinguished from other operations.

- Memory and I/O design can be separated

Drawback of isolated I/O is the requirement for extra decoding and extra instructions.

5.2.4 General Input/Output Interfacing and I/O Registers

I/O systems do not control only simple switches and leds. I/O systems usually transfer data to

and from more complex peripheral devices. Data is usually required to be input whenever it is

ready at the device side. Similarly data is usually required to be output whenever the peripheral

device is ready to accept it. Microcontrollers generally have built-in I/O subsystems because they

are designed to handle the different types of interface requirements commonly found in industry.

Some applications require more I/O than can be handled by the MCU‘s built in I/O subsystems.

In this case the MCU board could include programmable I/O peripheral chips.

Both microcontrollers and programmable I/O chips handle I/O processing using registers.

Generally, an I/O section has some associated registers like the control, status and data registers.

The control register is programmed (suitable data is written) to define the operation

characteristics of the I/O section. An I/O section can therefore be programmed as follows:

the signal lines can be defined as input or output

availability of the external data or the readiness of the external device can be

detected by a

transition in an associated signal line

the transition type can be defined to be level (high or low) or edge (rising or

falling edge) sensitive

whenever a transition occurs, an interrupt signal may or may not be generated.

The status register is read to check the status of the I/O. By reading it, one can understand,

whether the external data is available (external device made its data ready) or

whether the external device is ready to input its data

whether there is an error in the transfer or not.

The data register holds the input data that has been received or the output data that was most

recently sent out.

The above I/O functionality can be done on a separate chip which then can be connected to the

μP appropriately or the I/O functionality can be implemented on the microcontroller itself. The

MC6821 Peripheral Interface Adapter (PIA) chip is a programmable I/O interface chip.

5.2.5 The Peripheral Interface Adapter (PIA)

A set of ports (parallel I/O signal lines), sometimes on chip memory, registers, programmable

counter and a timer may constitute the peripheral interface adapter (PIA). In general, PIA is a

programmable

LSI device with the following features.

buffers and latches for input and output data

status and control signals for handshaking

other control and timing signals for peripherals

direct interface with the processor address, data and control buses

PIA usage:

For simple parallel input/output:

1. address the PIA control register

2. transfer control information into PIA

3. address the PIA data register

4. transfer data (in or out) through PIA

The MC6821 Peripheral Interface Adapter (PIA)

Data Registers (DR), when addressed, store the data present on the MPU data bus during an

MPU write operation.

During an MPU read operation, the data present on peripheral lines programmed as

inputs is transferred directly to the system data bus.

µP

PIA

µP buses

Device

The Data Direction Registers (DDR) are used to establish each individual peripheral bus line as

either an input or an output. This is accomplished by having the MPU write "ones" or

"zeros" into the eight bit positions of the DDR. Zeros or ones cause the corresponding

peripheral data lines to function as inputs or outputs, respectively.

Selection of 6821 and Internal Registers:

There are three chip select inputs and one enable input.

Since all data transfers take place during the high portion of the clock cycle, the Enable (E) input

is normally connected to E clock of the 6811.

The PIA occupies four memory locations through two RS pins. Since there are six registers, but

four addresses, DDR and DR share the same address from the point of MPU address bus. These

two are selected via bit-2 of CR. If it is zero DDR is selected, if one DR is selected. Internal

addressing (register selection) of the PIA is as follows:

RS1 RS0 CRA-2 CRB-2 Selected Register

0 0 0 X DDRA

0 0 1 X DRA (Peripheral register)

0 1 X X CRA

1 0 X 0 DDRB

1 0 X 1 DRB (Peripheral register)

1 1 X X CRB

Before the selection of DDR and DR, bit-2 of the corresponding CR has to be set to the proper

level.

The control registers (CR) allow the MPU to establish and control the operating modes of the

peripheral control lines, CA1, CA2, CB1, CB2.

Organization of the PIA control registers is as follows:

Bit-7 (IRQA1 Interrupt Flag): Goes high on active transition of CA.); automatically cleared by

MPU read of DRA, may also be cleared by hardware reset. It is read only (CRB-7).

Bit-6 (IRQA2 Interrupt Flag): If CA2 is input: Goes high on active transition of CA2, cleared in

the same way as bit-7. If CA2 is output: It is equal to zero, not affected by CA2 transitions.

(CRB-6)

Bit-0 (Interrupt Request Enable/Disable): If it is equal to zero, disables IRQA interrupt which

will be caused by CA1 active transition. If it is one, enable CA1 interrupt. (CRB-0)

Bit-1 (Active transition determination): if 0, high-to-low transition of CA1 sets IRQA1; if 1,

low-to-high transition sets IRQA1. (CRB-1)

Bit-2 (DDRA access): If 0, DDRA is selected; if 1, DRA selected. (CRB-2)

Bit-5 (CA2 input-output control):

RESET: The RESET input clears all the PIA registers. All the data and control lines are initially

inputs, all interrupts are disabled and DDR is selected.

Examples on I/O applications

If PIA is used, the device has to be initialized by programming. General initialization procedure

is as follows:

- clear bit-2 of CRA (CRB) to select DDRA (DDRB)

- load DDR in order to program the ports as input or output lines in the required manner

- set bit-2 of CRA (CRB) to select DRA (DRB)

- write and read

Example: Transfer the contents of location $0040 via port A of the PIA. Assume the following

PIA register address:

DDRA, DRA: $8008

CRA: $8009

mnemonic comment

CLR $8009 CRA-2 is cleared. $8008 is the address of DDRA

LDAB #$FF

STAB $8008 DDRA is loaded with all 1‘s. Port A is programmed as output

LDAB #$04

STAB $8009 CRA-2 is set. $8008 is the address of DRA

LDAA $40 Load the contents of location $40 to Acc.A

STAA $8008 Transfer the contents of Acc.A to Port A

-

-

-

Example: It is required to control a 4-bit LED display with a 4-bit DIP switch via a 6811+6821

system. You are allowed to use only Port A of the PIA and assume the following PIA register

address:

DDRA, DRA: $8008

CRA: $8009

PA0

PA1

PA2

PIA PA3

PA4

PA5

PA6

PA7

DIP

SWITCH

LED

SWITCH

label mnemonic comment

CLR $8009 CRA-2 is cleared. $8008 is the address of DDRA

LDAB #$F0

STAB $8008 DDRA is loaded with four 1‘s and four 0‘s. Port A

is programmed as half output and half input

LDAB #$04

STAB $8009 CRA-2 is set. $8008 is the address of DRA

LOOP LDAA $8008 Read the position of the DIP switch

ASLA

ASLA

ASLA

ASLA Transfer LSN to MSN

STAA $8008 Transfer the info to display

BRA LOOP

5.3 Interrupts in 8085

5.3.1 Interrupt Mechanism Types, and Priority Interrupts provide a mechanism for quickly changing program environment. Transfer of program

control is initiated by the occurrence of either an event to the microprocessor or an event in its

external hardware.

The 8088 and 8086 microcomputers are capable of implementing any combination of up to 256

interrupts. As Fig. 11-1 shows, they are divided into five groups.

Increasing priority

Reset

Internal interrupts and exceptions

Software interrupts

Nonmaskable interrupt

External hardware interrupts

The user defines the function of the external hardware, software, and nonmaskable interrupt. For

instance, hardware interrupts are often assigned to devices such as the keyboard, printer, and

timers. On the other hand, the functions of the internal interrupts and reset are not user defined.

They perform dedicated system functions. An example of a high-priority service routine that

should not be interrupted is that for a power failure. Once initiated, this routine should be quickly

run to completion to assure that the microcomputer goes through an orderly power-down. A

keyboard should also be assigned to a high-priority interrupt. This will assure that the keyboard

buffer does not get full and lock out additional entries. On the other hand, devices such as the

floppy disk or hard disk controller are typically assigned to a lower priority level.

5.3.3 Interrupt Instruction

A number of instructions are provided in the instruction set of the 8086 microprocessors for use

with interrupt processing. Figure below lists these instructions.

Mnemonic Meaning Format Operation Flag

Affected

CLI Clear interrupt flag CLI 0 → (IF) IF

STI Set interrupt flag STI 1 → (IF) IF

INT n Type n software interrupt INT n (Flags) → ((SP)-2)

0→TF,IF

(CS) → ((SP)-4)

(2+4*n) →CS

(IP) → ((SP)-6)

(4*n) → (IP)

TF, IF

IRET Interrupt return IRET ((SP)) → (IP)

((SP)+2) → (CS)

((SP)+4) → (Flags)

(SP)+ 6→ (SP)

ALL

INTO Interrupt on overflow INTO INT 4 steps TF, IF

HLT Halt HLT Wait for an external

interrupt or reset to occur

None

WAIT Wait WAIT Wait for TEST input to

go active

None

STI enables the external interrupt request (INTR) input for operation by setting IF, while

CLI disable the external interrupt input by resetting IF.

INT n instruction is used to initiate a vectored call of a subroutine.

For example

1. saves the flag register on the stack, : INT 50 initiates execution of a subroutine whose

starting point is identified by vector 50 in the pointer table (in Figure 11.2). It also :

2. saves the old program context on the stack,

3. and clears TF and IF.

IRET instruction must be included at the end of each interrupt service routine.

INTO is theinterrupt-on-overflow instruction. This instruction must be included after

arithmetic instructions that can result in an overflow condition, such as divide. It tests the

overflow flag, and if the flag is found to be set, a type 4 internal interrupt is initiated.

5.3.4 External Hardware Interrupt Interface Signals When an interrupt request has been recognized on the NMI pin, the 8086 initiate type 2

interrupt (CS2:IP2).

o It cannot be masked by IF.

o The NMI input is positive edge triggered. Therefore, a request for service is

automatically latched internal to the MPU.

When an interrupt request has been recognized on the INTR pin, then

o If IF= 0 then the interrupt request is ignored.

o If IF= 1 then 8086

1. saves the flag register on the stack,

2. saves the old program context on the stack,

3. and clears TF and IF.

4. respond with two pulses at INTA during interrupt acknowledge bus

cycle

The first pulse signals the external circuitry that the interrupt request has been

acknowledged and to prepare to sent the number to the 8086.

The second pulse tells the external circuitry to put the type number on the data

bus.

RESET :

o The reset input of the 8086 MPU provides a hardware means for initializing the

microcomputer.

o After reset the MPU start execution at address:

CS : IP = FFFFH : 0000H

This mean the physical address is FFFF0

What instructions should be written in this address?

5.3.5 Internal interrupt function

It is involve four types: divide error, overflow error, single step, and breakpoint. Single Step The

single-step function relates to an operation option of the 8086. If the trap flag (TF) is set, the

single-step mode of operation is enabled. When TF is set, the MPU initiates a type 1 interrupt to

the service routine defined by IP1 and CS1 at addresses 0000416 and 0000616, respectively, at

the completion of every instruction of the user program.

5.3.6 Interfacing using polling or interrupts

There are two methods for controlling the flow of data in and out of the computer:

1. Program controlled I/O (polling): μP repeatedly executes a program code and checks

periodically whether a peripheral requests servicing. When it finds that a

peripheral has requested service, the μP performs the data transfer operation, either a read

or write.

An external peripheral may request service by sending a pulse on an I/O request

line. The I/O request may be for a read or a write operation. Either a low-to-high

transition or a high-to-low transition on the I/O request line causes a bit in the associated

status register to set (or reset).

To determine whether or not to serve a peripheral, the MCU reads (polls) a status

register periodically to check the corresponding status bit (request flag). If an I/O request

is detected, then it proceeds to handle the request as required, i.e. the MCU executes an

I/O service routine. For a read operation, it may be something like ―read the data register

and pass the value to the main program in an accumulator.‖ For a write operation, it may

be an output routine that passes an accumulator value to the data register.

Advantage: Simple program.

Disadvantage: Inefficient use of μP time. μP may miss data if the input data changes

more rapidly than μP loop time.

2. Interrupt controlled I/O: An I/O device sends an interrupt signal to μP to notify the

computer that either the peripheral has data for the μP or it expects the computer

to output data for the peripheral. The μP then suspends its current task to service the

interrupt. μP goes to the interrupt service subroutine which then services the interrupt by

reading from or writing to I/O ports. After the service, Μp returns back to its original

execution.

Like polling, an active transition on the request line may set the request flag. In

this case it also asserts an interrupt.

The μP stacks the μP registers and sets I bit in the condition code register.

μP then executes the service routine addressed by the interrupt vector. If more

than one device could cause the same interrupt, the μP checks other status bits to

determine which service has caused the interrupt. The μP clears the request flag and then

completes the I/O depending on the requirements. After completion of the interrupt

service, return from interrupt (RTI) instruction is eceuted by the MPU, which returns the

control to the interrupted program.

Advantage: More efficient

Disadvantage: Complex program.

5.4 Ports

The 68HC11 has five 8-bit ports. Any of these can be used as parallel I/O ports, depending on

how their respective control registers are configured. Of these, ports B and C can only be used

for parallel I/O. Port D is for serial I/O, port A is for programmable timer and port E is for

analog/digital converter.

Any of the port C and D lines can be used as input or output, depending on how their

respective data direction bits are configured. Pin 7 of port A (PA7) is also bidirectional. When

port A is used for parallel I/O, lines 0,1 and 2 are input only and lines 3,4,5 and 6 are output

only. Port B is used for output only. Port E is an input port when used for parallel I/O.

Parallel I/O

• Each line carries 1 bit of data word.

• All 5 ports on the 68HC11 can be used for parallel I/O.

• Mostly used parallel ports are Port B and Port C.

• Port B is an output port.

• Port C can be configured to be either input or output.

• Ports B and C can be used for strobed I/O or full handshake I/O.

• Uses: LED, keyboard, printer interface, switches.

Serial I/O

• Uses a single line to transmit bits one after the other. This reduces the number of lines

but

slows down the rate of data transfer.

• May be synchronous or asynchronous.

• Port D used for serial I/O

• Often used for: Computer connection, modem, mouse, network

• One of the most common standards is asynchronous serial which is called the RS-232

interface.

Programmable timer

• Port A is used for timer functions such as timed outputs or measuring input times.

• Uses: Generate time delays, measure frequency of input signals, measure pulse widths

Analog/digital converter

• Converts an analog voltage into a binary number

• Port E is used for A/D conversion

• Uses: Many physical quantities are represented by anolog values such as temperature,

voltage, pressure, light intensity,...

Summary of port functions

• PORT A: Timer operations or parallel I/O

o PA0-PA2 input only

o PA4-PA6 output only

o PA3 and PA7 output or input

• PORT B: Upper 8 bits of address bus (expanded multiplexed mode) or parallel I/O

o PB0-PB7 output only

• PORT C: Multiplexed address/data bus (expanded multiplexed mode) or parallel I/O

PC0-PC7 input or output

• PORT D: Asynchronous serial I/O (PD0-PD1), synchronous serial I/O (PD2-PD5) or

parallel

I/O

o PD0-PD5 input or output

• PORT E: A/D converter or parallel I/O

o PE0-PE7 input only

5.5 Applications of Microprocessor

5.5.1 Temperature Control

5.5.1.1 General Description

The NE1617A is an accurate two-channel temperature monitor. It measures the temperature of

itself and the temperature of a remote sensor. The remote sensor is a diode connected transistor.

This can be in the form of either a discrete NPN/PNP, such as the 2N3904/2N3906, or a diode

connected PNP built into another die, such as is done on some Intel microprocessors.

The temperature of both the remote and local sensors is stored in a register that can be

read via a 2-wire SMBus. The temperatures are updated at a rate that is programmable via the

SMBus (the average supply current is dependent upon the update rate — the faster the rate, the

higher the current).

In addition to the normal operation, which is to update the temperature at the

programmed rate, there is a one-shot mode that will force a temperature update.

There is also an alarm that senses either an overtemperature or undertemperature

condition. The trip points for this alarm are also programmable.

The device can have one of nine addresses (determined by two address pins), so there can

be up to nine of the NE1617A on the SMBus.

It can also be put in standby mode (in order to save power). This can be done either with

software (over the SMBus) or with hardware

5.5.1.2 Features and Benefits

Replacement for Maxim MAX1617 and Analog Devices ADM1021

Monitors local and remote temperature

Local (on-chip) sensor accuracy:

±2 oC at 60

oC to 100

oC

±3 oC at -40

oC to 125

oC

Remote sensor accuracy:

±3 oC at 60

oC to 100

oC

±5 oC at -40

oC to 125

oC

No calibration required

Programmable overtemperature/undertemperature alarm

SMBus 2-wire serial interface up to 100 kHz

3 V to 5.5 V supply range; 5.5 V tolerant

70 µA supply current in operating mode

3 µA (typical) supply current in standby mode

ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-

C101

Latch-up testing is done to JEDEC standard JESD78, which exceeds 100 mA

Small 16-lead SSOP (QSOP) package


Desktop computers

Notebook computers

Smart battery packs

Industrial controllers

Telecommunications equipment

5.5.1.4 Functional Description

The NE1617A contains an integrating A-to-D converter, an analog multiplexer, a status register,

digital data registers, SMBus interface, associated control logic and a local temperature sensor or

channel. The remote diode-type sensor or channel should be connected to the D+ and D- pins

properly.

Temperature measurements or conversions are either automatically and periodically

activated when the device is in free-running mode (both STBY pin = HIGH, and the

configuration register bit 6 = LOW) or generated by one-shot command. The free-running period

is selected by changing the programmable data of the conversion rate register. For each

conversion, the multiplexer switches current sources through the remote and local temperature

sensors over a period of time, about 60 ms, and the voltages across the diode-type sensors are

sensed and converted into the temperature data by the A-to-D converter. The resulting

temperature data is then stored in the temperature registers, in 8-bit two's complement word

format and automatically compared with the limits which have been programmed in the

temperature limit registers. Results of the comparison are reflected accordingly by the flags

stored in the status register, an out-of-limit condition will set the ALERT output pin to its LOW

state. Because both channels are automatically measured for each conversion, the results are

updated for both channels at the end of every successful conversion.

Temperature Measurement

The method of the temperature measurement is based on the change of the diode VBE at two

different operating current levels given by:

Δ VBE = (n * KT/q) * LN(N)

where:

ΔVBE = change in base emitter voltage drop at two current levels

n = non-ideality

K = Boltzman‘s constant

T = absolute temperature in Kelvin

q = charge on the electron

LN = natural logarithm

N = ratio of the two currents

The NE1617A forces two well-controlled current sources of about 10 µA and 100 µA and

measures the remote diode VBE. The sensed voltage between two pins D+ and D- is limited

between 0.25 V and 0.95 V. The external diode must be selected to meet this voltage range at

these two current levels and also the non-ideality factor ‗n‘ must be close to the value of 1.008 to

be compatible with the Intel Pentium III internal thermal diode that the NE1617A was designed

to work with. The diode-connected PNP transistor provided on the microprocessor is typically

used, or the discrete diode-connected transistor 2N3904 or 2N3906 is recommended as an

alternative.

Even though the NE1617A integrating A-to-D converter has a good noise performance,

using the average of 10 measurement cycles, high frequency noise filtering between D+ and D-

should be considered. An external capacitor of 2200 pF typical (but not higher than 3300 pF)

connected between D+ and D is recommended. Capacitance higher than 3300 pF will introduce

measurement error due to the rise time of the switched current source.

No Calibration Required

The NE1617A uses two well-controlled current sources of 10 : 1 ratio to measure the forward

voltage of the diode (VBE). This technique eliminates the diode saturation current (a heavily

process and temperature dependent variable), and results in the forward voltage being

proportional to absolute temperature.

Address logic

The address pins of the NE1617A can be forced into one of three levels: LOW (GND), HIGH

(VDD), or ‗not connected‘ (n.c.). Because the NE1617A samples and latches the address pins at

the starting of every conversion, it is suggested that those address pins should be hard-wired to

the logic applied, so that the logic is consistently existed at the address pins. During the address

sensing period, the device forces a current at each address pin and compares the voltage

developed across the external connection with the predefined threshold voltage in order to define

the logic level. If an external resistor is used for the connection of the address, then its value

should be less than 2 kΩ to prevent the error in logic detection from happening. Resistors of 1

kΩ are recommended.

5.5.1.5 Temperature monitor with SMBus serial interface

1. Serial bus interface: The device can be connected to a standard 2-wire serial interface

System Management Bus (SMBus) as a slave device under the control of a master device,

using two device terminals SCLK and SDATA.

2. Slave address: The device address is defined by the logical connections applied to the

device pins ADD0 and ADD1. The device address can be set to any one of those nine

combinations and more than one device can reside on the same bus without address

conflict. Note that the state of the device address pins is sampled and latched not only at

power-up step, but also at starting point of every conversion.

3. Registers: The device contains more than 9 registers. They are used to store the data of

device set-up and operation results. Depending on the bus communication (either read or

write operations), each register may be called by different names because each register

may have different sub-addresses or commands for read and write operations. For

example, the configuration register is called as WC for write mode and as RC for read

mode.

i. Low power standby modes: Upon POR, the device is reset to its normal free-

running auto-conversion operation mode. The device can be put into standby

mode by either using hardware control (connect the STBY pin to LOW for

hardware standby mode) or using software control (set bit 6 of the

configuration register to HIGH for software standby mode). When the device

is put in either one of the standby modes, the supply current is reduced to less

than 10 µA if there is no SMBus activity, all data in the device registers are

retained and the SMBus interface is still alive to bus communication.

However, there is a difference in the device ADC conversion operation

between hardware standby and software standby modes. In hardware standby

mode, the device conversion is inhibited and the one-shot command does not

initiate a conversion. In software standby mode, the one-shot command will

initiate a conversion for both internal and external channels. If a hardware

standby command is received when the device is in normal mode and a

conversion is in progress, the conversion cycle will stop and data in reading

temperature registers will not be updated.

ii. Configuration register: The configuration register is used to mask the Alert

interrupt and/or to put the device in software standby mode. Bit 7 is used to

mask the device ALERT output from Alert interruption when this bit is set to

logic 1, and bit 6 is used to activate the standby software mode when this bit is

set to logic 1. This register can be written or read using the commands of

registers named WC and RC accordingly. Upon Power-On Reset (POR), both

bits are reset to zero.

iii. External and internal temperature registers: Results of temperature

measurements after every ADC conversion are stored in two registers: Internal

Temp register (RIT) for internal or local diode temperature, and External

Temp register (RET) for external or remote diode temperature. These registers

can be only read over the SMBus. The reading temperature data is in 2's

complement binary form consisting of 7-bit data and 1-bit sign (MSB), with

each data count represents 1 oC, and the MSB bit is transmitted first over the

serial bus. The contents of those two registers are updated upon completion of

each ADC conversion.

iv. Conversion rate register: The conversion rate register is used to store

programmable conversion data, which defines the time interval between

conversions in standard free-running auto-convert mode. Only three LSB bits

of the register are used and other bits are reserved for future use. This register

can be written to and read back over the SMBus using commands of the

registers named WCR and RCR, respectively. The POR default conversion

data is 02h (0.25 Hz).

v. Temperature limit registers: The device has four registers to be used for storing

programmable temperature limits, including the high limit and the low limit

for each channel of the external and internal diodes. Data of the temperature

register (RIT and RET) for each channel are compared with the contents of the

temperature limit registers of the same channel, resulting in alarm conditions.

If measured temperature either equals or exceeds the corresponding

temperature limits, an Alert interrupt is asserted and the corresponding flag bit

in the status register is set. The temperature limit registers can be written to

and read back using commands of registers named WIHL, WILL, WEHL,

WELL, RIHL, RILL, REHL, RELL, accordingly. The POR default values are

+127 oC (0111 1111) for the HIGH limit and -55

oC (1100 1001) for the LOW

limit.

vi. One-shot command: The one-shot command is not actually a data register as

such and a write operation to it will initiate an ADC conversion. The send byte

format of the SMBus, with the use of OSHT command (0Fh), is used for this

writing operation. In normal free-running-conversion operation mode of the

device, a one-shot command immediately forces a new conversion cycle to

begin. However, if a conversion is in progress when a one-shot command is

received, the command is ignored. In software standby mode the one-shot

command generates a single conversion and comparison cycle and then puts

the device back in its standby mode after the conversion. In hardware standby

mode, the one shot is inhibited.

vii. Status register: The content of the status register reflects condition status

resulting from all of these activities: comparisons between temperature

measurements and temperature limits, the status of ADC conversion, and the

hardware condition of the connection of external diode to the device. This

register can only be read using the command of register named RS. Upon

POR, the status of all flag bits are reset to zero. The status byte is cleared by

any successful read of the status register unless the fault condition persists.

viii. Alert interrupt: The ALERT output is used to signal Alert interruption from the

device to the SMBus and is active LOW. Because this output is an open-drain

output, a pull-up resistor (10 kΩ typical) to VDD is required, and slave devices

can share a common interrupt line on the same SMBus. An Alert interrupt is

asserted by the device whenever any one of the fault conditions, occurs:

measured temperature equals or exceeds corresponding temp limits, the remote

diode is physically disconnected from the device pins. Alert interrupt signal is

latched and can only be cleared by reading the Alert Response byte from the

Alert Response Address, which is a special slave address to the SMBus. The

ALERT output cannot be reset by reading the device status register.

4. Power-up default condition: Upon power-up reset (power is switched off-on), the

NE1617A goes into this default condition:

• Interrupt latch is cleared, the ALERT output is pulled HIGH by the external

pull-up resistor.

• The auto-conversion rate is at 0.25 Hz; conversion rate data is 02h.

• Temperature limits for both channels are +127 oC for high limit, and -55

oC for

low limit.

• Command pointer register is set to ‗00‘ for quickly reading the RIT.

5. Fault detection: The NE1617A has a fault detector to the diode connection. The

connection is checked when a conversion is initiated and the proper flags are set if the

fault condition has occurred.

6. SMBus interface: The device can communicate over a standard 2-wire serial interface

System Management Bus (SMBus) using the device pins SCLK and SDATA. The device

employs four standard SMBus protocols: write byte, read byte, send byte and receive

byte. Data formats of those protocols with following notifications:

• The SMBus master initiates data transfer by establishing a START condition (S)

and terminates data transfer by generating a STOP condition (P).

• Data is sent over the serial bus in sequence of 9 clock pulses according to each

8-bit data byte followed by 1-bit status of the device acknowledgement.

• The 7-bit slave address is equivalent to the selected address of the device.

• The command byte is equivalent to the selected command of the device register.

• The ‗send byte‘ format is often used for the one-shot conversion command.

• The ‗receive byte‘ format is used for quicker transfer data from a device reading

register that was previously selected by a read byte format.

5.5.2 Stepper Motor Control

A stepper-motor is not like a normal motor that runs on direct current. It does not move

continuously but rather in small increments. A stepper-motor has two coils that are connected to

four inputs as shown in figure below. Each small increment that the motor turns is produced by

energizing one of the two coils. The next increment is created by a energizing the other coil. If

the motor needs to turn in the opposite direction, then the each state of the coils must be

implemented in reverse order, that is the coil must be energized with reverse polarity.

There are several designs of stepper motors. A unipolar stepper motor is really two

motors sandwiched together. Each motor is composed of two windings. Wires connect to each of

the four windings of the motor pair, so there are eight wires coming from the motor. The

commons from the windings are often ganged together, which reduces the wire count to five or

six instead of eight.

Hardware interfacing: As the operating voltage of the Stepper Motor is 5V and the VCC of

MSP is only 3V, MSP cannot generate the required current to run both the motors. So Separate

power source with a VCC of 5V is used for this. To limit the current flow between MSP and

Stepper motor, ULN2803 is used as an interface. For port multiplexing 74HC595 shift register is

used between ULN2803 and MSP430.

5.5.2.1 STEPPER MOTOR DRIVER CIRCUIT:

The stepper motor cannot be directly driven using the MCU I/O pins as the MCU cannot supply

the required current to drive the Stepper Motor. Also, the Stepper Motor will cause a Back EMF

in the circuit while it is accelerating or decelerating. This can cause to MCU to be damaged.

Hence we use a Driver circuit which isolates the Stepper Motor circuit from the MCU circuit.

The driver circuit must be able to withstand the current required by the stepper motor. For this

purpose, we intend to use darlington arrays to isolate the MCU from the Stepper Motor and to

provide the current required for the Stepper Motor.

5.5.2.2 NUMERIC KEYPAD:

The Numeric keypad used is a 4x4 matrix keypad. This keypad is used to first select the mode of

operation – position or speed control and then is used to enter the required value of position or

speed respectively. There will be a Start/Stop button to enable the user to stop the motor before

changing modes. In this application, a 4x4 matrix keypad requiring eight Input/Output ports for

interfacing with the microcontroller. Rows are connected to Peripheral Input/Output (GPIO) pins

configured as output. Columns are connected to GPIO pins configured as input with interrupts.

The corresponding hexadecimal value of the pressed key is sent onto the LEDs.

After debouncing is completed, a detailed scan is executed. A second fast scan is done to

assure that any detection made during the first fast scan stage was valid. Then, rows are

configured as inputs. When a key is pressed a high level is applied in the corresponding row.

Hardware Interfacing : Interfacing of keypad to MSP is straightforward. Port2 of MSP is

exclusively used for this. Port 2, pins 0 to 3 were used as output to columns and port 2, pins 4 to

7 were used as input from rows

5.5.2.3 DISPLAY:

A seven segment display, as its name indicates, is composed of seven elements. Individually on

or off, they can be combined to produce simplified representations of numbers. The magnitude of

the speed or the value of the position is shown to the user by means of an LED display. The

magnitude of speed is proportional to the number of LED‘s in active state. A Seven Segment

LED display can also be used in place of the LED bar display without much change in the

circuit.

Hardware interfacing: Interfacing of seven segment Display with MSP430 is done through

74HC595 shift register which is used for port multiplexing.

5.5.2.4 SOFTWARE INTERFACING:

The software interfacing is mainly segregated into three parts:

1.Motor control

2.Display

3.Keypad

Brief procedure:

1. Initially the values are entered inputed from the keypad. The values entering will be

individual speed/position of each motor and the third selection will be mode seltion i.e.

the speed or position control.

2. The values are stored into the registers now and then are redirected to the LED diplay

segments to display the values entered via the keypad.

3. Now based on the mode selected motor operation takes place

Motor:

The values thus entered from the keypad are stored in the registers and are now used to calculate

the no: steps if the motor mode off operation is selected as position control, and if the mode of

operation is selected as speed control then the delay between the steps are calculated. The values

thus calculated are now sent into the respective motor sub-routine which now generate the

required stepping sequence to drive the motor according to the input configurations. The function

that is supposed to generate the values takes in the direction and speed as input and generates the

delay that has to be inserted between pulses and the amount of steps the motor has to rotate.

Display:

The seven segment display is used as out displaying device. For the display in the coding part

based on the appropriate number selection is checked using a switch function and the matched

data is sent out to the display corresponding to the number. These are represented in the decimal

form in the code.

Keypad:

For the keypad function we are mainly using he functions keypad(), keyeyfind(). The keypad

function is used too identify which keys are inputed on the keypad and the corresponding key

value is written into the function for the further proceedings i.e. the identification of the mode

and the steps that the motor has to run according to the inputed values on the keypad. This whole

operation is determining which key has gone high is identified by the keypad function.

5.5.3 Traffic Light Control

A traffic signal is typically controlled by a controller inside a cabinet mounted on a concrete pad.

Although some electro-mechanical controllers are still in use (New York City still has 4,800),

modern traffic controllers are solid state. The cabinet typically contains a power panel, to

distribute electrical power in the cabinet; a detector interface panel, to connect to loop detectors

and other detectors; detector amplifiers; the controller itself; a conflict monitor unit; flash

transfer relays; a police panel, to allow the police to disable the signal; and other components.

1. Fixed Time Control: The simplest control system uses a timer (fixed-time): each phase

of the signal lasts for a specific duration before the next phase occurs; this pattern repeats

itself regardless of traffic. Many older traffic light installations still use these, and timer-

based signals are effective in one way grids where it is often possible to coordinate the

traffic lights to the posted speed limit. They are however disadvantageous when the

signal timing of an intersection would profit from being adapted to the dominant flows

changing over the time of the day.

2. Dynamic Control: Dynamic, or actuated, signals are programmed to adjust their timing

and phasing to meet changing traffic conditions. The system adjusts signal phasing and

timing to minimize the delay of people going through the intersection. It is also

commonplace to alter the control strategy of a traffic light based on the time of day and

day of the week, or for other special circumstances such as a major event causing unusual

demand at an intersection.

The controller uses input from detectors, which are sensors that inform the

controller processor whether vehicles or other road users are present, to adjust signal

timing and phasing within the limits set by the controllersprogramming. It can give more

time to an intersection approach that is experiencing heavy traffic, or shorten or even skip

a phase that has little or no traffic waiting for a green light. Detectors can be grouped into

three classes: in-pavement detectors, non-intrusive detectors, and detection for non-

motorized road users.

5.5.3.1 Working Program

Design of a microprocessor system to control traffic lights. The traffic light arrangement is as

shown in Fig. The traffic should be controlled in the following manner.

1. Allow traffic from W to E and E to W transition for 20 seconds.

2. Give transition period of 5 seconds (Yellow bulbs ON)

3. Allow traffic from N to 5 and 5 to N for 20 seconds

4. Give transition period of 5 seconds (Yellow bulbs ON)

5. Repeat the process.

5.5.3.2 Source Program:

MVI A, 80H: Initialize 8255, port A and port B

OUT 83H (CR): in output mode

START: MVI A, 09H

OUT 80H (PA): Send data on PA to glow R1 and R2

MVI A, 24H

OUT 81H (PB): Send data on PB to glow G3 and G4

MVI C, 28H: Load multiplier count (40ıο) for delay

CALL DELAY: Call delay subroutine

MVI A, 12H

OUT (81H) PA: Send data on Port A to glow Y1 and Y2

OUT (81H) PB: Send data on port B to glow Y3 and Y4

MVI C, 0AH: Load multiplier count (10ıο) for delay

CALL: DELAY: Call delay subroutine

MVI A, 24H

OUT (80H) PA: Send data on port A to glow G1 and G2

MVI A, 09H

OUT (81H) PB: Send data on port B to glow R3 and R4

MVI C, 28H: Load multiplier count (40ıο) for delay


MVI A, 12H

OUT PA: Send data on port A to glow Y1 and Y2

OUT PB: Send data on port B to glow Y3 and Y4

MVI C, 0AH: Load multiplier count (10ıο) for delay


JMP START

5.5.3.3 Delay Subroutine:

DELAY: LXI D, Count: Load count to give 0.5 sec delay

BACK: DCX D: Decrement counter

MOV A, D

ORA E: Check whether count is 0

JNZ BACK: If not zero, repeat

DCR C: Check if multiplier zero, otherwise repeat

JNZ DELAY

RET: Return to main program

REVIEW QUESTIONS

1. Explain the concept of interfacing?

2. What do you mean by interfacing of input and output device?

3. Explain input/output mapping.

4. Describe Peripheral Interface Adapter PIA.

5. Discuss the various interrupts in 8085.

6. What are the various ports.

7. What do you mean by temperature Controller?

8. Explain the working of temperature controller.

9. Explain stepper motor control.

10. Explain Traffic Light Control.

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Basics electronics microprocessor