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By, J.Sheela Arokia Mary

Acceleration of stochastic algorithm on fpga system

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Page 1: Acceleration of stochastic algorithm on fpga system

By,

J.Sheela Arokia Mary

Page 2: Acceleration of stochastic algorithm on fpga system

Simulation of stochastic model like SIR model isvery useful. However, the software simulation ofthis kind of model becomes so slow with theindividual number increasing, so this projectprovides a much faster hardware solution for it.

A simulation is implemented on MATLAB to testand verify the mathematical algorithm

The final project is implemented on DE-115 boardusing Verilog, which gives a much fasterperformance than on PC

To make the Verilog code more flexible andvariable, a MATLAB program is designed toautomatically generate the Verilog code

Page 3: Acceleration of stochastic algorithm on fpga system

In SIR model, each individual has to be one of thethree stages: S(Susceptible), I(Infectious) orR(Recovered)

Once the individual is recovered, it can’t beinfected again

We can abstract the real world local relationshipnetwork to a simplified one, where each individualis connected to all the closely related ones, whichmeans they can infect others through connections

Initially, one or several individuals are set to beinfectious and the transition rates(possibility forinfecting and recovering) are fixed

Page 4: Acceleration of stochastic algorithm on fpga system

If we observe the number of individuals ofeach state, assuming all the individuals arerandomly connected, we should expect atheoretical result as below

The green one, which indicates the number ofinfected individuals, is the data that weobserve in the actual simulation

Page 5: Acceleration of stochastic algorithm on fpga system
Page 6: Acceleration of stochastic algorithm on fpga system

Instead of solving the problem in continuousdomain, we use discrete domain which iscompatible with hardware system. Moreover,we use a uniform time step for simulation,which lead to a fixed infecting and recoveringprobability for every step.

The most important component for this projectis a high performance random numbergenerator(RNG). In this case, we use a 64-bitXOR feedback shift register as the RNG, whichis easy to implement in FPGA

Page 7: Acceleration of stochastic algorithm on fpga system

Since we need a easily changeable code forimplementing, a MATLAB program is designedwith which users can change just the parametersand get auto-generated Verilog code.

If SIR cell is in S state, any connected infectedindividual could infect it with specified randomnumber

If SIR cell is in I state, it could recover withspecified random number

P_StoI and P_ItoR are fixed based on parameters, ifRNG gives out a number less than fixed P, thecomparer gives out 1 which enables the next stage.

Page 8: Acceleration of stochastic algorithm on fpga system

First of all, we test the algorithm in MATLABsimulation

MATLAB simulation gives out a similar resultas theoretical one which has a sharp rising anda slow decaying.

If we double the possibility for both infectingand recovering, the shapes of the figures staysimilar but the time steps decrease a half,which shows the validation of the algorithm

Page 9: Acceleration of stochastic algorithm on fpga system

For verification, there are three steps: First, with the same RNG, FPGA and MATLAB

should give out exactly same results, which provesthe Verilog code authentic

Second, test the RNG that we used, especiallycompare it with the MATLAB rand() functionwhich we assume is good enough

Last, repeat the simulation on FPGA, with thesame seeds for RNG, the result should not change

To examine the FPGA version, we build a sameRNG on MATLAB and give them the same seedsas FPGA. Also, setting a smaller group ofindividual makes it easier to identify them

Page 10: Acceleration of stochastic algorithm on fpga system

We designed a hardware solution to accelerate thesimulation for SIR model and implemented it on AlteraDE2-115 board

MATLAB simulation was introduced to validate themathematical algorithm for the simulation

Verilog code was automatically generated from a MATLABprogram which made it easier to change the parameters

We used a 64-bit XOR feedback shift register as randomnumber generator in FPGA and prove it to be good enoughfor simulation

Verilog code was verified by comparing to the MATLABversion with the same RNG

The final implementation was stable during repeats The hardware solution gave a 5000 times better speed with

120 individuals than software

Page 11: Acceleration of stochastic algorithm on fpga system

1]A. Hoogland, J. Spaa, B. Selman and A.Compagner, A special-purpose processor forthe Monte Carlo simulation of ising spinsystems, Journal of Computational Physics,Volume 51, Issue 2, August 1983, Pages 250-260

[2]http://www.cse.wustl.edu/~jain/cse567-08/ftp/k_27trg.pdf

[3]http://en.wikipedia.org/wiki/Compartmental_models_in_epide miology