The MATRICs RF-FPGA in 180nm SiGe-on-SOI BiCMOS Lawrence J. Kushner, Kevin W. Sliech, Gregory M. Flewelling, Joseph D. Cali, Curtis M. Grens,
Steven E. Turner, Douglas S. Jansen, Joseph L. Wood, and Gary M. Madison1 BAE Systems, Nashua, NH
1BAE Systems, Lexington, MA Abstract—MATRICs (Microwave Array Technology for Reconfigurable Integrated Circuits) is a DC-to-20 GHz general purpose reconfigurable array of RF circuits embedded in a flexible switch fabric. Fabricated in a commercial SiGe-on-SOI BiCMOS process, the MATRICs IC employs SiGe HBTs for high-linearity (> + 10 dBm IIP3) amplification and low phase-noise frequency generation, and SOI FETs for low-loss switching. It achieves high on-chip RF isolation (>80 dB at 16 GHz) due to the high-resistivity SOI substrate, differential signalling, and chip-scale flip-chip bump packaging. MATRICs will allow fixed-function RF systems to have the size, weight, and power benefits of a custom RF ASIC without the associated long development cycle and high NRE, and enable future RF subsystems to be dynamically reconfigured on-the-fly, adapting to changing environments.
Index Terms— RF-FPGA, reconfigurable, switch matrix, N-path filter, SiGe-on-SOI BiCMOS, PLL.
I. INTRODUCTION Much of the commercial RFIC industry is driven by
high-volume applications such as mobile phones and portable computing, where low per-unit cost and low dc power consumption are achieved by developing full-custom system-on-chips (SoCs) in advanced CMOS process nodes. These SoC development efforts require large engineering teams, and have multi-million dollar
fabrication costs due primarily to the fine-geometry CMOS mask expense.
In contrast, many military systems require ASIC size and weight, but do not require a large number of units and therefore cannot amortize the expense of custom ICs in fine-geometry CMOS. Still, raw performance is critical, as military systems must operate in hostile RF environments, so linearity, spectral purity, and interference rejection are of utmost importance. The MATRICs RF-FPGA IC described in this paper, fabricated in a commercial 180nm SiGe-on-SOI process [1], seeks to address these demanding requirements across a wide range of applications while minimizing non-recurring engineering (NRE) expense.
II. MATRICS RF-FPGA ARCHITECTURE Analogous to a digital FPGA, the MATRICs RF-FPGA
contains an array of reconfigurable RF blocks embedded in a flexible switch fabric (Fig. 1). Amplification, filtering, frequency conversion, and frequency generation are all included on the MATRICs IC, along with on-chip digital control and state memory. Unused blocks can be powered off and bypassed. Individual blocks have many (50 to 100) bits of fine-grained control, allowing gain, BW, linearity, center frequency, etc. to be adjusted statically,
Fig. 1. MATRIC V2 Architecture
I
SW
Microwave(IN)
LOB
SW
RF (IN/OUT)
RF (IN)
RF (OUT)
Baseband (OUT)
Baseband (IN)
I
I Q
I
Q
I Q
Baseband TIA (Out)
Baseb
and
TIA(O
ut)
SW SW
SWSW SW SW
RF (IN/OUT)
RF (IN/OUT)
SW SW
LOA
LO
Sele
ctio
n
SPI
...
MW
(IN
)
RF(IN)
MW (OUT)
RF (OUT)
AB
MicrowaveBlock
LO
Sele
ctio
n
SPI
...
MW
(IN
)
RF(IN)
MW (OUT)
RF (OUT)
AB
MicrowaveBlock
RF (IN/OUT)
RF (IN/OUT)
Microwave(IN)
Microwave(IN/OUT)
Microwave(IN/OUT)
Baseband TIA (Out )
I
Q
Baseband TIA (Out)
Baseband TIA (Out)
RF (IN/OUT)
Baseband (OUT)
Baseband (IN)
I QI Q
RF (IN/OUT)
RF (IN/OUT)
Microwave(OUT)
Microwave(OUT)
QB
aseband
TIA
(Out)
QBa
seb
and
TIA
(Ou
t)B
aseb
and
TI
A(O
ut)
Reference(IN)
LOBLOA
BC
D
RF / BasebandBlock
SPI
...
N-Phase LO Generator
LNA
LNAHPF0.2- 2GHz
BW
Not ch0.2-2GHz BW
0-15dB
1.8VLDO
2nd Order LPF
DAC I
Q
gmgm
Slice A8b
Down Converter
5 –1000 MHz BW, 15dB Gain
TIA
UpConverters
BB I/ Q Currents
(IN)
BB I/ Q Currents
(IN)
BB I/ Q Currents
(OUT)
BB I/ Q Currents
(OUT)
2nd Order LPF
2nd Order LPF
BB Q
(OUT)
BB I (O
UT)
RF(OUT)
RF (IN)
LO A
LO B
CM Feedback f or gm st ages
From BBInterconnect
÷ 4 |÷ 8
÷4
Input Stage
Skew AdjustmentDAC8b
Synchronization
LO
LORFBB
RF BBLO
RFBB
Q
I
BC
D
RF / BasebandBlock
SPI
...
N-Phase LO Generator
LNA
LNAHPF0.2-2 GHz
BW
Not ch0.2-2GHz BW
0- 15dB
1.8VLDO
2nd Order LPF
DAC
I
Q
gmgm
Slice A8b
Dow n Converter
5 – 1000 MHz BW , 15dB Gain
TIA
U pConverters
BB I/ Q Currents
(IN)
BB I/ Q Currents
(IN)
BB I/ Q Currents
(OUT)
BB I/ Q Currents
(OUT)
2nd Order LPF
2nd Order LPF
BB Q
(OUT)
BB I (OUT)
RF(OUT)
RF ( IN)
LO A
LO B
CM Feedback f or gm st ages
From BBInterconnect
÷ 4 |÷ 8
÷ 4
Input Stage
Skew A djustmentDAC8b
Synchr onization
LO
LORFBB
RF BBLO
RFBB
Q
I
BC
D
RF / BasebandBlock
SPI
...
N-Phase LO Generator
LNA
LNA HPF0.2-2GHz
BW
Not ch0.2-2GHz BW
0-15dB
1.8VLDO
2nd Order LPF
DACI
Q
gmgm
Sli ce A8b
Down Converter
5 – 1000 MHz BW, 15dB Gain
TIA
UpConverters
BB I/ Q Currents
(IN)
BB I/ Q Currents
(IN)
BB I/ Q Currents
(OUT)
BB I/ Q Currents
(OUT)
2nd Order LPF
2nd Order LPF
BB Q
(OU
T)BB
I (O
UT)
RF(OUT)
RF (IN)
LO A
LO B
CM Feedback f or gm st ages
From BBInt erconnect
÷ 4 |÷ 8
÷4
Input Stage
Skew Adjust ment DAC 8b
Synchronization
LO
LORF BB
RFBBLO
RF BB
Q
I
BC
D
RF / BasebandBlock
SPI
...
N-Phase LO Generator
LNA
LNA HPF0.2- 2GHz
BW
Not ch0.2- 2GHz BW
0-1 5dB
1.8VLDO
2nd Order LPF
DACI
Q
gmgm
Slice A8b
Down Converter
5 –1000 MHz BW, 15 dB Gain
TIA
U pConverters
BB I/ Q Currents
(IN)
BB I/ Q Currents
(IN)
BB I/ Q Cu rrents
(OUT)
BB I/ Q Cu rrents
(OUT)
2nd Order LPF
2nd Order LPF
BB Q
(OUT
)BB
I (O
UT)
RF(OUT)
RF (IN)
LO A
LO B
CM Feedback for gm st ages
From BBInt erconnect
÷ 4 |÷ 8
÷ 4
Input Stage
Skew Adjustment DAC 8b
Synchron ization
LO
LORF BB
RFBBLO
RF BB
Q
I
LO
Selection
SPI
... MW
(IN
)
RF(IN)
M W (OUT)
RF (OUT)
AB
MicrowaveBlock
M IXORAM P
MIXO
RAM
P
DarlingtonCascodeDarlington
Cascode
1.8VLDO
LO Selection
SPI
... MW
(IN
)
RF(IN)
M W (OUT)
RF (OUT)
AB
MicrowaveBlock
M IXORAM P
MIXO
RAM
P
DarlingtonCascodeDarlington
Cascode
1.8VLDO
Configurable Frequency Generator SPI
...
1.8VLDO
Reference (IN)
& State M emory
÷ 2 | ÷ 4 | ÷ 8
10 .0 – 1 3.0 GHz
1 2.6 – 15.2 GHz
14.8 – 17 .9 GHz
1 7.4 – 2 1.6 GHz
Phase Coherent S?M odulator
÷ 2K
SRetimeWord
Fractional Divide WordInteger Divide Word
PhaseDetector
÷ Integer N(EMM D)
CMOSCounter
RF(OUT)
- +
1b TuningVoltageCheck
4b VCO CoarseTuning
20
12
41212
DAC
Divided Frequency
(fDIV)
VCOBank
TunableN otchFilter
TunableLoopFilter (fREF)
7b Tuning Voltage
2b VCOSelect
OutputBuffer
FDC Word
91 1
K=0,1,…,9
9M SB
1
Configurable Frequency GeneratorSPI
...
1.8VLDO
Reference (IN)
& State M emory
÷ 2 | ÷ 4 | ÷ 8
1 0.0 – 13.0 GHz
12.6 – 15 .2 GHz
14.8 – 17.9 GHz
1 7.4 – 2 1.6 GHz
Phase Coherent S?Modulator
÷ 2K
S RetimeWord
Fractional Divide W ord In teger Divide Word
PhaseDetector
÷ Integer N(EMM D)
CM OSCounter
RF(OUT)
-+
1b TuningVoltageCheck
4b VCO CoarseTuning
20
12
4 12 12
DAC
Divided Frequency
(fDIV)
VCOBank
TunableN otchFilter
TunableLoopFilter(fREF)
7b TuningVoltage
FDC Word
2b VCOSelect
OutputBuffer
9
11
K=0,1,…,9
M SB
1
ConfigurableFrequency Generator
1 MHz to 20 GHz
CFGCFG
RF/BasebandDC to 6 GHz
RF/BB
RF/BB
RF/BB
RF/BBMicrowave1 to 20 GHz
MW MW
MW MW
PREPRESS PROOF FILE CAUSAL PRODUCTIONS1
after power-up, or dynamically, for on-the-fly reconfiguration. Similarly, the switch fabric interconnecting the blocks is also controlled by local, per-block, SPI and state memory.
Two generations of MATRICs RF-FPGAs have been developed along with additional test chips containing individual block break-outs (Fig. ). The full-up MATRICs ICs contain four 1-to-20 GHz Microwave blocks (MW), four DC-to-6 GHz RF/Baseband blocks (RF/BB), and two
0.01-to-20 GHz Configurable Frequency Generator (CFG) blocks. Most RF and baseband signals are differentially routed on chip, with the higher-frequency signals distributed by differential 100Ω grounded CPW transmission lines. Local Oscillator (LO) signals generated by the CFGs employ open-collector CML gates with load-side-only terminations (to save DC power while maximizing signal swing). Wherever signals cross, shielded RF cross-unders are employed to maintain isolation, with greater than 80 dB of isolation demonstrated at 16 GHz (in the MATRICs V1 chip). While the test chips are designed for wafer-probe, the MATRICs die are bumped and flip-chip mounted, providing low-impedance power supplies, low-parasitic RF connections, and superior RF isolation.
III. BLOCK DESIGN AND PERFORMANCE Design and performance of the Microwave and
RF/Baseband blocks are included in this section. The Configurable Frequency Generator has been submitted separately for publication [2] and is not discussed here.
A. Microwave Block (MW) The MATRICs V2 chip (and Test V2 chip) includes a
multi-function 1-to-20 GHz Microwave block (Fig. 3). In addition to amplification and frequency conversion, the Microwave block acts as an active 4-way switch, routing signals between adjacent blocks. The MW block has two inputs and two outputs: DC-to-6 GHz input and output, designed to interface with adjacent RF/Baseband blocks, and 1-to-20 GHz microwave input and output, designed to interface with other MW blocks or off-chip signals. The input stages of the MW block employ a Darlington feedback configuration for wideband, linear operation. The outputs of these input stages converge at a common-node in the center of the MW block, before exiting the MW block through one of two MIXORAMP output stages. As the name implies, the MIXORAMP stages can be configure as amplifiers or up/down conversion mixers.
At any given time, only one input stage and one output stage are powered up, with the off stages acting as active isolators. The “vertical” microwave path has a minimum
a. Test V1 (5x5mm2) b. MATRICs V1 (5x5mm2) c. Test V2 (5x5mm2) d. MATRICs V2 (8x10mm2) Fig. 2. First- and second-generation MATRICs RF-FPGA ICs.
Fig. 3. Microwave block (Test V2 IC)
Microwave SwitchesRF/BB
CFG 1
CFG 2
Microwave Amp
Tunable notch
Cal standards
Microwave Block
RF/BB Front-end
Baseline CFG
Experimental CFG
RF / BB RF / BB
RF / BB RF / BB
CFG CFG
MW MW
MW MW
2
of 70 dB on/off ratio to 15 GHz (Fig. 4a), while the “horizontal” RF path has better than 40 dB of on/off ratio out to 6 GHz (Fig. 4b). These ON/OFF ratios compare quite favorably to most passive switch designs.
Signals may also enter the (left) RF input and exit through the (top) MW output, or enter the (bottom) MW input and exit the (right) RF output. Noise figure remains under 9 dB in any of these amplifier configurations. As a mixer, the MW block conversion gain is between 8 to 15
dB (depending upon the frequencies at the 3 ports), with a noise figure between 12 and 13 dB.
B. RF/Baseband Block (RF/BB) The DC-to-6GHz RF/Baseband block (Fig. 5) performs
RF amplification and filtering, down-conversion, baseband gain and filtering, upconversion, and signal routing. The input stage of the RF/BB is reconfigurable, with switchable gain and RF filtering, and can be bypassed for high-linearity mixer-first operation.
The middle stage of the RF/BB block can be configured for 4-path I/Q or 8-path harmonic-reject downconversion, or bypassed entirely. Its SiGe HBT CML-based N-phase LO generator allows the RF/BB block to achieve outstanding 3rd- and 5th-harmonic rejection in 8-path mode (Fig. 6), at the expense of DC power. For narrow-band applications, or operation above 3 GHz, 4-path mode can be used, reducing the DC power significantly.
The RF/BB block performs filtering both at RF and baseband. As a direct-downconversion receiver, the RF/BB block’s N-path filtering tracks the LO frequency and can therefore be tuned precisely by tuning the LO.
The output stage of the RF/BB block provides further gain and filtering, and can also be configured to perform I/Q upconversion. Multiple RF/BB blocks may be cascaded either at RF or at baseband to achieve additional gain and filtering.
Table I compares the RF/Baseband block (in downconversion mode) to recent research results of similar N-path or harmonic-reject receivers. The MATRICs chips reported here operate over a much wider range of instantaneous bandwidths and achieve superior in-band (IB) and out-of-band (OOB) linearity. This level
a. MW-to-MW gain and isolation
b. RF-to-RF gain and isolation
Fig. 4. Microwave block as amplifier or switch. MW: 1 to 20 GHz; RF: DC to 6 GHz
Fig. 5. DC-to-6 GHz RF/Baseband Block (MATRICs V2)
0 5 10 15 20 25 30-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
Frequency (GHz)
Gai
n (d
B)
ON - measuredON - simulatedOFF - measuredOFF - simulated
> 70 dB
ON
OFF
0 5 10 15 20 25 30-60
-50
-40
-30
-20
-10
0
10
20
30
Frequency (GHz)
Gai
n (d
B)
ON - measuredON - simulatedOFF - measuredOFF - simulated
> 40 dB
ON
OFF
of performance was achieved primarily by employing SiGe HBTs, which results in significantly higher power consumption compared with the other research results.
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ACKNOWLEDGMENT This research was developed with funding from the
Defense Advanced Research Projects Agency (DARPA), under the guidance of Drs. Roy Olsson and William Chappell, and Chris Lesniak of AFRL. The views, opinions, and findings contained in this paper are those of the authors and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. Approved for Public Release on 1/8/15, Distribution Unlimited. “Non-Technical Data” - Releasable to Foreign Persons.
The authors would like to acknowledge Michael Scott , Scott Jordan, Edward Preisler, and the TowerJazz team for developing the SBC18H3B SiGe-on-SOI process, and thank them for their continued support.
REFERENCES [1] E. Priesler, J. Zheng, S. Chaudhry, Z. Yan, M. Qamar, and
M. Racanelli, “Adaptability of a 280GHz SiGe BiCMOS Process for High Frequency Commercial Applications,” Proc. CSICS 2012
[2] J. Cali, et. al., “20-GHz PLL-based Configurable Frequency Generator in 180nm SiGe-on-SOI BiCMOS,” submitted to RFIC 2015.
[3] C. Andrews and A. Molnar, “A passive mixer-first receiver with digitally controlled and widely tunable RF interface,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2696–2708, Dec. 2010.
[4] C.-Y. Yu, I. Lu, Y.-H. Chen, L.-C. Cho, C. Sun, C.-C. Tang, H.-H. Chang,W.-C. Lee, S.-J. Huang, T.-H. Wu, C.-S. Chiu, and G. Chien, “A SAW-less GSM/GPRS/EDGE receiver embedded in 65-nm SoC,”IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3047–3060, Dec. 2011.
[5] D. Murphy, H. Darabi, A. Abidi, A. A. Hafez, A. Mirzaei, M. Mikhemar, M.-C. Frank Chang, "A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications," IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2943-2963, Dec. 2012.
[6] J. Borremans , G. Mandal , V. Giannini , B. Debaillie , M. Ingels , T. Sano , B. Verbruggen and J. Craninckx, “A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers,” IEEE J. Solid-StateCircuits, vol. 46, no. 7, pp. 1659-1670, July 2011.
[7] R. Chenand H. Hashemi, “A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing,” IEEE J. Solid-StateCircuits, vol. 49, no. 5, pp. 1097-1111, May 2014.
[8] I. Fabiano, M. Sosio, A. Liscidini, R. Castello, “SAW-Less Analog Front-End Receivers for TDD and FDD,” IEEE J. Solid-StateCircuits, vol. 48, no. 12, pp. 3067-3079, Dec. 2013.
Fig. 6. RF/Baseband block harmonic rejection in 8-path mode, with on-chip pre-filter set to ~ 2 GHz. Measured in Test V1 IC.
1Measured 2Simulated
0 1 2 3 4 5 6 7 8-140
-120
-100
-80
-60
-40
-20
0
RF Frequency (GHz)
Har
mon
ic P
ower
(dB
c)
3x35x5
7x7
MeasuredModeled
1x1desired
Receivertuned to
1 GHz
[3] [4] [5] [6] [7] [8] This workMATRICs V11
This workMATRICs V22
Technology 65nm CMOS 65nm CMOS 40nm CMOS 40nm CMOS 65nm CMOS 40nm CMOS SiGe-on-180nm SOI CMOS
Frequency (MHz) 100 - 2400 850, 900, 1800, 1900 80 - 2700 400 - 6000 500 - 3000 1800 - 2400 20 - 6000
Instantaneous BW (MHz) 1 4 2 1.5 to 20 8 to 57 (?) 1 20 - 1500 10 - 2000
3rd/5th Harmonic Reject. (dB) 35-43 (<500MHz) 44/? 42/45 none 46/51 54 / 65 60/70 (8-path, with on-chip tunable pre-filter, <3 GHz)
Image Rejection (dB)(un-calibrated)
- - - - - - > 48 dB over 20 MHz BW> 40 dB over 1 GHz BW
Max Gain (dB) 70 60 72 70 35 45 45 dB per RF/BB
NF (dB) 7 2.9 2 - 12 3-9, LNA 1st
7-15, mix 1st5.5 – 8.8 2 – 3.5 10 - 12.5, LNA 1st
15 to 21, mix 1st
IB IIP3 (dBm) < -40 0 < -20 +6 -12 - -5 , LNA-1st
+5, mix-1st+6, LNA-1st
+16, mix-1st
OOB IIP3 (dBm) +25 - +13.5 +10 +11 +18 +12 , LNA-1st
+28, mix-1st+20, LNA-1st
+35, mix-1st
OOB IIP2 (dBm) +56 +50 +54 +30 un-cal’d+70 cal’d
+46, un-cal’d
+64 +40 un-calibrated
Pblocker_OOB for CP-1dB (dBm) - +1 -2 -8 -1 0 -10 to + 7 TBD
Power Consumption (mW) 37-70 240 35-78 55 250 - 600 32 1000 to 1500 800 to 2000
Supply Voltages 1.2, 2.5 2.5 1.3 1.1, 2.5 1.2, 2.5 1.2, 1.8 1.8, 3.3
Active Area (mm2) 2 1.4 1.2 2 5.9 0.74 2.2 4.1
TABLE I
COMPARISON OF RF/BASEBAND BLOCK IN N-PATH DOWNCONVERSION MODE TO RECENT RESEARCH.
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