Instituto de Informática, Programa de Pós-Graduação em ComputaçãoUniversidade Federal do Rio Grande do Sul
Porto Alegre, Brazil
Porto Alegre, May 16, 2007
Low Overhead System Level Approaches
for Mitigation of Long Duration
and Multiple Transient Faults
Thesis Proposalby Carlos Arthur Lang Lisbôa
Advisor: Luigi Carro
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 2
Outline
• Motivation• Proposal
• Related Work
• Previous Investigations
• Proposed Approach
• Future Tasks and Schedule
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 3
Single event, multiple effects[Rossi 2005 *]
[*] Multiple Transient Faults in Logic: An Issue for Next Generation ICs ?, Daniele Rossi et al, DFT 2005
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 4
Transient pulse width scalingacross technologies [Dodd 2004 *]
[*] Production and propagation of Single-Event Transients in High-Speed Digital Logic ICs, Paul Dodd et al, IEEE Transactions on Nuclear Science, Vol. 51 No. 6, Part2, December 2004
max.1.37 x
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 5
Propagation delay vs. technologies(*)
Technology (nm)* 180 130 90 32 180/32
10-inverter chain 508.4 157.8 120.2 79.6 6.39
(*) simulated using parameters from PTM web site and HSPICE tool
in out
clk clk
32 nm
90 nm
130 nm
180 nm
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 6
Cycle time x transient pulse scalingacross technologies
6.39 x
Transientwidth scaling:max. 1.37 x
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 7
Cycle time x transient pulse scalingacross technologies
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 8
Transient pulse width scalingacross technologies [Ferlet-Cavrois 2006 *]
[*] Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy Ion and Proton Irradiation, V. Ferlet-Cavoirs et al, IEEE Transactions on Nuclear Science, Vol. 53 No. 6, Part 1, Nov 2006.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 9
Cycle time x transient pulse scalingacross technologies
Data for 70 nm technology
[Ferlet-Cavrois 2006 *]
[*] Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy Ion and Proton Irradiation -Implications for Digital SETs, Ferlet-Cavrois et al, IEEE Tr. on Nuc. Sci., Vol. 53 No. 6, November 2006
Long duration transients !
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 10
4-bit ripple carry adder
a3 a2 a1 a0 b0b1b2b3
s3 s2 s1 s0s4
1 0 0 1 1 0 0 1
0 1 1 1 1
0 0 00
0 0 0
Fault model: long duration transients
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 11
a3 a2 a1 a0 b0b1b2b3
s3 s2 s1 s0s4
1 0 0 1 1 0 0 1
0 1 0 1 1
0 1 00
0 1 0
4-bit ripple carry adder
Fault model: long duration transients
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 12
a3 a2 a1 a0 b0b1b2b3
s3 s2 s1 s0s4
1 0 0 1 1 0 0 1
1 0 0 1 1
1 1 00
1 1 0
4-bit ripple carry adder
Fault model: long duration transients
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 13
Outline
• Motivation
• Proposal• Related Work
• Previous Investigations
• Proposed Approach
• Future Tasks and Schedule
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 14
Problem definition
♦ For future technologies, radiation inducedtransients pulses will last longer than thecycle time of circuits.
♦ Many current mitigation techniques, basedon time and/or space redundancy at lowlevel, will no longer be effective to cope witherrors due to those transients.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 15
The goal of this proposal
Development of system level
mitigation techniques to cope
with long duration transient
pulses and their effects
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 16
Outline
• Motivation
• Proposal
• Related Work• Previous Investigations
• Proposed Approach
• Future Tasks and Schedule
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 17
Time redundancy [Anghel 2000 *]
[*] Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, L. Anghel and M. Nicolaidis, in Proceedings of DATE 2000, March 2000
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 18
Time redundancy [Anghel 2000 *]
[*] Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, L. Anghel and M. Nicolaidis, in Proceedings of DATE 2000, March 2000
Increase delay ?⇒ Higher performance
penalty !!!
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 19
Time redundancy [Mitra 2005 *]
[*] Robust System Design with Built-in Soft Error Resilience, S. Mitra, IEEE Computer, V38, N2, February 2005
Reuses scan chain,but still relies on duration
of transient pulses.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 20
Space redundancy [Nieuwland 2006 *]
[*] Combinational Logic Soft Error Analysis and Protection, André Nieuwland et al, in Proceedings of IOLTS 2006, July 2006
Can not copewith long duration
transients !!!
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 21
Other proposed approaches
• Hardware based:• duplication and comparison
• checkers and I-IPs
• Software based:• duplication and comparison
• self-checking block signatures
• Hybrid: best features of SW and HW
High area and/or performanceoverheads !!!
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 22
Outline
• Motivation
• Proposal
• Related Work
• Previous Investigations• Proposed Approach
• Future Tasks and Schedule
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 23
MajorityLogic
Low costredundancy
Research Evolution - Overview
StochasticOperators
TMR andAnalogVoter
Bit StreamOperators
Use of Memory to Cope with Soft Errors
LongDuration
Transients
2004 2005 2006 2007
IOLTS 04
DFT 04WDES 04
LATW 06ETS 06
DFT 06
ETS 05SBCCI 05
ResearchReport
SRC 2005TechCon
ResearchReport
DATE 06PhD Forum
MemProc
DATE 07 ETS 07
ControlFlow ErrorDetection
LATW 07
OnlineHardening
Low CostChecker forMatrix Mult.
System levelapproaches
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 24
Research Approaches - 2004 / 2005
• Use of stochastic operators
• Use of bit stream operators
• Ensuring voter reliability to use n-MR
to cope with simultaneous faults -
cooperation
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 25
Research Evolution - 2004 / 2005
StochasticOperators
IOLTS2004
Stochastic multiplier circuit
1000100110011010
10010001000010111000000100001010
Stochastic Adder Circuit
01100010101
010111011001S1
S3
Sum
01010101101
0010100110101
S2
OK for s
ome
DSP
Applica
tions
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 26
DFT 2004WDES 2004
Look
ing fo
r
more sp
eed
StochasticOperators
Bit StreamOperators
Research Evolution - 2004 / 2005
A1 A0x B1 B0
B0.A1 B0.A0
B1.A1 B1.A0
p8 p7 p6 p5 p4 p3 p2 p1 p0
Conve
rsion
to
binar
y valu
e ?
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 27
Research Evolution - 2004 / 2005
Look
ing fo
r
more sp
eed
StochasticOperators
AnalogVoter
Bit StreamOperators
Looking for
tolerant converter
ETS 2005SBCCI 2005
Toler
ant to
multipl
e fau
lts in
n-MR so
lution
s
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 28
Research approaches - 2006 / 2007
• cooperation with peers• use of memory for computation
• analog voter + majority logic
• use of an I-IP to harden instructions
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 29
Research approaches - 2006 / 2007
• cooperation with peers• use of memory for computation
• analog voter + majority logic
• use of an I-IP to harden instructions
• low cost redundancy
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 30
Research approaches - 2006 / 2007
• cooperation with peers• use of memory for computation
• analog voter + majority logic
• use of an I-IP to harden instructions
• low cost redundancy
• system level approaches
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 31
Research Evolution - 2006
Use ofMemory
to Cope with Soft Errors
LATW 06ETS 06
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 32
MajorityLogic
Research Evolution - 2006
LATW 06ETS 06 DFT 06
Use ofMemory
to Cope with Soft Errors
AND gate OR gate inverter
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 33
Low costredundancy
MajorityLogic
Research Evolution - 2006
LATW 06ETS 06 DFT 06
Use ofMemory
to Cope with Soft Errors
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 34
Low costredundancy
OnlineHardening
MajorityLogic
Research Evolution - 2006
LATW 06ETS 06
DFT 06
DFT 06
Use ofMemory
to Cope with Soft Errors
µP
abus
cbus
dbus I - IP
error
IRQ
IRQ
abus
cbus
dbus
Code
Memory
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 35
Research Evolution - 2006 / 2007
Memory µPabus
cbus
dbus
errorI-IP
ControlFlow ErrorDetection
Low CostChecker forMatrix Mult.
Low costredundancy
LATW 07
LATW 07
Smaller I-IP,lower performanceoverhead, higher
efficacy
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 36
Research Evolution - 2006 / 2007
ControlFlow ErrorDetection
Low CostChecker forMatrix Mult.
Low costredundancy
LATW 07
LATW 07
C ← A * B
Cr ← C * rCrc ← C * rc
ABr ← A*(B*r)ABrc ← A*(B*rc)
output (C)
error
inputs (A, B)
Two timesFreivalds’ (25%), with 100%
detection probability
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 37
Research Evolution - 2006 / 2007
DATE 07
MemProc
ROM
RAM
MicrocodeMemory
PC
ALU
OperationMasks
Memory
ControlFlow ErrorDetection
Low CostChecker forMatrix Mult.
Low costredundancy
LATW 07
LATW 07
Smaller combinationallogic, with innovative add
and comparison ops
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 38
Low CostChecker forMatrix Mult.
Low costredundancy
Research Evolution - 2006 / 2007
System LevelApproaches
ETS 07(accepted)
LATW 07 DATE 07
MemProc
ControlFlow ErrorDetection
LATW 07
System levelapproaches
C ← A * B
Cr ← Σ CiABr ← A*(Σ Bi)
output (C)
error
inputs (A, B)
Much lower performanceand/or area overheads,
still with 100%detection probability
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 39
Outline
• Motivation
• Proposal
• Related Work
• Previous Investigations
• Proposed Approach• Future Tasks and Schedule
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 40
The goal of this proposal
Development of system level
mitigation techniques to cope
with long duration transient
pulses and their effects
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 41
Verification & Correction requirements
• Verification - very frequent
• much faster than computation
• low power consumption
• low area overhead (goal: ≤ 50%)
• Correction - very seldom (hours, weeks)
• performance is not the main issue
• static power consumption must be low or null
• low area overhead: desirable
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 42
Algorithmic level approachesVerification
Case study 1: sorting algorithm
keyi ≤ keyi+1, 1 ≤ i ≤ n-1
• verification requires only O(n) comparisons !
• low overhead verification mechanism
• best performance algorithms: O(n log n) operations
• intuitive verification condition at completion:
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 43
Algorithmic level approachesVerification
Case study 2: n × n matrix multiplication
• verification cost: O(n2) operations
• probability of error in verification: 50%
• multiplication cost: O(n3) operations
• Freivalds’ verification technique:
Cr ← C * rABr ← A*(B*r) Cr = ABr ?
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 44
Algorithmic level approachesVerification
Case study 2: matrix multiplication (cont.)
• verification cost: less than O(n2) operations
• probability of error in verification: 0%
• multiplication cost: O(n3) operations
• optimized Freivalds’ verification technique:
Cr ← Σ CiABr ← A*(Σ Bi)
Cr = ABr ?
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 45
Algorithmic level approachesVerification
Generalization of the approach• “keyi ≤ keyi+1, 1 ≤ i ≤ n-1” and “Cr = ABr”
are invariants at completion of the algorithms
• ideal solution: automated invariant determination (?)
• drawback: not every invariant is suitable:y=1;z=0;while z ~= x, z = z + 1; y = y * z;end
invariant: y = z! ⇒ high verification cost
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 46
Algorithmic level approachesError correction - main issues
• Recomputation
• Small control overhead: reuse of resources
• Must save initial state when start computation
• Power-off control circuit when not in use ?
• Circular buffer to cope with hard deadlines in
real-time systems ?
• Other (application specific) alternatives ?
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 47
Algorithmic level approachesHardware vs. software implementation
• Hardware implementation• requires access to HW description and modification
• not feasible when using COTS processors
• faster than software
• Software implementation• requires access to source code and modification
• implies memory overhead: instructions + variables
• slower than hardware
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 48
Algorithmic level approachesFuture research topics
• Invariants determination method⇒ generalization for other algorithms⇒ criteria for choice of best suited invariant
• Hardware vs. software implementation⇒ parameters for designers’ decision
• When to apply the verification mechanism ⇒ partial execution or at completion ?
• Efficient recomputation techniques
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 49
Outline
• Motivation
• Proposal
• Related Work
• Previous Investigations
• Proposed Approach
• Future Tasks and Schedule
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 50
1. Study of invariants2. Study of MP3 application3. Development of application specific techniques for MP34. Application of proposed techniques to MP3
and fault tolerance analysis5. Critical review of results, look for weak spots
and methods to cope with them
6. Comparison with arithmetic coding for mitigation of double errorsin arithmetic operators
7. Comparison with distance 6 Hamming codes for mitigation ofdouble errors in FSMs
8. Cooperation internship (Europe)9. Thesis writing10. Thesis presentation
2007 2008Task # May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
12345678910
Future Tasks and Schedule
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 51
Publications - already published
• Lisbôa, C. and Carro, L., “An Intrinsically Robust Technique for FaultTolerance Under Multiple Upsets”, 10th IEEE International Online TestSymposium - IOLTS 2004, IEEE Computer Society, Funchal, Madeira Island,Portugal, July 2004.
• Lisbôa, C. and Carro, L., “Highly Reliable Arithmetic Multipliers for FutureTechnologies”, in Proceedings of the International Workshop on DependableEmbedded Systems - WDES 2004 - in conjunction with the 23rd InternationalSymposium on Reliable Distributed Systems - SRDS 2004, pp. 13-18. Editedby Becker, L. B. and Kaiser, J., Florianópolis, October 17, 2004.
• Lisbôa, C. and Carro, L., “Arithmetic Operators Robust to MultipleSimultaneous Upsets”, in Proceedings of the 19th IEEE InternationalSymposium on Defect and Fault Tolerance in VLSI Systems - DFT 2004, pp.289-297, ISBN0-7695-2241-6. IEEE Computer Society, New York, October2004.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 52
Publications - already published
• Lisbôa, C. A. L., Carro, L. and Cota, E., “RobOps - Arithmetic Operators forFuture Technologies”, 10th European Test Symposium - ETS 2005, Tallin,Estonia, May 2005.
• Lisbôa, C. A. L., Schüler, E. and Carro, L., “Going Beyond TMR for ProtectionAgainst Multiple Faults”, in Proceedings of the 18th Symposium on IntegratedCircuits and Systems Design - SBCCI 2005, September 2005.
• Rhod, E.; Lisbôa, C. A. L. and Carro, L., “Using Memory to Cope withSimultaneous Transient Faults”, in Proceedings of the 7th Latin-AmericanTest Workshop - LATW 2006, pp. 151-156, IEEE Computer Society, NewYork, March 2006.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 53
Publications - already published
• Rhod, E.; Lisbôa, C. A. L.; Michels, Á. and Carro, L., “Fault Tolerance AgainstMultiple SEUs using Memory-Based Circuits to Improve the ArchitecturalVulnerability Factor”, in Informal Digest of Papers of the 11th IEEE EuropeanTest Symposium - ETS 2006, pp. 229-234, IEEE Computer Society, NewYork, May 2006.
• Michels, Á., Petroli, L., Lisbôa, C. A. L., Kastensmidt, F. and Carro, L. “SETFault Tolerant Combinational Circuits Based on Majority Logic”, inProceedings of the 21st IEEE International Symposium on Defect and FaultTolerance in VLSI Systems - DFT 2006, pp. 345-352, IEEE Computer Society,Los Alamitos, CA, October 2006..
• Lisbôa, C. A. L., Carro, L., Sonza Reorda, M., and Violante, M. “OnlineHardening of Programs against SEUs and SETs”, in Proceedings of the 21stIEEE International Symposium on Defect and Fault Tolerance in VLSISystems - DFT 2006, pp. 280-288, IEEE Computer Society, Los Alamitos, CA,October 2006.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 54
Publications - already published
• Lisbôa, C. A. L.; Erigson, M. I.; and Carro, L., “A Low Cost Checker for MatrixMultiplication”, in Informal Proceedings of the 8th IEEE Latin-American TestWorkshop - LATW 2007, Session 10, IEEE Computer Society TestTechnology Technical Council - TTTC, Cuzco, Peru, March 2007.
• Rhod, E. L.; Lisbôa, C. A. L.; Carro, L.; Violante, M.; and Sonza Reorda, M.,“A non-intrusive on-line control flow error detection technique for SoCs”, inInformal Proceedings of the 8th IEEE Latin-American Test Workshop - LATW2007, Sess ion 10, IEEE Computer Society Test Technology TechnicalCouncil - TTTC, Cuzco, Peru, March 2007.
• Rhod, E. L.; Lisbôa, C. A. L.; and Carro, L., “A Low-SER Efficient ProcessorArchitecture for Future Technologies”, in Proceedings of the Design,Automation and Test in Europe 2007 Conference - DATE 2007, IEEEComputer Society, Los Alamitos, CA, April 16-20, 2007, pp 1448-1453, ISBN978-3-9810801-2-4.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 55
Publications - accepted
• Lisbôa, C. A. L. and Carro, L., “System Level Approaches for Mitigation ofLong Duration Transient Faults in Future Technologies”, accepted forpresentation at the 12th European Test Symposium – ETS 2007, in Freiburg,Germany, May 20-24, 2007.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 56
Publications - under revision
• Petroli, L.; Lisboa, C. A. L.; Kastensmidt, F.; and Carro, L., “Majority LogicMapping for Soft Error Dependability”, accepted for publication in the specialissue for DFT 2006 of the Journal of Electronic Testing: Theory andApplications, subject to revisions, already re-submitted to the editor.
• Rhod, E.; Lisboa, C. A. L.; Carro, L., Violante, M.; and Sonza Reorda, M.,“Hardware and software transparency in the protection of programs againstSEUs and SETs”, accepted for publication in the special issue for DFT 2006of the Journal of Electronic Testing: Theory and Applications, subject torevisions, already re-submitted to the editor.
• Lisboa, C. A. L.; Kastensmidt, F.; Henes Neto, E.; Wirth, G.; and Carro, L.,“Using Built-in Sensors to Cope with Long Duration Transient Faults in FutureTechnologies”, submitted for the International Test Conference 2007, underreview.
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 57
Questions ?
Contact: [email protected]
Thank You !
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 59
Area comparison(*)
(thousands of gates)
Matrix width (n) 3 8 16 32
Size of multiplier 10.8 218.7 1,850.1 16,192.5
Size of checker 5.4 61.8 386.3 2,640.1
Checker areaoverhead (%) 50.0 28.3 20.9 16.3
☺DWC> 100%
TMR> 200%
(*) fully combinational circuit, using Quartus II tool
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 60
Time comparison in µs(*)
Matrix width (n) 3 8 16 32
Multiplication 1.94 25.94 184.98 1,350
Verification 0.50 2.90 10.90 40
Overhead (%) 25.8% 11.2% 5.9% 3.0%
(*) sequential circuit, 1120 lines of VHDL code, parameterized by n
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 61
Sequential circuit implementation
• implemented using VHDL• 1,120 lines of code• parameterized by n
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 62
Area comparison - FPGA usage(*)
Type ofcomponent
LogicElements
Registers
Multiplication 409 305
Verification 119 143
Overhead (%) 29.1% 46.9%
(*) sequential circuit, 1120 lines of VHDL code, parameterized by n
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 63
• when k = 2, if C ≠ A x B
the probability of Cr = ABr is ≤ ¼
• r: is a vector of randomly selected 1s and 0s
e.g.: r = [ 1 0 0 1 0 ... 0 1 1 1 0]
• rc: a vector in which rc[ i ] = 1 - r[ i ] (1s’ complement)
e.g.: rc = [ 0 1 1 0 1 ... 1 0 0 0 1]
Going beyond Freivalds’ technique
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 64
Σ,× ⇒C11 C12 C1n
C21 C22 C2n
Cn1 Cn2 Cnn
0
0
0
Crc 1
Crc 2
Crc n
... ... ...
...
...
...
...
... ...
= 0
Crc = C x rc(also for Brc)
rc
ABr ≠ Cr OR ABrc ≠ Crc
Crci = Ci1.rc1 + Ci2.rc2 + ... + Cin.rcn ⇒ Crci = 0because all rci = 0
Further optimizing the technique
Σ,× ⇒C11 C12 C1n
C21 C22 C2n
Cn1 Cn2 Cnn
1
1
1
Cr1
Cr2
Crn
... ... ...
...
...
...
...
... ...
= ABr1
Cr = C x r(also for Br)
r
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 65
Error correction - main issues
• Recomputation ⇒ small control overhead
• Must save initial state when start computation
• Power-off control circuit when not in use ?
• Circular buffer to cope with hard deadlines in
real-time systems ?
buffer out
buffercontrol
errordetector
maincircuit
Carlos A. L. Lisbôa Thesis Proposal - May 16, 2007 66
Time comparison - software(number of * and + operations)
Matrix width (n) 3 8 16 32
Multiplication 45 960 7,936 64,512
Verification 27 232 976 4,000
Overhead (%) 60% 24% 12% 6%