Sistemi Elettronici Programmabili 13-1
MULTI OSC+
CLOCK FILTER
LVD
POWERSUPPLY
CONTROL
8 BIT COREALU
PROGRAM MEMORY
RAM
I2C
PORT A
SPI
PORT B
16-BIT TIMER A
PORT C
8-BIT ADC
16-BIT TIMER B
WATCHDOG
INTERNALCLOCK
AD
DR
ES
S A
ND
DA
TA
BU
S
OSC1
OSC2
VDD
VSS
nRESET
PA7..0(8 bits)
PB7..0(8 bits)
PC5..0(6 bits)
ST7: Block Diagram
Sistemi Elettronici Programmabili 13-2
ST72254 - Package
Sistemi Elettronici Programmabili 13-3
ST72254 Memory Map
Sistemi Elettronici Programmabili 13-4
ST72254 – Interrupt Vector
Sistemi Elettronici Programmabili 13-5
ST
7225
4 R
egis
ters
(1)
Sistemi Elettronici Programmabili 13-6
ST
7225
4 R
egis
ters
(2)
Sistemi Elettronici Programmabili 13-7
ST72254 Registers (IO)
Sistemi Elettronici Programmabili 13-8
ST72254 Registers (Timer)
Sistemi Elettronici Programmabili 13-9
ST72254 Registers (ADC)
Sistemi Elettronici Programmabili 13-10
IO P
ort
: B
lock
Dia
gra
m
Sistemi Elettronici Programmabili 13-11
IO Port Configurations - Input
Sistemi Elettronici Programmabili 13-12
IO Port Configurations – Output Opendrain
Sistemi Elettronici Programmabili 13-13
IO Port Configurations – Output Push Pull
Sistemi Elettronici Programmabili 13-14
IO Port: Registers
Sistemi Elettronici Programmabili 13-15
ADC: Overview (1)
• 8-BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP TO 8
ANALOG CHANNELS
• FEATURE :
– Accuracy : 1 LSB
– Total Unajusted Error MAX : 1 LSB
– Conversion time : 24 CPU cycle ie 3µs at full speed (8MHz)
• FLAGS
– COCO : end of conversion (Status flag)
– ADON : ADC on/off bit (to reduce power consumption)
Sistemi Elettronici Programmabili 13-16
ADC: Overview (2)
• LOW CONSUMPTION MODES– Wait mode doesn't affect the ADC– Halt mode stops the ADC.
• HARDWARE– ST72334 and ST725xx : Vdda and Vssa must be connected
externally respectivelly to Vdd and Vss through decoupling capacitors.
– ST72254 : connection done internally
• RATIOMETRIC In the Functionnal Range– If analog voltage input > Vdd :
converted result = FFh (no overflow indication)– If analog voltage input < Vss :
converted result = 00h (no underflow indication)
Sistemi Elettronici Programmabili 13-17
ADC: Block Diagram
Sistemi Elettronici Programmabili 13-18
ADC: Registers
Sistemi Elettronici Programmabili 13-19
Tim
er:
Blo
ck D
iag
ram
Sistemi Elettronici Programmabili 13-20
Tim
er:
Blo
ck D
iag
ram
(H
)
Sistemi Elettronici Programmabili 13-21
Tim
er:
Blo
ck D
iag
ram
(L
)
Sistemi Elettronici Programmabili 13-22
Tim
er:
Rea
d S
equ
ence
Sistemi Elettronici Programmabili 13-23
Tim
er:
Inp
ut
Cap
ture
Sistemi Elettronici Programmabili 13-24
Tim
er:
Ou
tpu
t C
om
par
e
Sistemi Elettronici Programmabili 13-25
TIMER: PWM Mode
• Automatic generation of a Pulse Width Modulated signal
• Period &pulse lenght set by software: – The first Output Compare Register OC1R contains the length of
the pulse– The second Output Compare Register OCR2 contains the period
of the pulse
• Resolution up to 100 steps at 20 KHz (fCPU =4 MHz): 1% of accuracy on the duty cycle
t
T
Sistemi Elettronici Programmabili 13-26
Timer: PWM Flow
When the free running counter reaches
OC2R register value
When the free running counter reaches
OC1R register value
Free running counter is initialized to FFFCh
OLVL2 bit level is applied on the OCMP1 pin
ICF1 bit is set
OLVL1 bit level is applied on the OCMP1 pin
Sistemi Elettronici Programmabili 13-27
Timer: PWM Counter
OCMP1 Ouput Compare pinTimer output
FFFFh
Compare 1
0000h
Compare 2
FFFCh
Ttimer × 65535Tmax =
OLVL1=0
OLVL2= 1
FREE RUNNING COUNTER VALUE
time
time
Sistemi Elettronici Programmabili 13-28
Tim
er:
CR
1
Sistemi Elettronici Programmabili 13-29
Tim
er:
CR
2
Sistemi Elettronici Programmabili 13-30
Tim
er:
SR
Sistemi Elettronici Programmabili 13-31
Schmitt Trigger: Caratteristica Inverter
Sistemi Elettronici Programmabili 13-31t
t
Vin
Vout
Sistemi Elettronici Programmabili 13-32
Schmitt Trigger: Caratteristica
Vin
Vout
Sistemi Elettronici Programmabili 13-33
Schmitt Trigger: Inverter - Commutazioni Spurie
t
t
Vin
Vout
Sistemi Elettronici Programmabili 13-34
Schmitt Trigger: Commutazione
t
t
Vin
Vout