School of Microelectronic Engineering
EMT362: Microelectronic FabricationContact Technology For
The VLSI Process
Ramzan Mat AyubSchool of Microelectronic Engineering
School of Microelectronic Engineering
Lecture Objectives• Able to identify ALL back-end process modules from wafer cross section.
• Understand the important of ohmic contact and able to describe step by step ohmic contact formation.
• Understand the importance of contact resistance monitoring, extraction method and test structure.
• Understand the application of diffusion barrier layer
• Able to describe silicide and salicide processes.
School of Microelectronic Engineering
Main Process Modules (CMOS 1P2M 3.3V)1. Wells Formation2. Active Area Definition 3. Device Isolation (LOCOS)4. Vt Adjust5. Polygate Definition6. Source & Drain Formation7. Pre Metal Dielectrics Deposition (PMD)8. Contact Definition9. Metal-1 Deposition & Patterning10. Inter-Metal Dielectrics Deposition (IMD)11. Via Definition12. Metal-2 Deposition & Patterning13. Passivation14. Pad Definition
Full integration may require 300-500 process steps
FRONT END PROCESS(creating an electrically isolated devices)
BACK END PROCESS(connecting the devices to form the desiredcircuit function.)
Standard CMOS Process Flow
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Back-end Process Overview
School of Microelectronic Engineering
56. Resist Removal
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS
Capacitor
FOX FOX
BF2 S/D Implant
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
a. Strip resist
b. Wet strip
Plasma O2 ,
Etch stop :Endpoint/time
H2SO4 : H2SO4:H2O2
(3 : 1)10’, 130C
Matrix 106(AS101)
Verteq 1083
i. Visual inspection (referC10ETAS101OP).
ii. Weekly ash rate tests.iii. Weekly particle tests.Weelly particle test
Remove photoresist.
Removes remaining traces ofphotoresist.
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57. BPSG Deposition : To isolate metal 1 from polysilicon lines and gates
Sequence Operation Equipment Specification Process Control Purpose
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
USGdeposition
TEOS, O2 P5000(ET102) 100 nm Undoped oxide to act as barrierfor Boron/Phosphorus out-diffusion
BPSGdeposition
TEOS, O2TMP, TMB
750 nm ± 2%4 wt% B4 wt% P
Weekly thickness,uniformity testsWeekly Particle TestB/P content tests
Dielectric layer can be reflowedat low temperatures
Test InsertandScribe-line
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58. Reflow
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS
Capacitor
FOX FOX
BF2 S/D Implant
BPSG
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
Reflow 30’ 900C ASM SB/T1 To form a more planar layerof BPSG.To anneal S/D BF2 implant
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59. Lithography Contact
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSGResist
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
Anneal 800 C , 15 ‘, N2 ASM SB/T1 To prepare wafer surface for better
priminga. Resist coat HMDS: 45s, AZ
7212 DS4.1krpmSB: 115C
SVG 88 1.2 0.01um
thickness SPC chart To coat a layer ofphotosensitive resist ontowafer substrate
b. Exposure Reticle layer N1300 msec
NSR2005i8A
phototest To transfer pattern from reticleonto resist layer
c. Development PEB, Develope45s, HB
SVG 88 To create reticle pattern onresist layer upon development
d. CDmeasurement
Metra2150m
1.60.15um
3 wfrs/lot, 5 pts measurements,turning fork structure, SPC chart
To ensure the above operationsand equipments are undercontrol
e. Overlaymeasurement
Metra2150m
300 nm 3 wfrs/lot, 5 pts measurements,box-in-box structure, SPC chart,PM equipment calibration
To ensure stepper alignment isunder control
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60. Contact Etch
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSGResist
Sequence Operation Equipment Specification Process Control Purpose
a. DUV cure 170 C, 35s Fusion 150 PC Harden the photoresist toprevent resist reticulation.
b. Etch USG100 nm + BPSG650 nm
RIE CHF3, CF4, NF3,Ar
AMAT P5000(ET102)
i. Etch through 40nm of silicon
ii. Profileanisotropic > 87
iii. CD loss < 0.025m/side
i. Run trial etch beforeetching the whole lot.
ii. Visual inspection( refer to C10ETET1OP).
Open contact hole for metal1 and source/drain.
Test InsertandScribe-line
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61. Resist Coat, Backside Etch, Resist Removal
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSGResist
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
1a. Resist coat HMDS:45s, AZ7212 DS,
SVG 88/NanoSpec
1.2 0.01 um thickness SPCchart
To protect the front-side ofsubstrate during etch
1b. Hardbake 115C, 45min Oven To harden the resist
2. Backsideetch
isotropic etchNF3, He, O2
Matrix 303 E.R. > 7000A/min.
Backside rinse test.Weekly etchratetest.
Remove polysilicon and oxideon backside of wafer.
3a. Strip resist Plasma O2 Matrix 106 Remove photoresist
3b. Wet strip H2SO4:H2O2(3:1)10’ 130C
Verteq 1083 Removes remaining traces ofphotoresist
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62. Titanium/Titanium Nitride Deposition
Sequence Operation Equipment Specification Process Control Purpose
1. Contactcleaning
HF 1% dip 60 s Verteq 1083 etch rate test etch native oxide in the contacts
2.a. Titaniumdeposition2.b. TiNdeposition
400 C, 3.5 mTAr400 C, 3.5 mTAr/N2
Endura 20 nm ± 5%
80 nm ± 5%
resistivity, uniformityand reflectivity tests
provide silicide formation reduce contact resistance act as a barrier layer to prevent
spiking
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
Ti/TiN
Test InsertandScribe-line
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63. Anneal
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
Ti/TiN
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
Anneal 700 C, N2 , 1 min AST RTA Resistivity testsOxidation Test
to form TiSi for lower contactresistance
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64. Metal 1 Deposition
Sequence Operation Equipment Specification Process Control Purpose
1.a. AlSiCudeposition
1.b. TiNdeposition
175 C, 3.2 mTAr
400 C, 3.5 mTAr/N2
Endura 500 nm ± 5%
50 nm ± 10%
Resistivity ,uniformityand reflectivity testsWeekly Particle tests
to form metal-1 interconnection
to act as an ARC layer for thesubsequent photolithographystep
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCu
TiN ARC Layer
Test InsertandScribe-line
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65. Lithography Metal-1
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOSCapacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCu
TiN ARC LayerResist
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
a. Resist coat HMDS: 45s, AZ 7212 DS4.1krpm,SB:115C
SVG 88 1.2 0.01um
thickness SPC chart To coat a layer ofphotosensitive resist ontowafer substrate
b. Exposure Reticle layerG1, 300 msec
NSR2005i8A
phototest To transfer pattern fromreticle onto resist layer
c. Development PEB, Develope45s, HB
SVG 88 To create reticle pattern onresist layer upondevelopment
d. CDmeasurement
Metra2150m
1.60.1 um
3 wfrs/lot, 5 pts measurements,turning fork structure, SPC chart
To ensure the aboveoperations and equipmentsare under control
e. Overlaymeasurement
Program ___ Metra2150m
200nm
3 wfrs/lot, 5 pts measurements, box-in-box structure, SPC chart, PMequipment calibration
To ensure stepper alignmentis under control
School of Microelectronic Engineering
66. Metal-1 Etch/Resist Removal
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCu
TiN ARC Layer
Sequence Operation Equipment Specification Process Control Purpose
a. DUV cure 170 C, 35 s Fusion 150 PC(DU101)
Harden the photoresist toprevent resist reticulation.
b.Etch metalstack 650nm
RIE BCL3, CL2, CF4,N2, SF6
endpoint + 75% OE
AMAT P5000(ET101)
i. CD loss < 0.05m/side
ii. Profile Anisotropic> 87
iii. Oxide (BPSG) loss< 1000 A
visual inspection(refer toC10ETT10P)
Pattern the first metalinterconnection layer.
c. Strip resistand passivation
Plasma O2, N2, H2O AMAT P5000(ET101)
corrosion resistanceafter resist strip : 24hrs.
Remove photoresist andpassivate metal layer fromcorrosion.
Test InsertandScribe-line
School of Microelectronic Engineering
66. Metal-1 Etch / Capacitor
FOX FOX
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BPSG
N-Well
Metal 1
Sequence Operation Equipment Specification Process Control Purpose
a. DUV cure 170 C, 35 min Fusion 150 PC(DU101)
Harden the photoresist toprevent resis t reticulation.
b.Etch metalstack 650nm
RIE BCL3, CL2, CF4,N2, SF6
endpoint + 75% OE
AMAT P5000(ET101)
i. CD loss < 0.05m/side
ii. Profile Anisotropic> 87
iii. Oxide (BPSG) loss< 1000 Å
iv. Corrosionresistance 72 hrs.
Pattern the first metalinterconnection layer.
ii) Strip resistand passivation
Plasma O2, N2, H2O AMAT P5000(ET101)
Remove photoresist andpassivate metal layer fromcorrosion.
Test InsertandScribe-line
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67. Solvent Strip
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCu
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
Resist Strip EKC 265 (65C)IPA, DI H2O
Semitool metalcorrosionresistance :7 days
Weekly Particle Test To remove complex polymersand photoresist
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68. Parameter Test 1
Sequence Operation Equipment Specification Process Control Purpose
ParameterTest7200
5000 PT101 C10PDPT10P To extract electrical parametersof basic devices such astransistors, diodes, capacitors,etc. The extracted parameters areused to monitor fabricationprocesses.This step also serves as a firstwafer sort station.
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCu
Test InsertandScribe-line
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69. IMD-1 and Planarisation
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Sequence Operation Equipment Specification Process Control Purpose
a. Clean C1
b. Solvent strip
surfactant 10’
EKC 265, 65C
Verteq
Semitool
Remove contamination andparticles
c.1. DepositUSG 700 nm
PECVD TEOS, O2 AMAT P5000(ET102)
Target thickness700nm
Weekly deposition ratetest.
c.2. SputterEtch 120 nm
RIE Ar AMAT P5000(ET102)
Remaining thickness580nm.
Taper the edges.
c.3. DepositUSG 2500 nm
PECVD TEOS, O2 AMAT P5000(ET102)
Total thickness 3080nm.
Weekly deposition ratetest.
d. Etchback RIE O2, CF4, Ar, He AMAT P5000(ET102)
Final thickness 900nm.
Measure thicknessusing Nanospec.
Test InsertandScribe-line
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70. Lithography Via-Contact
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
a. Resist coat HMDS: 45s, AZ 7212 DS4.1krpm,SB:115C
SVG 88 1.2 0.01um
thickness SPC chart To coat a layer ofphotosensitive resist ontowafer substrate
b. Exposure Reticle layerG1, 300 msec
NSR2005i8A
phototest To transfer pattern fromreticle onto resist layer
c. Development PEB, Develope45s, HB
SVG 88 To create reticle pattern onresist layer upon development
d. CDmeasurement
Metra2150m
1.60.1 um
3 wfrs/lot, 5 pts measurements,turning fork structure, SPC chart
To ensure the aboveoperations and equipmentsare under control
e. Overlaymeasurement
Program ___ Metra2150m
200nm
3 wfrs/lot, 5 pts measurements, box-in-box structure, SPC chart, PMequipment calibration
To ensure stepper alignmentis under control
School of Microelectronic Engineering
71. Via-Contact Etch
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Sequence Operation Equipment Specification Process Control Purpose
a. DUV cure 160C, 35 s Fusion 150 PC ( Harden the photoresist toprevent resist reticulation.
b. Etch USG900 nm
RIE Ar, CHF3, CF4,O2
AMAT P5000(ET102)
i. Etch through 50nm of TiN ARC.
ii. Profile >87 .iii. CD loss < 0.05
m/feature.
Visual inspection( refer to C10ETET1OP).
Open via hole for metal 1and 2 interconnection.
Test InsertandScribe-line
School of Microelectronic Engineering
72. Resist Removal
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Sequence Operation Equipment Specification Process Control Purpose
a. Strip resist
b. Solvent strip
Plasma O2.Etch stop:Endpoint/time
EKC 265 (65C),IPA, DI H2O
Matrix 106(AS101)
Semitool
i. Visual inspection (referC10ETAS101OP).
ii. Weekly ash rate tests.iii. Weekly particle tests.
Weekly particle tests
Remove photoresist.
Remove complex polymers
Test InsertandScribe-line
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73. Metal 2 Deposition
AlSiCu
TiN ARC-Layer
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
AlSiCudeposition
175 C, 3.2 mTAr
Endura 1 m ± 5% Resistivity,uniformity testsWeekly Particle testWeekly reflectivity test
to form metal-2 interconnection
TiN deposition 400C, 3.5 mTAr/N2
50 nm ± 10% Resistivity, uniformityand reflectivity tests.
to act as an ARC layer for thesubsequent photolithography step
School of Microelectronic Engineering
74. Lithograpy Metal 2
AlSiCu
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
a. Resist coat HMDS: 45s, AZ 7212 DS4.1krpm,SB:115C
SVG 88 1.2 0.01um
thickness SPC chart To coat a layer ofphotosensitive resist ontowafer substrate
b. Exposure Reticle layerG1, 300 msec
NSR2005i8A
phototest To transfer pattern fromreticle onto resist layer
c. Development PEB, Develope45s, HB
SVG 88 To create reticle pattern onresist layer upon development
d. CDmeasurement
Metra2150m
1.60.1 um
3 wfrs/lot, 5 pts measurements,turning fork structure, SPC chart
To ensure the aboveoperations and equipmentsare under control
e. Overlaymeasurement
Program ___ Metra2150m
200nm
3 wfrs/lot, 5 pts measurements, box-in-box structure, SPC chart, PMequipment calibration
To ensure stepper alignmentis under control
School of Microelectronic Engineering
75. Metal 2 Etch / Resist Removal
Metal 2
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Sequence Operation Equipment Specification Process Control Purpose
a. DUV cure 160C, 35 s Fusion 150 PC(DU101)
Harden the photoresist toprevent resist reticulation.
b. Etch Metal 2 RIE Bcl3, Cl2, CF4,
N2, SF6
AMAT P5000(ET101)
i. CD loss < 0.05um/side
ii. Profile >87 .iii. Oxide loss
(USG)<1000A
Visual inspection( refer to C10ETET1OP).
Pattern the 2ndinterconnection layer
Test InsertandScribe-line
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76. Solvent Strip
Metal 2
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Test InsertandScribe-line
Sequence Operation Equipment Specification Process Control Purpose
Resist Strip EKC 265 (65C)IPA, DI H2O
Semitool Weekly Particle Test To remove complex polymersand photoresist
School of Microelectronic Engineering
77. Passivation
Sequence Operation Equipment Specification Process Control Purpose
PSGdeposition
PECVD TEOS,O2, TMP
P5000 ETI 02 750 ± 35 nm2 wt% P
Weekly etchrate testWeekly thickness,uniformity testsWeekly P-content test
Protective overcoat
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Metal 2Passivation
P+ Substrate
Test InsertandScribe-line
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78. Lithography Bond Pads
Field Oxide
BPSG
Metal 1
Metal 2
Planarisation
Passivation
Resist
Sequence Operation Equipment Specification Process Control Purpose
a. Resist coat HMDS: 45s, AZ 7212 DS4.1krpm,SB:115C
SVG 88 1.2 0.01um
thickness SPC chart To coat a layer ofphotosensitive resist ontowafer substrate
b. Exposure Reticle layerG1, 300 msec
NSR2005i8A
phototest To transfer pattern fromreticle onto resist layer
c. Development PEB, Develope45s, HB
SVG 88 To create reticle pattern onresist layer upon development
d. CDmeasurement
Metra2150m
1.60.1 um
3 wfrs/lot, 5 pts measurements,turning fork structure, SPC chart
To ensure the aboveoperations and equipmentsare under control
e. Overlaymeasurement
Program ___ Metra2150m
200nm
3 wfrs/lot, 5 pts measurements, box-in-box structure, SPC chart, PMequipment calibration
To ensure stepper alignmentis under control
School of Microelectronic Engineering
79. Passivation Etch
Resist
Silicon Substrate
Field Oxide
BPSG
Metal 1
Metal 2
Planarisation
Passivation
ResistBond Pad opening
Sequence Operation Equipment Specification Process Control Purpose
a. DUV cure 160 C, 83 s Fusion 150PC (DU101)
Harden the photoresistto prevent resistreticulation.
b. Etch PSG750 nm
RIEAr/CHF3/CF4/O2
AMAT P5000(ET102)
i. Etch through50 nm of TiNARC.
i. Visual inspectionii. (refer to
C10ETET1OP).
Open pads for probingand bonding.
School of Microelectronic Engineering
80. Resist Removal / Solvent Strip
Resist
Silicon Substrate
Field Oxide
BPSG
Metal 1
Metal 2
Planarisation
Passivation
Bond Pad opening
Sequence Operation Equipment Specification Process Control Purpose
a. Strip resist Plasma O2,Etch stop:Endpoint/time
Matrix 106(AS101)
i. Visual inspection (referC10ETAS101OP).
ii. Weekly ash rate tests.iii. Weekly particle tests.
Remove photoresist.
b. Solvent strip EKC 265 (65 )IPA, DI H2O
Semitool Weekly particle tests Remove complex polymers
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81. Anneal
Sequence Operation Equipment Specification Process Control Purpose
Anneal 440C, 10 minforming gas
ASM SA/T4 Weekly particle test to improve contact resistance,anneal radiation damage and H2 sat
saturation of dangling bonds
Resist
Silicon Substrate
Field Oxide
BPSG
Metal 1
Metal 2
Planarisation
Passivation
Bond Pad opening
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82. PATMOS / Final Test
Sequence Operation Equipment Specification Process Control Purpose
Finalparametric test8600
5000 PT101 C10PDPT10P To extract electrical parameters ofbasic devices such as transistors,diodes, capacitors, etc. Theextracted parameters are used tomonitor fab processes.
Functional test8700
5001 FT101 C10PDFT10P Lot and wafer yield To classify chips found in a fullyfabricated wafer according to itsfunctionality.
FOX FOX
N-Well N-Well
Arsenic ImplantLDD
As+ S/D ImplantP-Well
NMOSPMOS Capacitor
FOX FOX
BF2 S/D Implant
BPSG
AlSiCuPlanarisation
Metal 2Passivation
P+ Substrate
Spacer
Test InsertandScribe-line
School of Microelectronic Engineering
WHEN ICs ARE FABRICATED, ISOLATED ACTIVE-DEVICE REGIONS ARE CREATED WITHIN THE SINGLE-CRYSTAL SUBSTRATE.
THE TECHNOLOGY USED TO CONNECT THESE ISOLATED DEVICES THROUGH SPECIFIC ELECTRICAL PATHS EMPLOYS HIGH-CONDUCTIVITY, THIN FILM CONDUCTOR MATERIALS FABRICATED ABOVE THE SIO2 INSULATOR THAT COVERS THE SILICON SURFACE.
WHEREVER A CONNECTION IS NEEDED BETWEEN A CONDUCTOR FILM AND THE SILICON SUBSTRATE, AN OPENING IN THE SIO2 MUST BE PROVIDED TO ALLOW SUCH CONTACT TO OCCUR.
THE NEED FOR CONTACT
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GATE
Xj
In MOSFET, current enters the contact perpendicular to the wafer surface, then travels parallel to the surface to reach channel. The parasitic series resistance, RS of the current path from the contact to the edge of the channel can be modeled as;
RS = Rco + Rsh + Rsp + Rac
Rac
RspRsh
Rco
PMD
METAL
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Where;
Rco – contact resistance between the metal and the S/D region
Rsh – sheet resistance of S/D regions
Rsp – resistance due to current crowding effect near the channel end of the source
Rac – accumulation layer resistance
Rco need to be accurately determined !
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THEORY OF METAL-SEMICONDUCTOR CONTACT
V
I
VV
I I
Ideal ohmic contact Rectifying contact Low-resistance ohmiccontact
Ideal non-rectifying contacts would exhibit no resistance to the flow of current in both directions. In general, metal-semiconductor contacts tend to exhibit non-ohmic I-V (due to the work-function different of metal and semiconductor, potential energy barrier exist between metal-semiconductor at thermal equilibrium). For e.g. Metal-n type S/C potential barrier is 0.5V.
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Ev
EcEF
EF
vacuum level
qΦm
metal n-type s/conductor
qΦs
Ece
e
e
e
Energy band diagram of metal-semiconductor contact
potential barrier
EF
Rectifying contact
School of Microelectronic Engineering
However, it is still possible to fabricate metal - s/c contacts with I-V characteristics that approach those of ideal case. This actual contact is referred as low-resistance ohmic contact.
Surface concentration in silicon is high, ND > 1019 cm-3
Contact sintering (furnace anneal ~450ºC after metal deposition)
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SPECIFIC CONTACT RESISTIVITY, ρc
PHYSICAL PARAMETERS THAT CHARACTERIZE THE INTERFACE RESISTIVITY OF METAL – S/C CONTACT.
THE ρc DESCRIBES THE INCREMENTAL RESISTANCE OF AN INFINITELY SMALL AREA OF INTERFACE I.E THE INTERFACE QUALITY.
UNIT -cm2
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SPECIFIC CONTACT RESISTIVITY, ρc EXTRACTION
GATE
A – area of contact interface
V
Assume the current density over the entire area A is uniform;
ρc = Rk / A
Where Rk is V/I
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SPECIFIC CONTACT RESISTIVITY, ρc EXTRACTION
Three most commonly used structures Cross-bridge Kelvin Resistor – CBKR Contact-end resistor – CER Transmission line tap resistor - TLTR
In all of these structures, a specific current is sourced from the diffusion level up to metal level through the contact window. a voltage is measured between the two levels using two other terminals.
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metal
diffusion
LL
I
1
43
2
CROSS-BRIDGE KELVIN RESISTOR
ℓ δ
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PROCEDURE FOR EXTRACTING ρc FROM CBKR
ℓδ1. 2 sets of CBKR test structures of varying contact sizes, ℓ
varying in length between 1 to 25 um, with at least 2 different δ for each set of test structures.2. The diffused region under the contacts for CBKR should be
fabricated to closely emulate the actual junctions to be built in the actual devices. Normally both contacts on p+ and n+ need
to be built. The sheet resistance(ρsh) of diffused layers is to be measured.3. After test structures have been fabricated, the value of Kelvin contact
resistance, Rk = V/I, of each contact is measured.4. The value of log10 (Rk/ ρsh) is calculated for each contact.5. The value of log10 (ℓ/δ ) is calculated for each contact.6. The values of log10 (Rk/ ρsh) versus log10 (ℓ/δ ) are plotted for every set of different δ7. Two value of y = ℓt / δ could be extracted from the curves where ℓt is the transfer length and
defined as ℓt = √ ρc/ρsh (ℓt is effective length of current crowding effect)8. Since the δ values are known, ℓt can be found from ℓt = y δ9. Since ℓt = √ ρc/ρsh , ρc is found from ρc = ℓt
2 ρsh
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SPECIFIC CONTACT RESISTIVITIES OF VARIOUS METAL-SI CONTACTS
METAL-SI ρc (-m2)
AlSi to n+ Si 15AlSi-TiN to n+ Si 1.0AlSi-TiN to p+ Si 20CVD W to n+ Si 11Al-Ti:W – TiSi2 to p+ Si 60-80Al-Ti:W – TiSi2 to n+ Si 13-25
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CONTACT CHAIN FOR RCO MONITORING
Generally, accurate value of Rco cannot be extracted from resistance data obtained from simple contact chain structure. However, these kinds of contact chains are useful to provide rapid monitoring of the contact-fabrication process.
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contact metal diffused region
PMD
PAD 1 PAD 2
P-substrate
n+ n+n+
R12 = V12 / I12
Rco = R12 / number of contact
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BASIC PROCESS SEQUENCE OF CONVENTIONAL OHMIC-CONTACT
Creation of heavily doped regions (n+ or p+)
A window is etched in the oxide (contact hole etched in PMD)
Contact pre-clean (remove particles, contaminants and native oxide)
Metal deposition
Sintering or annealing process
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FORMATION OF HEAVILY DOPED REGIONS
Dopants selectively introduced through ion implantation or diffusion process
Masking layer is used to restrict the introduction of dopants into the desired regions
Heavy doping is needed, however the maximum doping concentration is limited by the solid solubility of material.
Clustering effect may reduce the electrically active dopants
ND > 1019
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FORMATION OF CONTACT OPENING
Key step in the fabrication of contact structure
The minimum size of contact holes usually determined by the minimum resolution capability of patterning technology. Contact size normally the same as gate length for e.g 0.5um CMOS technology, gate length = 0.5um, contact size = 0.5um (refer to the design rules).
In older technology (>2.0um process), wet etching is used for contact etch. Wetting and by product is introduced into the oxide etchant plus the application of ultrasonic agitation. Due to the isotrapic nature of wet etching, it is ineffective for the etching of smaller contact holes. Dry etching of contact etch is developed.
ND > 1019 ND > 1019 ND > 1019
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Dry etch introduced a new set of problems; polymer contamination – by product of dry etching. damage of silicon surface (high energy radicals in plasma), this plasma also could damaged gate oxide (plasma damaged, antenna structure is used to monitor this effect to oxide reliability) selectivity problem
Several approaches used; additional step to remove polymer combined isotropic and anisotropic dry etch combination of dry and wet etch many others
ND > 1019
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SIDEWALL CONTOURING
To give a shape that will result in good step coverage of metal.
Several approaches used; reflow, high temperature furnace annealing after contact etch wet etching followed by dry etch process PR contouring followed by dry etch many others
Sloped opening
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REMOVAL OF NATIVE OXIDE
Native oxide could result in high Rco
2 – 5 Å oxide posed not problem since it can be consumed by metals during sintering
Metal must be immediately deposited after native oxide removal
Methods of removing native oxide H2O:HF (100:1) dip for 1 minute, followed by rinsing and drying Sputter etch contact in sputtering system prior to metalization in-situ dry-etch (no commercial product available)
10 1000100
50
100
Time (min)
Thic
knes
s (Å
)
Native oxide growth rate on Si exposed to room air
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METAL DEPOSITION AND PATTERNING
Major issue is metal step coverage in the contact holes Metal deposition technique is important;
CVD is more capable to produce good step coverage (W plug, blanket or selective deposition) The drawback is process complexity and increase cost per process step Preferred deposition technique for high aspect ratio contact, > A.R of 3
PVD at elevated temperature (300-350 C) Hot aluminum PVD process (400-500 C)
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SINTERING THE CONTACTS
Performed to allow any interface layer that exists between the metal and silicon to be consumed by a chemical reaction. to allow metal and silicon to come into intimate contact through inter-diffusion.
Methods; 400-500C for 30 minutes in the presence of H2 or forming gas (a mixture of H2 (10%) and N2 (90%) RTP, laser annealing and several others.
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ALUMINUM JUNCTION SPIKING
Aluminum is chosen as metal interconnect because of; Al-Si ohmic contact could be fabricated with low Rco to n+ and p+ low resistivity (2.7 Ohm-cm) excellent compatibility with SiO2 (good adhesion). the drawback is low melting point (660C) and low eutectic temperature of Al/Si mixtures (577 C)
Grain boundaries of polycrystalline Aluminum provide fast diffusion path for Si at temperature > 400 C . As a result, large quantity of Si from Al-Si interface can diffuse into the Al film Simultaneously Al from film will move rapidly to fill the voids created by the departing Si. If the penetration of Al is deeper than the p-n junction depth below the contact, the junction will exhibit large leakage current / electrically shorted. This effect is referred as junction spiking.
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Si Si Si
Beginning of heat treatment
During heat treatment
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METHOD TO REDUCE JUNCTION SPIKING
Silicon is added to the Al film during deposition. sputter depositing the film from a single target containing both Al and Si. co-evaporation of Si and Al Silicon diffusion into Al will not occur if added Si concentration exceeds the Si solubility at process
temperature (normally 1 to 2 wt % Si is added).
However, this solution is only suitable for tchnology of 3um and above due to Si precipitation, thus increasing the Rco.
The introduction of Diffusion Barrier between Al and Si (typical solution to junction spiking in the sub-micron CMOS process)
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DIFFUSION BARRIERS The role of this material is to prevent the inter- diffusion of Al and Si. A diffusion barrier used is a thin film inserted between an overlying metal and underlying semiconductor material. Such diffusion barriers should have the following characteristics;
diffusion of Al and Si through it should be low barrier materials should be stable in the presence of Al and Si barrier materials should adhere well to both Al and Si barrier materials should have low contact resistivity to Al and Si barrier materials should have good electrical conductivity
3 types of barriers passive barriers (chemically inert with respect to Al and Si. sacrificial barriers (react with Al and Si) stuffed barriers (its grain boundaries is filled with other materials to block inter diffusion of Al and Si.
Diffusion barrier
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DIFFUSION BARRIER MATERIALS
Titanum – tungsten (Ti:W) – Stuffed Barrier Normally sputter-deposired from a single target. Initially used in Bipolar technology. Major draw-back for VLSI application is the film is quite brittle and of high stress.
Polysilicon – Sacrificial Barrier Easily integrated into NMOS technology but not as compatible with CMOS
Titanium – Sacrificial Barrier Good diffusion barrier to Si, has a relatively short barrier capability lifetime.
Titanium Nitride – Passive Barrier The most compatible and successful diffusion barrier in CMOS process. impermeable barrier to Si high activation energy for the diffusion of other materials. chemically and thermodynamically very stable. the lowest electrical resistivity among transitory metals.
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THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOSTRANSISTOR PERFORMANCE
Series resistance Rs is a combination of;
Rs = Rco + Rsh + Rsp + Rac
GATE
Xj
Rac
RspRsh
Rco
PMD
METAL
ℓ Contact length
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THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOSTRANSISTOR PERFORMANCE
When larger design rules were used, Rs was a minor component of the total MOS resistance. As devices got smaller, Rs grew larger due to;
shrinking contact size (Rco is dependence on contact size) shallower source / drain regions (Rsh is dependence on source / drain depth and width) under such conditions, Rs would degrade the device performance such as;
Idsat, transconductance, Vt
Rch = [Leff + VDS] / [0 Cox (VGS – VT – 0.5VDS]
Generally accepted that Rs to be kept < 10% of Rch.
A comprehensive analysis on the Rs components is needed to find the major contributor to the Rs and ways to reduce it.
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SUMMARY OF THE ANALYSIS
Rsh contribution is negligible The value of (Rac + Rsp) is likely to dominate the value of Rs for MOS devices with the channel length of < 0.5um. Minimum value of (Rac + Rsp) are achieved by fabricating source/drain junction with as steep a doping profile as possible. Rco can also important in degrading MOS device performance. Rco is essentially determined by;
value of specific contact resistivity, ρc contact length, ℓ. It was shown that ℓ will need to be 1 to 4 times the channel length, L, to produce with minimum value of Rco.
GATE
ℓ Contact length
L
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The requirement on minimum ℓ meaning the new way of performing contact structure is needed for deep sub-micron process technology.
WHY ???
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It is not possible to increase the contact size, ℓ, because it will defeat the purpose of device shrinkage.
Enlarge active area (to accommodate larger ℓ) will also resulted in increased parasitic junction capacitance, which further degrade the device performance
2λ x 2λ
DRAINW=4λ
5λ
2λ
Z=2λ
L=2λ
n+ diffusion
λ
2λ
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ALTERNATIVE CONTACT STRUCTURES
self-aligned silicides (SALICIDE)
buried-oxide MOS (BOMOS) contact
elevated source / drain
selective metal deposition
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Materials for Silicide Process
Group – VIII metal silicides PtSi (28-30 ohm-cm) CoSi2 (16-18 ohm-cm) NiSi2 (50 Ohm-cm) TiSi2 (13-20 ohm-cm)
TiSi2 and CoSi2 are the most developed silicide process mainly because of; lowest resistivities among the group members stable at temperature ~ 850 C
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Silicide Process
1. Contact etch2. Resist strip
Purpose : To reduce contact resistance, Rco between metal and silicon interface
3. Titanium deposition by sputtering technique ~ 400Å
GATE
GATE
n+
n+
PMD
PMD
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GATE
n+
4. TiN (barrier) deposition by sputtering technique ~ 1000 Å
5. TiSi2 (titanium silicide) formation by RTP annealing, 700C @ 30s
GATE
n+
PMD
PMD
TiSi2
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6. W Plug deposition ~ 6000 Å (by CVD) and etch back.
GATE
n+
PMD
TiSi2
7. AlSiCu deposition by sputtering ~ 3000 Å
8. TiN (ARC) deposition by sputtering ~ 1400 ÅGATE
n+
PMD
TiSi2
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9. Metal-1 pattern and etch
GATE
n+
PMD
TiSi2
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SALICIDE Process
1. After S/D implant2. Resist stripGATE
n+
GATE
n+
3. Titanium deposition by sputtering technique
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GATE
n+
4. TiSi2 (titanium silicide) formation by RTP annealing, 700C @ 30s
GATE
n+
5. Unreacted metal is selectively etched by etchant that does not attack the silicide, SiO2 and Si substrate
TiSi2
TiSi2
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GATE
n+
6. PMD Deposition and reflow
GATE
n+
7. Contact pattern and etch
Then to be deposited with TiN (barrier),W plug, AlSiCu and TiN (ARC).
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Advantages of SALICIDE over conventional contact
The value of Rsh becomes negligible, ρsh silicide = 1-2 Ohm/sq versus diffused junction = 40-120 ohm/sq
Rs = Rco + Rsh + Rsp + Rac
Contact area of silicide and the Si is much larger, thus, lower Rco for the same ρc
Recommended