FEATURES FET INPUT: IB = 50pA max
WIDE BANDWIDTH: 8MHz
HIGH SLEW RATE: 20V/µs
LOW NOISE: 8nV/√Hz (1kHz)
LOW DISTORTION: 0.00008%
HIGH OPEN-LOOP GAIN: 130dB (600Ω load)
WIDE SUPPLY RANGE: ±2.5 to ±18V
LOW OFFSET VOLTAGE: 500µV max
SINGLE, DUAL, AND QUAD VERSIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Out D
–In D
+In D
V–
+In C
–In C
Out C
Out A
–In A
+In A
V+
+In B
–In B
Out B
OPA4132
14-Pin DIPSO-14
A D
B C
OPA132OPA2132OPA4132
1
2
3
4
8
7
6
5
Offset Trim
V+
Output
NC
Offset Trim
–In
+In
V–
OPA132
8-Pin DIP, SO-8
1
2
3
4
8
7
6
5
V+
Out B
–In B
+In B
Out A
–In A
+In A
V–
OPA2132
8-Pin DIP, SO-8
A
B
High-SpeedFET-INPUT OPERATIONAL AMPLIFIERS
DESCRIPTIONThe OPA132 series of FET-input op amps provides high-speed and excellent dc performance. The combination ofhigh slew rate and wide bandwidth provide fast settling time.Single, dual, and quad versions have identical specificationsfor maximum design flexibility. High performance gradesare available in the single and dual versions. All are ideal forgeneral-purpose, audio, data acquisition and communica-tions applications, especially where high source impedanceis encountered.OPA132 op amps are easy to use and free from phaseinversion and overload problems often found incommon FET-input op amps. Input cascode circuitry pro-vides excellent common-mode rejection andmaintains low input bias current over its wide input voltagerange. OPA132 series op amps are stable in unity gain andprovide excellent dynamic behavior over a wide range ofload conditions, including high load capacitance. Dual andquad versions feature completely independent circuitry forlowest crosstalk and freedom from interaction, even whenoverdriven or overloaded.
Single and dual versions are available in 8-pin DIP andSO-8 surface-mount packages. Quad is available in 14-pinDIP and SO-14 surface-mount packages. All are specifiedfor –40°C to +85°C operation.
SBOS054A – JANUARY 1995 – REVISED JUNE 2004
www.ti.com
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
Copyright © 1995-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
OPA132OPA2132
OPA132OPA2132
OPA4132
OPA4132
OPA132, 2132, 41322SBOS054Awww.ti.com
ELECTROSTATICDISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits behandled with appropriate precautions. Failure to ob-serve proper handling and installation procedures cancause damage.
ESD damage can range from subtle performance deg-radation to complete device failure. Precision inte-grated circuits may be more susceptible to damagebecause very small parametric changes could causethe device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGSSupply Voltage, V+ to V– .................................................................... 36VInput Voltage ..................................................... (V–) –0.7V to (V+) +0.7VOutput Short-Circuit(1) .............................................................. ContinuousOperating Temperature .................................................. –40°C to +125°CStorage Temperature .....................................................–55°C to +125°CJunction Temperature ...................................................................... 150°CLead Temperature (soldering, 10s) ................................................. 300°C
NOTE: (1) Short-circuit to ground, one amplifier per package.
For the most current package and ordering information,see the Package Option Addendum located at the endof this data sheet.
PACKAGE/ORDERING INFORMATION
OPA132, 2132, 4132 3SBOS054A www.ti.com
SPECIFICATIONSAt TA = +25°C, VS = ±15V, unless otherwise noted.
OPA132P, UOPA2132P, U
OPA132PA, UAOPA2132PA, UAOPA4132PA, UA
PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS
OFFSET VOLTAGEInput Offset Voltage ±0.25 ±0.5 ±0.5 ±2 mV
vs Temperature(1) Operating Temperature Range ±2 ±10 µV/°Cvs Power Supply VS = ±2.5V to ±18V 5 15 30 µV/V
Channel Separation (dual and quad) RL = 2kΩ 0.2 µV/V
INPUT BIAS CURRENTInput Bias Current(2) VCM = 0V +5 ±50 pA
vs Temperature See Typical Curve
Input Offset Current(2) VCM = 0V ±2 ±50 pA
NOISEInput Voltage Noise
Noise Density, f = 10Hz 23 nV/√Hzf = 100Hz 10 nV/√Hzf = 1kHz 8 nV/√Hzf = 10kHz 8 nV/√Hz
Current Noise Density, f = 1kHz 3 fA/√Hz
INPUT VOLTAGE RANGECommon-Mode Voltage Range (V–)+2.5 ±13 (V+)–2.5 VCommon-Mode Rejection VCM = –12.5V to +12.5V 96 100 86 94 dB
INPUT IMPEDANCEDifferential 1013 || 2 Ω || pFCommon-Mode VCM = –12.5V to +12.5V 1013 || 6 Ω || pF
OPEN-LOOP GAINOpen-Loop Voltage Gain RL = 10kΩ, VO = –14.5V to +13.8V 110 120 104 dB
RL = 2kΩ, VO = –13.8V to +13.5V 110 126 104 120 dBRL = 600Ω, VO = –12.8V to +12.5V 110 130 104 120 dB
FREQUENCY RESPONSEGain-Bandwidth Product 8 MHzSlew Rate ±20 V/µsSettling Time: 0.1% G = –1, 10V Step, CL = 100pF 0.7 µs
0.01% G = –1, 10V Step, CL = 100pF 1 µsOverload Recovery Time G = ±1 0.5 µsTotal Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5Vrms
RL = 2kΩ 0.00008 %RL = 600Ω 0.00009 %
OUTPUTVoltage Output, Positive RL = 10kΩ (V+)–1.2 (V+)–0.9 V
Negative (V–)+0.5 (V–)+0.3 VPositive RL = 2kΩ (V+)–1.5 (V+)–1.2 VNegative (V–)+1.2 (V–)+0.9 VPositive RL = 600Ω (V+)–2.5 (V+)–2.0 VNegative (V–)+2.2 (V–)+1.9 V
Short-Circuit Current ±40 mACapacitive Load Drive (Stable Operation) See Typical Curve
POWER SUPPLYSpecified Operating Voltage ±15 VOperating Voltage Range ±2.5 ±18 VQuiescent Current (per amplifier) IO = 0 ±4 ±4.8 mA
TEMPERATURE RANGEOperating Range –40 +85 °CStorage –40 +125 °CThermal Resistance, θJA
8-Pin DIP 100 °C/WSO-8 Surface-Mount 150 °C/W14-Pin DIP 80 °C/WSO-14 Surface-Mount 110 °C/W
Specifications same as OPA132P, OPA132U.
NOTES: (1) Guaranteed by wafer test. (2) High-speed test at TJ = 25°C.
OPA132, 2132, 41324SBOS054Awww.ti.com
TYPICAL PERFORMANCE CURVESAt TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted.
OPEN-LOOP GAIN/PHASE vs FREQUENCY
0.1 1 10 100 1k 10k 100k 1M 10M
160
140
120
100
80
60
40
20
0
–20
0
–45
–90
–135
–180
Vol
tage
Gai
n (d
B)
Pha
se S
hift
(°)
Frequency (Hz)
φ
G
INPUT BIAS CURRENT vs TEMPERATURE
Ambient Temperature (°C)
Inpu
t Bia
s C
urre
nt (
pA)
100k
10k
1k
100
10
1
0.1–75 –50 –25 0 25 50 75 100 125
DualQuad
Single
High Speed TestWarmed Up
INPUT VOLTAGE AND CURRENT NOISESPECTRAL DENSITY vs FREQUENCY
1
1k
100
10
Vol
tage
Noi
se (
nV/√
Hz)
Frequency (Hz)
10 100 1k 10k 100k 1M
1
Cur
rent
Noi
se (
fA/√
Hz)
Voltage Noise
Current Noise
POWER SUPPLY AND COMMON-MODE REJECTIONvs FREQUENCY
Frequency (Hz)
PS
R, C
MR
(dB
)
120
100
80
60
40
20
010 100 1k 10k 100k 1M
CMR
–PSR
+PSR
CHANNEL SEPARATION vs FREQUENCY
Frequency (Hz)
Cha
nnel
Sep
arat
ion
(dB
)160
140
120
100
80100 1k 10k 100k
Dual and quad devices.G = 1, all channels.Quad measured channelA to D or B to C—othercombinations yield improvedrejection.
RL = ∞
RL = 2kΩ
INPUT BIAS CURRENTvs INPUT COMMON-MODE VOLTAGE
Common-Mode Voltage (V)
Inpu
t Bia
s C
urre
nt (
pA)
10
9
8
7
6
5
4
3
2
1
0
–15 –10 –5 0 5 10 15
High Speed Test
OPA132, 2132, 4132 5SBOS054A www.ti.com
TYPICAL PERFORMANCE CURVES (Cont.)At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted.
AOL, CMR, PSR vs TEMPERATURE
Ambient Temperature (°C)
AO
L, C
MR
, PS
R (
dB)
130
120
110
100
90–75 –50 –25 0 25 50 75 100 125
Open-LoopGain
PSR
CMR
OFFSET VOLTAGEPRODUCTION DISTRIBUTION
Per
cent
of A
mpl
ifier
s (%
)
Offset Voltage (µV)
–140
0
–120
0
–100
0
–800
–600
–400
–200 0
200
400
600
800
1000
1200
1400
12
10
8
6
4
2
0
Typical productiondistribution of packagedunits. Single, dual andquad units included.
OFFSET VOLTAGE DRIFTPRODUCTION DISTRIBUTION
Per
cent
of A
mpl
ifier
s (%
)
Offset Voltage Drift (µV/°C)
12
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
Typical production distributionof packaged units. Single,
dual and quad units included.
TOTAL HARMONIC DISTORTION + NOISEvs FREQUENCY
Frequency (Hz)
TH
D+
Noi
se (
%)
0.01
0.001
0.0001
0.00001
10 100 1k 10k 100k
2kΩ600Ω
RL
G = +10
G = +1
VO = 3.5Vrms
QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENTvs TEMPERATURE
Ambient Temperature (°C)
Qui
esce
nt C
urre
nt P
er A
mp
(mA
)
4.3
4.2
4.1
4.0
3.9
3.8
60
50
40
30
20
10
Sho
rt-C
ircui
t Cur
rent
(mA
)
–75 –50 –25 0 25 50 75 100 125
±ISC
±IQ
MAXIMUM OUTPUT VOLTAGEvs FREQUENCY
Frequency (Hz)
10k 100k 1M 10M
30
20
10
0
Out
put V
olta
ge (
Vp-
p)
VS = ±15V
VS = ±2.5V
VS = ±5V
Maximum output voltagewithout slew-rateinduced distortion
OPA132, 2132, 41326SBOS054Awww.ti.com
FPO
SMALL-SIGNAL OVERSHOOTvs LOAD CAPACITANCE
60
50
40
30
20
10
0100pF 1nF 10nF
Load Capacitance
Ove
rsho
ot (
%)
G = +1
G = ±10
G = –1
TYPICAL PERFORMANCE CURVES (Cont.)At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted.
SETTLING TIME vs CLOSED-LOOP GAIN
Closed-Loop Gain (V/V)
Set
tling
Tim
e (µ
s)
100
10
1
0.1±1 ±10 ±100 ±1000
0.01%
0.1%
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT15
14
13
12
11
10
–10
–11
–12
–13
–14
–15
0 10 20 30 40 50 60
Output Current (mA)
Out
put V
olta
ge S
win
g (V
) –55°C
–55°C
25°C25°C
85°C
85°C
125°C
125°C
25°C
VIN = –15V
VIN = 15V
SMALL-SIGNAL STEP RESPONSEG = 1, CL = 100pF
200ns/div
50m
V/d
iv
LARGE-SIGNAL STEP RESPONSEG = 1, CL = 100pF
1µs/div
5V/d
iv
OPA132, 2132, 4132 7SBOS054A www.ti.com
APPLICATIONS INFORMATIONOPA132 series op amps are unity-gain stable and suitablefor a wide range of general-purpose applications. Powersupply pins should be bypassed with 10nF ceramic capaci-tors or larger.
OPA132 op amps are free from unexpected output phase-reversal common with FET op amps. Many FET-input opamps exhibit phase-reversal of the output when the inputcommon-mode voltage range is exceeded. This can occur involtage-follower circuits, causing serious problems incontrol loop applications. OPA132 series op amps are freefrom this undesirable behavior. All circuitry is completelyindependent in dual and quad versions, assuring normalbehavior when one amplifier in a package is overdriven orshort-circuited.
OPERATING VOLTAGE
OPA132 series op amps operate with power supplies from±2.5V to ±18V with excellent performance. Althoughspecifications are production tested with ±15V supplies,most behavior remains unchanged throughout the fulloperating voltage range. Parameters which vary signifi-cantly with operating voltage are shown in the typicalperformance curves.
OFFSET VOLTAGE TRIM
Offset voltage of OPA132 series amplifiers is laser trimmedand usually requires no user adjustment. The OPA132(single op amp version) provides offset voltage trim con-nections on pins 1 and 8. Offset voltage can be adjusted byconnecting a potentiometer as shown in Figure 1. Thisadjustment should be used only to null the offset of the opamp, not to adjust system offset or offset produced by thesignal source. Nulling offset could degrade the offsetvoltage drift behavior of the op amp. While it is notpossible to predict the exact change in drift, the effect isusually small.
FIGURE 1. OPA132 Offset Voltage Trim Circuit.
INPUT BIAS CURRENT
The FET-inputs of the OPA132 series provide very lowinput bias current and cause negligible errors in most appli-cations. For applications where low input bias current iscrucial, junction temperature rise should be minimized. Theinput bias current of FET-input op amps increases withtemperature as shown in the typical performance curve“Input Bias Current vs Temperature.”
The OPA132 series may be operated at reduced powersupply voltage to minimize power dissipation and tempera-ture rise. Using ±3V supplies reduces power dissipation toone-fifth that at ±15V.
The dual and quad versions have higher total power dissipa-tion than the single, leading to higher junction temperature.Thus, a warmed-up quad will have higher input bias currentthan a warmed-up single. Furthermore, an SOIC will gener-ally have higher junction temperature than a DIP at the sameambient temperature because of a larger θJA. Refer to thespecifications table.
Circuit board layout can also help minimize junction tem-perature rise. Temperature rise can be minimized by solder-ing the devices to the circuit board rather than using a socket.Wide copper traces will also help dissipate the heat by actingas an additional heat sink.
Input stage cascode circuitry assures that the input biascurrent remains virtually unchanged throughout the fullinput common-mode range of the OPA132 series. See thetypical performance curve “Input Bias Current vs Common-Mode Voltage.”
V+
V–
100kΩ
OPA132 single op amp only. Use offset adjust pins only to null
offset voltage of op amp—see text.
Trim Range: ±4mV typ
OPA132 6
7
8
4
3
2 1
10nF
10nF
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jun-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
OPA132P OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA132P1 OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA132PA OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA132PA2 OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA132U ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR OPA132U
OPA132U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR OPA132U
OPA132U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR OPA132U
OPA132U1 OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA132UA ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA132UA
OPA132UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA132UA
OPA132UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA132UA
OPA132UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA132UA
OPA132UA2 OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA132UAE4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA132UA
OPA132UAG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA132UA
OPA132UG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR OPA132U
OPA2132P ACTIVE PDIP P 8 50 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type OPA2132P
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jun-2015
Addendum-Page 2
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
OPA2132PA ACTIVE PDIP P 8 50 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type OPA2132PA
OPA2132PAG4 ACTIVE PDIP P 8 50 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type OPA2132PA
OPA2132PG4 ACTIVE PDIP P 8 50 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type OPA2132P
OPA2132U ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132U
OPA2132U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132U
OPA2132U/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132U
OPA2132U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132U
OPA2132UA ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132UA
OPA2132UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132UA
OPA2132UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132UA
OPA2132UAE4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132UA
OPA2132UAG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132UA
OPA2132UE4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132U
OPA2132UG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA2132U
OPA4132PA OBSOLETE PDIP N 14 TBD Call TI Call TI
OPA4132UA ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jun-2015
Addendum-Page 3
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
OPA4132UA/2K5 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA
OPA4132UA/2K5E4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA
OPA4132UA/2K5G4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA
OPA4132UAE4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA
OPA4132UAG4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jun-2015
Addendum-Page 4
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
OPA132U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA132UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2132U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2132UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4132UA/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA132U/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA132UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA2132U/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA2132UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA4132UA/2K5 SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Sep-2013
Pack Materials-Page 2
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