Cypress Semiconductor Corporation, 198 Champion Court San Jose, CA 95134. Tel: (408) 943-2600
PRODUCT CHANGE NOTIFICATION
PCN: PCN155107 Date: December 20, 2015
Subject: 4Mb FAST and Micropower (MoBL®) Asynchronous SRAM Products: TechnologyTransition from 250-, 180-, 130- and 90-nanometer to 65-nanometer Technology.
To: FUTURE ELECTRONICSFUTURE [email protected]
Change Type: Major
Description of Change:Cypress is pleased to announce the transition of 4Mb FAST / Micropower (MoBL®)Asynchronous SRAM from the technology nodes listed below to the 65-nanometer technologynode at our partner fab- United Micro Electronics Corporation (UMC) in Tainan, Taiwan. Thischange is consistent with Cypress’s product roadmap of moving to the latest technology.
FAST Asynchronous SRAM - 90-nanometerFAST Asynchronous SRAM - 180-nanometerFAST Asynchronous SRAM - 250-nanometerMicropower (MoBL®) Asynchronous SRAM - 90-nanometerMicropower (MoBL®) Asynchronous SRAM - 130-nanometer
The new 65-nanometer products are drop-in replacement parts and form, fit, and functioncompatible with the 250-, 180-, 150- and 90-nanometer products.
4Mb FAST Asynchronous SRAM: Cypress will be discontinuing the 4Mb FAST AsynchronousSRAM 250-, 180- and 90-nanometer products. The new 65-nanometer products are drop-inreplacement parts and form, fit, and function compatible with the older technology products. Thelist of affected part numbers, replacement part numbers, next best alternatives, Last Time Buy(LTB) and Last Time Ship (LTS) dates are provided in the attached ‘Affected Parts List’ file.
4Mb Micropower (MoBL®) Asynchronous SRAM: Cypress will continue to support the existing130- and 90-nanometer 4Mb Micropower (MoBL®) Asynchronous SRAM products butencourages our customers to migrate to newer technology products.
Non-ECC (Error-Correcting Code) option for select 4Mb FAST & Micropower (MoBL®)Asynchronous SRAMs which are form, fit, and function compatible with the older technologydevices are also available in 65-nanometer. Refer to attached ‘Affected Parts List’ file for theofferings.
Document No. 001-12089 Rev. *G Page 1 of 3
Datasheets and models for both the old and the new part numbers can be downloaded from theCypress Website (www.cypress.com).
Benefit of Change:65-nanometer 4Mb Asynchronous SRAM devices use (38 and 32) Hamming Code for single-biterror detection and correction. A hardware ECC block performs all ECC-related functions in line,without the user intervention and without affecting the access-time performance of the devices.The single-bit error detection and correction capability is supplemented by an 8-bit interleavingscheme to prevent the occurrence of multi-bit errors. Together, these features providesignificant improvement in Soft Error Rate (SER) performance and product reliability, resulting inFIT rates less than 0.1 FIT/Mbit.
Migration to the 65-nanometer technology will result in improved product reliability and productavailability.
Affected Part Numbers: 58 (28 FAST Asynchronous SRAM + 30 Micropower (MoBL®)Asynchronous SRAM)Affected Parts: Please refer to attached ‘Affected Parts List’ file.
Qualification Status:The 65-nanometer products have been qualified through a series of tests identified in theQualification Test Plan (QTP) Report 145003. The QTP report can be found in the attachment tothis notification or by visiting www.cypress.com and typing the QTP number in the keywordsearch window.
Sample Status:Qualification samples are not built ahead of time for all part numbers affected by this change.Please refer to attached ‘Affected Parts List’ file for the list of older technology parts and theircorresponding 65-nanometer replacement parts. If you require qualification samples, pleasecontact your sales representative as soon as possible, but within 30 days of the date of thisPCN.
Approximate Implementation Date:4Mb FAST Asynchronous SRAM: The 250-, 180- and 90-nanometer parts listed in attached fileare subject to End of Life (EOL) with the Last Time Buy (LTB) and Last Time Ship (LTS) dates.Please refer to attached ‘Affected Parts List’ file for LTB/LTS dates
4Mb Micropower (MoBL®) Asynchronous SRAM: Products on 65-nanometer processtechnology are available immediately for sampling and production. 130-nanometer and90-nanometer products will continue to be available for order entry. No EOL is planned for theseparts.
Anticipated Impact:The 65-nanometer product are completely compatible with existing product from a functional,parametric, quality and reliability performance perspective, however the customer will need toupdate their ordering process for the 65-nanometer ordering part numbers as found in theattached ‘Affected Parts List’ file.
Cypress also recommends that customers take this opportunity to review the product datasheetand any applicable application notes to their system design and environment conditions toassess any impact to their application.
Method of Identification:The letter “G” affixed after the base part number designates the 65-nanometer technology withthe ECC functionality. The marketing part numbers with “GN” after the base part numberindicate non ECC devices.
For example, the 90-nanometer 4Mb FAST Asynchronous SRAM part CY7C1041D-10ZSXI willbe the replaced by the following 65-nanometer parts:CY7C1041G-10ZSXI with ECCCY7C1041GN-10ZSXI without ECC
Similarly, the 90-nanometer 4Mb Micropower (MoBL®) Asynchronous SRAM partCY62146ESL-45ZSXI will be the replaced by the following 65-nanometer parts:CY62146G-45ZSXI with ECCCY62146GN-45ZSXI without ECC
Please refer to www.cypress.com/products for datasheets and a complete listing of the65-nanometer 4Mb FAST / Micropower (MoBL®) Asynchronous SRAM Products.
Cypress maintains traceability of product to wafer level, including wafer fabrication location,through the lot number marked on the package.
Response Required:Please refer to LTB/LTS dates and request samples within 30 days of this notice.
For additional information regarding this change, contact your local sales representative orcontact the PCN Administrator at [email protected].
Sincerely,
Cypress PCN Administration
Marketing Part Number Last Time Buy Date Last Time Ship DateReplacement Part Number
with ECC (65nm)Replacement Part Number
without ECC (65nm)
Next Best Alternative with ECC
(65nm)
Next Best Alternative without ECC
(65nm)
CY7C1041BNL-15ZXC 6-Jul-16 2-Jan-17 CY7C1041G-10ZSXI CY7C1041GN-10ZSXI - -
CY7C1041BNL-15ZXCT 6-Jul-16 2-Jan-17 CY7C1041G-10ZSXIT CY7C1041GN-10ZSXIT - -
CY7C1041BNV33L-12ZXC 6-Jul-16 2-Jan-17 CY7C1041G30-10ZSXI CY7C1041GN30-10ZSXI - -
CY7C1041BNV33L-12ZXCT 6-Jul-16 2-Jan-17 CY7C1041G30-10ZSXIT CY7C1041GN30-10ZSXIT - -
CY7C1041D-10VXI 6-Jul-16 2-Jan-17 CY7C1041G-10VXI - - -
CY7C1041D-10VXIT 6-Jul-16 2-Jan-17 CY7C1041G-10VXIT - - -
CY7C1041D-10ZSXI 6-Jul-16 2-Jan-17 CY7C1041G-10ZSXI CY7C1041GN-10ZSXI - -
CY7C1041D-10ZSXIT 6-Jul-16 2-Jan-17 CY7C1041G-10ZSXIT CY7C1041GN-10ZSXIT - -
CY7C1041DV33-10BVI 6-Jul-16 2-Jan-17 - - *CY7C1041G30-10BVXI *CY7C1041GN30-10BVXI
CY7C1041DV33-10BVIT 6-Jul-16 2-Jan-17 - - *CY7C1041G30-10BVXIT *CY7C1041GN30-10BVXIT
CY7C1041DV33-10BVJXI 6-Jul-16 2-Jan-17 CY7C1041G30-10BVJXI CY7C1041GN30-10BVJXI - -
CY7C1041DV33-10BVJXIT 6-Jul-16 2-Jan-17 CY7C1041G30-10BVJXIT CY7C1041GN30-10BVJXIT - -
CY7C1041DV33-10BVXI 6-Jul-16 2-Jan-17 CY7C1041G30-10BVXI CY7C1041GN30-10BVXI - -
CY7C1041DV33-10BVXIT 6-Jul-16 2-Jan-17 CY7C1041G30-10BVXIT CY7C1041GN30-10BVXIT - -
CY7C1041DV33-10VXI 6-Jul-16 2-Jan-17 CY7C1041G30-10VXI - - -
CY7C1041DV33-10VXIT 6-Jul-16 2-Jan-17 CY7C1041G30-10VXIT - - -
CY7C1041DV33-10ZSXI 6-Jul-16 2-Jan-17 CY7C1041G30-10ZSXI CY7C1041GN30-10ZSXI - -
CY7C1041DV33-10ZSXIT 6-Jul-16 2-Jan-17 CY7C1041G30-10ZSXIT CY7C1041GN30-10ZSXIT - -
CY7C1049BNL-17VC 6-Jul-16 2-Jan-17 - - *CY7C1049G-10VXI *CY7C1049GN-10VXI
CY7C1049BNL-17VCT 6-Jul-16 2-Jan-17 - - *CY7C1049G-10VXIT *CY7C1049GN-10VXIT
CY7C1049D-10VXI 6-Jul-16 2-Jan-17 CY7C1049G-10VXI CY7C1049GN-10VXI - -
CY7C1049D-10VXIT 6-Jul-16 2-Jan-17 CY7C1049G-10VXIT CY7C1049GN-10VXIT - -
CY7C1049DV33-10VXI 6-Jul-16 2-Jan-17 CY7C1049G30-10VXI CY7C1049GN30-10VXI - -
CY7C1049DV33-10VXIT 6-Jul-16 2-Jan-17 CY7C1049G30-10VXIT CY7C1049GN30-10VXIT - -
CY7C1049DV33-10ZSXI 6-Jul-16 2-Jan-17 CY7C1049G30-10ZSXI CY7C1049GN30-10ZSXI - -
CY7C1049DV33-10ZSXIT 6-Jul-16 2-Jan-17 CY7C1049G30-10ZSXIT CY7C1049GN30-10ZSXIT - -
CG8539AA 6-Jul-16 2-Jan-17 CY7C1041G-10ZSXI CY7C1041GN-10ZSXI - -
CG8539AAT 6-Jul-16 2-Jan-17 CY7C1041G-10ZSXIT CY7C1041GN-10ZSXIT - -
CY62146ELL-45ZSXI No EOL is planned No EOL is planned CY62146G-45ZSXI CY62146GN-45ZSXI - -
CY62146ELL-45ZSXIT No EOL is planned No EOL is planned CY62146G-45ZSXIT CY62146GN-45ZSXIT - -
CY62146ESL-45ZSXI No EOL is planned No EOL is planned CY62146G-45ZSXI CY62146GN-45ZSXI - -
CY62146ESL-45ZSXIT No EOL is planned No EOL is planned CY62146G-45ZSXIT CY62146GN-45ZSXIT - -
CY62146EV30LL-45BVXI No EOL is planned No EOL is planned CY62146G30-45BVXI CY62146GN30-45BVXI - -
CY62146EV30LL-45BVXIT No EOL is planned No EOL is planned CY62146G30-45BVXIT CY62146GN30-45BVXIT - -
CY62146EV30LL-45ZSXI No EOL is planned No EOL is planned CY62146G30-45ZSXI CY62146GN30-45ZSXI - -
CY62146EV30LL-45ZSXIT No EOL is planned No EOL is planned CY62146G30-45ZSXIT CY62146GN30-45ZSXIT - -
CY621472E30LL-45ZSXI No EOL is planned No EOL is planned CY621472G30-45ZSXI - - -
CY621472E30LL-45ZSXIT No EOL is planned No EOL is planned CY621472G30-45ZSXIT - - -
CY62147EV18LL-55BVXI No EOL is planned No EOL is planned CY62147G18-55BVXI - - -
CY62147EV18LL-55BVXIT No EOL is planned No EOL is planned CY62147G18-55BVXIT - - -
CY62147EV30LL-45B2XI No EOL is planned No EOL is planned CY62147G30-45B2XI - - -
CY62147EV30LL-45B2XIT No EOL is planned No EOL is planned CY62147G30-45B2XIT - - -
CY62147EV30LL-45BVXI No EOL is planned No EOL is planned CY62147G30-45BVXI CY62147GN30-45BVXI - -
CY62147EV30LL-45BVXIT No EOL is planned No EOL is planned CY62147G30-45BVXIT CY62147GN30-45BVXIT - -
CY62147EV30LL-45ZSXI No EOL is planned No EOL is planned CY62147G30-45ZSXI CY62147GN30-45ZSXI - -
CY62147EV30LL-45ZSXIT No EOL is planned No EOL is planned CY62147G30-45ZSXIT CY62147GN30-45ZSXIT - -
CY62148DV30LL-55SXI No EOL is planned No EOL is planned CY62148G30-45SXI CY62148GN30-45SXI - -
CY62148DV30LL-55SXIT No EOL is planned No EOL is planned CY62148G30-45SXIT CY62148GN30-45SXIT - -
CY62148ELL-45ZSXI No EOL is planned No EOL is planned CY62148G-45ZSXI CY62148GN-45ZSXI - -
CY62148ELL-45ZSXIT No EOL is planned No EOL is planned CY62148G-45ZSXIT CY62148GN-45ZSXIT - -
CY62148ELL-55SXI No EOL is planned No EOL is planned CY62148G-45SXI CY62148GN-45SXI - -
CY62148ELL-55SXIT No EOL is planned No EOL is planned CY62148G-45SXIT CY62148GN-45SXIT - -
CY62148EV30LL-45ZSXI No EOL is planned No EOL is planned CY62148G30-45ZSXI CY62148GN30-45ZSXI - -
CY62148EV30LL-45ZSXIT No EOL is planned No EOL is planned CY62148G30-45ZSXIT CY62148GN30-45ZSXIT - -
CY62148EV30LL-55SXI No EOL is planned No EOL is planned CY62148G30-45SXI CY62148GN30-45SXI - -
CY62148EV30LL-55SXIT No EOL is planned No EOL is planned CY62148G30-45SXIT CY62148GN30-45SXIT - -
CG8187AA No EOL is planned No EOL is planned CY621472G30-45ZSXI - - -
CG8187AAT No EOL is planned No EOL is planned CY621472G30-45ZSXIT - - -
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Cypress Semiconductor Corporation CY62147G / CY621472G / CY62147GE Characterization Report
4-Mbit (256 K words × 16 bit) MoBL Static RAM with Error-Correcting Code (ECC)
Design Engineering Director or Manager Parag Patel
Product Engineering Director Binoy Jose Maliakal [email protected]
Product Engineer Sheena Mary John [email protected]
Applications Engineer
Vinay Manikkoth [email protected]
Marketing Engineer
Reuben George [email protected]
www.cypress.com
198 Champion Ct.
San Jose, CA 95134 USA
Tel: (408) 943 2600 Fax: (408) 943 4730
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 2 of 12
1.0 Table of Contents
1.0 Table of Contents .......................................................................................................................................................... 2
2.0 Introduction ................................................................................................................................................................... 3
2.1 General Description ................................................................................................................................................ 3 2.2 Datasheet ................................................................................................................................................................ 7 2.3 Application Notes .................................................................................................................................................... 7 2.4 White Papers .......................................................................................................................................................... 7 2.5 Qualification Report ................................................................................................................................................ 7
3.0 Characterization Hardware and Setup ........................................................................................................................ 8
3.1 Measurement System and Hardware ..................................................................................................................... 8 3.2 Characterization Conditions and Parameters ......................................................................................................... 8
4.0 DC Characterization ...................................................................................................................................................... 9
4.1 DC Characterization Summary over VDD and Temperature ................................................................................... 9
5.0 AC Characterization .................................................................................................................................................... 10
5.1 AC Characterization Summary over VDD and Temperature ............................................................................... …10
Document History Page ...................................................................................................................................................... 12
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 3 of 12
2.0 Introduction
2.1 General Description
CY62147G, CY621472G, CY62147GE are high-performance CMOS MoBL static RAM organized as 262,144 words by 16 bits with embedded ECC. These devices are offered in single (CY62147) and dual chip enable (CY621472) options and in multiple pin configurations. These MoBL devices feature ultra-low power standby currents which are as low as 8 µA, with typical standby currents as low as 3.5 µA. These devices also feature embedded ECC. The CY62147GE device includes an ERR pin that signals a single-bit error-detection and correction event during a read cycle. To access devices with a single chip enable input, assert the chip enable (CE) input LOW. To access dual chip enable devices, assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A17) respectively. The Byte High and Byte Low Enable (BHE, BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. Read data is accessible on I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH for a single chip enable device and CE1 HIGH / CE2 LOW for a dual chip enable device), or control signals are de-asserted (OE, BLE, BHE).
On the CY62147GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High)
The CY62147G and CY62147GE devices are available in 44-pin TSOP II, and 48-ball VFBGA packages.
Figure 1. CY62147G & CY62147GE Logic Block Diagram
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 4 of 12
Figure 2. CY62147G 48BGA/44TSOPII Pin Configurations
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 5 of 12
Figure 3. CY62147GE 48BGA/44TSOPII Pin Configurations
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 6 of 12
Figure 4. CY621472G 44TSOPII Pin Configuration
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 7 of 12
2.2 Datasheet
The CY62147G / CY621472G / CY62147GE meet all datasheet specifications. The datasheet is available from the Cypress Website at:
http://www.cypress.com/?rID=111276
2.3 Application Notes
The CY62147G / CY621472G / CY62147GE has the following associated Application Notes at this time. The Application Notes are available from the Cypress website at the URL provided below.
AN88889 - Mitigating Single-Event Upsets Using Cypress’s 65-nm Asynchronous SRAM http://www.cypress.com/?rID=84684
2.4 White Papers
The CY62147G / CY621472G / CY62147GE has no associated White Papers at this time.
2.5 Qualification Report
The CY62147G / CY621472G / CY62147GE is qualified under QTP 145003. The qualification report is available from the Cypress Website at:
http://www.cypress.com (the specific webpage URL is TBD).
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 8 of 12
3.0 Characterization Hardware and Setup
3.1 Measurement System and Hardware
The following equipments and hard wares are used for the DC and AC parametric characterization of this device.
3.1.1 Characterization Board
All the DC parameters and the AC parameters were measured using 44TSOP2 package with the D94915
hand test interface board connected to L042 load board. Pin capacitance was measured using the probe card type board.
3.1.2 ATE
Advantest 5581P tester was used for the DC and AC parameter characterization.
3.1.3 Temperature Forcing System
Temptronics TP04310A Precision Temperature Forcing System was used to force ambient temperature.
3.1.4 Frequency LCR Meter
HP4284A LCR Meter was used to measure input and output pin capacitance.
3.1.5 Power Supply
The Kiethley 2400 Source Meter was used to supply power for device for pin capacitance measurement.
3.2 Characterization Conditions and Parameters
Characterization was done on the following device and conditions as listed in Table 1. Units used for characterization are quick builds and chosen randomly unless specified.
Table 1. Characterization Conditions and Parameters
Parameter Device Fab Lot Assy Lot # of Devices Voltage Variation (V) Temperature Variation (C)
DC & AC CY62147GE30-45ZSXI 9507001 611513199 3 1.55V-5.65V -40, 25, 85
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 9 of 12
4.0 DC Characterization
4.1 DC Characterization Summary over VDD and Temperature
Table 2. DC Characterization Results across VDD and Temperature
Parameter Description Test Conditions Datasheet (45ns/55ns) Measured (45ns/55ns)
Unit Min Typ Max Min Mean Max
VOH Output HIGH voltage
1.65V to 2.2V VCC = Min, IOH = –0.1 mA 1.4 - - 1.61 1.61 1.62
V 2.2V to 2.7V VCC = Min, IOH = –1.0 mA 2.0 - - 2.16 2.16 2.16
2.7V to 3.6V VCC = Min, IOH = –4.0 mA 2.2 - - 2.60 2.61 2.62
4.5V to 5.5V VCC = Min, IOH = –4.0 mA 2.4 - - 4.25 5.33 5.41
VOL Output LOW voltage
1.65V to 2.2V VCC = Min, IOL = 0.1 mA - - 0.2 0.038 0.041 0.046
V 2.2V to 2.7V VCC = Min, IOL = 2 mA - - 0.4 0.036 0.039 0.042
2.7V to 3.6V VCC = Min, IOL = 8 mA - - 0.4 0.102 0.123 0.224
4.5V to 5.5V VCC = Min, IOL = 8 mA - - 0.4 0.98 0.115 0.148
VIH Input HIGH voltage
1.65V to 2.2V 1.4 - VCC + 0.2 1.21 1.23 1.25
V 2.2V to 2.7V 2.0 - VCC + 0.3 1.42 1.45 1.50
2.7V to 3.6V 2.0 - VCC + 0.3 1.42 1.45 1.50
4.5V to 5.5V 2.2 - VCC + 0.5 1.42 1.46 1.56
VIL Input LOW voltage
1.65V to 2.2V -0.2 - 0.4 0.68 0.75 0.80
V 2.2V to 2.7V -0.3 - 0.6 0.92 0.99 1.09
2.7V to 3.6V -0.3 - 0.8 1.12 1.18 1.20
4.5V to 5.5V -0.5 - 0.8 1.13 1.17 1.20
IIX Input leakage current GND < VIN < VCC -1.0 - 1.0 -0.040 0.044 0.120 μA
IOZ Output leakage current GND < VOUT < VCC, Output disabled -1.0 - 1.0 -0.020 0.035 0.040 μA
ICC Operating supply current VCC = Max, IOUT = 0 mA, CMOS levels
f = 22.22 MHz - 15.0 20.0 12.4 13.74 14.8 mA
f = 18.18 MHz - 15.0 20.0 10.0 12.8 11.32 mA
f = 1 MHz - 3.5 6 2.72 2.92 3.2 mA
Isb2
Automatic power down current – CMOS inputs: Vcc = 2.2 V to 3.6 V and 4.5 V to 5.5 V
CE1 ≥ Vcc – 0.2 V or CE2 ≤ 0.2 V or (BHEB and BLEB) ≥ Vcc – 0.2V Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX (address and data only), f = 0 (OEB and WEB)
25C - 3.5 3.7 - - pass[2]
μA
40C - - 4.8 - - pass[2]
μA
70C - - 7.0 - - pass[2]
μA
85C - - 8.7 4.68 6.98 7.89 μA
Automatic power down current – CMOS inputs: Vcc = 1.65 V to 2.2
CE1 ≥ Vcc – 0.2 V or CE2 ≤ 0.2 V or (BHEB and BLEB) ≥ Vcc – 0.2V Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX (address and data only), f = 0 (OEB and WEB)
25C - 3.5 4.3 - - pass[2]
μA
40C - - 5 - - pass[2]
μA
70C - - 7.5 - - pass[2]
μA
85C - - 10 4.88 7.80 8.98 μA
Isb1
Automatic power down current – CMOS inputs: Vcc = 2.2 V to 3.6 V and 4.5 V to 5.5 V
CE1 ≥ Vcc – 0.2 V or CE2 ≤ 0.2 V or (BHEB and BLEB) ≥ Vcc – 0.2V Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX (address and data only) f = 0 (OEB and WEB)
- - 8.7 4.28 5.79 7.26 μA
Automatic power down current – CMOS inputs: Vcc = 1.65 V to 2.2
- - 10 4.16 6.17 7.36 μA
Capacitance
Parameter Description Test Conditions
Datasheet Measured Unit
44TSOP2 48VBGA 44TSOP2 48VBGA
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
10 10 7.2 6.5 pF
COUT Output capacitance 10 10 5.6 5.3 pF
Data Retention Characteristics
Parameter Description Test Conditions Datasheet (10ns/15ns) Measured (10ns/15ns)
Unit Min Typ Max Min Mean Max
VDR Input leakage current VCC for data retention 1.0 - - pass[1]
- - V
ICCDR Data retention current VCC = 1.2V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V
- - 13 6.74 8.31 9.16 μA
tCDR Chip deselect to data retention time 0 - - pass[2]
- - ns
tR Operation recovery time VCC > 2.2 V 45.0 - - pass
[2] - -
ns VCC < 2.2 V 55.0 - - pass
[2] - -
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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5.0 AC Characterization
5.1 AC Characterization Summary over VDD and Temperature
Table 3. AC Characterization Results across VDD (2.2V-5.5V) and Temperature
Parameter Description Datasheet (10ns) Measured (10ns)
Min Max Min Mean Max Unit
Read Cycle
tPOWER VCC (stable) to the first access 100.0 - pass[2]
- - μs
tRC Read cycle time 45.0 - pass[1]
- - ns
tAA Address to data valid - 45.0 14.97 16.23 18.47 ns
Address to ERR valid - 45.0 13.21 15.97 20.46 ns
tOHA
Data hold from address change 10.0 15.07 15.3 15.72 ns ERR hold from address change 10.0 16.26 22.93 25.01 ns
tACE
CEB LOW to data valid - 45.0 28.05 30.08 32.80 ns CEB LOW to ERR valid - 45.0 26.44 29.41 35.62 ns
tDOE
OEB LOW to data valid - 22 6.86 7.24 7.90 ns OEB LOW to ERR valid - 22 7.19 7.57 8.00 ns
tLZOE OEB LOW to low-Z 5.0 - pass[2]
- - ns tHZOE OEB HIGH to high-Z - 18.0 - - pass
[2] ns
tLZCE CEB LOW to low-Z 10.0 - pass[2]
- - ns tHZCE CEB LOW to low-Z - 18.0 - - pass
[2] ns
tPU CEB LOW to power-up 0 - pass[2]
- - ns tpd CEB HIGH to power-down - 45.0 - - pass
[2] ns
tDBE
Byte enable to data valid - 45.0 28.02 30.12 32.84 ns Byte enable to ERR valid - 45.0 25.75 28.36 33.25 ns
tLZBE Byte enable to low-Z 5.0 - pass[2]
- - ns tHZBE Byte disable to high-Z - 18.0 - - pass
[2] ns
Parameter Description Datasheet (10ns) Measured (10ns)
Min Max Min Mean Max Unit
Write Cycle
tWC Write cycle time 45.0 - pass[1]
- - μs
tSCE CE LOW to write end 35.0 - 24.94 25.93 26.85 ns
tAW Address setup to write end 35.0 - 26.96 27.86 28.71 ns tHA Address hold from write end 0 - -15.04 -13.77 -13.12 ns tSA Address setup to write start 0 - -9.41 -8.73 -8.26 ns
tPWE WE pulse width 35.0 - 8.09 8.81 10.01 ns tSD Data setup to write end 25.0 - 6.62 6.89 7.27 ns tHD Data hold from write end 0 - -4.38 -4.13 -3.94 ns
tLZWE WE HIGH to low-Z 10.0 - pass[2]
- - ns tHZWE WE LOW to high-Z - 18.0 - - pass
[2] ns
tBW Byte Enable to write end 35.0 - 27.62 28.42 29.48 ns
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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Table 4. AC Characterization Results across VDD (1.65V-2.2V) and Temperature
Parameter Description Datasheet (15ns) Measured (15ns)
Min Max Min Mean Max Unit
Read Cycle
tPOWER VCC (stable) to the first access 100.0 - pass[2]
- - μs
tRC Read cycle time 55.0 - pass[1]
- - ns
tAA Address to data valid - 55.0 14.28 15.49 17.62 ns
Address to ERR valid - 55.0 13.08 16.16 20.40 ns
tOHA
Data hold from address change 10.0 15.18 15.46 16.00 ns ERR hold from address change 10.0 15.33 16.78 17.58 ns
tACE
CEB LOW to data valid - 55.0 28.05 29.92 32.64 ns CEB LOW to ERR valid - 55.0 27.19 30.07 36.19 ns
tDOE
OEB LOW to data valid - 25 8.17 8.49 8.83 ns OEB LOW to ERR valid - 25 8.25 8.73 9.06 ns
tLZOE OEB LOW to low-Z 5.0 - pass[2]
- - ns tHZOE OEB HIGH to high-Z - 18.0 - - pass
[2] ns
tLZCE CEB LOW to low-Z 10.0 - pass[2]
- - ns tHZCE CEB LOW to low-Z - 18.0 - - pass
[2] ns
tPU CEB LOW to power-up 0 - pass[2]
- - ns tpd CEB HIGH to power-down - 55.0 - - pass
[2] ns
tDBE
Byte enable to data valid - 55.0 31.2 33.5 32.25 ns Byte enable to ERR valid - 55.0 29.56 32.81 37.19 ns
tLZBE Byte enable to low-Z 5.0 - pass[2]
- - ns tHZBE Byte disable to high-Z - 18.0 - - pass
[2]
ns
Parameter Description Datasheet (15ns) Measured (15ns)
Min Max Min Mean Max Unit
Write Cycle
tWC Write cycle time 55.0 - pass[1]
- - μs
tSCE CE LOW to write end 45.0 - 25.7 26.94 28.16 ns
tAW Address setup to write end 45.0 - 27.67 28.59 29.64 ns tHA Address hold from write end 0 - -15.04 -14.07 -13.4 ns tSA Address setup to write start 0 - -9.13 -8.71 -8.42 ns
tPWE WE pulse width 40.0 - 8.31 8.77 9.9 ns tSD Data setup to write end 25.0 - 7.33 7.53 7.82 ns tHD Data hold from write end 0 - -4.32 -4.00 -3.66 ns
tLZWE WE HIGH to low-Z 10.0 - pass[2]
- - ns tHZWE WE LOW to high-Z - 18.0 - - pass
[2] ns
tBW Byte Enable to write end 45.0 - 28.11 28.97 29.80 ns
Note: 1 Parameter is screened against datasheet limit during production test.
2 Guaranteed by design and not characterized or tested in production. 3 Characterized at room temp only.
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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© Cypress Semiconductor Corporation, 2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders.
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Document History Page
Rev. ECN No. Orig. of Change
Description of Change
** 4797604 AVNI New Characterization Report.
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Cypress Semiconductor Corporation CY7C1041G / CY7C1041GE / CY7S1041G / CY7S1041GE
Characterization Report
4-Mbit (256 K words × 16 bit) Fast Static RAM with Error-Correcting Code (ECC) / 4-Mbit (256 K words × 16 bit) Fast Static RAM with Deep-Sleep Feature and Error-Correcting Code
Design Engineering Director or Manager Parag Patel
Product Engineering Director Binoy Jose Maliakal [email protected]
Product Engineer Sheena Mary John [email protected]
Applications Engineer
Vinay Manikkoth [email protected]
Marketing Engineer
Reuben George [email protected]
www.cypress.com
198 Champion Ct.
San Jose, CA 95134 USA
Tel: (408) 943 2600 Fax: (408) 943 4730
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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1.0 Table of Contents
1.0 Table of Contents .......................................................................................................................................................... 2
2.0 Introduction ................................................................................................................................................................... 3
2.1 General Description ................................................................................................................................................ 3 2.2 Datasheet ................................................................................................................................................................ 8 2.3 Application Notes .................................................................................................................................................... 8 2.4 White Papers .......................................................................................................................................................... 8 2.5 Qualification Report ................................................................................................................................................ 8
3.0 Characterization Hardware and Setup ........................................................................................................................ 9
3.1 Measurement System and Hardware ..................................................................................................................... 9 3.2 Characterization Conditions and Parameters ......................................................................................................... 9
4.0 DC Characterization .................................................................................................................................................... 10
4.1 DC Characterization Summary over VDD and Temperature ................................................................................. 10
5.0 AC Characterization .................................................................................................................................................... 11
5.1 AC Characterization Summary over VDD and Temperature ............................................................................... …11
Document History Page ...................................................................................................................................................... 13
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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2.0 Introduction
2.1 General Description
CY7C1041G, CY7C1041GE, CY7S1041G, CY7S1041GE are high-performance CMOS fast static RAM organized as 262,144 words by 16 bits with embedded ECC. These devices are offered in single chip enable option and in multiple pin configurations. The CY7S1041G and CY7S1041GE devices feature fast access times and a unique ultra-low power Deep Sleep mode. With Sleep mode currents as low as 15 µA, the CY7S1041G and CY7S1041GE devices combines the best features of fast and low-power SRAM in industry-standard package options. These devices also feature embedded ECC. The CY7C1041GE and CY7S1041GE devices includes an ERR pin that signals a single-bit error-detection and correction event during a read cycle. To access devices with a single chip enable input, assert the chip enable (CE) input LOW.
To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A17) respectively. The Byte High and Byte Low Enable (BHE, BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. Read data is accessible on I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), or control signals are de-asserted (OE, BLE, BHE).
On the CY7C1041GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High)
The CY7C1041G and CY7C1041GE devices are available in 44-pin TSOP II, 44-pin (400-mil) molded SOJ, and 48-ball VFBGA packages.
Figure 1. CY7C1041G & CY7C1041GE Logic Block Diagram
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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Figure 2. CY7S1041G/CY7S1041GE Logic Block Diagram
Figure 3. CY7C1041G/CY7C1041GE BGA Pin Configurations
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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Figure 4. CY7C1041GE & CY7C1041G 44TSOPII/44SOJ Pin Configurations
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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Figure 5. CY7S1041G & CY7S1041GE 44TSOPII/44SOJ and 48BGA Pin Configurations
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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Figure 6. CY7S1041G & CY7S1041GE 48BGA Pin Configurations
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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2.2 Datasheet
The CY7C1041G / CY7C1041GE, CY7S1041G / CY7S1041GE meet all datasheet specifications. The datasheet is available from the Cypress Website at:
http://www.cypress.com/?rID=111275
2.3 Application Notes
The CY7C1041GE, CY7S1041G / CY7S1041GE has the following associated Application Notes at this time. The Application Notes are available from the Cypress website at the URL provided below.
AN88889 - Mitigating Single-Event Upsets Using Cypress’s 65-nm Asynchronous SRAM http://www.cypress.com/?rID=84684 AN89371 - Power Saving With Cypress’s 65-nm Asynchronous Power Snooze™ SRAM http://www.cypress.com/?rID=86077
2.4 White Papers
The CY7C1041GE, CY7S1041G / CY7S1041GE has no associated White Papers at this time.
2.5 Qualification Report
The CY7C1041GE, CY7S1041G / CY7S1041GE is qualified under QTP 145003. The qualification report is available from the Cypress Website at:
http://www.cypress.com (the specific webpage URL is TBD).
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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3.0 Characterization Hardware and Setup
3.1 Measurement System and Hardware
The following equipments and hard wares are used for the DC and AC parametric characterization of this device.
3.1.1 Characterization Board
All the DC parameters and the AC parameters were measured using 44TSOP2 package with the D94915
hand test interface board connected to L042 load board. Pin capacitance was measured using the probe card type board.
3.1.2 ATE
Advantest 5581P tester was used for the DC and AC parameter characterization.
3.1.3 Temperature Forcing System
Temptronics TP04310A Precision Temperature Forcing System was used to force ambient temperature.
3.1.4 Frequency LCR Meter
HP4284A LCR Meter was used to measure input and output pin capacitance.
3.1.5 Power Supply
The Kiethley 2400 Source Meter was used to supply power for device for pin capacitance measurement.
3.2 Characterization Conditions and Parameters
Characterization was done on the following device and conditions as listed in Table 1. Units used for characterization are quick builds and chosen randomly unless specified.
Table 1. Characterization Conditions and Parameters
Parameter Device Fab Lot Assy Lot # of Devices Voltage Variation (V) Temperature Variation (C)
DC & AC CY7C1041G30-10ZSXI 9507001 611513203 3 1.55V-5.65V -40, 25, 85
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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4.0 DC Characterization
4.1 DC Characterization Summary over VDD and Temperature
Table 2. DC Characterization Results across VDD and Temperature
Parameter Description Test Conditions Datasheet (10ns/15ns) Measured (10ns/15ns)
Unit Min Typ Max Min Mean Max
VOH Output HIGH voltage
1.65V to 2.2V VCC = Min, IOH = –0.1 mA 1.4 - - 1.60 1.61 1.62
V 2.2V to 2.7V VCC = Min, IOH = –1.0 mA 2.0 - - 2.08 2.10 2.11
2.7V to 3.6V VCC = Min, IOH = –4.0 mA 2.2 - - 2.36 2.42 2.45
4.5V to 5.5V VCC = Min, IOH = –4.0 mA 2.4 - - 4.14 4.18 4.22
VOL Output LOW voltage
1.65V to 2.2V VCC = Min, IOL = 0.1 mA - - 0.2 0.046 0.050 0.056
V 2.2V to 2.7V VCC = Min, IOL = 2 mA - - 0.4 0.114 0.136 0.162
2.7V to 3.6V VCC = Min, IOL = 8 mA - - 0.4 0.238 0.266 0.247
4.5V to 5.5V VCC = Min, IOL = 8 mA - - 0.4 0.236 0.239 0.250
VIH Input HIGH voltage
1.65V to 2.2V 1.4 - VCC + 0.2 1.07 1.09 1.10
V 2.2V to 2.7V 2.0 - VCC + 0.3 1.45 1.49 1.62
2.7V to 3.6V 2.0 - VCC + 0.3 1.45 1.49 1.62
4.5V to 5.5V 2.2 - VCC + 0.5 1.42 1.49 1.64
VIL Input LOW voltage
1.65V to 2.2V -0.2 - 0.4 0.71 0.73 0.74
V 2.2V to 2.7V -0.3 - 0.6 0.96 0.98 1.01
2.7V to 3.6V -0.3 - 0.8 1.01 1.12 1.18
4.5V to 5.5V -0.5 - 0.8 1.05 1.15 1.20
IIX Input leakage current GND < VIN < VCC -1.0 - 1.0 -0.080 0.0395 0.160 μA
IOZ Output leakage current GND < VOUT < VCC, Output disabled -1.0 - 1.0 -0.080 0.0355 0.120 μA
ICC Operating supply current VCC = Max, IOUT = 0 mA, CMOS levels
f = 100 MHz - 38.0 45.0 27.2 30.9 33.2 mA
f = 66.7 MHz - - 40.0 19.2 22.7 25.2 mA
Isb1 Automatic CE power down current – TTL inputs
Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX
- - 15.0 7.52 7.76 8.04 mA
Isb2 Automatic CE power down current – CMOS inputs
Max VCC, CE > VCC – 0.2 V VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
- 6.0 8.0 3.26 3.45 3.67 mA
Capacitance
Parameter Description Test Conditions
Datasheet Measured Unit
44TSOP2 48VBGA 44TSOP2 48VBGA
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
10 10 7.2 6.5 pF
COUT Output capacitance 10 10 5.6 5.3 pF
Data Retention Characteristics
Parameter Description Test Conditions Datasheet (10ns/15ns) Measured (10ns/15ns)
Unit Min Typ Max Min Mean Max
VDR Input leakage current VCC for data retention 1.0 - - pass[1]
- - V
ICCDR Data retention current VCC = 1.2V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V
- - 8.0 2.31 2.44 2.63 mA
tCDR Chip deselect to data retention time 0 - - pass[2]
- - ns
tR Operation recovery time VCC > 2.2 V 10.0 - - pass
[2] - -
ns VCC < 2.2 V 15.0 - - pass
[2] - -
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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Deep Sleep Mode Characteristics
Parameter Description Test Conditions Datasheet (10ns/15ns) Measured (10ns/15ns)
Unit Min Typ Max Min Mean Max
IDS Deep Sleep Mode current VCC = VCC (max), CEB > VCC – 0.2 V, DS < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V
- - 15 5.96 6.50 7.08 μA
tPDS
Minimum time for DSB to be LOW for part to successfully exit Deep-Sleep mode
100 - - pass[2]
- - ns
tDS DSB assertion to Deep-Sleep mode transition time
- - 1 - - pass[1]
ms
tDSCD DSB deassertion to chip disable If tPDS ≥ tPDS(min) - - 100 - - pass
[1] μs
If tPDS < tPDS(min) - - 0 - - pass[1]
μs
tDSCA DSB deassertion to chip access (Active/Standby)
- - 300 122 - 291 μs
5.0 AC Characterization
5.1 AC Characterization Summary over VDD and Temperature
Table 3. AC Characterization Results across VDD (2.2V-5.5V) and Temperature
Parameter Description Datasheet (10ns) Measured (10ns)
Min Max Min Mean Max Unit
Read Cycle
tPOWER VCC (stable) to the first access 100.0 - pass[2]
- - μs
tRC Read cycle time 10.0 - pass[1]
- - ns
tAA Address to data valid - 10.0 8.44 9.10 9.50 ns
Address to ERR valid - 10.0 8.00 8.85 9.44 ns
tOHA
Data hold from address change 3.0 4.78 5.22 5.66 ns ERR hold from address change 3.0 5.31 5.67 5.94 ns
tACE
CEB LOW to data valid - 10.0 7.45 7.75 8.11 ns CEB LOW to ERR valid - 10.0 7.44 8.21 9.00 ns
tDOE
OEB LOW to data valid - 4.5 3.35 3.58 3.84 ns OEB LOW to ERR valid - 4.5 3.13 3.28 3.50 ns
tLZOE OEB LOW to low-Z 0 - pass[2]
- - ns tHZOE OEB HIGH to high-Z - 5.0 - - pass
[2] ns
tLZCE CEB LOW to low-Z 3.0 - pass[2]
- - ns tHZCE CEB LOW to low-Z - 5.0 - - pass
[2] ns
tPU CEB LOW to power-up 0 - pass[2]
- - ns tpd CEB HIGH to power-down - 10.0 - - pass
[2] ns
tDBE
Byte enable to data valid - 4.5 3.57 3.81 4.06 ns Byte enable to ERR valid - 4.5 3.00 3.23 3.44 ns
tLZBE Byte enable to low-Z 0 - pass[2]
- - ns tHZBE Byte disable to high-Z - 6.0 - - pass
[2] ns
Parameter Description Datasheet (10ns) Measured (10ns)
Min Max Min Mean Max Unit
Write Cycle
tWC Write cycle time 10.0 - pass[1]
- - μs
tSCE CE LOW to write end 7.0 - 4.95 5.20 5.39 ns
tAW Address setup to write end 7.0 - 5.94 6.13 6.44 ns tHA Address hold from write end 0 - -5.50 -5.10 -4.63 ns tSA Address setup to write start 0 - -4.72 -4.44 -4.17 ns
tPWE WE pulse width 7.0 - 4.24 4.52 4.90 ns tSD Data setup to write end 5.0 - 3.31 3.42 3.59 ns tHD Data hold from write end 0 - -1.56 -1.43 -1.13 ns
tLZWE WE HIGH to low-Z 3.0 - pass[2]
- - ns tHZWE WE LOW to high-Z - 5.0 - - pass
[2] ns
tBW Byte Enable to write end 7.0 - 4.30 4.53 4.68 ns
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
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Table 4. AC Characterization Results across VDD (1.65V-2.2V) and Temperature
Parameter Description Datasheet (15ns) Measured (15ns)
Min Max Min Mean Max Unit
Read Cycle
tPOWER VCC (stable) to the first access 100.0 - pass[2]
- - μs
tRC Read cycle time 15.0 - pass[1]
- - ns
tAA Address to data valid - 15.0 10.35 10.60 10.95 ns
Address to ERR valid - 15.0 8.81 9.57 10.85 ns
tOHA
Data hold from address change 3.0 5.22 5.51 5.88 ns ERR hold from address change 3.0 5.56 5.90 6.25 ns
tACE
CEB LOW to data valid - 15.0 7.84 8.10 8.44 ns CEB LOW to ERR valid - 15.0 8.06 9.38 8.78 ns
tDOE
OEB LOW to data valid - 8.0 3.79 4.08 4.34 ns OEB LOW to ERR valid - 8.0 3.69 3.82 3.94 ns
tLZOE OEB LOW to low-Z 1.0 - pass[2]
- - ns tHZOE OEB HIGH to high-Z - 8.0 - - pass
[2] ns
tLZCE CEB LOW to low-Z 3.0 - pass[2]
- - ns tHZCE CEB LOW to low-Z - 8.0 - - pass
[2] ns
tPU CEB LOW to power-up 0 - pass[2]
- - ns tpd CEB HIGH to power-down - 15.0 - - pass
[2] ns
tDBE
Byte enable to data valid - 8.0 3.52 3.78 4.28 ns Byte enable to ERR valid - 8.0 3.38 3.65 3.75 ns
tLZBE Byte enable to low-Z 1.0 - pass[2]
- - ns tHZBE Byte disable to high-Z - 8.0 - - pass
[2]
ns
Parameter Description Datasheet (15ns) Measured (15ns)
Min Max Min Mean Max Unit
Write Cycle
tWC Write cycle time 15.0 - pass[1]
- - μs
tSCE CE LOW to write end 12.0 - 4.63 5.00 5.34 ns
tAW Address setup to write end 12.0 - 6.96 7.20 7.51 ns tHA Address hold from write end 0 - -5.50 -5.11 -4.63 ns tSA Address setup to write start 0 - -4.28 -4.08 -3.79 ns
tPWE WE pulse width 12.0 - 4.30 4.61 5.01 ns tSD Data setup to write end 8.0 - 3.59 3.73 3.86 ns tHD Data hold from write end 0 - -1.56 -1.37 -1.07 ns
tLZWE WE HIGH to low-Z 3.0 - pass[2]
- - ns tHZWE WE LOW to high-Z - 8.0 - - pass
[2] ns
tBW Byte Enable to write end 12.0 - 4.08 4.27 4.46 ns
Note: 1 Parameter is screened against datasheet limit during production test.
2 Guaranteed by design and not characterized or tested in production. 3 Characterized at room temp only.
CY7C1061G / CY7C1061GE / CY7S1061G / CY7S1061GE Characterization Report 16-Mbit (1 M words × 16 bit) FAST Static RAM with Error-Correcting Code (ECC)
Document No. XXX-XXXXX Rev. **
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© Cypress Semiconductor Corporation, 2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders.
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 13 of 13
Document History Page
Rev. ECN No. Orig. of Change
Description of Change
** 4797566 AVNI New Characterization Report.
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 1 of 29
Cypress Semiconductor Product Qualification Report
QTP# 145003 VERSION** July 2015
\
4-MBIT Asynchronous SRAM Family ULL65nm (LL65UP-25ODR) Technology, UMC Fab 12A
CY62147G*
MoBL(R), 4-MBIT (256K WORDS X 16 BIT) STATIC RAM WITH ERROR-CORRECTING CODE (ECC)
CY621472G*
CY62147GE*
CY62146G*
CY62146GE*
CY62148G* MoBL(R), 4-MBIT (512K WORDS X 8 BIT) STATIC RAM WITH ERROR-CORRECTING CODE (ECC)
CY7C1041G* FAST, 4-MBIT (256K WORDS X 16 BIT) STATIC RAM WITH ERROR-CORRECTING CODE (ECC) CY7C1041GE*
CY7C1049G* FAST, 4-MBIT (512K WORDS X 8 BIT) STATIC RAM WITH ERROR-CORRECTING CODE (ECC) CY7C1049GE*
CY7S1041G* FAST, 4-MBIT (256K WORDS X 16 BIT) STATIC RAM WITH POWERSNOOZE(TM) AND ERROR CORRECTING CODE (ECC) CY7S1041GE*
CY7S1049G* FAST, 4-MBIT (512K WORDS X 8 BIT) STATIC RAM WITH POWERSNOOZE(TM) AND ERROR CORRECTING CODE (ECC) CY7S1049GE*
FOR ANY QUESTIONS ON THIS REPORT, PLEASE CONTACT [email protected] or via a CYLINK CRM CASE
Prepared By: Josephine Pineda (JYF)
Reviewed By: Zhaomin Ji (ZIJ)
Reliability Engineer Reliability Engineer Principal
Approved By: Don Darling
Reliability Director
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 2 of 29
QUALIFICATION HISTORY
QTP Number
Description of Qualification Purpose Date Comp
091706
Qualification of 65nm (LL65) Technology at UMC Fab 12A and New Device CY7C1553K Base Die Product Family
Aug 2009
124902 Qualification of 16-MBIT Asynchronous SRAM Family ,ULL65nm (LL65UP-25ODR) Technology at UMC Fab 12A
Aug 2014
144804 Qualification of 16-MBIT Asynchronous SRAM Family Rev.*D Silicon, ULL65nm (LL65UP-25ODR) Technology at UMC Fab 12A
Feb 2015
145003 Qualification of 4-MBIT Asynchronous SRAM Family ,ULL65nm (LL65UP-25ODR) Technology at UMC Fab 12A
July 2015
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 3 of 29
PRODUCT DESCRIPTION (for qualification)
Qualification Purpose:
Qualify 4-MBIT Asynchronous SRAM Family ,ULL65nm (LL65UP-25ODR) Technology at UMC Fab 12A
Marketing Part #: CY62147G*/ CY621472G*/ CY62147GE*/ CY62146G*/ CY62146GE*/ CY62148G*
CY7C1041G*/ CY7C1041GE*/ CY7C1049G*/ CY7C1049GE*/ CY7S1041G*
CY7S1041GE*/ CY7S1049G*/ CY7S1049GE*
Device Description: 4-MBIT Asynchronous SRAM Family
Cypress Division: Cypress Semiconductor Corporation –Memory Product Division
TECHNOLOGY/FAB PROCESS DESCRIPTION – LL65P-18R
Number of Metal Layers: 5+RDL Metal Composition:
Metal 1: Cu 0.18um
Metal 2: Cu 0.22um
Metal 3: Cu 0.22um
Metal 4: Cu 0.36um
Metal 5: Cu 1.25um
Metal 6 (RDL): Al 1.2um
Passivation Type and Materials: 0.4um Oxide / 0.5um Nitride
Number of Transistors in Device 35M
Number of Logic Gates in Device 1.25M
Generic Process Technology/Design Rule (µ-drawn): CMOS, 65nm
Gate Oxide Material/Thickness (MOS): SiON/ 19.5A
Name/Location of Die Fab (prime) Facility: UMC Fab 12A
Die Fab Line ID/Wafer Process ID: L65LL
PACKAGE AVAILABILITY
PACKAGE ASSEMBLY SITE FACILITY QTP REFERENCE
48-Ball VFBGA CML-RA QTP#150414
ASE-Taiwan (G) QTP#150413
32L TSOPII OSE-Taiwan (G) QTP# 150412
44L TSOP II CML-RA QTP# 150409
JCET-China (JT) QTP# 150410
32L SOIC,36L/44L SOJ JCET-China (JT) QTP# 150411
Note: Package Qualification details upon request
Document No.001-99388 Rev. ** ECN # 4865969
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Page 4 of 29
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation: BZ48A (6x8x1.0mm)
Package Outline, Type, or Name: VFBGA (Very Fine Ball Grid Array)
Mold Compound Name/Manufacturer: GR9810/Henkel
Mold Compound Flammability Rating: V-0 / UL94
Oxygen Rating Index: >28%
Substrate Material: BT resin
Lead Finish, Composition / Thickness: SAC105
Die Backside Preparation Method/Metallization: Backgrind
Die Separation Method: Saw
Die Attach Supplier: Henkel
Die Attach Material: QMI 506
Bond Diagram Designation: 001-95770
Wire Bond Method: Thermosonic
Wire Material/Size: CuPd, 0.8 mil
Thermal Resistance Theta JA °C/W: 31.35°C/W
Package Cross Section Yes/No: N/A
Assembly Process Flow: 11-21099
Name/Location of Assembly (prime) facility: CML-RA
MSL Level 3
Reflow Profile 260C
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location: CML-RA, CML-R
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 5 of 29
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation: BZ48A (6x8x1.0mm)
Package Outline, Type, or Name: VFBGA (Very Fine Ball Grid Array)
Mold Compound Name/Manufacturer: KE-G2250/Kyocera
Mold Compound Flammability Rating: V-0 / UL94
Oxygen Rating Index: >28%
Substrate Material: BT resin
Lead Finish, Composition / Thickness: SAC105
Die Backside Preparation Method/Metallization: Backgrind
Die Separation Method: Saw
Die Attach Supplier: Ablestik
Die Attach Material: Ablebond 2100A
Bond Diagram Designation: 001-95771
Wire Bond Method: Thermosonic
Wire Material/Size: CuPd, 0.8 mil
Thermal Resistance Theta JA °C/W: 31.35°C/W
Package Cross Section Yes/No: N/A
Assembly Process Flow: 49-41999
Name/Location of Assembly (prime) facility: ASE-Taiwan (G)
MSL Level 3
Reflow Profile 260C
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location: CML-RA, CML-R
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 6 of 29
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation: ZW32A
Package Outline, Type, or Name: TSOP II (Thin Small Outline Package)
Mold Compound Name/Manufacturer: EME-G631SH/Sumitomo
Mold Compound Flammability Rating: V-0 / UL94
Oxygen Rating Index: >28%
Leadframe Material: Copper
Lead Finish, Composition / Thickness: Pure Sn
Die Backside Preparation Method/Metallization: Backgrind
Die Separation Method: Saw
Die Attach Supplier: Sumitomo
Die Attach Material: CRM-1076WA
Bond Diagram Designation: 001-95774
Wire Bond Method: Thermosonic
Wire Material/Size: CuPd, 0.8 mil
Thermal Resistance Theta JA °C/W: 79.03°C/W
Package Cross Section Yes/No: N/A
Assembly Process Flow: 49-35999
Name/Location of Assembly (prime) facility: OSE-Taiwan (T)
MSL Level 3
Reflow Profile 260C
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location: OSE-Taiwan (T)
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 7 of 29
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation: ZW44A
Package Outline, Type, or Name: TSOP II (Thin Small Outline Package)
Mold Compound Name/Manufacturer: KE-G6000DA/ Kyocera
Mold Compound Flammability Rating: V-0 / UL94
Oxygen Rating Index: >28%
Leadframe Material: Copper
Lead Finish, Composition / Thickness: NiPdAu
Die Backside Preparation Method/Metallization: Backgrind
Die Separation Method: Saw
Die Attach Supplier: Henkel
Die Attach Material: QMI 509
Bond Diagram Designation: 001-95718
Wire Bond Method: Thermosonic
Wire Material/Size: CuPd, 0.8 mil
Thermal Resistance Theta JA °C/W: 69.20°C/W
Package Cross Section Yes/No: N/A
Assembly Process Flow: 11-21099
Name/Location of Assembly (prime) facility: CML-RA
MSL Level 3
Reflow Profile 260C
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location: CML-RA, CML-R
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 8 of 29
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation: ZW44A
Package Outline, Type, or Name: TSOP II (Thin Small Outline Package Type) Mold Compound Name/Manufacturer: EME- G631SH-Q/Sumitomo
Mold Compound Flammability Rating: V-0 / UL94
Oxygen Rating Index: >28%
Leadframe Material: Copper
Lead Finish, Composition / Thickness: Pure Sn
Die Backside Preparation Method/Metallization: Backgrind
Die Separation Method: Saw
Die Attach Supplier: Henkel
Die Attach Material: QMI 509
Bond Diagram Designation: 001-95753
Wire Bond Method: Thermosonic
Wire Material/Size: CuPd, 0.8 mil
Thermal Resistance Theta JA °C/W: 68.85°C/W
Package Cross Section Yes/No: N/A
Assembly Process Flow: 001-64159
Name/Location of Assembly (prime) facility: JCET-China (JT)
MSL Level 3
Reflow Profile 260C
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location: JCET-China (JT)
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 9 of 29
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation: SZ324, VZ364/VZ44A
Package Outline, Type, or Name: SOIC (400 mils), SOJ (400 mils) Mold Compound Name/Manufacturer: EME- G631SH-Q/Sumitomo
Mold Compound Flammability Rating: V-0 / UL94
Oxygen Rating Index: >28%
Leadframe Material: Copper
Lead Finish, Composition / Thickness: Pure Sn
Die Backside Preparation Method/Metallization: Backgrind
Die Separation Method: Saw
Die Attach Supplier: Henkel
Die Attach Material: QMI 509
Bond Diagram Designation: SZ324: 001-95775 VZ364: 001-95776 VZ444: 001-95777
Wire Bond Method: Thermosonic
Wire Material/Size: CuPd, 0.8 mil
Thermal Resistance Theta JA °C/W: SZ324: 51.79°C/W VZ364: 55.37°C/W VZ444: 59.52 °C/W
Package Cross Section Yes/No: N/A
Assembly Process Flow: 001-64159
Name/Location of Assembly (prime) facility: JCET-China (JT)
MSL Level 3
Reflow Profile 260C
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location: JCET-China (JT)
Document No.001-99388 Rev. ** ECN # 4865969
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Page 10 of 29
RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT
Stress/Test Test Condition (Temp/Bias)
Result P/F
Acoustic Microscopy
J-STD-020 Precondition: JESD22 Moisture Sensitivity Level
(192 Hrs., 30C, 60% RH, 260C Reflow) P
Age Bond Strength 200C, 4HRS MIL-STD-883, Method 883-2011
P
Constructional Analysis Criteria: Meet external and internal characteristics of Cypress package
P
Dynamic Latch-up 125C , 8.25V JESD78 P
Electrostatic Discharge Charge Device Model (ESD-CDM)
750V JESD22-C101 P
Electrostatic Discharge Human Body Model (ESD-HBM)
1100V to 8000V JESD22-A114 P
Electrostatic Discharge Machine Model (ESD-MM)
200V JESD22-A115
P
High Accelerated Saturation Test (HAST)
JEDEC STD 22-A110: 130°C, 85%RH, 2.25V 110°C/130°C, 85%RH, 3.65V Precondition: JESD22 Moisture Sensitivity Level
(192 Hrs., 30C, 60% RH, 260C Reflow)
P
High Temperature Steady State Life Static Operating Condition, Vcc Max= 1.37/2.25V, 150°C JESD22-A108 P
High Temperature Storage JESD22-A103:150°C No bias P
High Temperature Operating Life Early Failure Rate
Dynamic Operating Condition, Vcc Max = 1.44V, 125°C JESD22-A108
P
High Temperature Operating Life Latent Failure Rate
Dynamic Operating Condition, Vcc Max = 1.44V, 125°C JESD22-A108
P
High Temperature Operating Life Latent Failure Rate
Dynamic Operating Condition, Boost Regulated at Core, 1.45V,External 2.05V,125°C /150°C JESD22-A108
P
Low Temperature Operating Life Dynamic Operating Condition, Vcc = 1.62V/2.25V, -30°C JESD22-A108 P
Pressure Cooker JESD22-A102: 121C, 100%RH, 15 PSIG Precondition: JESD22 Moisture Sensitivity Level
(192 Hrs., 30C, 60% RH, 260C Reflow) P
Pre/Post LFR AC/DC Char AC/DC Critical Parameter Char at 0 hour/500/168/1000hrs P
Static Latch-up 85°C/125°C , 140mA,
85°C , 200mA, 300mA JESD78
P
Temperature Cycle
MIL-STD-883, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity Level
(192 Hrs., 30C, 60% RH, 260C Reflow) P
Temperature Humidity Bias Test (THB)
JESD22-A101: 85°C/ 85% RH , 2.25V Precondition: JESD22 Moisture Sensitivity Level
(192 Hrs., 30C, 60% RH, 260C Reflow) P
Soft Error (Alpha Particle) JESD89 P
Soft Error (Neutron) JESD89 P
Document No.001-99388 Rev. ** ECN # 4865969
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Page 11 of 29
RELIABILITY FAILURE RATE SUMMARY
Stress/Test Device Tested/ Device Hours
# Fails
Activation Energy
Thermal AF3
Failure Rate
High Temperature Operating Life1
Early Failure Rate
3,092 Devices 0 N/A N/A 0 PPM
High Temperature Operating Life2 Long Term Failure Rate (150°C)
89,000 DHRs 0 0.7 170
9 FIT High Temperature Operating Life2 Long Term Failure Rate (125°C)
1,668,000 DHRs 0 0.7 55
1 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. 2 Chi-squared 60% estimations used to calculate the failure rate.. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation
where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction
temperature of the device at use conditions.
1Early Failure Rate was computed from QTP# 145003 data.
2 Long Term Failure Rate was computed from QTP# 091706, QTP# 124902 and QTP# 145003 data.
AF = E
k
1
T-
1
T
A
2 1
exp
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Page 12 of 29
Reliability Test Data QTP #: 091706
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ACOUSTIC, MSL3
CY7C1514KV18 (7C1553K) 8842022 610851583 TAIWN-G COMP 15 0
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G COMP 15 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G COMP 15 0
STRESS: AGE BOND STRENGTH
CY7C1514KV18 (7C1553K) 8842022 610851583 TAIWN-G COMP 5 0
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G COMP 5 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G COMP 5 0
STRESS: DYNAMIC LATCH-UP
CY7C1470V33 (7C1470A) 4321389 610417278 CML-R COMP 3 0
STRESS: ESD-HUMAN BODY MODEL, 2,200V
CY7C1514KV18 (7C1553K) 8842022 610852338 TAIWN-G COMP 8 0
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G COMP 8 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G COMP 8 0
CY7C1514KV18 (7C1553K) 8844021 610908348 TAIWN-G COMP 8 0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY7C1514KV18 (7C1553K) 8842022 610852338 TAIWN-G COMP 9 0
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G COMP 9 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G COMP 9 0
STRESS: ESD-MACHINE MODEL, 200V
CY7C1514KV18 (7C1553K) 8842022 610852338 TAIWN-G COMP 5 0
STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 2.25V, PRE COND 192 HR 30C/60%RH, MSL3
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G 128 78 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G 128 77 0
STRESS: HIGH TEMPERATURE STORAGE, PLASTIC, 150C
CY7C1514KV18 (7C1553K) 8844020 610851583 TAIWN-G 1000 70 0
STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 2.25V, Vcc Max
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G 336 77 0
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Page 13 of 29
Reliability Test Data QTP #: 091706
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, BOOST REGULATED AT CORE 1.45V, EXTERNAL 2.05V
CY7C15631KV18 (7C1553K) 8908001 610920385 TAIWN-G 96 2367 0
CY7C15631KV18 (7C1553K) 8912000 610920386 TAIWN-G 96 2217 0
CY7C15631KV18 (7C1553K) 8910015 610920548 TAIWN-G 96 1321 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, BOOST REGULATED AT CORE 1.45V, EXTERNAL 2.05V
CY7C1514KV18 (7C1553K) 8844021 610908348 TAIWN-G 500 178 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, BOOST REGULATED AT CORE 1.45V, EXTERNAL 2.05V
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G 1000 178 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G 1000 178 0
STRESS: LOW TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, -30C, 2.25V Vcc
CY7C1514KV18 (7C1553K) 8842022 610852338 TAIWN-G 500 45 0
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, 15 Psig, PRE COND 192 HR 30C/60%RH, MSL3
CY7C1514KV18 (7C1553K) 8842022 610851583 TAIWN-G 168 76 0
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G 168 78 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G 168 77 0
STRESS: Pre-/ Post HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE CHAR
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G COMP 10 0
STRESS: STATIC LATCH-UP TESTING, 125C, 3.42V, +/-240mA
CY7C1514KV18 (7C1553K) 8844020 610854680 TAIWN-G COMP 9 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G COMP 9 0
CY7C1514KV18 (7C1553K) 8844021 610908348 TAIWN-G COMP 9 0
CY7C15631KV18 (7C1553K) 8911000 610922436 TAIWN-G COMP 9 0
STRESS: TEMPERATURE CYCLE COND. C -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3
CY7C1514KV18 (7C1553K) 8842022 610851583 TAIWN-G 1000 77 0
CY7C1514KV18 (7C1553K) 8844020 610854240 TAIWN-G 1000 78 0
CY7C1514KV18 (7C1553K) 8844022 610906896 TAIWN-G 1000 77 0
STRESS: STRESS: TEMPRATURE HUMIDITY TEST, 85C, 85%RH, 2.25V, PRE COND 192 HR 30C/60%RH, MSL3
CY7C1514KV18 (7C1553K) 8842022 610851583 TAIWN-G 1000 77 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 14 of 29
Reliability Test Data QTP #: 091706
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: SER – ALPHA PARTICLE, 3-TEMP, 3-VOLTAGE, @ 85C, Vcc Nom
CY7C1514KV18 (7C1553K) 8842022 610851583 TAIWN-G COMP 3 0
STRESS: X-SECTION/STEM XY AUDIT
CY7C1514KV18 (7C1553K) 8842022 610851583 TAIWN-G COMP 1WF
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 15 of 29
Reliability Test Data QTP #: 124902
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ACOUSTIC, MSL3
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA COMP 15 0
CY7C1061G30 (7CC171061A) 9313001 611348182 CML-RA COMP 170 0
CY7C1061G30 (7CC171061A) 9313001 611348184 CML-RA COMP 15 0
STRESS: AGE BOND STRENGTH
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA COMP 3 0
CY7C1061G30 (7CC171061A) 9313001 611348182 CML-RA COMP 3 0
STRESS: CONSTRUCTIONAL ANALYSIS
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA COMP 5 0
CY7C1061G30 (7CC171061A) 9313001 611348182 CML-RA COMP 5 0
STRESS: DYNAMIC LATCH-UP TESTING, 125C, 8.25V
CY7C1061G30 (7CC171061A) 9313001 611348182 CML-RA COMP 3 0
STRESS: ESD-CHARGE DEVICE MODEL
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA 500 9 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA 1000 3 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA 1250 3 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 500 9 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 1000 3 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 1250 3 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN 500 9 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN 1000 3 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN 1250 3 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN 500 9 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN 1000 3 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN 1250 3 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 16 of 29
Reliability Test Data QTP #: 124902
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ESD-CHARGE DEVICE MODEL
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN 500 9 0
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN 750 3 0
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN 500 9 0
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN 1000 3 0
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN 1250 3 0
STRESS: ESD-HUMAN BODY MODEL
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN 1100 3 0
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN 2200 8 0
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN 3300 3 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN 1100 3 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN 2200 8 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN 3300 3 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN 1100 3 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN 2200 8 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN 3300 3 0
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN 1100 3 0
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN 2200 8 0
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN 3300 3 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA 1100 3 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA 2200 8 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA 3300 3 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 1100 3 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 2200 8 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 3300 3 0
STRESS: HI-ACCEL SATURATION TEST, 110C, 85%RH, 3.65V, PRE COND 192 HR 30C/60%RH, MSL3
CY7C1061G30 (7CC171061A) 9313001 611348182 CML-RA 264 30 0
STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.65V, PRE COND 192 HR 30C/60%RH, MSL3
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA 128 79 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 17 of 29
Reliability Test Data QTP #: 124902
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE – REG-ON, 125C, 6.0V
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 96 50 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 96 50 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE , 125C, 1.44V
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 96 2107 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 96 1818 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 1.44V
CY7C1061G30 (7CC171061A) 9312001 611414530 CML-RA 168 179 0 0
CY7C1061G30 (7CC171061A) 9312001 611414530 CML-RA 1000 175 0 0
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 168 180 0 0
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 1000 180 0 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 168 179 0 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 1000 178 0 0
STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 1.37V
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 168 80 0
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN 168 80 0
STRESS: HIGH TEMPERATURE STORAGE, PLASTIC, 150C
CY7C1061G30 (7CC171061A) 9313001 611333088 CML-RA 500 79 0
CY7C1061G30 (7CC171061A) 9313001 611333088 CML-RA 1000 79 0
STRESS: LOW TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, -30C, 1.62V
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 500 83 0
STRESS: PRE/POST LFR CRITICAL PARAMETERS
CY7C1061G30 (7CC171061A) 9312001 611414530 CML-RA 0 10+2 0
CY7C1061G30 (7CC171061A) 9312001 611414530 CML-RA 1000 10+2 0
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 0 10+2 0
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 1000 10+2 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 0 10+2 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN 1000 10+2 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 18 of 29
Reliability Test Data QTP #: 124902
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: PRE/POST LTOL CRITICAL PARAMETERS
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 0 10+2 0
CY7C1061G30 (7CC171061A) 9313001 611333269 CML-RA 500 10+2 0
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, 15 Psig, PRE COND 192 HR 30C/60%RH, MSL3
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA 168 79 0
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA 288 79 0
CY7C1061G30 (7CC171061A) 9313001 611333088 CML-RA 168 78 0
CY7C1061G30 (7CC171061A) 9313001 611333088 CML-RA 288 78 0
STRESS: STATIC LATCH-UP TESTING, 85C, 8.25V/9.1V, +/-140mA
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN COMP 6 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN COMP 6 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN COMP 6 0
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN COMP 6 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA COMP 6 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN COMP 6 0
STRESS: STATIC LATCH-UP TESTING, 125C, 8.25V/9.1V, +/-140mA
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN COMP 2 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN COMP 2 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN COMP 2 0
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN COMP 2 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA COMP 2 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN COMP 2 0
STRESS: STATIC LATCH-UP TESTING, 85C, 8.25V/9.1V, +/-180mA
CY7C1062G30 (7CC171062A) 9302002 611321701 G-TAIWAN COMP 2 0
CY7C1061G30 (7CC171061A) 9302002 611320002 G-TAIWAN COMP 2 0
CY7C1069G30 (7CC171069A) 9302002 611320107 G-TAIWAN COMP 2 0
CY7C1061GE30(7CC1710613A)9308001 611340082 G-TAIWAN COMP 2 0
CY7C1061G30 (7CC171061A) 9312001 611328720 CML-RA COMP 2 0
CY7C1061G30 (7CC171061A) 9324001 611342911 G-TAIWAN COMP 2 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 19 of 29
Reliability Test Data QTP #: 124902
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: SER – ALPHA PARTICLE SEL, 25C/85C/120C, 1.65V/3.3V/5.5V
7C1710614GE 0 0 UMC COMP 3 0
STRESS: SER – NEUTRON SEL, 85C/125C, 5.25V
7C17165A 0 0 UMC COMP 3 0
STRESS: TEMPERATURE CYCLE COND. C -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA 500 80 0
CY7C1061G30 (7CC171061A) 9313001 611348183 CML-RA 1000 79 0
CY7C1061G30 (7CC171061A) 9313001 611348182 CML-RA 500 80 0
CY7C1061G30 (7CC171061A) 9313001 611348182 CML-RA 1000 78 0
CY7C1061G30 (7CP1710612A) 9313001 611420263 CML-RA 500 80 0
CY7C1061G30 (7CP1710612A) 9313001 611420263 CML-RA 1000 80 0
CY7C1061G30 (7CC171061A) 9313001 611348184 CML-RA 500 80 0
CY7C1061G30 (7CC171061A) 9313001 611348184 CML-RA 1000 80 0
STRESS: X-SECTION/STEM XY AUDIT
7C17165A 9302002 0 UMC COMP 1WF 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 20 of 29
Reliability Test Data QTP #:144804
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ESD-CHARGE DEVICE MODEL
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA 500 9 0
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA 1000 3 0
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA 1250 3 0
STRESS: ESD-HUMAN BODY MODEL
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA 1100 3 0
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA 2200 8 0
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA 3300 3 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE , 125C, 1.44V
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA 96 927 0
CY62167G30 (7CC172167A) 9438001 611503292 G-Taiwan 96 695 0
STRESS: STATIC LATCH-UP TESTING, 85C, 8.25V, +/-140mA
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA COMP 3 0
STRESS: STATIC LATCH-UP TESTING, 85C, 9.1V, +/-200mA
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA COMP 3 0
STRESS: STATIC LATCH-UP TESTING, 125C, 8.25V, +/-140mA
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA COMP 3 0
YIELD: CLASS
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA COMP EQUIVALENT
YIELD: E-TEST
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA COMP EQUIVALENT
YIELD: SORT
CY62167GE30 (7CC1721673A) 9423005 611500929 CML-RA COMP EQUIVALENT
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 21 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ACOUSTIC, MSL3
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA COMP 15 0
CY62147GE30 (7CP1721473A) 9508002 611520638 CML-RA COMP 15 0
STRESS: ESD-CHARGE DEVICE MODEL
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 500 9 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 750 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 1000 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 1250 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 500 9 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 750 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 1000 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 1250 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 500 9 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 750 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 1000 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 1250 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 500 9 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 750 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 1000 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 1250 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 1500 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 500 9 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 750 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 1000 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 1250 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 1500 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 500 9 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 750 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 1000 3 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 22 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ESD-CHARGE DEVICE MODEL
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 500 9 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 750 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 1000 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 1250 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 1500 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 1750 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 500 9 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 750 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 1000 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 1250 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 1500 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 1750 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 500 9 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 750 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515680 JT-China 500 9 0
CY7S1049GE30 (7CP1710496A) 9507001 611515680 JT-China 750 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515680 JT-China 1000 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515680 JT-China 1250 3 0
CY7S1041G30 (7CP1710414A) 9507001 611515681 JT-China 500 9 0
CY7S1041G30 (7CP1710414A) 9507001 611515681 JT-China 750 3 0
CY7S1041G30 (7CP1710414A) 9507001 611515681 JT-China 1000 3 0
CY7S1041G30 (7CP1710414A) 9507001 611515681 JT-China 1250 3 0
CY7S1041G30 (7CP1710414A) 9507001 611515681 JT-China 1500 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515682 JT-China 500 9 0
CY7C1041GE30 (7CP1710413A) 9507001 611515682 JT-China 750 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515682 JT-China 1000 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515682 JT-China 1250 3 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 23 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ESD-CHARGE DEVICE MODEL
CY7C1041GE30 (7CP1710413A) 9507001 611515682 JT-China 1500 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515682 JT-China 1750 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515682 JT-China 2000 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 500 18 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 750 9 0
STRESS: ESD-HUMAN BODY MODEL
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 1100 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 2200 8 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 3300 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 4000 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 5000 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 6000 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 7000 3 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 8000 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 1100 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 2200 8 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 3300 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 4000 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 5000 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 6000 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 7000 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA 8000 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 1100 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 2200 8 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 3300 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 4000 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 5000 3 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 24 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ESD-HUMAN BODY MODEL
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 6000 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 7000 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA 8000 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 1100 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 2200 8 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 3300 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 4000 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 5000 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 6000 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 7000 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA 8000 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 1100 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 2200 8 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 3300 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 4000 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 5000 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 6000 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 7000 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China 8000 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 1100 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 2200 8 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 3300 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 4000 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 5000 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 6000 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 7000 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China 8000 3 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 25 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ESD-HUMAN BODY MODEL
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 1100 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 2200 8 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 3300 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 4000 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 5000 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 6000 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 7000 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China 8000 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 1100 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 2200 8 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 3300 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 4000 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 5000 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 6000 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan 7000 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 1100 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 2200 8 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 3300 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 4000 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 5000 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 6000 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 7000 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China 8000 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 1100 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 2200 8 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 3300 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 4000 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 5000 3 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 26 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: ESD-HUMAN BODY MODEL
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 6000 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 7000 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan 8000 3 0
STRESS: ESD-MACHINE MODEL
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 200 5 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE , 125C, 1.44V
CY7C1041G30 (7CP171041A) 9507001 611516374 CML-RA 96 1549 0
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 96 1543 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE REGULATOR ON , 125C, 1.44V
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 96 50 0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 1.44V
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 168 193 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 1000 193 0
CY62147G30 (7CP172147A) 9507001 611510721 CML-RA 168 197 0
CY62147G30 (7CP172147A) 9507001 611510721 CML-RA 1000 197 0
CY7C1041G30 (7CP171041A) 9507001 611516374 CML-RA 168 198 0
CY7C1041G30 (7CP171041A) 9507001 611516374 CML-RA 1000 198 0
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 168 191 0
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 1000 191 0
STRESS: PRE/POST LFR CRITICAL PARAMETERS
CY7C1041G30 (7CP171041A) 9507001 611516374 CML-RA 0 10+2 0
CY7C1041G30 (7CP171041A) 9507001 611516374 CML-RA 168 10+2 0
CY7C1041G30 (7CP171041A) 9507001 611516374 CML-RA 500 10+2 0
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 0 10+2 0
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 168 10+2 0
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 500 10+2 0
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, 15 Psig, PRE COND 192 HR 30C/60%RH, MSL3
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 168 79 0
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA 288 78 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 27 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: SER – ALPHA PARTICLE
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA COMP 3 0
STRESS: SER – NEUTRON
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA COMP 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China COMP 3 0
STRESS: STATIC LATCH-UP TESTING, 85C, 8.25V, +/-140mA
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA COMP 6 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA COMP 6 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA COMP 6 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA COMP 6 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China COMP 6 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China COMP 6 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China COMP 6 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan COMP 6 0
CY62148G (7CP172148A) 9507001 611513574 JT-China COMP 6 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan COMP 6 0
STRESS: STATIC LATCH-UP TESTING, 85C, 9.1V, +/-200mA
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA COMP 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA COMP 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA COMP 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA COMP 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China COMP 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China COMP 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China COMP 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan COMP 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China COMP 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan COMP 3 0
Document No.001-99388 Rev. ** ECN # 4865969
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 28 of 29
Reliability Test Data QTP #:145003
Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism
STRESS: STATIC LATCH-UP TESTING, 125C, 8.25V, +/-140mA
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA COMP 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA COMP 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA COMP 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA COMP 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China COMP 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China COMP 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China COMP 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan COMP 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China COMP 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan COMP 3 0
STRESS: STATIC LATCH-UP TESTING, 85C, 9.1V, +/-300mA
CY62147GE30 (7CP1721473A) 9507001 611513199 CML-RA COMP 3 0
CY7S1041GE30 (7CP1710416A) 9507001 611513220 CML-RA COMP 3 0
CY62147GE30 (7CP1721473A) 9507001 611514757 CML-RA COMP 3 0
CY7C1041GE30 (7CP1710413A) 9507001 611515056 CML-RA COMP 3 0
CY7S1041G30 (7CP1710414A) 9507001 611513575 JT-China COMP 3 0
CY7S1049GE30 (7CP1710496A) 9507001 611515679 JT-China COMP 3 0
CY621472G30 (7CP1721472A) 9507001 611515678 JT-China COMP 3 0
CY62147G30 (7CP1721472A) 9507001 611515060 G-Taiwan COMP 3 0
CY62148G (7CP172148A) 9507001 611513574 JT-China COMP 3 0
CY62148G (7CP172148A) 9507001 611513173 T-Taiwan COMP 3 0
STRESS: TEMPERATURE CYCLE COND. C -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3
CY62147G30 (7CP172147A) 9507001 611516367 CML-RA 500 80 0
CY62147GE30 (7CP1721473A) 9508002 611520638 CML-RA 500 80 0
Document No.001-99388 Rev. ** ECN # 4865969
Document History Page
Document Title: QTP# 145003: 4-MBIT ASYNCHRONOUS SRAM FAMILY ULL65NM (LL65UP-25ODR) TECHNOLOGY, UMC FAB 12A Document Number: 001-99388
Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 29 of 29
Rev. ECN No.
Orig. of Change
Description of Change
** 4865969 JYF Initial spec release.