Princess Sumaya Univ.Computer Engineering Dept.
Review:Review:
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Digital Logic ReviewDigital Logic Review
Objective
Review a sample of MSI components and establish a standard drawing representation.
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Digital Logic ReviewDigital Logic Review
Logic Components
Small Scale Integration (SSI)
AND, OR, NOT …
Medium Scale Integration (MSI)
Multiplexer, Decoder, Register …
Large Scale Integration (LSI)
Microprocessor, Memory …
Very Large Scale Integration (VLSI)
Microprocessor, Memory …
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Digital Logic ReviewDigital Logic Review
Logic Circuits
Combinational
Output depends on the current input.
Sequential
Output depends on the current input and the previous output (history).
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Digital Logic ReviewDigital Logic Review
Logic Signals
Values
● Totem–Pole (Binary):
0 or 1
● Tri–State:
0, 1, or high–impedance
● Open–Collector:
0 or high–impedance
Inversion (bubble)
ENB
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Digital Logic ReviewDigital Logic Review
Logic Signals
Input
● 0 or 1
Output
● 0 or 1
10
10
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Digital Logic ReviewDigital Logic Review
Logic Signals
Values
● Totem–Pole (Binary):Never leave inputs “open-circuit”Never “short circuit” outputs
● Tri–State:May connect multiple outputs but never enable more than one simultaneously
● Open–Collector:May connect multiple outputs
Inactive value ?
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Digital Logic ReviewDigital Logic Review
Logic Signals
Values
● Totem–Pole (Binary):
● Tri–State:
● Open–Collector:R
ENB
ENB
+Vcc
Use pull-up resistor
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Digital Logic ReviewDigital Logic Review
Signal Labels
MUX
MUX
MUX
I0
I1
I2
I3
Y
S1 S0
Active High Signal
Active Low Signal
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Digital Logic ReviewDigital Logic Review
Signal Labels
Decoder
DECODER
DECODER
E
Y0
Y1
Y2
Y3
S1 S0
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CLK
Digital Logic ReviewDigital Logic Review
Timing Diagram
Clock Edge
D Q^
D Q^
D Q^
QA QB QC
S
CLK
S
QA
QB
QC
CLK
S
Last value
Next value
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Digital Logic ReviewDigital Logic Review
Registers
Group of “D” Flip – flops
Single “Clock”
Parallel “Load”
REGISTER
REGISTER
D0D1D2D3D4D5D6D7
Q0Q1Q2Q3Q4Q5Q6Q7
CLKLD
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Digital Logic ReviewDigital Logic Review
Registers
Parallel “Load”
MUXMUX0
1Y
SSD Q
D Q
D Q
MUXMUX0
1Y
SS
MUXMUX0
1Y
SS
MUXMUX0
1Y
SSD Q
D0D0
D1D1
D2D2
D3D3
LoadLoad
CLKCLK
Q0Q0
Q1Q1
Q2Q2
Q3Q3
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Digital Logic ReviewDigital Logic Review
Buses
4
REG
RAM
Q0
Q3
A7
A0
REG
D
D3 D0
Data Bus
Q0
Q3
A7
A0
A0
A3
A4
A7
CLK
Bus 22 33
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End of Review
Digital Logic ReviewDigital Logic Review