PEX 8616 RDK Hardware Reference Manual
Version 1.1
May 2010
Website: HUwww.plxtech.comUH
Technical Support: Uwww.plxtech.com/support U
Copyright © 2010 by PLX Technology, Inc. All Rights Reserved – Version 1.1 May 3, 2010
© 2010 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX8616-RDK-HRM-1.1
May 3, 2010
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2010 by PLX Technology, Inc. All rights reserved i
PREFACE
0BNOTICE This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this document is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
1BABOUT THIS MANUAL This document describes the PLX PEX 8616 RDK, a Rapid Development Kit, from a hardware perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for the creation of software for this product. This manual also includes complete schematics and bill of materials.
Note: This Hardware Reference Manual is specific to the PEX 8616 RDK. In the event of a discrepancy between this Hardware Reference Manual and the PEX 8616 Data Book, please be sure to follow the instructions and guidelines as stated in the PEX 8616 Data Book when designing your systems.
6BREVISION HISTORY
Date Version Comments
January 4, 2008
0.50 Hardware Reference Manual initial release.
January 17, 2008
0.60 Added SHP configuration, updated the BOM and Schematics
April 2008
1.0 Updated BOM and Schematics.
May 2010 1.1 Updated BOM and Schematics for the replacement On Semi CAT25080LI-G EEPROM. Added note to follower Data Book in the case of a discrepancy with Hardware Reference Manual in “About This Manual” section.
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved ii
CONTENTS 0BNOTICE ....................................................................................................................................................... i 1BABOUT THIS MANUAL ................................................................................................................................... i
6BREVISION HISTORY .................................................................................................................................. i 1. 2BGeneral Information .......................................................................................................................... 1
1.1 7BPEX 8616 Features ................................................................................................................... 2 1.2 8BPEX 8616 RDK Features .......................................................................................................... 3
2. 3BPEX 8616 RDK Hardware Architecture ............................................................................................ 4 2.1.1 29BPEX 8616 PCI Express Gen 2 Switch ................................................................................... 4
2.2 9BPEX 8616 RDK PCI Express Interfaces .................................................................................... 4 2.2.1 30BConfiguration Modules and Receptacle CM1 ........................................................................ 5 2.2.2 31BPCI Express Card Edge Connector P1 ................................................................................. 6 2.2.3 32BPCI Express Edge Card Connector SLOT 1 ......................................................................... 6 2.2.4 33BPCI Express Edge Card Connector SLOT 2 ......................................................................... 6 2.2.5 34BPCI Express Edge Card Connector SLOT 3 ......................................................................... 6 2.2.6 35B4X Mini-SAS Connector IP1 .................................................................................................. 6
2.3 10BReference Clock Circuitry ......................................................................................................... 7 2.4 11BReset Circuitry ........................................................................................................................... 8 2.5 12BHot-Plug Circuits ....................................................................................................................... 8
2.5.1 36BParallel Hot-Plug Controller Circuit........................................................................................ 8 2.5.2 37BSerial Hot-Plug Controller Circuits ......................................................................................... 9
2.6 13BSerial EEPROM ...................................................................................................................... 10 2.7 14BI2C Interface ............................................................................................................................ 10 2.8 15BPower Distribution ................................................................................................................... 11 2.9 16BLED Indicators ......................................................................................................................... 11
2.9.1 38BPort Link Status Indication (D17 – D20) .............................................................................. 12 2.9.2 39BFatal Error Indication (D24) ................................................................................................. 12 2.9.3 40BPEX_INTA Interrupt Indication (D23) .................................................................................. 12 2.9.4 41BPEX 8616 Voltage Level Monitoring (D10 – D11) ............................................................... 13
2.10 17BGPIO Pins ............................................................................................................................... 13 2.11 18BReserved Pins ......................................................................................................................... 13
3. 4BOn-Board Connectors, Switches, and Jumpers .............................................................................. 14 3.1 19BDIP Switches ........................................................................................................................... 14
3.1.1 42BSlot ID Selection (SW1) ...................................................................................................... 14 3.1.2 43BSerial Hot-Plug Signal and Control (SW2) .......................................................................... 14 3.1.3 44BParallel Hot-Plug Signal and Control (SW3) ........................................................................ 15 3.1.4 45BDC/DC Converter and Mode Controls (SW4) ...................................................................... 15 3.1.5 46BUpstream Port Select (SW5) ............................................................................................... 16 3.1.6 47BPort Configuration and NT Upstream Port Select (SW6) .................................................... 16 3.1.7 48BTest Mode Select (SW7) ..................................................................................................... 17 3.1.8 49BI2C Address and Other Mode Select (SW8) ........................................................................ 18
3.2 20BPush-Button Switches ............................................................................................................. 19 3.2.1 Manual Reset# (S1) ............................................................................................................ 19 3.2.2 Serial Hot-Plug Controller Attention Button (S2) ................................................................. 19 3.2.3 Parallel Hot-Plug Controller Attention Button (S3) .............................................................. 19
3.3 21BMidbus probe footprints (JP1 – JP2) ....................................................................................... 19 3.4 22B2.5V Header (JP3) .................................................................................................................. 21 3.5 23BJTAG Header (JP4) ................................................................................................................. 21 3.6 24BI2C Port (JP5 – JP6) ................................................................................................................ 21 3.7 25BATX HD Power Connector (J1) ............................................................................................... 22 3.8 26BReference Clock Header (J2) .................................................................................................. 22
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2010 by PLX Technology, Inc. All rights reserved iii
3.9 27BProbe Mode Input Header (J3) ................................................................................................ 22 3.10 28BPLX Use Header (J4) .............................................................................................................. 23
4. 5BBill of Materials/ Schematics ........................................................................................................... 24
FIGURES Figure 1-1. PEX 8616 RDK Front View ..................................................................................................... 1 Figure 2-1. PEX 8616 RDK Hardware Architecture .................................................................................. 4 Figure 2-2. PCI Express up to 5GT/s Gen 2 Connections ........................................................................ 5 Figure 2-3. Use mini-SAS Connector for NT Function Setup ................................................................... 7 Figure 2-4. PEX 8616 RDK Reference Clock Circuit ................................................................................ 7 Figure 2-5. PEX 8616 RDK Reset Circuit ................................................................................................. 8 Figure 2-6. PEX 8616 RDK Parallel Hot-Plug Circuits .............................................................................. 9 Figure 2-7. PEX 8616 RDK Serial Hot-Plug Circuits ............................................................................... 10 Figure 2-8. PEX 8616 RDK Power Subsystem ....................................................................................... 11 Figure 3-1. Switch SW1 Default Settings ................................................................................................ 14 Figure 3-2. Switch SW2 Default Settings ................................................................................................ 14 Figure 3-3. Switch SW3 Default Settings ................................................................................................ 15 Figure 3-4. Switch SW4 Default Settings ................................................................................................ 15 Figure 3-5. Switch SW5 Default Settings ................................................................................................ 16 Figure 3-6. Switch SW6 Default Settings ................................................................................................ 16 Figure 3-7. Switch SW7 Default Settings ................................................................................................ 17 Figure 3-8. Switch SW8 Default Settings ................................................................................................ 18 Figure 3-9. Midbus 2.0 footprint Dimensions, pin numbering and specification
(Copied from Agilent’s document) ................................................................................................... 20
TABLES Table 2-1. PEX 8616 RDK LED Indicator descriptions ........................................................................... 11 Table 2-2. Port Link Status LED Functions ............................................................................................. 12 Table 2-3. Voltage Level Monitoring LED Functions............................................................................... 13 Table 2-4. Strap_Reserved Pin Connections.......................................................................................... 13 Table 3-1. Switch SW2 Description ........................................................................................................ 14 Table 3-2. Switch SW3 Description ........................................................................................................ 15 Table 3-3. Switch SW5 Description ........................................................................................................ 16 Table 3-4. Switch SW6 Description ........................................................................................................ 17 Table 3-5. Switch SW7 Description ........................................................................................................ 18 Table 3-6. Switch SW8 Description ........................................................................................................ 18 Table 3-7. Signal Names of x8 PCI Express Midbus probe footprint ...................................................... 20 Table 3-8. Midbus probe footprints VS. Lanes of PEX 8616 .................................................................. 21 Table 3-9. Pin assignment of JP4 ........................................................................................................... 21 Table 3-10. Pin assignment of JP5 and JP6 ........................................................................................... 21 Table 3-11. Pin assignment of J1 ........................................................................................................... 22 Table 3-12. Pin assignment of J2 ........................................................................................................... 22 Table 3-13. Pin assignment of J3 ........................................................................................................... 22 Table 3-14. Pin assignment of J4 ........................................................................................................... 23
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 1
1. 2BGeneral Information The PLX PEX 8616 RDK is a Rapid Development Kit based on the PEX 8616, a 16-lane, 4-port PCI Express Gen 2 switch. The PEX 8616 RDK provides a complete hardware and software development platform that facilitates getting designs up and running quickly, lowering risk and reducing time-to-market. This RDK allows the upstream port of the PEX 8616 to be directly plugged into a system board’s x8 or x16 PCI Express connector, or plugged into an x4/x1 PCI Express connector by using card edge adapters.
Figure 1-1. PEX 8616 RDK Front View
1V
P1
ManualReset
JTAG port
EEPROMPEX 8616(U1)
U17
PORT 8 (X8)SLOT 3
PORT 5 (X8)
PORT 1 (X4)
SLOT 1
SLOT 2
PORT 5
PEX 8616RDK
Configuration Module IP1
B1
B13A13
A1
1
2
MC1
MC2
12
J3
JP1
Lanes 0-7
JP2
Lanes 24-31
PORT 6D18 D17
PORT 8 PORT 9D21 D22
PORT 0 PORT 1D19 D20
D8 D9 D6 D712
V_S
L1
3.3V
_SL
1
AT
NL
ED
#_B
PW
RL
ED
#_B
D1 D2 D3D4 D5
INT
LK
S
12V
_SL
2
3.3V
_SL
2
AT
NL
ED
#_S
PW
RL
ED
#_S
U11
J1
BJ3
BJ2
BJ1
2.5V
BJ5BJ3
SW6
SW5
SW8
SW7
U12
1
1
U5
U3SW1
U7
SW3
on
on
on
on
ON
SW2
ON ON
U13U10
D11
1.0Vpwrgd
D10
2.5Vpwrgd ON
SW4
JP3J4
JP4
U2
U8 U9
SW9
ON
1
2
1
2
I2C ports
JP6
JP5
S1
S2
Button#_S
S1
Button#_B
U14
U15
U16
U12
_Ctr
Nm
l#/D
ebu
g
USPT_SEL0USPT_SEL1USPT_SEL2RSV_13
STN0_PCFG1STN1_PCFG0RSV_9NT_USPT_SEL0NT_USPT_SEL1NT_ENABLE#
TMODE0TMODE1TMODE2TMODE3
SERDES_MODE#PROBE_MODE#RSV_17#I2C_ADD0I2C_ADD1I2C_ADD2
PH
P_
Ctr
Mrl
#_B
SLT
0S
LT1
SLT
2S
TL3
Mrl
#_S
SH
P_C
tr
Probe ModeHeader
Power provided by J1
12V_A
5V_A
3.3V_A
D12
D14
D16
12VCC
3.3VCC
D15
D13
D23
INTA#
D24
F_ERR#
GND
GND
GND
GND
To Logic “0”
Hot Plug
1
1
1
1
AT
X p
ower
con
tr
PLX Technology Inc. Copyright 2008
J2
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 2
1.1 7BPEX 8616 Features
16-lane, 4-port PCI Express Gen 2 switch with integrated on-chip SerDes 160 GT/s aggregate bandwidth (5.0GT/s/Lane x 16 Lanes x 2 (full duplex)) 19mm2 324-ball Flip-Chip Plastic Ball Grid Array (FCBGA) package Typical Power – 2.2 W Cut-Thru packet latency of less than 150ns (x8 to x8) Low power SerDes (under 90mW per lane) Fully non-blocking switch architecture Flexible port configuration
o Ports configurable as x8 or x4, with auto link-width negotiation to x2 and x1 Flexible device configuration
o Configurable via serial EEPROM, I2C, hardware strapping, or by the host Maximum packet payload size of 2,048 bytes Designate any Port as the Upstream Port (Port 0 is recommended) Dynamic Buffer Pool Architecture Read Pacing (allows user to throttle Read requests from Downstream Ports to allow for more efficient
performance) Dual casting (enhances performance by sending date from one ingress port to two egress ports) Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic
density) Lane and polarity reversal Non-Transparent Bridging support
o Enables Dual-Host, Dual-Fabric, Host-Failover applications Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 (with
Vaux not supported) Conventional PCI-compatible Device Power Management states – D0 and D3hot Active State Power Management Quality of Service (QoS)
o One Virtual Channels (VC0) and Eight Traffic classes (TC) o Round-Robin and Weighted Round-Robin Port arbitration
Reliability, Availability, Serviceability (RAS) features o PCI Express Standard Hot-Plug Controller for two Ports, include optional usage models for
Manually operated Retention Latch, by way of MRL Sensor and Attention Button support o Electromechanical Interlock supported with Power Enable output o Baseline and Advanced Error Reporting capability o Performance Monitoring
Per-Port Payload and Header Counters Per-traffic type (write, Read, Completion) Counters
o JTAG AC/DC boundary scan o 4 port link status indicators (PEX_PORT_GOOD[6,5,1,0]#) o 16 GPIO and/or Serial Hot-Plug PERST# pins
INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball support
Compliant to the following specifications: o PCI Local Bus Specification, Revision 3.0 (PCI r3.0) o PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2) o PCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2) o PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) o PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0) o PCI Express Card Electromechanical (CEM) Specification, Revision 2.0 o PCI ExpressCard CEM r2.0) o PCI Express Mini Card Electromechanical (CEM) Specification, Revision 1.1
(PCI ExpressCard Mini CEM r1.1)
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 3
o IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 (IEEE Standard 1149.1-1990)
o IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture o IEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions o IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture
Extensions (IEEE Standard 1149.6-2003) o The I2C-Bus Specification, Version 2.1 (I2C Bus v2.1)
1.2 8BPEX 8616 RDK Features
PLX PEX 8616 PCI Express switch in a 324-ball Flip-Chip Plastic BGA package Form factor based on PCI Express Card Electromechanical (CEM) Specification 2.0 Ships with default configuration of one x8 upstream and two x4 downstream ports
o All PEX 8616 lane/port configurations supported with breakout boards and configuration modules Non-Transparent Bridging support Two x8 Gen 2 Midbus probe footprints for one upstream and one downstream port PCI Express signal
probing On-board PCI Express RefClk buffer which supports Spread Spectrum Clocking Socketable Serial EEPROM (2.5V) Serial Hot-Plug and Parallel Hot-Plug Circuits Two standard 2x2 headers provides the I2C interface to an I2C master DIP switches for port configuration, upstream port or NT port select and I2C address settings Manual push-button PERST# capability Up to four port status indicator LEDs for visual inspection of link speed and status Voltage level monitoring circuit for 1.0V and 2.5V power to the PEX 8616
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 4
2. 3BPEX 8616 RDK Hardware Architecture
PEX 8616EEPROM
I2C
Voltage Monitor
2
5
4
Reset Timer
RefClk
PERST#
REFCLK
JTAG
connector5Lane 24-31
(Port 5 or Port 5&6)
x16 PCI Express Edge Card Connectors
x4
X8 PCI Express Card Edge Connector P1
RefClkBuffer
x8
DC/DC Converters
Link StatusLEDs
X8 midbus probe footprint (JP2)
SLOT1
SLOT2
SLOT3
x8
x4
Lane 0-7(Port 0 or Port 0&1)
Lane 0-3
x4
Lane 4-7
Configuration Module
x4
Use Module 3
X8 midbus probe footprint (JP1)
IP1
4X Mini-SASConnector
x4
Use Module 1
Use Module 2
x4
SHPPHP
6
Configuration Dipswitches
DC/DC Converter
ATX HD power Connector J1
Not Use
J2 Reflk Header
Figure 2-1. PEX 8616 RDK Hardware Architecture
2.1.1 29BPEX 8616 PCI Express Gen 2 Switch
The PEX 8616 is a 16-lane, 4-port PCI Express Gen 2 (5.0GT/s) switch. It is designed with two stations, with each station housing eight lanes. Station 0 contains lanes 0 thru 7 and Station 1 contains lanes 24 thru 31. Each station can be configured as one x8 port or two x4 ports. Each port can then auto-negotiate its link-width down to x2 or x1.
2.2 9BPEX 8616 RDK PCI Express Interfaces
The PEX 8616 RDK is designed around the PEX 8616, a 4-port, 16-lane Gen 2 switch, and is based on the form factor specified in the PCI Express CEM 2.0 Specification. The PEX 8616 RDK PCI offers four PCI Express (PCIe) interfaces: a x8 PCI Express Card Edge connector (P1), two x16 PCI Express Edge Card connectors (SLOT 1 and SLOT 2; SLOT 3 is not used), and a 4X Mini-SAS connector (IP1).
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 5
Although two PCIe slots (SLOT 1-2) have a x16 link-width form factors, the slots themselves are configured as x8 for SLOT1, and x4 for SLOT 2 as shown in XFigure 2-1X above. Using a x8-to-x4x4 Breakout Board, the x8 link SLOT 1 can be broken out into two x4 slots, creating two x4 ports from a x8 slot.
Figure 2-2. PCI Express up to 5GT/s Gen 2 Connections
2.2.1 30BConfiguration Modules and Receptacle CM1
Configuration Module Receptacle CM1 is a 200-pin high-speed Mezzanine Connector. It is soldered on the PCB of PEX 8616 RDK. It directly connects to lane 4 to lane 7 of the PEX 8616, lane 4 to lane 7 of PCI Express card edge connector P1, lane 0 to lane 3 of PCI Express Edge Card Connector SLOT 2, and lane 0 to lane 3 of 4x mini-SAS connector IP1. One of three configuration modules (see XFigure 2-2X) can be plugged into the Configuration Module Receptacle (CM1) of the PEX 8616 RDK. Which Configuration Module is used determines how lanes 4-7 of the PEX 8616 are routed:
1) Configuration Module 1 (marked “Enable Cable IP1”) routes lanes 4-7 to the 4X Mini-SAS Connector. 2) Configuration Module 2 (marked “Enable SLOT 2” routes lanes 4-7 to PCIe SLOT 2. 3) Configuration Module 3 (marked “Enable P1 as x8”) routes lanes 4-7 to the x8 PCIe Card Edge
Connector to enable P1 as a x8 port.
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 6
XFigure 2-2X shows the RDK PCI Express Gen 2 connections and the top view of the three configuration modules. By default, PEX 8616 RDKs are shipped to customers with Configuration Module 3, enabling a x8 upstream port and two x4 downstream ports. To achieve other configurations, a combination of x8-to-x4x4 Breakout Boards and/or Configuration Modules 1 or 2 will be required.
2.2.2 31BPCI Express Card Edge Connector P1
Card Edge Connector P1 can directly plug into a x8 or x16 PCI Express slot. Lanes 0-3 of PEX 8616’s Port 0 is connected to this connector through a x8 midbus probe footprint (JP1). PEX 8616’s lanes 4-7 also passes through the x8 midbus probe footprint (JP1) and connects to the CM1 receptacle. When Configuration Module 3 is plugged into the CM1 receptacle, the PEX 8616’s lanes 4-7 are routed to Connector P1 and become the upper four lanes of Port 0’s x8 link. By default, the PEX 8616 RDK sets this port to be the x8 link upstream port. Connector P1 also provides 12V and 3.3V power, along with PERST# and REFCLK_P/N to the RDK.
2.2.3 32BPCI Express Edge Card Connector SLOT 1
Connector SLOT 1 is a straddle-mount, x16 PCI Express connector. Eight lanes, lanes 24-31, from the PEX 8616 are connected to this connector. The default configuration of the PEX 8616 RDK sets two x4 downstream ports at this connector. A x8-to-x4x4 breakout board is used to break the 8 lanes going to SLOT 1 into two x4 ports, Port 5 and Port 6, which can be accessed individually. Cards being plugged into the x8-to-x4x4 breakout board will be perpendicular to the RDK. When configured as a x8 port (port 5), cards plugging into this slot will be in-line with the RDK. Power is provided to this connector from the ATX hard disk power connector J1 through the power MOSFETs which are controlled by the Parallel Hot-Plug Controller (PHPC) of PEX 8616 (see Section X2.5.1 X for details).
2.2.4 33BPCI Express Edge Card Connector SLOT 2
Connector SLOT 2 is a vertical-mount through-hole x16 PCI Express connector. Cards plugging into this slot will be perpendicular to the RDK. When Configuration Module 2 is plugged into the CM1 receptacle, lanes 4-7 from the PEX 8616 pass the midbus probe footprint JP1 and CM1 and connects to Lane 0 to lane 3 of this connector. Depending on the port configuration, port 1 at connector SLOT 2 can be a downstream port, upstream port or an NT port. Power is provided to this connector from the ATX hard disk power connector J1 through the power MOSFETs which are controlled by the Serial Hot-Plug Controller of the PEX 8616 (see Section X2.5.2 X for details).
2.2.5 34BPCI Express Edge Card Connector SLOT 3
(Connector SLOT 3 is not used.)
2.2.6 35B4X Mini-SAS Connector IP1
PEX 8616 only supports Non-Transparent (NT) mode on Port 0 or Port 1 of Station 0. The 4X mini-SAS connector IP1 provides the simplified connections for the customers to connect the PEX 8616 RDK to two PC motherboards. When the Configuration Module 1 is plugged into the CM1 receptacle, lanes 4-7 from the PEX 8616 pass the midbus probe footprint JP1 and CM1 and connects to the 4X mini-SAS connector IP1. Depending on the port configuration, Port 1 at connector IP1 can be set as a downstream port, upstream port or an NT port. XFigure 2-3X shows a set up using PEX 8616 RDK’s NT function. Either Motherboard A or B can be connected to an upstream port or NT port of the PEX 8616.
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 7
P1
PEX 8616
Lane 0-3
Lane 4-7
PC Motherboard (A)PC Motherboard (B)
PEX 8616RDK
Cable Card4 x Mini- SAS
cable
Port 0
Port 1
Figure 2-3. Use mini-SAS Connector for NT Function Setup
2.3 10BReference Clock Circuitry
The PEX 8616 RDK reference clock circuitry contains a one-to-four differential clock fan out buffer (U2) from SpectraLinear (CY28400-2). The clock fan out buffer supports four 100 MHz PCI Express reference clocks with the option for constant frequency and spread spectrum outputs. When the RDK is plugged into a PCI Express slot of a PC motherboard, the differential reference clock input to the fan out buffer is taken from the PCI Express card-edge connector (P1), and the differential clock outputs are distributed to the PEX 8616 reference clock input (PEX_REFCLKP/PEX_REFCLKN), downstream slot connectors (SLOT 1 and SLOT 2), and the reference clock header J2. The 3-pin reference clock header (J2) provides a reference clock input which is to be used in conjunction with the midbus probe(s). The reference clock outputs from the fan out buffer (U2) to SLOT1 and SLOT 2 are controlled by the parallel Hot-Plug circuit and the Serial Hot-Plug circuit respectively. (See XFigure 2-4X and Section X2.5 X for details)
Figure 2-4. PEX 8616 RDK Reference Clock Circuit
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 8
2.4 11BReset Circuitry
The PEX 8616 RDK reset circuitry includes a MAX6420 adjustable reset timer (U9), a Fairchild 2-input AND gate NC7S08 (U8) and manual reset push-button switch (S1). The reset timer accepts PERST# from the card edge (P1) and from S1 (logical-OR via U8). The MAX6420 has the capability of adjusting the reset timeout period by changing the value of C70 (0.001F ≈ 3ms). (See XFigure 2-5X for details)
Slot 1
Slot 2
PEX8616
PERST# from PCIe Card Edge
Connector P1
R
3.3V
R
3.3V
S3
PCI Express Edge Card Connectors
NC7S08 MAX6420(U9)
R
3.3V
(U1)
NC7S08(U8)
C70
x8
x4
Slot 3Not Use
Figure 2-5. PEX 8616 RDK Reset Circuit
2.5 12BHot-Plug Circuits
PEX 8616 provides on-chip Parallel Hot-Plug controllers to downstream ports 1 and 5. The remaining downstream port is also Hot-Plug capable through the use of the I2C bus and external I/O expander devices. The PEX 8616 RDK implements Hot-Plug control circuitry for SLOT 1 and SLOT 2. SLOT 1 uses the on-chip parallel Hot-Plug controller while SLOT 2 uses the Serial Hot-Plug control capability through the I2C and I/O expander. Note that additional device configuration is required when using the Serial Hot-Plug capability. (See Section 2.5.2 and HUPEX 8616 Data Book UH for details).
2.5.1 36BParallel Hot-Plug Controller Circuit
PEX 8616 RDK uses the Parallel Hot-Plug controller on Port 5 for PCI Express connector SLOT 1. The parallel Hot-Plug controller consists of five input elements (HP_BUTTON_B#, HP_MRL_B#, HP_PRSNT_B#, HP_PWR_GOOD_B, HP_PWRFLT_B#) and five output elements (HP_ATNLED_B#, HP_CLKEN_B#, HP_PERST_B#, HP_PWREN_B, HP_PWRLED_B#).
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 9
PCI ExpressSLOT 1
VCC
System power supply
12V, 3.3V
VCC
VCCHot plug controller
FETs
Hp_clken_b#
Hp_atnled_b#Hp_pwrled_b#
Hp_pwren_b
Hp_perst_b#
Hp_button_b#
Hp_pwrflt_b#
Hp_mrl_b#Hp_prsnt_b#
Hp_pwr_good_b
S2
D6 D7
TPS2311(U6)
Pos1/SW3
Quad 2-to-1 Mux(U7)
SN74LVC157
x8
Pwren
Perst#
RefclkFrom refclk buffer (U2)
Refclk
VCC
Pos2/SW3HP_SL1_CTL
PEX 8616(U1)
3.3V_SL1D8
12V_SL1D9VCC VCC
VCC VCC
Refclk Buffer
Clken#
Fault
Pwrgd1&2
Prsnt2#
Figure 2-6. PEX 8616 RDK Parallel Hot-Plug Circuits
XFigure 2-6X shows the parallel Hot-Plug circuit. It includes a low cost TI dual hot–swap power controller TPS2311 (U6), a quad 2-to-1 multiplexer SN74LVC157 (U7), two International Rectifier power MOSFET IRF7470 (Q3 and Q4), LEDs, manual switch, dipswitch and resistors. The manual switch (S1) connects to the HP_BUTTON_B# input of the PEX 8616. It is used to generate the active low Hot-Plug attention button signal to the parallel Hot-Plug controller. LEDs D6 and D7 represent the HP_ATNLED_B# (the attention LED) and HP_PWRLED_B# (power LED) respectively on the parallel Hot-Plug controller. The PRSNT2# signal from SLOT 1 connects to the HP_PRSNT_B# signal on the parallel Hot-Plug controller. This signal is used to detect when a PCI Express adapter card is plugged into the connector SLOT 1. SW3 (position 1) is used to emulate the manually operated retention latch sensor input HP_MRL_B# to the parallel Hot-Plug controller. When set to “ON” position, the internal state machine of the parallel Hot-Plug controller is enabled. SW3 (position 2) is used to enable the power and clock to SLOT 1. When set to the “ON” position, the active low signal HP_SL1_CTL on the multiplexer (U7) will select HP_PWREN_B# to enable the hot-swap power controller (U6), HP_CLKEN_B# to enable the RefClk output to connector SLOT 1, and the reset signal HP_PERST_B# to connector SLOT 1. Inversely when set to the “OFF” position (SW3 position 2), the active high signal HP_SL1_CTL will bypass the Hot-Plug control outputs from the parallel Hot-Plug controller and select another set of outputs to enable the hot-swap power controller (U6), and enable the RefClk output and PERST# to connector SLOT 1.
When enabled, the hot-swap power controller (U6) monitors the 12V and 3.3V voltage supplies to SLOT 1. When current levels exceed 5A, HP_PWRFLT# becomes active. Similarly, HP_PWR_GOOD_B will be pull high with external pull-up resistor when normal voltage levels are detected.
Two additional LEDs, D8 and D9, are used to indicate 3.3V and 12V power at the connector SLOT 1.
2.5.2 37BSerial Hot-Plug Controller Circuits
PEX 8616 RDK also implements the serial Hot-Plug controller circuitry to PCI Express SLOT 2. By default, the RDK is configured to bypass the serial Hot-Plug controller. Note that additional configuration on the PEX 8616 might be required in order to use the serial Hot-Plug controller. In order to configure Port 1 at PCI Express SLOT 2 as a Serial Hot-Plug port with Port 0 configured as a x4 upstream port, use the EEPROM to write 2’b00 to the bit [14:13] of station 0’s Parallel Hop-Plug capable configuration register at offset 1E0h.
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 10
x4
Figure 2-7. PEX 8616 RDK Serial Hot-Plug Circuits
The serial Hot-Plug controller consists of an I/O expander (MAX 7311 (U3)), a dual hot–swap power controller (TPS2311 (U4)), a quad 2-to-1 multiplexer (SN74LVC157 (U5)), two power MOSFET IRF7470 (Q1 and Q2), LEDs, manual switch, dipswitches and resistors. The PEX 8616 master I2C interface is designed for the specific control use of the serial Hot-Plug controller. The master I2C interface connected to the I/O expander and the interrupt output from the I/O expander connects to the SHPC_INT# of the PEX 8616. When power is applied to the PEX 8616, the master I2C interface will scan the bus and attempts to detect the presence of the I/O expander. If an I/O expander is detected, the I2C master will program it as a “remote parallel Hot-Plug controller” and assign an available serial Hot-Plug port to the I/O expander. (see Section X2.5.1 X, XFigure 2-6X and XFigure 2-7X for details).
The RDK also provides dipswitches for setting the SLTID [3:0], a test point for access the GPIO pin, and three pull-down resistors to set AD [2:0] of the I/O expander U3. The LEDs D1 and D2 are 12V and 3.3V power indicators when power reaches PCI Express connector SLOT 2.
2.6 13BSerial EEPROM
The PEX 8616 RDK contains an 8-pin DIP socket for a serial EEPROM (U17). The board is populated with a blank On Semi CAT25080LI-G 32-Kbit device. The CAT25080LI-G device can directly interface to the PEX8616. When programmed correctly, the serial EEPROM can be used to change the default configuration of the PEX 8616. A blank EEPROM results in the default register values set in the PEX 8616. Please refer to the Software Development Kit (SDK) documentation for additional information on how to program the serial EEPROM.
2.7 14BI2C Interface
The PEX 8616 implements an I2C slave interface (I2C port 0), which allows an external I2C master to read and write device registers through an out-of-band mechanism. The PEX 8616 I2C interface is accessible via a 7-bit address, at data rates from 100 Kbps up to 3.4 Mbps. The RDK provides two cascaded 2x2, 0.1” pitch headers (JP5 and JP6), which interface to the PEX 8616’s I2C port. That allows for cascading multiple RDKs together using standard ribbon cable, and/or connecting to an I2C master such as the Total Phase Aardvark I2C controller. (See Section X3.6 X for pin assignment of JP5 and JP6.)
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 11
2.8 15BPower Distribution
The PEX 8616 RDK has two sources of DC power. The first source is the card edge connector (P1). The x8 connector provides up to 2.1A at 12V and 3.0A at 3.3V from the PCI Express edge card connector it plugs in. The power from P1 is intended to power the PEX 8616, PCI Express connector SLOT 2, and the on-board electronic components. The dc/dc converter U12 converts 12V from the Card Edge connector to 1.0VCC to support the SerDes and core power of the PEX 8616. The LDO U13 converts 3.3V to 2.5VCC to support the I/O power of the PEX 8616.
The second source of power includes an ATX HD power connector J1, and a 5V to 3.3V step down dc/dc converter U11. Through controlled power MOSFETS, connector J1 provides 12VCC up to 5A to each of PCI Express Edge Card Connectors SLOT 1 and SLOT 2. The J1 also provides enough 5V power for the dc/dc converter U11 to generate 3.3VCC up to 3A for each of SLOT 1 and SLOT 2 (See XFigure 2-8X for details).
12V
_A
5V_A
Figure 2-8. PEX 8616 RDK Power Subsystem
2.9 16BLED Indicators
The PEX 8616 RDK provides a number of LED indicators including power-on indication, PEX 8616 port link status indication, Hot-Plug LED indication, fatal error indication, event/error indication, and voltage level monitoring indications. XTable 2-1X below provides a quick explanation of the various board indicators.
Table 2-1. PEX 8616 RDK LED Indicator descriptions
Indicator Type Locations LED Functions
Slot Power LED/green color D1 On: 12V at PCI Express connectors SLOT 2
D2 On: 3.3V at PCI Express connectors SLOT 2
Slot Power LED/green color D8 On: 12V at PCI Express connectors SLOT 1
D9 On: 3.3V at PCI Express connectors SLOT 1
SERIAL HOT-PLUG LED/green color
D3 On: HP power LED output active at port 1
D4 On: HP Attention LED output active at port 1
D5 On: HP interlock output active at port 1
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 12
Indicator Type Locations LED Functions
PARALLEL HOT-PLUG LED/green color D6 On: HP Attention LED output active at port 5
D7 On: HP power LED output active at port 5
Slot Power LED/green color D8 On: 12V at PCI Express connectors SLOT 1
D9 On: 3.3V at PCI Express connectors SLOT 1
Voltage level monitoring / bi-color LED D10 Monitor 2.5V to PEX 8616 (see XTable 2-3X for details)
D11 Monitor 1V to PEX 8616 (see XTable 2-3X for details)
Slot 1-2 Power LED/green color
D12 On: 12V at ATX HD power connector J1
D14 On: 5V at ATX HD power connector J1
D16 On: 3.3V at dc/dc converter U11 output
Board Power LED/green color D13 On: 12V at edge card connector P1
D15 On: 3.3V at edge card connector P1
PEX 8616 Port Link Status LED (driven by PEX_PORT_GOOD pins) /green color
D19 Port 0 speed and link activity (see XTable 2-2X for details)
D20 Port 1 speed and link activity (see XTable 2-2X for details)
D18 Port 5 speed and link activity (see XTable 2-2X for details)
D17 Port 6 speed and link activity (see XTable 2-2X for details)
D21 Not used
D22 Not used
INTA# of PEX 8616/green color D23 On: event/error occurs
FATAL_ERR#/red color D24 On: error(s) occurs (see Data Book)
2.9.1 38BPort Link Status Indication (D17 – D20)
The PEX 8616 RDK provides up to four green color link status LEDs, D17 to D20, to indicate its port 0, 1, 5 and 6 link states. LED on, off, and three blinking patterns cover all five states of port link status. (See XTable 2-2X for details)
Table 2-2. Port Link Status LED Functions
Port Link State LED Pattern Link down off
Link up, 5Gbps, all lanes are up on
Link up, 5Gbps, reduced lanes are up Blinking: 0.5 second on, 0.5 second off
Link up, 2.5Gbps, all lanes are up Blinking: 1.5 second on, 0.5 second off
Link up, 2.5Gbps, reduced lanes are up Blinking: 0.5 second on, 1.5 second off
2.9.2 39BFatal Error Indication (D24)
The PEX 8616 provides an output status pin (FATAL_ERR#) which reports the event of a PCI Express fatal error condition. The RDK connects this output to a red LED (D24) which is lit when a fatal error condition is detected. Examples of fatal error conditions are data link layer protocol errors, receiver overflow and malformed TLPs. The PCI Express Base specification provides a complete listing of fatal error conditions. The HUPEX 8616 Data BookUH also provides additional details on the assertion of FATAL_ERR#.
2.9.3 40BPEX_INTA Interrupt Indication (D23)
The PEX 8616 provides an output status pin (PEX_INTA#) for signaling various programmable events. The RDK connects this output to a green LED (D23) for this interrupt output. Please refer to the HUPEX 8616 Data Book UH for additional information on the programmable events for PEX_INTA#.
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2.9.4 41BPEX 8616 Voltage Level Monitoring (D10 – D11)
The PEX 8616 RDK provides voltage level monitoring circuit to monitor the 1 volt and 2.5 volt power to the PEX 8616. The circuit contains an Intersil multiple voltage supervisory ISL6132, two bi-color LEDs, D10 and D11, and various value resistors. When the 1 volt or 2.5 volt is within the +/- 10% range the green LED will turn on. Otherwise the red LED will be on. (See XTable 2-3X for details)
Table 2-3. Voltage Level Monitoring LED Functions
LED Green LED on/ Red LED off Green LED off/Red LED on D8 1 volt to PEX 8616 within +/- 10% range 1 volt to PEX 8616 out of +/- 10% range
D9 2.5 volt to PEX 8616 within +/- 10% range 2.5 volt to PEX 8616 out of +/- 10% range
2.10 17BGPIO Pins
The PEX 8616 has twenty GPIO pins. Four are configured for port link status drivers and remain GPIO pins are connected to mictor connectors (MC1 and MC2) to be used by external applications.
2.11 18BReserved Pins
The PEX 8616 has 9 STRAP_RESERVED pins. They are factory use only and should be set to know logic states. XTable 2-4X shows the list of these reserved pins and their connections in the RDK.
Table 2-4. Strap_Reserved Pin Connections
Name Pin Location Connections on PEX 8616 RDK
STRAP_SESERVED0 J4 Pull-up with a 4.7K ohm resistor
STRAP_SESERVED1 P2 Pull-down with a 1K ohm resistor
STRAP_SESERVED2 K5 Pull-up with a 4.7K ohm resistor
STRAP_SESERVED3 E2 Pull-down with a 1K ohm resistor
STRAP_SESERVED4 V12 Pull-down with a 1K ohm resistor
STRAP_SESERVED7 F3 Pull-up with a 4.7K ohm resistor
STRAP_SESERVED8 E12 Pull-down with a 1K ohm resistor
STRAP_SESERVED9 B12 Set dipswitch to “OFF” position
STRAP_SESERVED13 D12 Set dipswitch to “ON” position
STRAP_SESERVED16 T13 Pull-down with a zero ohm resistor
STRAP_SESERVED17# D18 Set DIP switch to OFF (logic ‘HIGH’)
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 14
3. 4BOn-Board Connectors, Switches, and Jumpers
3.1 19BDIP Switches
The PEX 8616 RDK contains nine user controllable DIP switches (SW1-SW8) for selecting the slot ID for the serial Hot-Plug, enable/disable Hot-Plug signals, enable/bypass the serial Hot-Plug and parallel Hot-Plug, upstream port select, port configuration, NT upstream port select, I2C address settings and test mode settings. The dipswitches are presented following the orientations shown in XFigure 3-1X.
3.1.1 42BSlot ID Selection (SW1)
Figure 3-1. Switch SW1 Default Settings
Switch SW1 is used to set the slot ID for the PCI Express SLOT 2. Users can select one of 16 combinations.
3.1.2 43BSerial Hot-Plug Signal and Control (SW2)
Figure 3-2. Switch SW2 Default Settings
Table 3-1. Switch SW2 Description
SW2 Functional Description Switch Position Settings
Enable/bypass SERIAL HOT-PLUG outputs to generate power, RefClk
and PERST#, to connector SLOT 2
Position 2 ON: enable SERIAL HOT-PLUG outputs to generate power, RefClk and PERST# to SLOT 2 OFF: bypass SERIAL HOT-PLUG and still provide power, RefClk and PERST# to SLOT 2
Enable/disable MRL#_S at Serial Hot-Plug
Position 1 ON: enable MRL#_S OFF: disable MRL#_S
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 15
3.1.3 44BParallel Hot-Plug Signal and Control (SW3)
Figure 3-3. Switch SW3 Default Settings
Table 3-2. Switch SW3 Description
SW2 Functional Description Switch Position Settings
Enable/bypass PHP outputs to generate power, RefClk and
PERST#, to connector SLOT 1
Position 2 ON: enable SERIAL HOT-PLUG outputs to generate power, RefClk and PERST# to SLOT 1 OFF: bypass SERIAL HOT-PLUG and still provide power, RefClk and PERST# to SLOT 1
Enable/disable HP_MRL_B# at Parallel Hot-Plug
Position 1 ON: enable HP_MRL_B# OFF: disable HP_MRL_B#
3.1.4 45BDC/DC Converter and Mode Controls (SW4)
Figure 3-4. Switch SW4 Default Settings
Switch SW4 is for PLX internal test only. Changing the settings for SW4 is not recommended.
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 16
3.1.5 46BUpstream Port Select (SW5)
SW5
USPT_SEL0 ON
HIGH LOW
1
RSV_13 ON
USPT_SEL2 ON
default
USPT_SEL1 ON
Figure 3-5. Switch SW5 Default Settings
Table 3-3. Switch SW5 Description
SW5 Functional Description Switch Position Settings
Strap Upstream Port Select
1: USPT_SEL0 2: USPT_SEL1 3: USPT_SEL2
4: RSV_13
UPSTREAM PORT USPT_SEL[2:0]
0 ON,ON,ON
1 ON,ON,OFF
5 OFF,ON,OFF
6 OFF,OFF,ON
3.1.6 47BPort Configuration and NT Upstream Port Select (SW6)
SW6
STN0_PCFG1 OFF
HIGH LOW
11
ON
23
4 NT_USPT_SEL0 ON
RSV_9 OFF
default
STN1_PCFG0 OFF
56
NT_USPT_SEL1 ON
NT_ENABLE# OFF
Figure 3-6. Switch SW6 Default Settings
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 17
Table 3-4. Switch SW6 Description
SW5 Functional Description Switch Position Settings
Strap Port Configuration & NT Upstream Port Select
1: STN0_PCFG1 2: STN1_PCFG0 3: RSV_9 4: NT_USPT_SEL0 5: NT_USPT_SEL1 6: NT_ENABLE#
a. Strap Port Configuration
Strap Pin Name Setting Port Configurations
STN0_PCFG1 ON X4X4
OFF X8
STN1_PCFG0 ON X8
OFF X4X4
b. NT Upstream Port Select When NT Port Enable (NT_ENABLE# :ON), NT port select are:
Strap Pin Name Setting NT Port
NT_USPT_SEL[1:0] ON, ON Port 0
ON, OFF Port 1
3.1.7 48BTest Mode Select (SW7)
1 ON
23
4
Figure 3-7. Switch SW7 Default Settings
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 18
Table 3-5. Switch SW7 Description
SW7 Functional Description
Switch Position Settings
Strap Test Mode Select
1: TMODE0 2: TMODE1 3: TMODE2 3: TMODE3
TMODE[3:0] Description of Functions
OFF,OFF,OFF,OFF All PEX_PORT_GOOD pins became GPIO pins
OFF, ON,OFF,OFF All PEX_PORT_GOOD pins are used for port link status
outputs
OFF,OFF,ON,ON PEX_PORT_GOOD and GPIO pins are programmed for different functions
(see the HUPEX 8616 Data BookUH for details) OFF,OFF,ON,OFF
3.1.8 49BI2C Address and Other Mode Select (SW8)
SW8
SERDES_MODE# OFF
HIGH LOW
11
ON
23
4 I2C_ADD0 ON
RSV_17# OFF
default
PROBE_MODE# OFF5
6
I2C_ADD1 ON
I2C_ADD2 ON
Figure 3-8. Switch SW8 Default Settings
Table 3-6. Switch SW8 Description
SW8 Functional Description Switch Position Settings
Other Mode Settings a. SERDES_MODE# relates to STRAP_SERDES_MODE_EN# pin b. PROBE_MODE# relates to STRAP_PROBE_MODE# pin c. RSV_17# relates to STRAP_RESERVED17# pin
1: SERSES_MODE# ON: For PLX use only OFF: For normal operation 2: PROBE_MODE# ON: For PLX use only OFF: For normal operation 3: RSV_17# ON: For PLX use only OFF: For normal operation
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SW8 Functional Description Switch Position Settings
PEX 8616 I2C Address bits[2:0]. Default setting is 000b.
4: I2C_ADDR[0] 5: I2C_ADDR[1] 6: I2C_ADDR[2]
I2C_ADD[2:0] PEX 8616 I2C Slave Address
ON,ON,ON 68h
ON,ON,OFF 69h
ON,OFF,ON 6Ah
ON,OFF,OFF 6Bh
OFF,ON,ON 6Ch
OFF,ON,OFF 6Dh
OFF,OFF,ON 6Eh
OFF,OFF,OFF 6Fh
3.2 20BPush-Button Switches
3.2.1 Manual Reset# (S1)
The PEX 8616 RDK provides a manual switch (S1) for manual PERST# capability. Note that manual PERST# will only apply warm reset to the PEX 8616 as well as SLOT 1 to SLOT 2.
3.2.2 Serial Hot-Plug Controller Attention Button (S2)
The PEX 8616 RDK provides a manual switch S2 for the attention button to the serial Hot-Plug circuit. When pushed and released, the switch generates an active low pulse to the Attention Button Input of the serial Hot-Plug controller.
3.2.3 Parallel Hot-Plug Controller Attention Button (S3)
The PEX 8616 RDK provides a manual switch S3 for attention button to the parallel Hot-Plug circuit. When pushed and released, the switch generates an active low pulse to the Attention Button Input of parallel Hot-Plug controller.
3.3 21BMidbus probe footprints (JP1 – JP2)
The PEX 8616 RDK provides two strategically placed midbus probe footprints. Each footprint provides 16 channels and each can support eight PCI Express lanes. The midbus footprints are based on Agilent’s Soft Touch Midbus Probe, as shown in XFigure 3-9X, and can be used with Agilent, LeCroy as well as Tektronix retention mechanism. XTable 3-7X below shows the signal names of x8 PCI Express midbus probe footprint and XTable 3-8X shows the PCI Express lanes of the PEX 8616 and their midbus probe footprints.
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 20
Figure 3-9. Midbus 2.0 footprint Dimensions, pin numbering and specification (Copied from Agilent’s document)
Table 3-7. Signal Names of x8 PCI Express Midbus probe footprint
Pin # Signal Name Pin # Signal Name
G1 GND
2 GND 1 C0p-Upstream
4 C0p-Downstream 3 C0n-Upstream
6 C0n-Downstream 5 GND
8 GND 7 C1p-Upstream
10 C1p-Downstream 9 C1n-Upstream
12 C1n-Downstream 11 GND
14 GND 13 C2p-Upstream
16 C2p-Downstream 15 C2n-Upstream
18 C2n-Downstream 17 GND
20 GND 19 C3p-Upstream
22 C3p-Downstream 21 C3n-Upstream
24 C3n-Downstream 23 GND
26 GND 25 C4p-Upstream
28 C4p-Downstream 27 C4n-Upstream
30 C4n-Downstream 29 GND
32 GND 31 C5p-Upstream
34 C5p-Downstream 33 C5n-Upstream
36 C5n-Downstream 35 GND
38 GND 37 C6p-Upstream
40 C6p-Downstream 39 C6n-Upstream
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Pin # Signal Name Pin # Signal Name
42 C6n-Downstream 41 GND
44 GND 43 C7p-Upstream
46 C7p-Downstream 45 C7n-Upstream
48 C7n-Downstream 47
G2 GND
Table 3-8. Midbus probe footprints VS. Lanes of PEX 8616
Midbus Probe Footprint Lanes of PEX 8616
JP1 Lane 0 – Lane 7
JP2 Lane 24 – Lane 31
3.4 22B2.5V Header (JP3)
This 2-pin header provides the mechanism for 2.5 volt measurement, which is for PLX use only. For regular RDKs, no header will be assembled and instead a wire will be used to connect pin 1-2 of JP7.
3.5 23BJTAG Header (JP4)
The 2x5 header JP4 provides a direct connection to the PEX 8616 JTAG interface. The 10-pin connector is designed to allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E controller. The pin assignment for the JTAG header (JP4) is listed at XTable 3-9 X.
Table 3-9. Pin assignment of JP4
Pin # Signal name
1 JTAG_TRST
3 JTAG_TDI
5 JTAG_TDO
7 JTAG_TMS
9 JTAG_TCK
2,4,6,8,10 GND
3.6 24BI2C Port (JP5 – JP6)
(See Section X2.7 X for details)
Table 3-10. Pin assignment of JP5 and JP6
Pin # Signal name 1 I2C_SCL
2 GND
3 I2C_SDA
4 NC
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3.7 25BATX HD Power Connector (J1)
(See Section X2.8 X for details)
Table 3-11. Pin assignment of J1
Pin # Signal name 1 +12VDC
2 COM (GND)
3 COM (GND)
4 +5VCC
3.8 26BReference Clock Header (J2)
(See Section X2.3 X for details)
Table 3-12. Pin assignment of J2
Pin # Signal name
1 RefClkp (+)
2 GND
3 RefClkn (-)
3.9 27BProbe Mode Input Header (J3)
This is for PLX use only.
Table 3-13. Pin assignment of J3
Pin Number Signal Name In Schematics 1 GND
2 DB_SEL0_I
3 PWRFLT_B#_I
4 DB_SEL1_I
5 MRL_B#_I
6 PRSNT_B#_I
7 BUTTON_B#_I
8 GND
9 MRL_C#_I
10 BUTTON_C#_I
11 PWRFLT_C#_I
12 PRSNT_C#_I
13 GND
14 PWRGD_A_I
15 PWRGD_B_I
16 MRL_A#_I
17 BUTTON_A#_I
18 PWRFLT_A#_I
19 PRSMT_A#_I
20 GND
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 23
3.10 28BPLX Use Header (J4)
This is for PLX use only.
Table 3-14. Pin assignment of J4
Pin Number Signal Name In Schematics 1 SPARE2_O
2 SPARE1_IO
3 STRAP_RESERVED16
4 GND
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4. 5BBill of Materials/ Schematics
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 25
Item Number Quantity Manufacturer
Manufacturer's Part Number Description Package Type
Component Designator(s)
Distributor Part Number
SURFACE MOUNT COMPONENTS
1 1 PLX PEX8616-AA50BC F
IC, PCI Express Gen2 switch, 16 lane and up to 4 ports
SMT 324-pin BGA,
19x19mm,1mm pitch
U1
2 1 SpectraLinear CY28400OXC-2 IC, 100MHz Differential Clock Buffer
SMT, 28-pin SSOP
U2 408-855-0555 fax: 408-855-
0550
3 1 Maxim MAX7311AUG
IC, 2 wire interface 16-bit IO port expander with interrupt and hot insertion protection
SMT, 24-pin TSSOP
U3
4 2 TI TPS2311IPW IC, Dual-power Hot Plug Controller, active high enable,
SMT, 20-lead TSSOP
U4, U6
5 2 TI SN74LVC157AP
W
IC, quadruple 2-line to 1-line data selectors/multiplexers
SMT, 16-pin TSSOP
U5,U7
Mouser: pn: 595-
SN74lvc157APW
6 1 Fairchild NC7S08M5X IC, Tiny Logic 2-input AND gate
SMT, 5-pin SOT-23
U8
7 1 Maxim MAX6420UK29-
T IC, Reset controller, Adj. reset timeout
SMT, SOT23-5 U9
8 1 Intersil ISL6132IR IC, multiple voltage supervisory
SMT, 4mmx4mm QFN
package U10
9 2 Belfuse S7AH-08E1A0 IC, Non-iso DC/DC converter, 4.5-14V-to-0.8/3.63V @ 8A
SMT, 7-pin U11-U12
10 1 Micrel MIC37100-
2.5BS
IC, LDO linear regulator, output: 2.5V@1A
SMT, SOT-223 U13
11 2 TI SN74CBTLV324
5APWR IC, low voltage 8-bit FET bus switch, 3.3V
SMT,20-pin TSSOP
U14-U15
Mouser: pn: 595-
SNCBTLV3245APWR
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 26
Item Number Quantity Manufacturer
Manufacturer's Part Number Description Package Type
Component Designator(s)
Distributor Part Number
12 1 TI SN74CB3T3306
DCTR IC, low voltage 2-bit FET bus switch, 3.3V
SMT, 8-pin SSOP
U16
Mouser pn: 595-
SN74CB3T3306DCTR
13 3 ITTCANON TDA02H0SK1 Dip Switch, 2-pos, half pitch
SMT, dual in line SW2-SW4, CKN1362-ND
14 1 ITTCANON TDA04H0SK1 Dip Switch, 4-pos, half pitch,
SMT, dual in line SW1 CKN1364-ND
15 2 ITTCANON SDA04H1SKD Dip Switch, 4-pos, 1mm pitch
SMT, dual in line SW5,SW7 CKN1288-ND
16 2 ITTCANON SDA06H1SKD Dip Switch, 6-pos, 1mm pitch
SMT, dual in line SW6,SW8 CKN1290-ND
17 1 FCI 84517-101LF Connector, MEG-Array receptacle, 10x20 pos, 4mm
SMT,200 pos, 1.27mm pitch
CM1
18 4 International
Rectifier IRF7470
IC, N-Channel MOSFET
SMT, 8-pin, SO-8
Q1-Q4
19 21 Chicago Miniature
Lamp CMDA5CG7D1Z
LED, green, Vf=2.1V, 20mA,
SMT 0805 D1-D9,D12-D23
20 2 Chicago Miniature
CMD15-22SRUGC
LED, bi-color LED, green-red
SMT, 4-pins D10-D11
21 1 Chicago Miniature
Lamp CMDA5DR7D1Z
LED, red, Vf=1.7V, 20mA,
SMT 0805 D24
22 1 Molex MOL75783-
0036
Connector, right angle with shell 0.8mm pitch for mini-SAS,4x 26 CKT internal cable,
shell TH, SMT 26-pin connector
IP1
23 1 Adex CONN-PCIEXP-
16X-SM
PCI Express x16 straddle-mount connector
SMT, 164-pin SLOT1
24 3 Omron B3S1002 Switch, Push Button SMT S1-S3
30 1 Kemet C0603C102J5RACTU
Cap. Ceramic, 0.001uF, X7R, 50V 5%
SMT, 0603 C70 399-1083-2-
ND
31 5 Kemet C0603C103J5R
AC Cap, Ceramic, 0.01uF,50V 5%
SMT, 0603 C58-C60,C89-
C90,
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 27
Item Number Quantity Manufacturer
Manufacturer's Part Number Description Package Type
Component Designator(s)
Distributor Part Number
32 2 Muurata GRM033R60J22
3KE01D
Cap. Ceramic 0.022uF 6.3V X5R 10%
SMT 0201 C95-C96 490-3169-1-
ND
33 2 Murata GRM033R60J33
3KE01D
Cap. Ceramic 0.033uF 6.3V X5R 10%
SMT 0201 C97-C98 490-3170-1-
ND
34 1 Murata GRM033R71C1
02KD01D
Cap, Ceramic 0.001uF,16V X7R, 10%
SMT 0201 C99 490-1261-1-
ND
35 5 Murata GRM033R61A1
03KA01D Cap, Ceramic, 0.01uF,X5R,10V 10%
SMT, 0201 C93-C94,C107-
C109 490-3166-1-
ND
36 5 Panasonic ECJ-
ZEB1A104M Cap, Ceramic, 0.1uF, X5R, 10V, 20%
SMT, 0201 C100-C102,C110-
C111 PCC2424CT-
ND
37 54 Kemet C0402C104K4R
ACTU Cap. Ceramic, 0.1uF, X7R, 16V, 10%
SMT, 0402 C1-C8,C15-C46, C49-C56, C85-C88,C91-C92
38 7 AVX 0603YC104KAT
2A Cap, Ceramic, 0.1uF, X7R, 16V, 10%
SMT, 0603 C62-C64,C66-
C68, C71
39 8 AVX 0603YD105KAT
2A Cap, Ceramic, 1uF, X5R, 16V, 10%
SMT. 0603 C65,C69,C73,C75,C77,C79,C82,C8
3,
40 12 AVX 1206YD106KAT
2A Cap, Ceramic, 10uF,X5R, 16V, 10%
SMT, 1206 C57,C61,C78,C81,C84, C103-C106,
C112-C114
41 10 AVX
Corporation TAJB226K020R
Cap. Tantalum, 22uF, 20V 20%
SMT, B-case C9-C14,C47-C48,C72,C74,
60 1 CTS 742C083102J Chip Res. Array, 1K ohm, 5%, 4R isolated
SMT RN4
61 7 CTS 742C083472J Chip Res. Array, 4.7K ohm, 5%, 4R isolated
SMT RN1-RN3, RN5-
RN8
62 4 TTelectronics LRF2512-LF-
R020-F Res. 2W, 0.02 ohm 1%
SMT, 2512 R32,R35,R41,R44
63 1 Panasonic ERJ-
3GEYJ4R7V Res. 1/10W, 4.7 ohm 5%
SMT, 0603 R4
64 4 Panasonic ERJ-
3GEY0R00V Res. 1/10W, zero ohm 5%
SMT, 0603 R56,R58,R86,R89
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 28
Item Number Quantity Manufacturer
Manufacturer's Part Number Description Package Type
Component Designator(s)
Distributor Part Number
65 8 Panasonic ERJ-2GEJ330X Res. 1/16W, 33 ohm 5%
SMT 0402 R7-R8,R11-
R12,R15-R16, R19-R20,
66 8 Panasonic ERJ-
2RKF49R9X Res. 1/16W, 49.9 ohm 1%
SMT 0402 R9-R10,R13-R14,R17-R18,
R21-R22,
67 16 Panasonic ERJ-
6GEYJ151V Res. 1/18W, 150 ohm 5%
SMT 0805
R26-R27,R31,R51,
R53-R54, 79-R85, R98,R121-R122,
68 1 Panasonic ERJ-
6GEYJ361V Res. 1/8W, 360 ohm, 5%
SMT, 0805 R78
69 1 Panasonic ERJ-
3EKF4750V Res. 1/16W, 475 ohm 1%
SMT 0603 R6
70 12 Panasonic ERJ-
3GEYJ102V Res. 1/10W, 1 K ohm, 5%
SMT, 0603
R23-R25,R38, R47, R103-
R104,R106-R107, R125, R127-R128
P1.0KGCT-ND
71 4 Panasonic ERJ-
6GEYJ122V Res. 1/8W, 1.2K ohm, 5%
SMT 0805 R30,R50,R76-R77
72 4 Panasonic ERJ-
3EKF2001V Res. 1/10W, 2.0K ohm, 1%
SMT, 0603 R33-R34,R42-
R43,
73 33 Panasonic ERJ-
3GEYJ472V Res. 1/10W, 4.7K ohm, 5%
SMT, 0603
R1-R3,R5,R29, R36-R37,R39-R40,R45-R46, R48-R49,R52,
R66-R67,R72,R87-
R88, R101-R102,R105,R111-
R116, R119-R120,R123,R129-
R130
74 1 Panasonic ERJ-
3GEYJ512V Res. 1/10W, 5.1K ohm, 5%
SMT, 0603 R59 P5.1KGCT-ND
75 3 Panasonic ERJ-
3GEYJ103V Res. 1/10W, 10K ohm, 5%
SMT 0603 R55,R117-R118
76 1 Panasonic ERJ-
3GEYJ513V Res. 1/10W, 51K ohm 5%
SMT, 0603 R57
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 29
Item Number Quantity Manufacturer
Manufacturer's Part Number Description Package Type
Component Designator(s)
Distributor Part Number
77 2 Yageo
America 90C6031A1242
FKHFT Res. 1/10W, 12.4K ohm, 1%
SMT, 0603 R91,R94
78 2 Yageo
America 90C6031A1372
FKHFT Res. 1/10W, 13.7K ohm, 1%
SMT, 0603 R92,R96
79 2 Yageo
America 90C6031A2002
FKHFT Res. 1/10W, 20K ohm, 1%
SMT, 0603 R90,R95
80 2 Yageo
America 9C06031A1003
FKHFT Res. 1/10W,100K ohm, 1%
SMT, 0603 R93,R97 311-
100KHCT-ND
81 1 Yageo
America 9C06031A4640
FKHFT Res. 1/10W, 464 ohm, 1%
SMT, 0603 R64 311-464HTR-
ND
82 1 Yageo
America 9C06031A1181
FKHFT Res. 1/10W, 1.18K ohm, 1%
SMT, 0603 R61 311-
1.18KHTR-ND
83 1 Yageo
America 9C06031A2321
FKHFT Res. 1/10W, 2.32K ohm, 1%
SMT, 0603 R65 311-
2.32KHTR-ND
84 1 Yageo
America 9C06031A3091
FKHFT Res. 1/10W, 3.09K ohm, 1%
SMT, 0603 R60 311-
3.09KHTR-ND
85 1 Yageo
America 9C06031A5761
FKHFT Res. 1/10W, 5.76K ohm, 1%
SMT, 0603 R62 311-
5.769KHTR-ND
86 1 Yageo
America 9C06031A7321
FKHFT Res. 1/10W,7.32K ohm, 1%
SMT, 0603 R63 311-
5.769KHTR-ND
87 1 Yageo
America 9C06031A1301
FKHFT Res. 1/10W,1.30K ohm, 1%
SMT, 0603 R74 311-
1.30KHTR-ND
88 1 Yageo
America 9C06031A3742
FKHFT Res. 1/10W,37.4K ohm, 1%
SMT, 0603 R75 311-
37.4KHCT-ND
89 3 Panasonic 9C06031A1431
FKHFT Res. 1/16W, 1.43K ohm 1%
SMT, 0603 R108-R110 311-
1.43KHCT-ND
90 1 Panasonic ERJ-
3GEYJ510V Res. 1/10W, 51 ohm 5%
SMT, 0603 R28 P51GCT-ND
91 1 Panasonic ERJ-
3GEYJ150V Res. 1/10W, 15 ohm 5%
SMT 0603 R124 P15GCT-ND
92 4 Panasonic ERJ-
6GEYJ391V Res. 1/18W, 390 ohm 5%
SMT 0805 R68-R71 P390ACT-ND
THROUGH-HOLE COMPONENTS
101 1 AMP 103240-5 Header, 2x5, 100mil pitch
2x5 th JP4 A26528-05-
ND
102 2 AMP 103240-2 Header, 2x2, 100 mil pitch
2x2 th JP5-JP6 A26528-02-
ND
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 30
Item Number Quantity Manufacturer
Manufacturer's Part Number Description Package Type
Component Designator(s)
Distributor Part Number
103 1 Molex 53113-0410 Connector, 4-pin right angle
6 hole, PCB mount
J1
104 1 AMP 103185-4 Header, 1x4, 100 mil pitch
1x4 th J4 A26513-04-
ND
105 2 Molex 87715-3302 Connector, PCI Express edge card connector, x16
164 pin, 4 row. TH
SLOT2-SLO3
106 2 Vishay 94SP187X0020
FBP Cap, solid aluminum, 180uF, 20V
F case C76,C80
107 1 Samtec ICA-308-S-TT Socket, 8-pin DIP
300 mil 8-pin DIP U17
MANUALLY INSERTED COMPONENTS
200 1 Om Semi CAT25080LI-G
IC, 1Kx8 SPI serial EEPROM, 1.8-5.5V, upto 10MHz, 8-pin
DIP
8-pin DIP U17
201 1 Keystone
Electronics 9203
PCI bracket w/ two tabs (cut 1.5" from the top)
202 1 Building
Fasteners PMSSS 440
0025 PH
Phillips Panhead screw, 4-40 thread, 0.25"
203 1 The Olander Company Inc
FWN-4-312-032 Nylon washer, #4x.312O.D.x.032THK
between the PCB and the tap of the
PCI bracket
Phone: 800-538-1500, fax:800-355-6515
MISCELLANEOUS COMPONENTS
300 1 TBD TBD PCB (90-0080-100-A)
301 1 PLX 91-0096-000-A Configuration Module #3, x8 to card edge connector P1
SMT, Plug Plug to receptacle
CM1 of PEX 8616RDK
302 1 PLX 91-0084-000-A Breakout Board, PCI Express Gen2, x8tox4x4
Board Ship with PEX 8616RDK Kit
PARTS SHOULD NOT BE ASSEMBLED
13 0 ITTCANON TDA02H0SK1 Dip Switch, 2-pos, half pitch
SMT, dual in line SW9
PEX 8616 RDK Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 31
Item Number Quantity Manufacturer
Manufacturer's Part Number Description Package Type
Component Designator(s)
Distributor Part Number
25 0 AMP 767054-1 Connector, 38-pin Mictor connector, vertical
SMT vertical MC1-MC2
70 0 Panasonic ERJ-
3GEYJ102V Res. 1/10W, 1 K ohm, 5%
SMT, 0603 R126
73 0 Panasonic ERJ-
3GEYJ472V Res. 1/10W, 4.7K ohm, 5%
SMT, 0603 R100
90 0 TBD SMT 0603 R73,R99
100 0 AMP 103185-2 Header, 1x2 100mil pitch
1x2 th JP3
108 0 Samtec TMS-103-02-S-
S Header, micro terminal strip, 100mil
3-p through hole J2
109 0 AMP 1-103240-0 Header, 2x10, 100 mil pitch
2x10 th J3
110 0 Concord
Electronics 09-9127-1-0210
Banana panel jack, black, insulated
through hole BJ2
111 0 Concord
Electronics 09-9127-1-0212
Banana panel jack, red, insulated
through hole BJ1,BJ3
112 0 AMP/Tyco 382811-6 Jumper shunt for 0.1 header
2-pin JP3(1-2)
Customer Name PLX PLX Part # 91-0098-102-B Product Name PEX8616RDK Date 04/05/2010
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
1 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
1 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
1 9Monday, April 05, 2010
www.plxtech.com
PEX8616RDK
BLOCK DIAGRAM
Page 6: Parallel HP& Reset Circuits
TABLE OF CONTENTS
Page 1: Block Diagram
Page 3: PCI Express SLOT 1-2
Page 4: Reference Clock Circuits
Page 5: Serial Hot Plug Circuits
Two x16 PCI Express Slots
Voltage Monitor Circuit
Power & Link LEDsRefClk Circuit
DC/DCConverters I2C PORT
CONFIGURATION DIPSWITCHES
Power-onReset JTAG PORT
PEX8616
PEX8616RDK
REVISON HISTORY
Revision Date Description
X8 Midbus Probe Footprints JP1-JP2
EEPROMINTERFACE
Serial HPto SLOT2 Debug Circuits
Exernal Powerto PLX chip
Parallel HPto SLOT 1
Page 9: PEX8616 Power and Config. Circuits
Page 7: Power & Voltage Monitor
Page 8: PEX8616 Interface
0 9/28/2007 First Released
1 1/2/2008 Changed R119&R120 to pull-up andC65&C69 to 1uF
Page 2: CM receptacle & mini SAS connector
2 1/15/2008 Modified tx/rx signals to IP1, changedpackage symbol of U3 and added R129-R130 at I2C master pins
3 2/7/2008 Changed R1&R2 to pull-up to 3.3VCC.Renamed some net name on Page8.
4 4/5/2010 Change U17 to SPI Serial EEPROM
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TX0p_IP1TX0n_IP1RX0p_IP1RX0n_IP1TX1p_IP1TX1n_IP1RX1p_IP1RX1n_IP1TX2p_IP1TX2n_IP1RX2p_IP1RX2n_IP1TX3p_IP1TX3n_IP1RX3p_IP1RX3n_IP1
TX0p_SL2TX0n_SL2RX0p_SL2RX0n_SL2TX1p_SL2TX1n_SL2RX1p_SL2RX1n_SL2TX2p_SL2TX2n_SL2RX2p_SL2RX2n_SL2TX3p_SL2TX3n_SL2RX3p_SL2RX3n_SL2
RX7p_P1RX7n_P1
TX4p_P1TX4n_P1RX4p_P1RX4n_P1TX5p_P1TX5n_P1RX5p_P1RX5n_P1TX6p_P1TX6n_P1RX6p_P1RX6n_P1TX7p_P1TX7n_P1
RX4pRX4n
RX5pRX5n
RX6pRX6n
RX7pRX7n
TX4pTX4n
TX5pTX5n
TX6pTX6n
TX7pTX7n
RX0pRX0n
RX1pRX1n
RX2pRX2n
RX3pRX3n
CTX4pCTX4n
CTX5pCTX5n
CTX6pCTX6n
CTX7pCTX7nRX7pRX7n
RX6pRX6n
RX5pRX5n
RX4pRX4n
TX4p
TX4n
TX5p
TX5n
TX6p
TX6n
TX7p
TX7n
TX0pTX0n
TX1pTX1n
TX2pTX2n
TX3pTX3n
TX0p_IP1TX0n_IP1
TX1p_IP1
TX2p_IP1
RX0p_IP1RX0n_IP1
RX1p_IP1RX1n_IP1
RX2p_IP1RX2n_IP1
RX3p_IP1RX3n_IP1
TX1n_IP1
TX3p_IP1TX3n_IP1
TX2n_IP1
RX4n_P1 {4}RX4p_P1 {4}
RX6p_P1 {4}
RX7n_P1 {4}RX7p_P1 {4}
RX5p_P1 {4}
TX7n_P1 {4}
RX5n_P1 {4}TX6p_P1 {4}TX6n_P1 {4}
RX6n_P1 {4}TX7p_P1 {4}
TX4n_P1 {4}TX4p_P1 {4}
TX5n_P1 {4}TX5p_P1 {4}
RX0n_SL2 {3}RX0p_SL2 {3}
RX2p_SL2 {3}
RX3n_SL2 {3}RX3p_SL2 {3}
RX1p_SL2 {3}
TX3n_SL2 {3}
RX1n_SL2 {3}TX2p_SL2 {3}TX2n_SL2 {3}
RX2n_SL2 {3}TX3p_SL2 {3}
TX0n_SL2 {3}TX0p_SL2 {3}
TX1n_SL2 {3}TX1p_SL2 {3}
RX0p{4,8}RX0n{4,8}
RX1p{4,8}RX1n{4,8}
RX2p{4,8}RX2n{4,8}
RX3p{4,8}RX3n{4,8}
RX4p{8}RX4n{8}
RX5p{8}RX5n{8}
RX6p{8}RX6n{8}
RX7p{8}RX7n{8}
TX4p {8}TX4n {8}
TX5p {8}TX5n {8}
TX6p {8}TX6n {8}
TX7p {8}TX7n {8}
TX0p {4,8}TX0n {4,8}
TX1p {4,8}TX1n {4,8}
TX2p {4,8}TX2n {4,8}
TX3p {4,8}TX3n {4,8}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
2 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
2 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
2 9Monday, April 05, 2010
www.plxtech.com
CONFIG. MODULE RECEPTACLE
PEX8616RDK
CONFIGURATION MODULE
x8 MIDBUS PROBE FOOTPRINTFOR THE UPSTREAM PORT
MINI SAS CONNECTOR
C1 0.1uFC1 0.1uFCM1
FCI84517_10x20
CM1
FCI84517_10x20
TX4p_U1J12TX4n_U1J13RX4p_U1I12RX4n_U1I13TX5p_U1H12TX5n_U1H13RX5p_U1G12RX5n_U1G13TX6p_U1F12TX6n_U1F13RX6p_U1E12RX6n_U1E13TX7p_U1D13TX7n_U1D14RX7p_U1C15RX7n_U1C16
TX0p_IP1 J1TX0n_IP1 J2RX0p_IP1 I1RX0n_IP1 I2TX1p_IP1 H1TX1n_IP1 H2RX1p_IP1 G1RX1n_IP1 G2TX2p_IP1 F1TX2n_IP1 F2RX2p_IP1 E1RX2n_IP1 E2TX3p_IP1 D1TX3n_IP1 D2RX3p_IP1 C1RX3n_IP1 C2
TX4p_P1 A8TX4n_P1 B8RX4p_P1 A9RX4n_P1 B9TX5p_P1 A10TX5n_P1 B10RX5p_P1 A11RX5n_P1 B11TX6p_P1 A12TX6n_P1 B12RX6p_P1 A13RX6n_P1 B13TX7p_P1 A14TX7n_P1 B14RX7p_P1 A16RX7n_P1 B16
TX0p_SL2 J20TX0n_SL2 J19RX0p_SL2 I20RX0n_SL2 I19TX1p_SL2 H20TX1n_SL2 H19RX1p_SL2 G20RX1n_SL2 G19TX2p_SL2 F20TX2n_SL2 F19RX2p_SL2 E20RX2n_SL2 E19TX3p_SL2 D20TX3n_SL2 D19RX3p_SL2 C20RX3n_SL2 C19
NCA4NCA5NCA6NCB4NCB5NCB6NCC4NCC5NCC6NCD4NCD5NCD6NCD7NCD8NCD9NCD10NCD17NCE4NCE5NCE6NCE7NCE8NCE9NCE10NCE15NCE16NCE17NCF4NCF5NCF6NCF7
NC
G4
NC
G5
NC
G6
NC
G7
NC
G8
NC
G9
NC
G10
NC
G15
NC
G16
NC
G17
NC
H4
NC
H5
NC
H6
NC
H7
NC
H8
NC
H9
NC
H10
NC
H15
NC
H16
NC
H17
NC
I4N
CI5
NC
I6N
CI7
NC
I8N
CI9
NC
I10
NC
I15
NC
I16
NC
I17
NC
J4N
CJ5
NC
J6N
CJ7
NC
J8N
CJ9
NC
J10
NC
J15
NC
J16
NC
J17
NC
F8N
CF9
NC
F10
NC
F15
NC
F16
NC
F17
GN
DA
1G
ND
A2
GN
DA
3G
ND
A7
GN
DA
15G
ND
A17
GN
DA
18G
ND
A19
GN
DA
20G
ND
B1
GN
DB
2G
ND
B3
GN
DB
7G
ND
B15
GN
DB
17G
ND
B18
GN
DB
19G
ND
B20
GN
DC
3G
ND
C7
GN
DC
8G
ND
C9
GN
DC
10G
ND
C11
GN
DC
12G
ND
C13
GN
DC
14G
ND
C17
GN
DC
18G
ND
D3
GN
DD
11G
ND
D12
GN
DD
15G
ND
D16
GN
DD
18G
ND
E3
GN
DE
11G
ND
E14
GN
DE
18G
ND
F3G
ND
F11
GN
DF1
4G
ND
F18
GN
DG
3G
ND
G11
GN
DG
14G
ND
G18
GN
DH
3G
ND
H11
GN
DH
14G
ND
H18
GN
DI1
1G
ND
I14
GN
DI1
8
GN
DI3
GN
DJ1
1G
ND
J14
GN
DJ1
8
GN
DJ3
C3 0.1uFC3 0.1uF
C8 0.1uFC8 0.1uF
C5 0.1uFC5 0.1uF
C2 0.1uFC2 0.1uF
C4 0.1uFC4 0.1uF
C6 0.1uFC6 0.1uF
C7 0.1uFC7 0.1uF
JP1
16CH_MIDBUS_CONTR
JP1
16CH_MIDBUS_CONTR
GND2 CAp 1CAn 3GND 5
GND 11
GND 17
GND 23
GND 29
GND 35
GND 41
GND 47
CBp4CBn6GND8CDp10CDn12GND14CFp16CFn18GND20CHp22CHn24GND26CJp28CJn30GND32CLp34CLn36GND38CNp40CNn42GND44CQp46CQn48
CCp 7CCn 9
CEp 13CEn 15
CGp 19CGn 21
CIp 25CIn 27
CKp 31CKn 33
CMp 37CMn 39
CPp 43CPn 45
G1G1 G2 G2
IP1
I_PASS_26CKT_75783_0036
IP1
I_PASS_26CKT_75783_0036
GNDB1TX0+B2TX0-B3GNDB4TX1+B5TX1-B6GNDB7TX2+B8TX2-B9GNDB10TX3+B11TX3-B12GNDB13
GND A1RX0+ A2RX0- A3GND A4
RX1+ A5RX1- A6GND A7
RX2+ A8RX2- A9GND A10
RX3+ A11RX3- A12GND A13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PERST#_SL2PERST#_SL1
SL2_RCKpSL2_RCKn
RX0p_SL2RX0n_SL2
TX0p_SL2TX0n_SL2
TX1p_SL2TX1n_SL2
TX2p_SL2TX2n_SL2
TX3p_SL2TX3n_SL2
RX1p_SL2RX1n_SL2
RX2p_SL2RX2n_SL2
RX3p_SL2RX3n_SL2
RX25pRX25n
RX26pRX26n
RX27pRX27n
RX24pRX24n
CTX24p
CTX24n
TX24p
TX24n
CTX25p
CTX25n
TX25p
TX25n
CTX26p
CTX26n
TX26p
TX26n
CTX27p
CTX27n
TX27p
TX27n
CTX28p
CTX28n
CTX29p
CTX29n
CTX30p
CTX30n
CTX31p
CTX31n
TX28p
TX28n
TX29p
TX29n
TX30p
TX30n
TX31n
TX31p
SL1_RCKpSL1_RCKn
CTX37n
TX38p
TX38n
TX34n
CTX38p
TX32p
CTX38n
TX39n
TX39p
TX32n
CTX39p
CTX39n
SL3_RCKpSL3_RCKn
PERST#
CTX35p
CTX33p
CTX33n
CTX35n
TX33p
TX35p
TX33n
TX36p
TX35n
TX36n
CTX32p
CTX34p
CTX36p
CTX34n
TX37p
TX37n
CTX36n
RX33pRX33n
RX34pRX34n
RX35pRX35n
RX32pRX32n
CTX32n
CTX37p
TX34p
TX24pTX24n
TX25pTX25n
RX28pRX28n
RX29pRX29n
RX30pRX30n
RX31pRX31n
TX26pTX26n
TX27pTX27n
TX28pTX28n
TX29pTX29n
TX30pTX30n
TX31pTX31n
RX24pRX24n
RX25pRX25n
RX26pRX26n
RX27pRX27n
PRSNT_B#_I
RX28pRX28n
RX29pRX29n
RX30pRX30n
RX31pRX31n
RX38pRX38n
RX39pRX39n
RX37pRX37n
RX36pRX36n
PRSNT#_S
12V_SL2
3.3V_SL2 3.3V_SL2
12V_SL1
3.3V_SL13.3V_SL1
12VCC
3.3VCC3.3VCC
3.3VCC3.3VCC
PERST#_SL2 {5}
SL2_RCKp {4}SL2_RCKn {4}
PERST#_SL1 {6}
SL1_RCKp {4}SL1_RCKn {4} TX0p_SL2{2}
TX0n_SL2{2}
TX1p_SL2{2}TX1n_SL2{2}
TX2p_SL2{2}TX2n_SL2{2}
TX3p_SL2{2}TX3n_SL2{2}
RX0p_SL2 {2}RX0n_SL2 {2}
RX1p_SL2 {2}RX1n_SL2 {2}
RX2p_SL2 {2}RX2n_SL2 {2}
RX3p_SL2 {2}RX3n_SL2 {2}RX27n {8}
RX24p {8}RX24n {8}
RX25p {8}RX25n {8}
RX26p {8}RX26n {8}
RX27p {8}
TX24p{8}
TX24n{8}
TX25p{8}
TX25n{8}
TX26p{8}
TX26n{8}
TX27p{8}
TX27n{8}
TX28p{8}
TX28n{8}
TX29p{8}
TX29n{8}
TX30p{8}
TX30n{8}
TX31p{8}
TX31n{8}
TX38p{8}
TX38n{8}
TX34n{8}
TX32p{8}
TX39p{8}
TX39n{8}
TX32n{8}
PERST# {5,6,9}
SL3_RCKp {4}SL3_RCKn {4}
TX33p{8}
TX35p{8}
TX33n{8}
TX36p{8}
TX35n{8}
TX36n{8}
TX37p{8}
TX37n{8}
RX35n {8}
RX32p {8}RX32n {8}
RX33p {8}RX33n {8}
RX34p {8}RX34n {8}
RX35p {8}
TX34p{8}
RX26p{8} TX26n {8}RX26n{8}
TX27p {8}RX27p{8} TX27n {8}RX27n{8}
TX28p {8}RX28p{8} TX28n {8}RX28n{8}
TX29p {8}RX29p{8} TX29n {8}RX29n{8}
TX30p {8}RX30p{8} TX30n {8}RX30n{8}
TX31p {8}RX31p{8} TX31n {8}RX31n{8}
TX24p {8}RX24p{8} TX24n {8}RX24n{8}
TX25p {8}RX25p{8} TX25n {8}RX25n{8}
TX26p {8}
PRSNT_B#_I{8}
RX28p {8}RX28n {8}
RX29p {8}RX29n {8}
RX31n {8}
RX30p {8}RX30n {8}
RX31p {8}RX39n {8}
RX38p {8}RX38n {8}
RX39p {8}
RX37p {8}RX37n {8}
RX36p {8}RX36n {8}
PRSNT#_S{5}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
Custom
3 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
Custom
3 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
Custom
3 9Monday, April 05, 2010
www.plxtech.com
PCI EXPRESS SLOT1-3
PEX8616RDK
SLOT 1 SLOT 2
Impedance Test Traces
ITP1-ITP16 are probe holes for impendance test. Theyshould be 25mils in diameter
P1_1/P1_2 to P4_1/P4_2 are probing holes for refclksignals at SLOT2-3. They should be placed close to the connector. See layout requirement for details.
SLOT 3
x8 MIDBUS PROBE FOOTPRINTFOR A DDOWNSTREAM PORT
Pin1&2 of J2 should be placedon the refclk traces and closeto SLOT2 without stubs
The hole size of GP1-4 should besame as the jumper header
Ground Posts
This PCI Express slotis not used
ITP13ITP13
P4_1P4_1
ITP7ITP7 ITP8ITP8
C32 0.1uFC32 0.1uF
C46 0.1uFC46 0.1uF
ITP5ITP5GP3GP3
ITP10ITP10
C25 0.1uFC25 0.1uF
R1
4.7K
R1
4.7K
C15 0.1uFC15 0.1uF
C41 0.1uFC41 0.1uF
P2_1P2_1
ITP4ITP4
C30 0.1uFC30 0.1uF
R2
4.7K
R2
4.7K
C36 0.1uFC36 0.1uF
C34 0.1uFC34 0.1uF
+ C10
22uF
+ C10
22uF
C43 0.1uFC43 0.1uF
+C1122uF
+C1122uF
C24 0.1uFC24 0.1uF
C39 0.1uFC39 0.1uF
C31 0.1uFC31 0.1uF
C18 0.1uFC18 0.1uF
C38 0.1uFC38 0.1uF
P3_1P3_1
SLOT2
x16 PCI Express Contr
SLOT2
x16 PCI Express Contr
PRSNT1# A1+12V A2+12V A3GND A4
TCLK A5TDI A6
TDO A7TMS A8
+3.3V A9+3.3V A10
PERST# A11
+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3.3VB8TRST#B93.3VAUXB10WAKE#B11
RSVDB12
PETp0B14PETn0B15GNDB16PRSNT2#B17GNDB18PETp1B19PETn1B20GNDB21GNDB22PETp2B23PETn2B24GNDB25GNDB26PETp3B27PETn3B28GNDB29RSVDB30
GND A12REFCLK+ A13REFCLK- A14
GND A15PERp0 A16PERn0 A17
GND A18RSVD A19
GND A20PERp1 A21PERn1 A22
GND A23GND A24
PERp2 A25PERn2 A26
GND A27GND A28
PERp3 A29PERn3 A30
GNDB13
GND A31RSVD A32RSVD A33
GND A34PERp4 A35PERn4 A36
GND A37GND A38
PERp5 A39PERn5 A40
GND A41GND A42
PERp6 A43PERn6 A44
GND A45GND A46
PERp7 A47PERn7 A48
GND A49RSVD A50
GND A51PERp8 A52PERn8 A53
GND A54GND A55
PERp9 A56PERn9 A57
GND A58GND A59
PERp10 A60
PRSNT2#B31GNDB32PETp4B33PETn4B34GNDB35GNDB36PETp5B37PETn5B38GNDB39GNDB40PETp6B41PETn6B42GNDB43GNDB44PETp7B45PETn7B46GNDB47PRSNT2#B48GNDB49PETp8B50PETn8B51GNDB52GNDB53PETp9B54PETn9B55GNDB56GNDB57PETp10B58PETn10B59GNDB60
PERn10 A61GND A62GND A63
PERp11 A64PERn11 A65
GND A66GND A67
PERp12 A68PERn12 A69
GND A70GND A71
PERp13 A72PERn13 A73
GND A74GND A75
PERp14 A76PERn14 A77
GND A78GND A79
PERp15 A80PERn15 A81
GND A82
GNDB61PETp11B62PETn11B63GNDB64GNDB65PETp12B66PETn12B67GNDB68GNDB69PETp13B70PETn13B71GNDB72GNDB73PETp14B74PETn14B75GNDB76GNDB77PETp15B78PETn15B79GNDB80PRSNT2#B81RSVDB82
C22 0.1uFC22 0.1uF
+C922uF+
C922uF
ITP3ITP3
ITP16ITP16
ITP6ITP6
C27 0.1uFC27 0.1uF
GP2GP2
JP2
16CH_MIDBUS_CONTR
JP2
16CH_MIDBUS_CONTR
GND2 CAp 1CAn 3GND 5
GND 11
GND 17
GND 23
GND 29
GND 35
GND 41
GND 47
CBp4CBn6GND8CDp10CDn12GND14CFp16CFn18GND20CHp22CHn24GND26CJp28CJn30GND32CLp34CLn36GND38CNp40CNn42GND44CQp46CQn48
CCp 7CCn 9
CEp 13CEn 15
CGp 19CGn 21
CIp 25CIn 27
CKp 31CKn 33
CMp 37CMn 39
CPp 43CPn 45
G1G1 G2 G2
ITP14ITP14
C20 0.1uFC20 0.1uF
P1_1P1_1
+C1322uF+
C1322uF
C45 0.1uFC45 0.1uF
C26 0.1uFC26 0.1uF
GP1GP1
C42 0.1uFC42 0.1uF
C16 0.1uFC16 0.1uF
P3_2P3_2
ITP12ITP12
SLOT1
x16 PCI Express Contr
SLOT1
x16 PCI Express Contr
PRSNT1# A1+12V A2+12V A3GND A4
TCLK A5TDI A6
TDO A7TMS A8
+3.3V A9+3.3V A10
PERST# A11
+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3.3VB8TRST#B93.3VAUXB10WAKE#B11
RSVDB12
PETp0B14PETn0B15GNDB16PRSNT2#B17GNDB18PETp1B19PETn1B20GNDB21GNDB22PETp2B23PETn2B24GNDB25GNDB26PETp3B27PETn3B28GNDB29RSVDB30
GND A12REFCLK+ A13REFCLK- A14
GND A15PERp0 A16PERn0 A17
GND A18RSVD A19
GND A20PERp1 A21PERn1 A22
GND A23GND A24
PERp2 A25PERn2 A26
GND A27GND A28
PERp3 A29PERn3 A30
GNDB13
GND A31RSVD A32RSVD A33
GND A34PERp4 A35PERn4 A36
GND A37GND A38
PERp5 A39PERn5 A40
GND A41GND A42
PERp6 A43PERn6 A44
GND A45GND A46
PERp7 A47PERn7 A48
GND A49RSVD A50
GND A51PERp8 A52PERn8 A53
GND A54GND A55
PERp9 A56PERn9 A57
GND A58GND A59
PERp10 A60
PRSNT2#B31GNDB32PETp4B33PETn4B34GNDB35GNDB36PETp5B37PETn5B38GNDB39GNDB40PETp6B41PETn6B42GNDB43GNDB44PETp7B45PETn7B46GNDB47PRSNT2#B48GNDB49PETp8B50PETn8B51GNDB52GNDB53PETp9B54PETn9B55GNDB56GNDB57PETp10B58PETn10B59GNDB60
PERn10 A61GND A62GND A63
PERp11 A64PERn11 A65
GND A66GND A67
PERp12 A68PERn12 A69
GND A70GND A71
PERp13 A72PERn13 A73
GND A74GND A75
PERp14 A76PERn14 A77
GND A78GND A79
PERp15 A80PERn15 A81
GND A82
GNDB61PETp11B62PETn11B63GNDB64GNDB65PETp12B66PETn12B67GNDB68GNDB69PETp13B70PETn13B71GNDB72GNDB73PETp14B74PETn14B75GNDB76GNDB77PETp15B78PETn15B79GNDB80PRSNT2#B81RSVDB82
C29 0.1uFC29 0.1uF
C35 0.1uFC35 0.1uF
C33 0.1uFC33 0.1uF
J2
HRD 3-P
J2
HRD 3-P
123
ITP9ITP9
ITP2ITP2
GP4GP4ITP11ITP11
C44 0.1uFC44 0.1uF
R3
4.7K
R3
4.7K
P4_2P4_2
P1_2P1_2
ITP15ITP15
ITP1ITP1
+ C12
22uF
+ C12
22uF
C23 0.1uFC23 0.1uF
C40 0.1uFC40 0.1uF
C17 0.1uFC17 0.1uF
+ C14
22uF
+ C14
22uF
C21 0.1uFC21 0.1uF
C28 0.1uFC28 0.1uF
C37 0.1uFC37 0.1uF
SLOT3
x16 PCI Express Contr
SLOT3
x16 PCI Express Contr
PRSNT1# A1+12V A2+12V A3GND A4
TCLK A5TDI A6
TDO A7TMS A8
+3.3V A9+3.3V A10
PERST# A11
+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3.3VB8TRST#B93.3VAUXB10WAKE#B11
RSVDB12
PETp0B14PETn0B15GNDB16PRSNT2#B17GNDB18PETp1B19PETn1B20GNDB21GNDB22PETp2B23PETn2B24GNDB25GNDB26PETp3B27PETn3B28GNDB29RSVDB30
GND A12REFCLK+ A13REFCLK- A14
GND A15PERp0 A16PERn0 A17
GND A18RSVD A19
GND A20PERp1 A21PERn1 A22
GND A23GND A24
PERp2 A25PERn2 A26
GND A27GND A28
PERp3 A29PERn3 A30
GNDB13
GND A31RSVD A32RSVD A33
GND A34PERp4 A35PERn4 A36
GND A37GND A38
PERp5 A39PERn5 A40
GND A41GND A42
PERp6 A43PERn6 A44
GND A45GND A46
PERp7 A47PERn7 A48
GND A49RSVD A50
GND A51PERp8 A52PERn8 A53
GND A54GND A55
PERp9 A56PERn9 A57
GND A58GND A59
PERp10 A60
PRSNT2#B31GNDB32PETp4B33PETn4B34GNDB35GNDB36PETp5B37PETn5B38GNDB39GNDB40PETp6B41PETn6B42GNDB43GNDB44PETp7B45PETn7B46GNDB47PRSNT2#B48GNDB49PETp8B50PETn8B51GNDB52GNDB53PETp9B54PETn9B55GNDB56GNDB57PETp10B58PETn10B59GNDB60
PERn10 A61GND A62GND A63
PERp11 A64PERn11 A65
GND A66GND A67
PERp12 A68PERn12 A69
GND A70GND A71
PERp13 A72PERn13 A73
GND A74GND A75
PERp14 A76PERn14 A77
GND A78GND A79
PERp15 A80PERn15 A81
GND A82
GNDB61PETp11B62PETn11B63GNDB64GNDB65PETp12B66PETn12B67GNDB68GNDB69PETp13B70PETn13B71GNDB72GNDB73PETp14B74PETn14B75GNDB76GNDB77PETp15B78PETn15B79GNDB80PRSNT2#B81RSVDB82
C19 0.1uFC19 0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RX5n_P1
RX6p_P1RX6n_P1
RX7p_P1
REFCLKpREFCLKn
RX7n_P1
PERST#_P1
RX3p
RX1p
RX3n
RX1n
RX0p
RX2pRX2n
RX4p_P1
CTX1pCTX1n
CTX2pCTX2n
CTX3pCTX3n
CTX0pCTX0n
RX0n
RX4n_P1
RX5p_P1
PRSNT#
TX3p
TX5p_P1TX5n_P1
TX4p_P1TX4n_P1
TX6p_P1TX6n_P1
TX7p_P1TX7n_P1
OEINV_2
CLKEN#_SL2HBW_2BP_2
RCLKP1
CLKEN#_SL1
RCLKN1
CLKEN#_SL2
HBW_2
RCLKP2RCLKN2
BP_2
SL1_RCKpSL1_RCKn
SL3_RCKnSL3_RCKp
RCLKP5RCLKN5
RCLKP6RCLKN6
IREF_2
VDDA_2
SS_2PWD_2
CLKEN#_SL1
REFCLKp_U1REFCLKn_U1
SL2_RCKpSL2_RCKn
TX3n
TX2n
TX2p
TX1n
TX1p
TX0n
TX0p
12VCC
3.3VCC3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
PERST#_P1 {6}
RX0p{2,8}RX0n{2,8}
RX1p{2,8}RX1n{2,8}
RX2p{2,8}RX2n{2,8}
RX3p{2,8}RX3n{2,8}
RX4p_P1{2}RX4n_P1{2}
RX5p_P1{2}RX5n_P1{2}
RX6p_P1{2}RX6n_P1{2}
RX7p_P1{2}RX7n_P1{2}
TX3p {2,8}
TX4p_P1 {2}TX4n_P1 {2}
TX5p_P1 {2}TX5n_P1 {2}
TX6p_P1 {2}TX6n_P1 {2}
TX7p_P1 {2}TX7n_P1 {2}
SL1_RCKp {3}SL1_RCKn {3}
SL3_RCKp {3}SL3_RCKn {3}
REFCLKp_U1 {9}REFCLKn_U1 {9}
SL2_RCKp {3}SL2_RCKn {3}
CLKEN#_SL1{6}CLKEN#_SL2{5}
TX3n {2,8}
TX2n {2,8}
TX2p {2,8}
TX1n {2,8}
TX1p {2,8}
TX0n {2,8}
TX0p {2,8}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
4 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
4 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
4 9Monday, April 05, 2010
www.plxtech.com
REFERENCE CLOCK CIRCUITS
PEX8616RDK
PCIE MALE CONNECTOR
R7-R10 SHOUD BE CLOSE TO PIN 6& 7 OF U2
REFCLK CIRCUITS
R11-R14 SHOUD BE CLOSE TO PIN9 & 10 OF U2
R15-R18 SHOUD BE CLOSE TO PIN19 & 20 OF U2
R19-R22 SHOUD BE CLOSE TO PIN22 & 23 OF U2
R14 49.9, 1%R14 49.9, 1%
C58
0.01uF
C58
0.01uF
P6_1P6_1
+C47
22uF+
C47
22uF
R15 33R15 33
P1
x8 PCI Express Contr
P1
x8 PCI Express Contr
PRSNT1# A1+12V A2+12V A3GND A4
TCLK A5TDI A6
TDO A7TMS A8
+3.3V A9+3.3V A10
PERST# A11
+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3.3VB8TRST#B93.3VAUXB10WAKE#B11
RSVDB12
PETp0B14PETn0B15GNDB16PRSNT2#B17GNDB18PETp1B19PETn1B20GNDB21GNDB22PETp2B23PETn2B24GNDB25GNDB26PETp3B27PETn3B28GNDB29RSVDB30
GND A12REFCLK+ A13REFCLK- A14
GND A15PERp0 A16PERn0 A17
GND A18RSVD A19GND A20
PERp1 A21PERn1 A22
GND A23GND A24
PERp2 A25PERn2 A26
GND A27GND A28
PERp3 A29PERn3 A30
GNDB13
GND A31RSVD A32RSVD A33GND A34
PERp4 A35PERn4 A36
GND A37GND A38
PERp5 A39PERn5 A40
GND A41GND A42
PERp6 A43PERn6 A44
GND A45GND A46
PERp7 A47PERn7 A48
GND A49
PRSNT2#B31GNDB32PETp4B33PETn4B34GNDB35GNDB36PETp5B37PETn5B38GNDB39GNDB40PETp6B41PETn6B42GNDB43GNDB44PETp7B45PETn7B46GNDB47PRSNT2#B48GNDB49
C55 0.1uFC55 0.1uF
R22 49.9, 1%R22 49.9, 1%
C51 0.1uFC51 0.1uF
U2
CY28400-2
U2
CY28400-2
VD
D1
VD
D5
VD
D11
VD
D18
VD
D24
VS
S4
OE_INV25
VD
D_A
28
VS
S_A
27
SRC_IN2SRC_IN#3
OE_18OE_621
HIGH_BW#17SRC_STP16PWRDWN15
SCLK13SDATA14
IREF 26
PLL/BYPASS#12
DIFT1 6DIFC1 7
DIFT2 9DIFC2 10
DIFT5 20DIFC5 19
DIFT6 23DIFC6 22
C50 0.1uFC50 0.1uF
C54 0.1uFC54 0.1uFR5 4.7KR5 4.7K
P6_2P6_2
P5_1P5_1
R19 33R19 33
R9 49.9, 1%R9 49.9, 1%
R11 33R11 33
R6
475 1%
R6
475 1%
R7 33R7 33
C49 0.1uFC49 0.1uF
R4 4.7R4 4.7
R16 33R16 33
C60
0.01uF
C60
0.01uF
R13 49.9, 1%R13 49.9, 1%
R17 49.9, 1%R17 49.9, 1%
R8 33R8 33
C56 0.1uFC56 0.1uF
RN1
4.7K
RN1
4.7K
12345
678
C52 0.1uFC52 0.1uF
P5_2P5_2
C53 0.1uFC53 0.1uF
R21 49.9, 1%R21 49.9, 1%
+ C48
22uF
+ C48
22uF
C57
10uF
C57
10uF
C61
10uF
C61
10uF
R10 49.9, 1%R10 49.9, 1%
C59
0.01uF
C59
0.01uF
R20 33R20 33
R12 33R12 33
R18 49.9, 1%R18 49.9, 1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C_SCL1I2C_SDA1
PWRLED#_SATNLED#_SPWREN_SCLKEN#_SPERST#_S
SLOT0_3SLOT1_3SLOT2_3SLOT3_3
PRSNTI#_SMRLI#_SBUTTONI#_SPWRFLT#_SPWRGOOD_S
V_4 T_4
PWREN_5
FAULT#_4
12VSENSE_4
IS1_4
3VSENSE_4
IS_4
PWRGOOD_S
HP_SL2_CTL
PWREN_S
PERST#_SPERST#CLKEN#_S
PERST#_SL2CLKEN#_SL2
D2_
2
D1_
2
D3_2
D4_2
D5_1
MRLI#_S
VS1_
4
VS2_
4
PWRFLT#_S
GPIO_S
SHPC_INT#
INTERLOCK_S
12VG_4 3VG_4
AD0_3AD1_3AD2_3
I2C_SCL1
3.3VCC 3.3VCC
12V_A
12V_SL2
3.3V_A
3.3V_SL2
3.3VCC
3.3VCC
3.3V_SL212V_SL2
3.3VCC
3.3VCC
3.3V_SL2
3.3V_A
3.3VCC
3.3VCC
I2C_SCL1{9}I2C_SDA1{9}
PERST#_SL2 {3}CLKEN#_SL2 {4}
PERST#{3,6,9}
PRSNT#_S {3}SHPC_INT#{9}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
5 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
5 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
5 9Monday, April 05, 2010
www.plxtech.com
SERIAL HOT PLUG CIRCUITS
PEX8616RDK
SERIAL HOT PLUG CIRCUIT FOR PORT 1 AT SLOT 2
Default Setting of SW2:1: off (disable MRL#_S)2: off (disable Serial HP)
To demonstrate the serial hot plug function of PEX 8616 requires the chip to boot with EEPROM and sets both pos. 1 and 2 of SW3 to "on" position.
R32 0.02 1%R32 0.02 1%
R31
150
R31
150
R37 4.7KR37 4.7K
R130 4.7KR130 4.7K
C115 NLC115 NL
R72 4.7KR72 4.7K
C64
0.1uF
C64
0.1uF
R39
4.7K
R39
4.7K
R40
4.7K
R40
4.7K
D4 GREEND4 GREEN21
C88
0.1uF
C88
0.1uF
Q1
N-MOS
Q1
N-MOS
D5D6D7D8
S 1S 2S 3
G 4
C65
1uF
C65
1uF
R36 4.7KR36 4.7K
R29
4.7K
R29
4.7K
R34 2KR34 2K
C116 NLC116 NL
R28
51
R28
51
R27
150
R27
150R25 1KR25 1K
SW1
SW DIP-4
SW1
SW DIP-4
1234
8765
R86 0R86 0
R33 2KR33 2K
C63 0.1uFC63 0.1uF
R24 1KR24 1K
D5
GREEN
D5
GREEN
2 1
ON
SW2
SW DIP-2
ON
SW2
SW DIP-2
12
43
C62 0.1uFC62 0.1uF
Q2
N-MOS
Q2
N-MOS
D 5D 6D 7D 8
S1S2S3
G4
RN2
4R 4.7K
RN2
4R 4.7K
12345
678
D2
GREEN
D2
GREEN
21
R38 4.7KR38 4.7K
D1
GREEN
D1
GREEN
21
TP10TP10
U5
SN74LVC157APW
U5
SN74LVC157APW
2A5 VC
C16
1A21B3
4B13
GN
D8
4A14 3B10
2B63A11
1Y 42Y 73Y 94Y 12
A#/B1 G# 15
R129 4.7KR129 4.7K
R30
1.2K
R30
1.2K
D3 GREEND3 GREEN21
U4
TPS2311PW
U4
TPS2311PW
GATE11 GATE2 2
DGND3 TIMER 4
AGND8
DISCH120 DISCH2 19
ENABLE18
FAULT# 16
IN111 IN2 12
ISENSE110 ISENSE2 9
ISET115 ISET2 14
PWRGD1# 17
PWRGD2# 13
VREG5
VSENSE17 VSENSE2 6
R92
13.7K 1%
R92
13.7K 1%
R91
12.4K 1%
R91
12.4K 1%
R87 4.7KR87 4.7K
R26
150
R26
150
R90
20K 1%
R90
20K 1%
S1
SW PUSHBUTTON
S1
SW PUSHBUTTON
13
R23 1KR23 1K
U3
MAX7311AUG
U3
MAX7311AUG
SCL22
AD23
AD021AD12
SDA23
V+24
INT#1
GND12
IO0 4IO1 5IO2 6IO3 7IO4 8IO5 9IO6 10IO7 11IO8 13IO9 14
IO10 15IO11 16IO12 17IO13 18IO14 19IO15 20
C85
0.1uF
C85
0.1uF
R97
100K 1%
R97
100K 1%
R35 0.02 1%R35 0.02 1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A AD
9_2
D8_
2D6_2
D7_2PWRLED_B#
V_6
PERST_B#PERST#CLKEN_B#
MRL_B#_I
PWREN_7
PWRFLT_B#_I
CLKEN#_SL1
PWRGD_B_I
PERST#_SL1
12VSENSE_6
IS1_6
3VG_6
3VSENSE_6
IS_6
HP_SL1_CTL
PWREN_B
BUTTON_B#_I
ATNLED_B#
MAN_PST_S3
RST_8
SRT_8
PERST_8
PERST#_9
VS2_
6
VS1_
6
FAULT#_6
12VG_6 3VG_6
3.3V_SL112V_SL13.3VCC
3.3VCC
12V_A
12V_SL1
3.3V_A
3.3V_SL1
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3V_SL1
3.3V_A
PERST#{3,5,9} PERST#_SL1 {3}CLKEN#_SL1 {4}
MRL_B#_I {8}
BUTTON_B#_I {8}
ATNLED_B#{8}
PWRLED_B#{8}
PERST#_P1{4}
PERST# {3,5,9}
PWRGD_B_I
PWRFLT_B#_I {8}
PWREN_B{8}
PERST_B#{8}
CLKEN_B#{8}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
6 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
6 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
6 9Monday, April 05, 2010
www.plxtech.com
PARALLEL HP & RESET CIRCUIT
PEX8616RDK
PARALLEL HOT PLUG CIRCUIT FOR SLOT 1
C70 IS USED TO SET THE RESET TIMEOUTPERIOD FOR U9. A VALUE OF 0.001UF RESULTSIS APPROXIMATELY 3MS. SEE MANUFACTURERDATASHEET FOR DETAILS.
RESET CIRCUIT
SW3 SETTINGS1: ON2: ON
C69
1uF
C69
1uF
D8
GREEN
D8
GREEN
21
R57
51K
R57
51K
C86
0.1uF
C86
0.1uF
C118 NLC118 NL
R89 0R89 0
D7 GREEND7 GREEN21
S2
SW PUSHBUTTON
S2
SW PUSHBUTTON
1 3
R50
1.2K
R50
1.2K
U8
NC7S08
U8
NC7S08
VCC5
GND 3
A1
B2
Y 4
R94
12.4K 1%
R94
12.4K 1%
R474.7KR474.7K
R41 0.02 1%R41 0.02 1% R44 0.02 1%R44 0.02 1%
C71
0.1uF
C71
0.1uF
R96
13.7K 1%
R96
13.7K 1%
C67 0.1uFC67 0.1uF
R49
4.7K
R49
4.7K
R45 4.7KR45 4.7K
S3
SW PUSHBUTTON
S3
SW PUSHBUTTON
1 3
R46 4.7KR46 4.7K
R56 0R56 0
R51
150
R51
150
U6
TPS2311PW
U6
TPS2311PW
GATE11 GATE2 2
DGND3 TIMER 4
AGND8
DISCH120 DISCH2 19
ENABLE18
FAULT# 16
IN111 IN2 12
ISENSE110 ISENSE2 9
ISET115 ISET2 14
PWRGD1# 17
PWRGD2# 13
VREG5
VSENSE17 VSENSE2 6
C117 NLC117 NL
R43 2KR43 2K
D6 GREEND6 GREEN21
R52
4.7K
R52
4.7K
R53
150
R53
150
R42 2KR42 2K
R55
10K
R55
10K
U9
MAX6420
U9
MAX6420
RST IN3 VCC 5
SRT4 GND 2
RESET# 1
R95
20K 1%
R95
20K 1%
C66 0.1uFC66 0.1uF
R58 0R58 0
C70
0.001uF
C70
0.001uF
Q3
N-MOS
Q3
N-MOS
D5D6D7D8
S 1S 2S 3
G 4
ONSW3
SW DIP-2
ONSW3
SW DIP-2
12
43
Q4
N-MOS
Q4
N-MOS
D 5D 6D 7D 8
S1S2S3
G4
R54
150
R54
150
D9
GREEN
D9
GREEN
21
R59
5.1K
R59
5.1K
R93
100K 1%
R93
100K 1%
C68
0.1uF
C68
0.1uF
R48
4.7K
R48
4.7K
R88 4.7KR88 4.7K
U7
SN74LVC157PW
U7
SN74LVC157PW
2A5 VC
C16
1A21B3
4B13
GN
D8
4A14 3B10
2B63A11
1Y 42Y 73Y 94Y 12
A#/B1 G# 15
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWRGD_10
E1_10E2_10
U1_10O1_10U2_10O2_10
PWRGD2_10
TRIM_11
TRIM_12
VO_13
CTR_12
DR_14
DR_13
DR_12
DR_15
DR_16
ST1_10ST2_10ST3_10ST4_10
NORMAL#/DEBUGNORMAL#/DEBUG3.3VCC
3.3VCC
1.0VCC 2.5VCC
3.3VCC
12V_A
5V_A
3.3V_A
12VCC1.0VCC
1.0VCC 2.5VCC
2.5VCC3.3VCC
12VCC
5V_A
12V_A
3.3VCC
3.3V_A
3.3VCC
3.3VCC
5V_A
12V_A 3.3V_A
NORMAL#/DEBUG{5,8}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
7 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
7 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
7 9Monday, April 05, 2010
www.plxtech.com
POWER AND VOLTAGE MONITOR
PEX8616RDK
PEX8616 VOLTAGE MONITOR CIRCUIT
R73 is not loaded
ATX HD POWER CONNECTOR
POWER FOR SLOT 1 & SLOT 2
5V-TO-3.3V DC/DC CONVERTER
Trim up
12V-TO-1.0V DC/DC CONVERTER 3.3V-TO-2.5V LDO
POWER INDICATOR LEDS
10A
4A
6A
1A8A
D10 is green: 2.5VCC is within the 10% rangeD10 is red: 2.5VCC is out of range
D11 is green: 1.0VCC is within the 10% rangeD11 is red: 1.0VCC is out of range
R99 is not loaded
A trace connectd pin 1&2 of JP3
Trim up
SW4 SETTINGS:1: ON2: OFF
C75
1uF
C75
1uF
BJ1
red
BJ1
red
1
D13GREEN
D13GREEN
2 1
TV3TV3
R71390R71390
TV4TV4
U12
S7AH-08E1A0
U12
S7AH-08E1A0
Vin2 Vout 4
On/Off#1
Gnd
3
Trim 5
NC
6
NC
7
C81
10uF
C81
10uF
TV18TV18
GR
D10
CMD15-22SRUGC
GR
D10
CMD15-22SRUGC
21
34
R73 NLR73 NL
R99 NLR99 NL
C87
0.1uF
C87
0.1uF
TV14TV14
R7537.4K 1%
R7537.4K 1%
C82
1uF
C82
1uF
J1
53113-0410
J1
53113-0410
+12VDC 1
COM 2
COM 3
+5VDC 4
R98 150R98 150
U11
S7AH-08E1A0
U11
S7AH-08E1A0
Vin2 Vout 4
On/Off#1
Gnd
3
Trim 5
NC
6
NC
7
R64
464 1%
R64
464 1%
TV11TV11
R67 4.7KR67 4.7K
R79 150R79 150
C83
1uF
C83
1uF
R63
7.32K 1%
R63
7.32K 1%
R66 4.7KR66 4.7K
R70390R70390
TV19TV19
TV15TV15
JP3 2-P JPRJP3 2-P JPR1 2
+C76
180uF
+C76
180uF R74
1.30K, 1%
R74
1.30K, 1%
R69390R69390
TV16TV16
GR
D11
CMD15-22SRUGC
GR
D11
CMD15-22SRUGC
21
34
BJ2
black
BJ2
black
1
TV8TV8
R68390R68390
D14GREEN
D14GREEN
2 1TV12TV12
C84
10uF
C84
10uF
R77 1.2KR77 1.2K
D16GREEN
D16GREEN
2 1
+C80
180uF
+C80
180uF
R611.18K 1% R611.18K 1%
RN3
4.7K
RN3
4.7K
12345
678
U10
ISL6132
U10
ISL6132
VD
D23
GN
D10
EN11EN211
UVMON_120OVMON_112UVMON_217OVMON_214
UVSTATUS_1 2OVSTATUS_1 5UVSTATUS_2 6OVSTATUS_2 7
PGOOD 24PGOOD2 9
NC
13N
C15
NC
16N
C18
NC
19N
C21
NC
22NC3NC4 N
C8
U13
MIC37100
U13
MIC37100
VIN1 VOUT 3
GN
D2
TAB
4
C73
1uF
C73
1uF
R65
2.32K 1%
R65
2.32K 1%
R60
3.09K 1%
R60
3.09K 1%
D12GREEN
D12GREEN
2 1
R123
4.7K
R123
4.7K
TV17TV17D15GREEN
D15GREEN
2 1
R625.76K 1% R625.76K 1%
TV13TV13
TV6TV6
TV9TV9
TV5TV5
ON
SW4
SW DIP-2
ON
SW4
SW DIP-2
12
43
TV2TV2
BJ3
red
BJ3
red
1
+C74
22uF
+C74
22uF
C78
10uF
C78
10uF
TV10TV10
TV7TV7
C77
1uF
C77
1uF
R78 360R78 360
+C72
22uF
+C72
22uF
C791uFC791uF
TV1TV1
R76 1.2KR76 1.2K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TX0p
RX2nTX3pTX3nRX3pRX3nTX4pTX4nRX4p
TX5pTX5nRX5pRX5nTX6pTX6nRX6pRX6nTX7pTX7nRX7pRX7nTX24pTX24nRX24pRX24nTX25pTX25nRX25pRX25nTX26pTX26nRX26pRX26nTX27pTX27nRX27p
TX28pTX28nRX28pRX28nTX29pTX29nRX29pRX29nTX30pTX30nRX30pRX30nTX31pTX31nRX31pRX31nTX32pTX32nRX32pRX32nTX33pTX33nRX33pRX33nTX34pTX34nRX34pRX34nTX35pTX35nRX35pRX35nTX36pTX36nRX36pRX36nTX37pTX37nRX37pRX37nTX38pTX38nRX38pRX38nTX39pTX39nRX39pRX39n
RX27n
RX4n
RX0p
TX2p
RX1p
TX0n
TX1nTX1p
RX2p
RX0n
TX2n
RX1n
PROCMON_O
BUTTON_B#_IPRSNT_B#_IPWRFLT_B#_IPWREN_B_OATNLED_B#_OPERST_B#_OPWRLED_B#_OGPIO7_OCLKEN_B#_OGPIO5_OGPIO6_ODB_SEL0_IGPIO4_O
PERST_A#_OATNLED_A#_OCLKEN_A#_OPWREN_A_OPWRLED_A#_O
CLKEN_C#_OGPIO1_OPRSNT_C#_IGPIO0_OBUTTON_C#_I
PT_GD9_O
ATNLED_C#_O
PRSNT_A#_IPWRFLT_A#_IBUTTON_A#_IGPIO2_OPT_GD11_OGPIO3_OMRL_A#_IPWRGD_A_IPWRLED_C#_OPWREN_C_OPWRFLT_C#_IMRL_C#_IPERST_C#_O
PWRFLT_B#_IMRL_B#_IBUTTON_B#_IMRL_C#_IPWRFLT_C#_I
PWRGD_B_IBUTTON_A#_IPRSNT_A#_I
DB_SEL0_IDB_SEL1_IPRSNT_B#_I
BUTTON_C#_IPRSNT_C#_IPWRGD_A_IMRL_A#_IPWRFLT_A#_I
PT_GOOD1#_O
PT_GD2_OMRL_B#_IPT_GD3_OSPARE1_IODB_SEL1_ISPARE2_OPWRGD_B_IPT_GD7_OPT_GOOD6#_OPT_GOOD5#_OPT_GD4_OSPARE0_OPT_GOOD0#_O
PT_GD8_OPT_GD10_O
NORMAL#/DEBUG
LED5
LED1LED0
LED6
NORMAL#/DEBUG
PWREN_BATNLED_B#PERST_B#PWRLED_B#
CLKEN_B#
NORMAL#/DEBUG
LED9
LED8
DR
_21
DR
_22
ATNLED_A#_O
BUTTON_A#_I
CLKEN_A#_O
MRL_A#_I
PERST_A#_O
PRSNT_A#_I
PWRGD_A_I
PWREN_A_O
PWRFLT_A#_I
PWRLED_A#_O
ATNLED_B#_O
BUTTON_B#_I
CLKEN_B#_O
MRL_B#_I
PERST_B#_O
PRSNT_B#_I
PWRGD_B_I
PWREN_B_O
PWRFLT_B#_I
PWRLED_B#_O
ATNLED_C#_O
BUTTON_C#_I
CLKEN_C#_O
MRL_C#_I
PERST_C#_O
PRSNT_C#_I
PWREN_C_OPWRLED_C#_O
SPARE0_O
SP3SP4
TDpTDn
REXT_0
REXT_3
REXT_4
PT_GOOD0#_OPT_GOOD1#_OPT_GOOD5#_OPT_GOOD6#_OPT_GD8_OPT_GD9_O
RSV_3RSV_4RSV_7RSV_8
GPIO0_OGPIO1_OGPIO2_OGPIO3_OGPIO4_OGPIO5_OGPIO6_OGPIO7_OPT_GD2_OPT_GD3_OPT_GD4_OPT_GD7_OPT_GD10_OPT_GD11_O
DR
_17
DR
_18
DR
_19
DR
_20
RSV_16
SPARE1_IOSPARE2_O
RSV_0RSV_1RSV_2
PWRFLT_C#_I
3.3VCC
3.3VCC
3.3VCC
3.3VCC
2.5VCC
3.3VCC
2.5VCC
TX0p {2,4}TX0n {2,4}
TX1p {2,4}TX1n {2,4}
RX0p {2,4}RX0n {2,4}
RX1p {2,4}RX1n {2,4}
TX2p {2,4}TX2n {2,4}
TX3p {2,4}TX3n {2,4}
RX2p {2,4}RX2n {2,4}
RX3p {2,4}RX3n {2,4}
TX4p {2}TX4n {2}
TX5p {2}TX5n {2}
RX4p {2}RX4n {2}
RX5p {2}RX5n {2}
TX6p {2}TX6n {2}
TX7p {2}TX7n {2}
RX6p {2}RX6n {2}
RX7p {2}RX7n {2}
TX24p {3}TX24n {3}
TX25p {3}TX25n {3}
RX24p {3}RX24n {3}
RX25p {3}RX25n {3}
TX26p {3}TX26n {3}
TX27p {3}TX27n {3}
RX26p {3}RX26n {3}
RX27p {3}RX27n {3}
TX28p {3}TX28n {3}
TX29p {3}TX29n {3}
RX28p {3}RX28n {3}
RX29p {3}RX29n {3}
TX30p {3}TX30n {3}
TX31p {3}TX31n {3}
RX30p {3}RX30n {3}
RX31p {3}RX31n {3}
TX32p {3}TX32n {3}
TX33p {3}TX33n {3}
RX32p {3}RX32n {3}
RX33p {3}RX33n {3}
TX34p {3}TX34n {3}
TX35p {3}TX35n {3}
RX34p {3}RX34n {3}
RX35p {3}RX35n {3}
TX36p {3}TX36n {3}
TX37p {3}TX37n {3}
RX36p {3}RX36n {3}
RX37p {3}RX37n {3}
TX38p {3}TX38n {3}
TX39p {3}TX39n {3}
RX38p {3}RX38n {3}
RX39p {3}RX39n {3}
NORMAL#/DEBUG{5,7}
BUTTON_B#_I{6}MRL_B#_I{6}
PRSNT_B#_I{3}
PWRGD_B_I{6}PWRFLT_B#_I{6}
PWREN_B {6}ATNLED_B# {6}PERST_B# {6}PWRLED_B# {6}
CLKEN_B# {6}
PROCMON_O{9}
DB_SEL1_I{9}
DB_SEL0_I {9}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
Custom
8 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
Custom
8 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
Custom
8 9Monday, April 05, 2010
www.plxtech.com
INTERFACE OF PEX8616
PEX8616RDK
MICTOR PROBE C
MICTOR PROBE A
Header J3, mictor connectorsMC1 & MC2 are for PLX internalused only and not loaded
Resistors, R100 & R126and SW9 are not load
TP8TP8
R108 1.43K 1%R108 1.43K 1%
R101 4.7KR101 4.7K
D18
GREEN
D18
GREEN
21
R85150R85150
R104 1KR104 1K
D17
GREEN
D17
GREEN
21
R1281KR1281K
R109 1.43K 1%R109 1.43K 1%
R82
150
R82
150
R81
150
R81
150
PEX8616
U1A
PEX8616AA_19X19
PEX8616
U1A
PEX8616AA_19X19
PEX_PETp0 U3PEX_PETn0 V3PEX_PERp0 P3PEX_PERn0 R3PEX_PETp1 U4PEX_PETn1 V4PEX_PERp1 P4PEX_PERn1 R4PEX_PETp2 U5PEX_PETn2 V5PEX_PERp2 P5PEX_PERn2 R5PEX_PETp3 U6PEX_PETn3 V6PEX_PERp3 P6PEX_PERn3 R6PEX_PETp4 U8PEX_PETn4 V8PEX_PERp4 P8PEX_PERn4 R8PEX_PETp5 U9PEX_PETn5 V9PEX_PERp5 P9PEX_PERn5 R9PEX_PETp6 U10PEX_PETn6 V10PEX_PERp6 P10PEX_PERn6 R10PEX_PETp7 U11PEX_PETn7 V11PEX_PERp7 P11PEX_PERn7 R11
PEX_PETn24 A3PEX_PERp24 E3PEX_PERn24 D3PEX_PETp25 B4PEX_PETn25 A4PEX_PERp25 E4PEX_PERn25 D4PEX_PETp26 B5PEX_PETn26 A5PEX_PERp26 E5PEX_PERn26 D5PEX_PETp27 B6PEX_PETn27 A6PEX_PERp27 E6PEX_PERn27 D6PEX_PETp28 B8PEX_PETn28 A8PEX_PERp28 E8PEX_PERn28 D8PEX_PETp29 B9PEX_PETn29 A9PEX_PERp29 E9PEX_PERn29 D9PEX_PETp30 B10PEX_PETn30 A10PEX_PERp30 E10PEX_PERn30 D10PEX_PETp31 B11PEX_PETn31 A11PEX_PERp31 E11PEX_PERn31 D11
N/C N17N/C N18N/C N14N/C N15N/C M17N/C M18N/C M14N/C M15N/C L17N/C L18N/C L14N/C L15N/C K17N/C K18N/C K14N/C K15N/C H17N/C H18N/C H14N/C H15N/C G17N/C G18N/C G14N/C G15N/C F17N/C F18N/C F14N/C F15N/C E17N/C E18N/C E14N/C E15
HP_BUTTON_A#U17
HP_PWRLED_A#T14
HP_PRSNT_A#V18
HP_ATNLED_A#U16
HP_PWRFLT_A#V17
HP_MRL_A#R15
HP_PWREN_AU15 HP_PERST_A#V16 HP_CLKEN_A#V15
SPARE0G2SPARE1K1SPARE2K3
PEX_PETp24 B3
HP_BUTTON_B#M1HP_MRL_B#L2HP_PRSNT_B#M2HP_PWRFLT_B#M5
HP_ATNLED_B#K2HP_CLKEN_B#R1HP_PERST_B#N1HP_PWREN_BM4HP_PWRLED_B#N2
N/CA14N/CD13N/CA16N/CC14
N/CA13N/CA18N/CB13N/CB14N/CB16
GPIO12B15GPIO13A17GPIO14U18GPIO15R16GPIO16V1GPIO17T1GPIO18U1GPIO19P1
HP_PWR_GOOD_AR14
HP_PWR_GOOD_BK4
N/CC16
GPIO2L1GPIO3L5GPIO4H5GPIO7J1GPIO10R17GPIO11T17
SPARE3L4SPARE4R13
N/CB7N/CA7
N/CJ17N/CJ18
REXT_A0R7REXT_B0P7
REXT_A3D7REXT_B3E7
N/CJ15N/CJ14
N/CN7
N/CF7
N/CJ13
PEX_PORT_GOOD0#G1PEX_PORT_GOOD1#F1PEX_PORT_GOOD5#H3PEX_PORT_GOOD6#H4GPIO8R18GPIO9T18
STRAP_RESERVED16T13
THERMAL_DIODEpV13THERMAL_DIODEnP13
STRAP_RESERVED0J4STRAP_RESERVED1P2STRAP_RESERVED2K5STRAP_RESERVED3E2STRAP_RESERVED4V12STRAP_RESERVED7F3STRAP_RESERVED8E12
R100 4.7KR100 4.7K
D21
GREEN
D21
GREEN
21
R103 1KR103 1K
D20
GREEN
D20
GREEN
21
R84150R84150
R125 1KR125 1K
R83
150
R83
150
TP6TP6
R80
150
R80
150
J3
HEADER 10X2
J3
HEADER 10X2
13579
1113151719
2468101214161820
R127 1KR127 1K
U15
SN74CBTLV3245APWR
U15
SN74CBTLV3245APWR
BE#19
VCC 20
NC1 GND 10
A02A13A24A35A46A57A68A79
B0 18B1 17B2 16B3 15B4 14B5 13B6 12B7 11
R106 1KR106 1K
U16
SN74CB3T3306DCTR
U16
SN74CB3T3306DCTR
1OE#12OE# 7
2B 62A 5
VCC 8
GND4
1A21B3
C90
0.01uF
C90
0.01uF
12
MC2
MICTOR 38
MC2
MICTOR 38
NC1 NC 2GND3 NC 4CLK/Q5 CLK/Q 6L3:77 R1:7 8L3:69 R1:6 10L3:511 R1:5 12L3:413 R1:4 14L3:315 R1:3 16L3:217 R1:2 18L3:119 R1:1 20L3:021 R1:0 22L2:723 R0:7 24L2:625 R0:6 26L2:527 R0:5 28L2:429 R0:4 30L2:331 R0:3 32
R0:2 34R0:1 36R0:0 38GND 40GND 42
L2:233L2:135L2:037GND39GND41GND43
U14
SN74CBTLV3245APWR
U14
SN74CBTLV3245APWR
BE#19
VCC 20
NC1 GND 10
A02A13A24A35A46A57A68A79
B0 18B1 17B2 16B3 15B4 14B5 13B6 12B7 11
C89
0.01uF
C89
0.01uF
12
R110 1.43K 1%R110 1.43K 1%
R1071KR1071K
D22GREEND22GREEN
21
R105 4.7KR105 4.7K
J4
1X4 HDR
J4
1X4 HDR
1234
ONSW9
SW DIP-2
ONSW9
SW DIP-2
12
43
MC1
MICTOR 38
MC1
MICTOR 38
NC1 NC 2GND3 NC 4CLK/Q5 CLK/Q 6L3:77 R1:7 8L3:69 R1:6 10L3:511 R1:5 12L3:413 R1:4 14L3:315 R1:3 16L3:217 R1:2 18L3:119 R1:1 20L3:021 R1:0 22L2:723 R0:7 24L2:625 R0:6 26L2:527 R0:5 28L2:429 R0:4 30L2:331 R0:3 32
R0:2 34R0:1 36R0:0 38GND 40GND 42
L2:233L2:135L2:037GND39GND41GND43
R102 4.7KR102 4.7KR126 1KR126 1K
TP7TP7
TP5TP5
D19
GREEN
D19
GREEN
21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
REFCLKp_U1 CCLKpREFCLKn_U1 CCLKn
PERST#
DB_SEL0_IDB_SEL1_I
JTAG_TMSJTAG_TRST#
JTAG_TDOJTAG_TDIJTAG_TCK
EE_CS#EE_DIEE_DOEE_SK
NT_USPT_SEL0NT_USPT_SEL1
USPT_SEL0USPT_SEL1USPT_SEL2RSV_13
NT_ENABLE#
STN0_PCFG1STN1_PCFG0RSV_9
TMODE0TMODE1TMODE2TMODE3
USPT_SEL0USPT_SEL1
NT_ENABLE#
RSV_9NT_USPT_SEL0
STN0_PCFG1STN1_PCFG0
NT_USPT_SEL1
RSV_13USPT_SEL2USPT_SEL1USPT_SEL0
USPT_SEL2RSV_13
NT_USPT_SEL1
RSV_9
STN0_PCFG1
NT_ENABLE#
NT_USPT_SEL0
STN1_PCFG0
D24_2
D23_2 INTA#
F_ERR#
I2C_SCL0I2C_SDA0
PRMN_1
PROCMON_O
SHPC_INT#
TMODE3TMODE2TMODE1TMODE0
RSV_17#
I2C_ADD2I2C_ADD1I2C_ADD0
TMODE3TMODE2TMODE1TMODE0
I2C_ADD1
RSV_17#
SERDES_MODE#
I2C_ADD2
I2C_ADD0
PROBE_MODE#
I2C_SCL1I2C_SDA1
I2C_SCL0I2C_SDA0
PROBE_MODE#SERDES_MODE#
PLL_BP#F_BUP#
I2C_ADD2
RSV_17#I2C_ADD0
SERDES_MODE#PROBE_MODE#
I2C_ADD1
1.0VCC
1.0VCC 2.5VCC
2.5VCC
3.3VCC
2.5VCC
2.5VCC
3.3VCC
3.3VCC
3.3VCC
REFCLKp_U1{4}REFCLKn_U1{4}
PERST#{3,5,6}
DB_SEL0_I{8}DB_SEL1_I{8}
PROCMON_O{8}
I2C_SCL1{5}I2C_SDA1{5}
SHPC_INT#{5}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
9 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
9 9Monday, April 05, 2010
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085
B
9 9Monday, April 05, 2010
www.plxtech.com
POWER & CONFIG. OF PEX8616
PEX8616RDK
JTAG PORT
EEPROM
SW54: RSV_133: USPT_SEL22: USPT_SEL11: USPT_SEL0
SW66: NT_ENABLE#5: NT_USPT_SEL14: NT_USPT_SEL03: RSV_92: STN1_PCFG01: STN0_PCFG1
PORT CONFIGUATIONDIP SWITCHES
SW74: TMODE33: TMODE22: TMODE11: TMODE0
I2C INTERFACE
SW86: I2C_ADD25: I2C_ADD14: I2C_ADD03: RSV_17#2: PROBE_MODE#1: SERDES_MODE#
TP1 marks with 1.0VTP2 marks with GND
TP3 marks with 2.5VTP4 marks with GND
C95
0.022uF
C95
0.022uF
12 TP4TP4
SW7 SW DIP-4SW7 SW DIP-4
1234
8765
RN6 4R 4.7KRN6 4R 4.7K1234 5
678
C111
0.1uF
C111
0.1uF
12
C112
10uF
C112
10uF1
2
R121 150R121 150
C92 0.1uFC92 0.1uF
D24 REDD24 RED2 1
C98
0.033uF
C98
0.033uF
12
RN4
4R 1K
RN4
4R 1K
1234 5
678
R113 4.7KR113 4.7K
C110
0.1uF
C110
0.1uF
12
C97
0.033uF
C97
0.033uF
12
C100
0.1uF
C100
0.1uF
12
RN7 4R 4.7KRN7 4R 4.7K1234 5
678
RN5 4R 4.7KRN5 4R 4.7K1234 5
678
C114
10uF
C114
10uF
12
SW6 SW DIP-6SW6 SW DIP-6
123456
121110987
R124 150R124 150
R118 10KR118 10K
C91 0.1uFC91 0.1uF
C106
10uF
C106
10uF
12
C113
10uF
C113
10uF
12
R112 4.7KR112 4.7K
RN8 4R 4.7KRN8 4R 4.7K1234 5
678
JP5
HEADER 2X2
JP5
HEADER 2X2
1234
C104
10uF
C104
10uF
12
R114 4.7KR114 4.7K
JP6
HEADER 2X2
JP6
HEADER 2X2
1234
TP2TP2
C103
10uF
C103
10uF
12
R116 4.7KR116 4.7K
TP1TP1
R119 4.7KR119 4.7K
PEX8616
U1B
PEX8616AA_19X19
PEX8616
U1B
PEX8616AA_19X19
PEX_INTA#G5
VS
SE
13V
SS
E16
VS
SF4
VS
SF9
VS
SF1
1V
SS
F16
VS
SG
6V
SS
G8
VS
SG
10V
SS
G12
VS
SG
16V
SS
H7
VS
SH
9V
SS
H11
VS
SH
13V
SS
H16
VS
SJ3
STRAP_SERDES_MODE_EN#P17STRAP_PLL_BYPASS#P18
STRAP_PROBE_MODE#U12
JTAG_TMSD1JTAG_TRST#F2JTAG_TCKB1JTAG_TDIE1JTAG_TDOC1
PEX_PERST#M3PEX_NT_RESET#V14
PEX_REFCLKpU7PEX_REFCLKnV7
STRAP_FAST_BRINGUP#P12
FATAL_ERR#C13
STRAP_DEBUG_SEL0U2STRAP_DEBUG_SEL1N3
I2C_ADD0H2I2C_ADD1H1I2C_ADD2J2
STRAP_RESERVED17#D18
N/CL3
STRAP_STN0_PORTCFG1R12STRAP_STN1_PORTCFG0B2STRAP_RESERVED9B12
STRAP_UPSTRM_PORTSEL0A12STRAP_UPSTRM_PORTSEL1C18STRAP_UPSTRM_PORTSEL2D17STRAP_RESERVED13D12
STRAP_NT_ENABLE#A2STRAP_NT_UPSTRM_PORTSEL0C2STRAP_NT_UPSTRM_PORTSEL1D2
EE_CS#B18
EE_DOC17 EE_DIC15
EE_SKB17
STRAP_TESTMODE0R2STRAP_TESTMODE1T2STRAP_TESTMODE2V2STRAP_TESTMODE3J5
VS
SA
15V
SS
C3
VS
SC
4V
SS
C5
VS
SC
6V
SS
C7
VS
SC
8V
SS
C9
VS
SC
10V
SS
C11
VS
SC
12V
SS
D14
VS
SD
15V
SS
D16
VD
D10
G7
VD
D10
G9
VD
D10
G11
VD
D10
H8
VD
D10
H10
VD
D10
H12
VD
D10
J7V
DD
10J9
VD
D10
J11
VD
D10
K8
VD
D10
K10
VD
D10
K12
VD
D10
L7V
DD
10L9
VD
D10
L11
VD
D10
M8
VD
D10
M10
VD
D10
M12
VD
D10
AF6
VD
D10
AF1
0V
DD
10A
F12
VD
D10
AG
13V
DD
10A
H6
VD
D10
AK
6V
DD
10A
L13
VD
D10
AM
6V
DD
10A
N9
VD
D10
AN
11
VDD25 F5VDD25 F13VDD25 N5VDD25 N13VDD25 T15
VDD25A F8VDD25A K13VDD25A N8
VSS J6VSS J8VSS J10VSS J12VSS J16VSS K7VSS K9VSS K11VSS K16VSS L6VSS L8VSS L10VSS L12VSS L16VSS M7VSS M9VSS M11VSS M13VSS M16VSS N4VSS N6VSS N10VSS N12VSS N16VSS P14VSS P15VSS P16VSS T3VSS T4VSS T5VSS T6VSS T7VSS T8
I2C_SCL0G4I2C_SDA0G3
I2C_SCL1U14I2C_SDA1U13SHPC_INT#A1
VSS T9VSS T10VSS T11VSS T12VSS T16
SW5 SW DIP-4SW5 SW DIP-4
1234
8765
D23 GREEND23 GREEN2 1
R122 150R122 150
R117 10KR117 10K
C108
0.01uF
C108
0.01uF
12
C109
0.01uF
C109
0.01uF
12
TP9TP9
C101
0.1uF
C101
0.1uF
12
C107
0.01uF
C107
0.01uF
12
U17
SPI Serial EEPROM
U17
SPI Serial EEPROMSCLK 6
CS# 1SI 5
SO 2HOLD#7 VCC8
WP#3GND4
C102
0.1uF
C102
0.1uF
12
JP4
HDR 5X2
JP4
HDR 5X2
1 23 45 67 89 10
C105
10uF
C105
10uF
12
C99
0.001uF
C99
0.001uF
12
SW8 SW DIP-6SW8 SW DIP-6
123456
121110987
C94
0.01uF
C94
0.01uF
12
TP3TP3C96
0.022uF
C96
0.022uF
12
R120 4.7KR120 4.7K
C93
0.01uF
C93
0.01uF
12
R111 4.7KR111 4.7K
R115 4.7KR115 4.7K