October 10, 2000 2
USB 2.0 Host Controllers
(EHCI Specification)
USB 2.0 Host Controllers
(EHCI Specification)John S. HowardJohn S. HowardIntel CorporationIntel Corporation
October 10, 2000 3
AgendaAgenda
Project OverviewProject Overview Key Features OverviewKey Features Overview
– USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture– EHCI HC Interface ArchitectureEHCI HC Interface Architecture– EHCI HC Data StructuresEHCI HC Data Structures– Operational Models (Overview/Examples)Operational Models (Overview/Examples)
Host Controller Compliance ProgramHost Controller Compliance Program SummarySummary
October 10, 2000 4
Project OverviewProject Overview
Intel developed specification with contributionsIntel developed specification with contributionsfrom from – NEC, Lucent, Philips, Compaq and Microsoft NEC, Lucent, Philips, Compaq and Microsoft – LicenseesLicensees**** can also contribute to specification can also contribute to specification
Enhanced Host Controller Specification for USBEnhanced Host Controller Specification for USB– Defines the architecture for a USB 2.0 capable host Defines the architecture for a USB 2.0 capable host
controller, andcontroller, and– Defines register (hardware/software) interfaceDefines register (hardware/software) interface
for a high-speed capable host controller for a high-speed capable host controller
October 10, 2000 5
Project OverviewProject Overview
Public revisions will be available soonPublic revisions will be available soon– Each revision comes with a license agreementEach revision comes with a license agreement– Revision 0.95 will be the first public releaseRevision 0.95 will be the first public release
License agreement provides reciprocal royalty free license License agreement provides reciprocal royalty free license to manufacture compliant discrete USB 2.0 host controllers to manufacture compliant discrete USB 2.0 host controllers based on this specificationbased on this specification
– Revision 1.0 is the final specificationRevision 1.0 is the final specification License agreement provides reciprocal royalty free license License agreement provides reciprocal royalty free license
to manufacture compliant USB 2.0 host controllers based on to manufacture compliant USB 2.0 host controllers based on this specification this specification
ContinuedContinued
October 10, 2000 6
USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture
Multi-function Controller delivers 3 port speedsMulti-function Controller delivers 3 port speeds– Simplifies High-speed Host Controller Simplifies High-speed Host Controller
Optimize for high-speed functionalityOptimize for high-speed functionality– Reuses USB 1.1 Host Controller Designs (drop-in)Reuses USB 1.1 Host Controller Designs (drop-in)– USB ports USB ports workwork independent of high-speed capable software independent of high-speed capable software
USB 2.0 Host Controller (HC)USB 2.0 Host Controller (HC)
Port 1Port 1
Companion USB HCs for FS/LS Companion USB HCs for FS/LS
Port 1Port 1 Port 2Port 2
Port OwnerPort Owner Control(s) Control(s)
Port 1Port 1 PortPort 22
Port Routing LogicPort Routing Logic
Port NPort N
HC Control Logic/DataHC Control Logic/DataBufferingBuffering
Enhanced HC Control LogicEnhanced HC Control Logic Enhanced Data Buffering Enhanced Data Buffering
Port 2Port 2 Port NPort N
Port NPort N
High-SpeedHigh-Speed(Enhanced Interface) USB HC(Enhanced Interface) USB HC
October 10, 2000 7
USB 2.0 Host Controller Architecture: Port Routing RulesUSB 2.0 Host Controller Architecture: Port Routing Rules
Ports owned by Companion controllers when HS HC software is absentPorts owned by Companion controllers when HS HC software is absent When HS HC Software is present, it “configures” High-Speed HC then:When HS HC Software is present, it “configures” High-Speed HC then:
– Retains ownership for high-speed devicesRetains ownership for high-speed devices– Releases individual port ownership if attached device is not high speedReleases individual port ownership if attached device is not high speed
Routing Logic signals a disconnect on HS HC and a connect on Companion HCRouting Logic signals a disconnect on HS HC and a connect on Companion HC– Ownership returns to HS HC on a disconnect eventOwnership returns to HS HC on a disconnect event
Companion Companion USB 1.1 HCUSB 1.1 HCXX
Companion Companion USB 1.1 HCUSB 1.1 HCXX
Port RegisterPort RegisterPort RegisterPort Register
High Speed HCHigh Speed HC(EHCI)(EHCI)
High Speed HCHigh Speed HC(EHCI)(EHCI)
TransceiverTransceiverTransceiverTransceiver
Port Routing LogicPort Routing LogicPort Routing LogicPort Routing LogicPort Owner ControlPort Owner ControlPort Owner ControlPort Owner Control
HC HC ConfiguredConfigured
HC HC ConfiguredConfigured
Port RegisterPort RegisterPort RegisterPort Register
October 10, 2000 8
EHCI Interface Architecture (Overview)EHCI Interface Architecture (Overview)
CapabilityCapabilityRegistersRegisters
CapabilityCapabilityRegistersRegisters
OperationalOperationalRegistersRegisters
OperationalOperationalRegistersRegisters
Memory-BasedMemory-BasedI/O RegistersI/O Registers
Memory-BasedMemory-BasedI/O RegistersI/O Registers
PCI ClassPCI ClassCode, etc.Code, etc.PCI ClassPCI ClassCode, etc.Code, etc.
USB Base USB Base AddressAddress
USB Base USB Base AddressAddress
PCI PowerPCI PowerManagementManagement
InterfaceInterface
PCI PowerPCI PowerManagementManagement
InterfaceInterface
PCI ConfigurationPCI ConfigurationRegisterRegister
PCI ConfigurationPCI ConfigurationRegisterRegister Shared Memory Work ListsShared Memory Work ListsShared Memory Work ListsShared Memory Work Lists
Periodic ListPeriodic ListPeriodic ListPeriodic List
Asynchronous ListAsynchronous ListAsynchronous ListAsynchronous List
October 10, 2000 9
Operational I/O Registers Operational I/O Registers
Command/ConfigurationCommand/Configuration– Management of HC, schedules on/off, etc.Management of HC, schedules on/off, etc.
StatusStatus Interrupt ManagementInterrupt Management Schedule ManagementSchedule Management
– Periodic Base PointerPeriodic Base Pointer– Frame IndexFrame Index– Asynchronous List PointerAsynchronous List Pointer
Port Status and Control Port Status and Control
October 10, 2000 10
AgendaAgenda
Project OverviewProject Overview Key Features OverviewKey Features Overview
– USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture– EHCI HC Interface ArchitectureEHCI HC Interface Architecture– EHCI HC Data StructuresEHCI HC Data Structures– Operational Models (Overview/Examples)Operational Models (Overview/Examples)
Host Controller Compliance ProgramHost Controller Compliance Program SummarySummary
October 10, 2000 11
EHCI Data StructuresEHCI Data Structures
Five (5) basic data structures (schedule objects)Five (5) basic data structures (schedule objects)– Queuing Data Structure (2)Queuing Data Structure (2)– High-speed isochronous (1) High-speed isochronous (1) – Full-speed isochronous (1)Full-speed isochronous (1)– Frame List (1)Frame List (1)
Used to build construct Periodic and Used to build construct Periodic and Asynchronous SchedulesAsynchronous Schedules
All data structures support simple data buffer All data structures support simple data buffer scatter/gatherscatter/gather
October 10, 2000 12
Queuing Data StructuresOverviewQueuing Data StructuresOverview
Queues are used for ALL Non-Isochronous transfersQueues are used for ALL Non-Isochronous transfers Uses 2 data structures:Uses 2 data structures:
– qHead and a qElementqHead and a qElement 1 queue per endpoint1 queue per endpoint Each queue element (transaction descriptor)Each queue element (transaction descriptor)
describes a buffer (1 to many transactions)describes a buffer (1 to many transactions)– Up to 20 Kbytes per transaction descriptorUp to 20 Kbytes per transaction descriptor
16Kbytes with worst-case buffer alignment16Kbytes with worst-case buffer alignment
No Hardware/software sync required to add work to a queueNo Hardware/software sync required to add work to a queue Architecture optimized to provide efficient memory accessesArchitecture optimized to provide efficient memory accesses
– Block, burst accessesBlock, burst accesses– Efficient, cache execution modelEfficient, cache execution model
October 10, 2000 13
HS Isochronous Data Structure OverviewHS Isochronous Data Structure Overview
HS Isochronous use isochronous Transfer HS Isochronous use isochronous Transfer Descriptors (iTDs)Descriptors (iTDs)
Linked into periodic schedule (made ‘reachable’ Linked into periodic schedule (made ‘reachable’ in the appropriate frames)in the appropriate frames)
Time-oriented data structureTime-oriented data structure– ““Frame number” encoded in topology of listFrame number” encoded in topology of list– No hardware (micro)-frame arithmetic requiredNo hardware (micro)-frame arithmetic required– Position of work item in periodic list determines Position of work item in periodic list determines
whenwhenit will be “seen” and executed by the host it will be “seen” and executed by the host controllercontroller
8 transaction descriptions per iTD8 transaction descriptions per iTD Supports High-bandwidthSupports High-bandwidth Supports up to 28K bytes per iTDSupports up to 28K bytes per iTD Requires multiple iTDs to maintain HS Requires multiple iTDs to maintain HS
isochronous data streamisochronous data stream
Buffer Buffer pointer pointer ArrayArray
NextNext
Transaction Transaction RecordRecordDescriptionDescriptionArray (8)Array (8)
Endpoint Endpoint InformationInformation
Isochronous Transfer Descriptor (iTD)
October 10, 2000 14
FS Isochronous Data Structure OverviewFS Isochronous Data Structure Overview
FS Isochronous uses split isochronous FS Isochronous uses split isochronous Transfer Descriptors (siTDs)Transfer Descriptors (siTDs)
Similar usage and behavioral model as Similar usage and behavioral model as iTDs, except:iTDs, except:
Will only use split transactionsWill only use split transactions 1 FS transaction per siTD1 FS transaction per siTD
– Linked in one siTD per FrameLinked in one siTD per Frame Supports one page boundarySupports one page boundary Appropriate mechanisms to care and feed Appropriate mechanisms to care and feed
isoch split transactionisoch split transaction
NextNext
Endpoint Info.Endpoint Info.
Transfer StateTransfer State
Buffer pointer(s)Buffer pointer(s)
October 10, 2000 15
Periodic Frame ListPeriodic Frame List
Array of schedule object pointersArray of schedule object pointers Represents a rolling window of Represents a rolling window of
timetime– Each location is base pointer for one Each location is base pointer for one
frame’s worth of work (8 micro-frame’s worth of work (8 micro-frames) frames)
– Frame work for establishing time Frame work for establishing time oriented reachabilityoriented reachability
HC builds a Periodic Frame list HC builds a Periodic Frame list address from:address from:– Periodic frame list base addressPeriodic frame list base address– Frame Index Register [12:3]Frame Index Register [12:3]
increments once each frame (1ms)increments once each frame (1ms)
Frame List BaseFrame List Base
12123131 1313 1212 33 00
Frame IndexFrame Index
3131 1212 1111 22
Periodic Frame List Periodic Frame List
… To schedule graphTo schedule graph
Accesses same offset 8 micro-Accesses same offset 8 micro-frames before preceding to frames before preceding to next locationnext location
October 10, 2000 16
AgendaAgenda
Project OverviewProject Overview Key Features OverviewKey Features Overview
– USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture– EHCI HC Interface ArchitectureEHCI HC Interface Architecture– EHCI HC Data StructuresEHCI HC Data Structures– Operational Models (Overview/Examples)Operational Models (Overview/Examples)
Host Controller Compliance ProgramHost Controller Compliance Program SummarySummary
October 10, 2000 17
EHCI Operational ModelsEHCI Operational Models
Asynchronous Schedule OverviewAsynchronous Schedule Overview Queuing example operationQueuing example operation Periodic Schedule OverviewPeriodic Schedule Overview HS IsochronousHS Isochronous HS InterruptHS Interrupt Asynchronous split transactionsAsynchronous split transactions Periodic split transactionsPeriodic split transactions
October 10, 2000 18
Current qHead PointerCurrent qHead Pointer
Asynchronous Schedule OverviewAsynchronous Schedule Overview
Schedule includes only Queue HeadsSchedule includes only Queue Heads Organized in simple, circular list Organized in simple, circular list Manages HS/FS/LS asynchronous endpointsManages HS/FS/LS asynchronous endpoints Yields Round-Robin Service OrderYields Round-Robin Service Order Supports FS/LS asynchronousSupports FS/LS asynchronous
I/O Register:I/O Register:Asynchronous List PointerAsynchronous List Pointer
October 10, 2000 19
Queuing Example OperationQueuing Example Operation
Transfer DescriptorsTransfer Descriptors
Linked to queue head Linked to queue head by software driverby software driver
Transfer DescriptorsTransfer Descriptors
Linked to queue head Linked to queue head by software driverby software driver
qTDqTD00qTDqTD00
qTDqTD22qTDqTD22
Data Data BufferBuffer00
Data Data BufferBuffer00
Data Data BufferBuffer11
Data Data BufferBuffer11
qTDqTD11qTDqTD11
DataDataBufferBuffer22
DataDataBufferBuffer22
Queue Head:Queue Head:Static queue head informationStatic queue head informationDynamic transfer execution areaDynamic transfer execution area
Queue Head:Queue Head:Static queue head informationStatic queue head informationDynamic transfer execution areaDynamic transfer execution area
SetupSetupSetupSetup
StatusStatusStatusStatus
Setup Setup DataData
Setup Setup DataData
Receive Receive DataData
BufferBuffer
Receive Receive DataData
BufferBuffer
DataDataDataData
Example: Control TransferExample: Control Transfer
Initial Condition: QHD emptyInitial Condition: QHD empty
Example: Control TransferExample: Control Transfer
Initial Condition: QHD emptyInitial Condition: QHD empty
Example: Control TransferExample: Control Transfer
Software attaches list to QHDSoftware attaches list to QHD
Example: Control TransferExample: Control Transfer
Software attaches list to QHDSoftware attaches list to QHDCurrentCurrent
(A)(A)
(A) HC Finds an active qTD via a QHD (A) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Setup Stage)area (Setup Stage)
Copy results in QHD Next pointer Copy results in QHD Next pointer inheriting from overlay’d qTDinheriting from overlay’d qTD
HC executes from QHD for 1 HC executes from QHD for 1 transactiontransaction
NextNextNext
(B)(B)(B)(B)
(B) HC Finds an active qTD via a QHD (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Data Stage)area (Data Stage)
Copy results in QHD Next pointer Copy results in QHD Next pointer inheriting from overlay’d qTDinheriting from overlay’d qTD
HC executes from QHD until doneHC executes from QHD until done
(B) HC Finds an active qTD via a QHD (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Data Stage)area (Data Stage)
Copy results in QHD Next pointer Copy results in QHD Next pointer inheriting from overlay’d qTDinheriting from overlay’d qTD
HC executes from QHD until doneHC executes from QHD until doneCurrentCurrentCurrentCurrentCurrentCurrentCurrentCurrent
NextNextNextNext
(C) HC Finds an active qTD via a QHD (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Status Stage)area (Status Stage)
Copy results in QHD Next pointer Copy results in QHD Next pointer inheriting from overlay’d qTDinheriting from overlay’d qTD
HC executes from QHD for 1 HC executes from QHD for 1 transactiontransaction
(C) HC Finds an active qTD via a QHD (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Status Stage)area (Status Stage)
Copy results in QHD Next pointer Copy results in QHD Next pointer inheriting from overlay’d qTDinheriting from overlay’d qTD
HC executes from QHD for 1 HC executes from QHD for 1 transactiontransaction
(C)(C)(C)(C)
October 10, 2000 20
Periodic Schedule OverviewPeriodic Schedule Overview
Periodic Frame List is the basePeriodic Frame List is the base– Size is optionally programmableSize is optionally programmable
Objects linked so are ‘reachable’ Objects linked so are ‘reachable’ at the correct timeat the correct time
Schedule graph includes:Schedule graph includes:– Queue Heads for InterruptQueue Heads for Interrupt– HS Isochronous,HS Isochronous,– FS IsochronousFS Isochronous
Poll Rate: N Poll Rate: N 1 1
Periodic Frame ListPeriodic Frame List
End of List MarkEnd of List Mark
44
22
Periodic List Base + Periodic List Base + Frame Index[12:3] = Frame Index[12:3] = current Frame offsetcurrent Frame offset
October 10, 2000 21
• Frame Index [2:0] bits serve as index to select a transaction record; e.g. a value of 010b will select transaction record #2.
• If the Status.Active field of selected transaction record is a one, then a transaction will be executed.
13 12 3 0
Frame Index
HS Isochronous Example OperationHS Isochronous Example Operation
Starting data buffer is derived from:
x = FRAME INDEX[2:0]
BufferPageA[tRec[x].PG] concatenated with tRec[x].TransactionOffset
Token is derived from EndPt and Device Address fields.
Length of the transaction is: tRec[x].TransactionLength or Max Packet Size field, whichever is less.
Direction of transfer is determined by the I/O field.
Host controller decrements Transaction Length by the number of bytes moved, and updates the Status field appropriately.
Concat.Concat.
Buffer Buffer pointer pointer ArrayArray
NextNext
Transaction Transaction RecordRecordDescriptionDescriptionArray (8)Array (8)
Endpoint Endpoint InformationInformation
Isochronous Transfer Descriptor (iTD)
October 10, 2000 22
HS InterruptHS Interrupt
Uses queuing data structuresUses queuing data structures– No change to behavioral modelNo change to behavioral model
Linked into periodic schedule (made ‘reachable’ in Linked into periodic schedule (made ‘reachable’ in the appropriate frames)the appropriate frames)– HS poll rates are micro-framesHS poll rates are micro-frames– Embedded bit-mask in qHead describes micro-frame Embedded bit-mask in qHead describes micro-frame
patternpattern Simple mechanism to support high-bandwidthSimple mechanism to support high-bandwidth
October 10, 2000 23
Asynchronous Split TransactionsAsynchronous Split Transactions
Micro-machine extension to the HS queue Micro-machine extension to the HS queue execution modelexecution model– HS transfer advancement occurs when HS transaction HS transfer advancement occurs when HS transaction
is completeis complete– FS/LS transfer advancement occurs when start-split FS/LS transfer advancement occurs when start-split
and complete splits are completeand complete splits are complete Endpoint speed encoding directs HC to use split Endpoint speed encoding directs HC to use split
protocolprotocol All other behavior same as HS asynchronousAll other behavior same as HS asynchronous
October 10, 2000 24
Periodic Split TransactionsPeriodic Split Transactions
Used to service data streams through TT periodic Used to service data streams through TT periodic pipelinespipelines
Requirement on HC is to:Requirement on HC is to:– Execute starts and completes when they need to occurExecute starts and completes when they need to occur
Each endpoint data structure contains:Each endpoint data structure contains:– Masks for Starts/CompletesMasks for Starts/Completes– Micro-state to track progress (to detect lost data, etc.)Micro-state to track progress (to detect lost data, etc.)
Projection of core-spec bus frame boundaries into Projection of core-spec bus frame boundaries into the host schedule created many scheduling the host schedule created many scheduling boundary conditions, so…boundary conditions, so…
October 10, 2000 25
7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 0
CS CS CS CS SS CS CS CS CS
7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2
HHSS BBuuss FFrraammeess
HHCC PPeerriiooddiicc SScchheedduullee
MMiiccrroo--ffrraammeess
HHSS//FFSS//LLSS BBuuss FFrraammee BBoouunnddaarriieess
HHCC PPeerriiooddiicc SScchheedd.. FFrraammee BBoouunnddaarriieess
SS
BB--FFrraammee NN BB--FFrraammee NN++11
IInntteerrffaaccee DDaattaa SSttrruuccttuurree
IInntteerrffaaccee DDaattaa SSttrruuccttuurree
HH--FFrraammee NN HH--FFrraammee NN++11
ffuullll//llooww--ssppeeeedd ttrraannssaaccttiioonn
ffuullll//llooww--ssppeeeedd ttrraannssaaccttiioonn
Mapping Bus Frames to Host FramesMapping Bus Frames to Host Frames
In order to simplify host for TT pipeline support:In order to simplify host for TT pipeline support:– Host view of frame boundaries is shifted one micro-frameHost view of frame boundaries is shifted one micro-frame
October 10, 2000 26
FS/LS Interrupt INExample OperationFS/LS Interrupt INExample Operation
Start-MaskStart-Mask 40h40hComplete-MaskComplete-Mask 03h03h
00 11 22 33 44 55 66 77 00 11 22H-FrameH-Frame
00 11 22 33 44 55 66 77 00 11B-FrameB-Frame 77
Queue Queue HeadHead
SSSS CSCS00 CSCS11
Reachable from Frame list Reachable from Frame list locations: 0,1, 8,9, 16,17 … locations: 0,1, 8,9, 16,17 … (poll period of 8)(poll period of 8)
October 10, 2000 27
FS Isochronous INExample OperationFS Isochronous INExample Operation
Start-MaskStart-Mask 08h08hComplete-MaskComplete-Mask C3hC3h
00 11 22 33 44 55 66 77 00 11 22H-Frame XH-Frame X
00 11 22 33 44 55 66 77 00 11B-FrameB-Frame
77
siTDsiTDXX
SSSS CSCS00 CSCS11 CSCS22 CSCS33
H-Frame X+1H-Frame X+1
siTDsiTDX+1X+1
October 10, 2000 28
AgendaAgenda
Project OverviewProject Overview Key Features OverviewKey Features Overview
– USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture– EHCI HC Interface ArchitectureEHCI HC Interface Architecture– EHCI HC Data StructuresEHCI HC Data Structures– Operational Models (Overview/Examples)Operational Models (Overview/Examples)
Host Controller Compliance ProgramHost Controller Compliance Program SummarySummary
October 10, 2000 29
EHCI Compliance ProgramEHCI Compliance Program
EHCI EHCI ComplianceCompliance
Standard USB 2.0 Standard USB 2.0 Compliance TestsCompliance Tests
EHCI-specific EHCI-specific Functional TestingFunctional Testing
Data Data IntegrityIntegrity
Basic Basic Feature Feature FunctionFunction
Singleton Singleton StreamingStreaming
Streaming Streaming Interoperability Interoperability StressStress
USB 2.0 USB 2.0 Electricals Electricals (HS/FS/LS)(HS/FS/LS)
Hub Hub TestsTests
October 10, 2000 30
EHCI Compliance ProgramEHCI Compliance Program
EHCI-specific compliance EHCI-specific compliance software under development at software under development at IntelIntel
Special compliance devicesSpecial compliance devices(high-speed and full/low speed)(high-speed and full/low speed)
Special-purpose application and Special-purpose application and driver for controlled testingdriver for controlled testingand analysisand analysis
Interface Functional TestingInterface Functional Testing– Device InteroperabilityDevice Interoperability– USB 2.0 protocol andUSB 2.0 protocol and
transfer extensionstransfer extensions– System InteractionSystem Interaction– Etcetera, …Etcetera, …
EHCI Compliance EHCI Compliance ApplicationApplication
EHCI Compliance EHCI Compliance ApplicationApplication
EHCI Compliance EHCI Compliance Test DriverTest Driver
EHCI Compliance EHCI Compliance Test DriverTest Driver
EHCI Unit EHCI Unit Under TestUnder TestEHCI Unit EHCI Unit Under TestUnder Test
USB 2.0 USB 2.0 Hub (s)Hub (s)
USB 2.0 USB 2.0 Hub (s)Hub (s)
HS HS Compliance Compliance
Device(s)Device(s)
HS HS Compliance Compliance
Device(s)Device(s)FS/LS FS/LS
Compliance Compliance Device (s)Device (s)
FS/LS FS/LS Compliance Compliance Device (s)Device (s)
October 10, 2000 31
EHCI Compliance ProgramEHCI Compliance Program
Test AvailabilityTest Availability HC compliance test will be available from IntelHC compliance test will be available from Intel
– Method of distribution (to be defined)Method of distribution (to be defined) Alpha-level tools available in Q1 2001Alpha-level tools available in Q1 2001 Beta-level tools available in Q2 2001Beta-level tools available in Q2 2001 Production release available with release of 1.0 Production release available with release of 1.0
EHCI host controller specification in Q3EHCI host controller specification in Q3
Note: all dates provided are for planning purposes only and are subject to change
October 10, 2000 32
SummarySummary
Low-risk IntroductionLow-risk Introduction– All ports are HS/FS/LS CapableAll ports are HS/FS/LS Capable– Legacy (non-high-speed aware) software just worksLegacy (non-high-speed aware) software just works– Re-use of 1.1 controllers simplifies high-speed controllerRe-use of 1.1 controllers simplifies high-speed controller
Interface optimized for good memoryInterface optimized for good memoryaccess efficiencyaccess efficiency
Reasonable tradeoff of hardware/software Reasonable tradeoff of hardware/software complexitycomplexity
October 10, 2000 33
SummarySummary
Host controller compliance programHost controller compliance program– Alpha release Q1, 2001Alpha release Q1, 2001– Beta release Q2, 2001Beta release Q2, 2001– Final with 1.0 EHCI SpecificationFinal with 1.0 EHCI Specification
Specification Revisions available:Specification Revisions available:– Revision 0.95 for discrete HC Q3 2000Revision 0.95 for discrete HC Q3 2000– Revision 1.0 in 2001Revision 1.0 in 2001
Gating item is validation of integrated host controllerGating item is validation of integrated host controller
ContinuedContinued
Note: all dates provided are for planning purposes only and are subject to change