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EE141 EECS141 1 Lecture #9
Guest Lecturer: Andrei Vladimirescu
EE141 EECS141 2 Lecture #9
Midterm on Friday Febr 19 6:30-8pm in 2060 Valley LSB Open book Do not forget your important class material nor
calculator Covers from start of semester to optimization of
complex logic – wires not included! Review session tomorrow Th 2/18 at 6:30pm
Room to be announced on web-site No lab this week Hw 4 due next week Friday
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EE141 EECS141 3 Lecture #9
Last lecture Wiring + first glimpse at transitors
(threshold) Today’s lecture
Transistor models Reading (Ch 3)
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What do digital IC designers need to know?
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EE141 EECS141 5 Lecture #9
With positive gate bias, electrons pulled toward the gate With large enough bias, enough electrons will be pulled to "invert"
the surface (p→n type) Voltage at which surface inverts: “magic” threshold voltage VT
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Threshold
Fermi potential
2ΦF is approximately 0.6V for p-type substrates γ is the body factor VT0 is approximately 0.45V for our process
Depletion charge
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EE141 EECS141 7 Lecture #9
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Pinch-off
0< VGS - VT < VDS
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EE141 EECS141 9 Lecture #9
For (VGS – VT) < VDS, the effective drain voltage and current saturate:
’
Of course, real drain current isn’t totally independent of VDS For example, approx. for channel-length modulation:
’
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Cutoff: VGS -VT< 0
Linear (Resistive): VGS-VT > VDS
Saturation: 0 < VGS-VT < VDS
’
’
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EE141 EECS141 11 Lecture #9
Quadratic Relationship
0 0.5 1 1.5 2 2.5 0
1
2
3
4
5
6 x 10 -4
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
VDS (V)
I D (A
)
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Linear Relationship
-4
0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5 x 10
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
VDS (V)
I D (A
)
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EE141 EECS141 13 Lecture #9
ξ (V/µm)
υ n
( m / s
)
υ sat = 10 5
Constant mobility "(slope = µ)
Constant velocity
ξ c
Velocity saturates due to carrier scattering effects
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I D Long-channel device
Short-channel device
V DS V DSAT V GS - V T
V GS = V DD
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EE141 EECS141 15 Lecture #9
0 0.5 1 1.5 2 2.5 0
1
2
3
4
5
6 x 10 -4
V GS (V)
I D (A
)
0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5 x 10 -4
V GS (V) I D (
A) quadratic
quadratic
linear
Long Channel"(L=2.5µm)
Short Channel"(L=0.25µm)
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Approximate velocity:
Continuity requires that:
Integrating to find the current again:
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EE141 EECS141 17 Lecture #9
-4
0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5 x 10 VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V
0 0.5 1 1.5 2 2.5 0
1
2
3
4
5
6 x 10 -4 VGS= 2.5 V
VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V
Resistive Saturation VDS = VGS - VT
VDS (V) VDS (V)
I D (A
)
I D (A
)
Resistive Velocity Saturation
Long Channel"(L=2.5µm)
Short Channel"(L=0.25µm)
W/L=1.5
VDSAT VGS-VT
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Exact behavior of transistor in velocity sat. somewhat challenging if want simple/easy to use models
So, many different models developed over the years v-sat, alpha, unified, VT*, etc.
Simple model for manual analysis desirable Assume velocity perfectly linear until υsat
Assume VDSAT constant
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EE141 EECS141 19 Lecture #9 19
ξ (V/µm)
υ n
( m / s
)
υ sat = 10 5
Constant velocity
Assume velocity perfectly linear until hit υsat
ξ c = υsat/µ
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VGS-VT (V)
Assume VDSAT = ξcL when (VGS – VT) > ξcL
ξcL
V DSA
T (V)
ξcL
Actual VDSAT
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EE141 EECS141 21 Lecture #9
B
D
G
ID
S
for VGT ≤ 0: ID = 0
with VDS,eff = min (VGT, VDS, VD,VSAT)
for VGT ≥ 0:
define VGT = VGS – VT
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-4
0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5 x 10
Velocity Saturation
VDS (V)
I D (A
)
VDS = VGT
VGT = VD,VSAT
Saturation
Linear
VDS = VD,VSAT
Define VGT = VGS – VT, VD,VSAT = ξc·L
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EE141 EECS141 23 Lecture #9
0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5 x 10 -4
V DS (V)
I D (A
)
VDS=VD,VSAT
VDS=VGT
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If device always operates in velocity sat.:
“VT*” model:
Good for first cut, simple analysis
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Textbook: page 103
V
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-2.5 -2 -1.5 -1 -0.5 0 -1
-0.8
-0.6
-0.4
-0.2
0 x 10 -4
V DS (V)
I D (A
)
• All variables negative
• I prefer to work with absolute values – makes life easier.
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
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EE141 EECS141 27 Lecture #9
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= CGCS + CGSO = CGCD + CGDO
= CGCB = Cdiff
G
S D
B
= Cdiff
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EE141 EECS141 29 Lecture #9
Capacitance (per area) from gate across the oxide is W·L·Cox, where Cox=εox/tox
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Distribution between terminals is complex Capacitance is really distributed
– Useful models lump it to the terminals Several operating regions:
– Way off, off, transistor linear, transistor saturated
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EE141 EECS141 31 Lecture #9
When the transistor is off, no carriers in channel to form the other side of the capacitor. – Substrate acts as the other capacitor terminal – Capacitance becomes series combination of gate
oxide and depletion capacitance
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When |VGS| < |VT|, total CGCB much smaller than W·L·Cox – Usually just approximate with CGCB = 0 in this region.
(If VGS is “very” negative (for NMOS), depletion region shrinks and CGCB goes back to ~W·L·Cox)
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EE141 EECS141 33 Lecture #9
Channel is formed and acts as the other terminal – CGCB drops to zero (shielded by channel)
Model by splitting oxide cap equally between source and drain – Changing either voltage changes the channel charge
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Changing source voltage doesn’t change VGC uniformly – E.g. VGC at pinch off point still VTH
Bottom line: CGCS ≈ 2/3·W·L·Cox
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EE141 EECS141 35 Lecture #9
Drain voltage no longer affects channel charge – Set by source and VDS_sat
If change in charge is 0, CGCD = 0
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Cgate vs. VGS (with VDS = 0)
Cgate vs. operating region
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EE141 EECS141 37 Lecture #9 37
Off/Lin/Sat CGSO = CGDO = CO·W
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COV not just from metallurgic overlap – get fringing fields too
Typical value: ~0.2fF·W(in µm)/edge
n + n +
Cross section
n + n +
Cross section
Fringing fields