ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPDENG
DATE
APPDCK
ECNZONEREV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTIOND
SIZE
APPLICABLENOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OFSHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
12345678
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B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
DRAWING
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
630-4843
630-4902
LINK630-4902630-4843
PCBA,LINK,Q51
BOM Option Table
(Nimitz)
02/23/2004 EVT1
Q51 Specific design/Connectors
Signal Cross Reference (1 of 2)
Sync
VESTA1V2_BURST
VESTA_PWR_CLASS_0
CPU_AVDD_2V8CPU_PLL_MEDIUMN/A
Module
(Nimitz)
Power Block Diagram
2.5V / NB Vcore / PMU Regulators
Processor
Memory Series Termination
Alternates Components
NO_SMU_I2C_DAGP_BUSYSTOP
(Fizzy)
07/28/03THERM_2
MPIC_NB
BOM Options
Shasta HyperTransport InterfaceU3Lite HyperTransport Interface
(Nimitz)
N/A
GPU VCore Regulator
5958
Table of Contents
Battery Charger
System Management Unit (SMU)
VESTA_DS_ONLY_EN0
M11CSP64Component Cross Reference (1 of 2)Signal Cross Reference (2 of 2)
N/A
09/18/03
10/01/03
N/A
(Nimitz)
Contents
EI_3TO1
SMU_CPU_I2C
09/30/03
(100)
(94)
Vesta FireWire
(Link)
54
3.3V / 5V Regulators
Thermal Sensor / Fans
2
(Link)
6665
6362
64
6160
57
51
56
48
50
52
55
49
53
47
40393837
41
4344
42
4546
36
Interface
MainMemory 35
34
N/A
(Link)
I2C ConnectionsLMU Support
(18)
21 Shasta Core
15(16)
(40)
(29)
(28)
(37)
(36)
(33)
(38)
(30)
(31)
(32)
(27)
(20)
(21)
(24)
(26)
(25)
(22)
(23)
SO-DIMM Connectors
U3Lite Misc
CPU Temperature Monitoring
PPC970 Processor Interface
PPC970 BypassingPPC970 Core
Pulsar Core
U3Lite Processor Interface
CPU VCore Regulator
Shasta Misc
Pulsar Clocks
08/01/03
Gila
Gila
Gila
Gila
U3Lite
Gila
(Gila)
U3Lite
09/18/03
09/25/03
09/18/03
09/18/03
09/18/03
09/18/03
09/18/03
09/11/03
Gila
(Fizzy)
(Gila)
(Nimitz)
Gila
(Gila)
(Fizzy)
09/18/03
09/18/03
08/01/03
07/28/03
07/28/03
07/28/03
17
1920
222324
2625
2728
3029
313233
Schematic / PCB #’s
CRef
Ethernet
FireWire
Vesta Power / Misc
System Power Connectors
Power & Signal AliasesM10-CSP64 Core
09/11/03
Vesta Ethernet
Page
South Bridge Disk Interfaces
M10-CSP64 Misc Power
Serial ATA to Parallel ATA Bridge
Modem
Transport
Graphics
Functional Test Properties
Revision Notes
System Block Diagram
(.csa)
M10-CSP64 AGP Interface
7
(Fizzy)
Sync1
Fizzy
(77)
N/A
(Fizzy) PCI09/01/03
TOP
CardBus Controller & Connector
(Nimitz)
South Bridge Firewire
Misc Internal Connectors
11
N/A
07/28/03
(smu_real)13
(Link)
09/25/03
Date
09/18/03
09/18/03
Audio
(Fizzy)
(Link)
(Fizzy)
(59)
09/11/03
09/11/03
09/11/03(Link)
(52)
(48)
6
89
(1)
(89)
(74)
N/A
34 (4)
(2)
(90)
(76)
(81)
(84)
(80)
(86)
(50)
(57)
(51)
(49)
(62)
(60)
(.csa)
Fizzy
Fizzy
07/28/03
07/28/03
(Nimitz)
Fizzy
07/01/03
08/01/03
Date
(75)
(87)
N/A(103)
(99)
(95)
(101)
(83)
Modem Interface
(102)
(5)
(6)
(13)
(7)
BootROM
08/06/03
Gila
(12)12
5
(Fizzy)
(Fizzy)
07/28/03
09/15/03
10
(Nimitz)
07/01/03(Link)
Disk
(91)
ContentsU3Lite AGP Interface
07/28/03
USB2 Controller PCI Interface
09/13/03South Bridge PCI Interface
09/30/03
09/30/03
07/01/03
(10)
(11)
09/26/03
(Link)(15)
14
Video Connectors
UATA/PATA Connectors
AirPort Extreme Connector
Fizzy
(Nimitz)
N/A
(Link)
16 08/01/03
(9)
09/30/03
USB InterfacesFireWire Ports
(88)
Audio Interface (Fizzy)
09/30/03
07/28/03
07/28/03
08/01/03
07/01/03
08/06/03
08/06/03
Ethernet Magnetics & Connector
South Bridge Ethernet
(78)
(Fizzy/Nimitz)
09/25/03
08/01/03
(3)
Hyper-
USB
Page
09/01/03
(Nimitz)
(14)
NO STUFFSTUFF
THERM_1B
MPIC_SB
THERM_3
GPU_SSDEVELOPMENT
THERM_2B
SMU_CPU_JTAGTHERM_1
PCI_64BITPATA_5V_LOGIC
THERM_3B
INT_TMDSEXT_TMDS
(Fizzy)
(Fizzy)
(Fizzy/Nimitz)
End of Modules Placeholder
(Fizzy)
VESTA1V2_PULSE
08/01/03
PPC970 Pull-ups / Pull-downs
U3Lite Core
Power Sequencing Connections
U3Lite Memory Interface
Component Cross Reference (2 of 2)
TMDS Terminations
Module
18
08/01/03
1.8V / 1.5V/ 1.2V Regulators
(8)
Module Components
U3Lite
PATA_3V3_LOGIC
(Fizzy)
(Fizzy/Nimitz)
SB_HT_200M
M11CSP128
SCHEM,LINK,Q51
ENGINEERING RELEASED31600803 02/23/04
1 10303051-6532
?
1 IC,ATI,M11-CSP64,NO HEATSPREADER338S0154 CRITICALU4900 M11CSP64
CRITICALU86001343S0288 IC,ASIC,VESTA,V1.1
PCBF,LINK,Q51820-1573 1 PCB1
SCHEM,LINK,Q51051-6532 SCH11
U1300SMU,PROTO,Q51 CRITICAL1341S1394
341S1340 BOOTROM,PROTO,Q51 U7500 CRITICAL1
TITLE=LINKABBREV=DRAWINGLAST_MODIFIED=Mon Feb 23 18:35:53 2004
1 IC,ATI,M11-CSP128,NO HEATSPREADER U4900 M11CSP128CRITICAL338S0158
343S0283 IC,ASIC,SHASTA,V1.1,484BALL,PBGA CRITICAL1 U2300
IC,U3LITE,V1.1,300MM,PBGA1 CRITICALU3343S0284
337S2835 IC,PPC970,1.8GHz,1.1V,80C,25W,576CBGA1 U2900 CRITICAL
343S0282 U3 U3L,V1.1,200MM,PBGA343S0284
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.2V/600MHz
ELASTIC INTERFACE44-BIT/Directional
PAGE 12Core
PAGE 53
ETHERNET
VESTA
SCCAI2S1 I2S2
J9500
USB 1.1
33MHZ
3.3V/5V
Bluetooth = USB 1.1 (Low/Full Speed)
PORT = USB 2.0 (Low/Full/High Speed)
J7800
133MHz/3.3V/16 Bit1.5Gbps/1.2V/1 Bit/Directonal
133MHz/3.3V/16 Bit
CPU
APPLE PI
SYSTEM BLOCK DIAGRAM
PAGE 21
P.17J4010/J4020Level shifting
SMU
I2C buses
P.7
NEO 10S
P.15Thermal
RTC Max1668P.13
DDR SDRAM DIMM 1
I2C
EI Clocks
DDR SDRAM DIMM 0
MISC
PAGE 25
APPLE PIP.26-29
P.23-24Connector
BatteryConnector
Power Supply
Nicky (PWR)
U2600
Connector
Bluetooth
Hard DRIVE
PCI BUS
uPD720101
U7500
P.18P.18
P.48
3.3V
PCI1510
PAGE 44
PCI
UATA
SATA
P.34
CardbusPAGE 46
P.51
P.50
Cardbus
HT Clocks
PAGE 48 PAGE 47
PAGE 43
PAGE 55
PAGE 52
PAGE 49
PAGE 49
GPIO/PCI64PAGE 22
PAGE 20
PAGE 22
PAGE 45P.60 P.18 P.59
P.16
PAGE 56
FIREWIRE
P.57
P.57
P.54
P.41P.41
ENET Pairs
P.41
P.41
P.36,38-40
PAGE 42
PAGE 35
PAGE 32
PAGE 19
P.51
P.16
VSP Clock
U2900
Not Used
Sound (Kazoo)Connector
4 Datapairs @125MHz
Connector
S-Video/Comp
HYPERTRANSPORT8-BIT/Direction
SYSTEM BLOCK DIAGRAM
J700
ConnectorP.7
267/533MHZ32BITS1.5V/0.8V4X/8XAGP BUS
Pulsar
P.7-12
DVI-IConnector
J5900
GigabitJ8700
EthernetConnector
ConnectorFirewire A
J9010
2 Datapairs @200MHz
TMDS
RGB
DDC
(INTERNAL MEM)
CH. DMEMORY
(INTERNAL MEM)
CH. CMEMORY
MEMORYCH. B
CH. AMEMORY
(INTERNAL MEM)
(INTERNAL MEM)
ATIU4900
HYPERTRANSPORT
MEMORY BUS
MAIN MEMORY
AGP
U3
CORE
U3LITE
LVDS
U8600
J5970
InverterConnector
GMII (3.3V/125MHz)
ETHERNET
FIREWIRE
SCCB
J5980
CONTROL = 2.5V
SHASTA
SATA1
U2300
128BITS333MHz
I2S
I2S0
AirportExtreme
J7600
U8150
J8300
OPTICAL DRIVE
HYPERTRANSPORT
Connector
33MHZ
BOOTROM
SATA2
2 Datapairs @400MHzConnectorFirewire B
32BITS
CORE
J790Backup Battery
ConnectorP.7
Right USB
FW-B pairs
U7700
LEFT USBJ1600
1394 OHCI (3.3V/98MHz)
Connector
1.2V/400MHZ
SODIMM Connector
J8350
2.5V
LCD Panel
USB 2.0
S-VideoJ5960
Connector
USB 2.0 (Low/Full/High Speed)
USB 1.1 (Low/Full Speed)
ModemJ9400
8-bit TX & 8-bit RX
Connector
J1699SMU/JRDebug
U7800
J2130
USB TrackpadConnector
16/32 BITS
ConnectorLEDSleep
LEDKB
& Charger
J9020
FW-A Pairs
J750P.13
Clock Gen
U1300
Serial ATABridge
SATA ClockPCI ClocksAGP Clocks
Connector
64/128MBM11
103203051-6532
Preliminary
www.vinafix.vn
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
MAX1544
PP5V_PWRON
(pg 39)
FETSLEEP
Inverter Connector
Circuit
5VPWRON => 20W/25W
1V2PWRON => 10W
TOTAL => 58W/67WTOTAL => 46W+?
Firewire => 8W/15W
2V5PWRON => 10W3V3PWRON => 10W/6.6W
Power BudgetPPBUS_ALL_B
1V8_RUN => 5WCharger => ??W
PPBUS_ALL_A
Power Budget
CPU_Core => 28WGPU_Core => 6WInverter => 7W
Enable Circuit A
PPBUS_ALL_A(pg 11)
Power Supplies4.6V/3.3V
SMU
Battery
(pg 7)
Max1535
(pg 8)
Battery ChargerStops charging when
than xxWsystem draws more
Enable Circuit BBattery Out
(pg 8)
(pg 8)
(pg 8)ProtectionBackfeed
(pg 7)LimiterIn-Rush
(pg 7)
AC Adapter
Battery Out
GPU Vcore SwitcherSelectable 1.2V/1.0V
MAX1993
(pg 35)
Circuit(pg 8)
Charge Enable
Backup
CurrentSense(pg 8)
PBUS Isolation
(pg 8)
Voltage Toggled by SMUCPU Vcore Switcher
(pg 29)
PP18V5_ALL_DCIN PP18V5_ALL_INRUSH PP18V5_ALL_SENSE
(MAX1544 Built-in Current Sense)
(overcurrent shutoff)
Connector
5A Fuse (pg 8)
5A Fuse (pg 8)
PPBUS_ALL_B
PPVCORE_RUN_CPU
PPBUS_INVERTER
PP1V2_RUN_GPU
3S3P Prismatic Battery Pack
Power Block Diagram
(pg 9)
FET
FETSLEEP
FETSLEEP
LTC3412
(pg 56)Firewire A Conn
(pg 56)Firewire B Conn
1.5A Fuse (pg 56)
(pg 56)
PP3V3_PWRON
PP2V5_RUNSLEEPFET
PP2V5_PWRON
(pg 11)
TPS5120NBVCORE/2.5V DC Switcher
(pg 9)
(pg 10)
LP39821.8V LDO
TPS5120
PP1V8_RUN
(pg 9)
Enable Circuit1.5A Fuse (pg 12)
LEGEND
_RUN=ON during Run_PWRON=ON during Run/Sleep_ALL=ON during Shutdown/Run/SleepPN=Power NegativePP=Power Positive
PP1V5_RUN
TP620501.5V DC Switcher
5V/3.3V DC Switcher
1.2V DC Switcher PP1V2_PWRON
PP1V2_RUN
FETSLEEP
SLEEP PP5V_RUN_HD
PP5V_RUN
PP3V3_RUN
PP1V5_PWRON
PPVCORE_NB_PWRON
Port PWR
Connector(pg 11)
Cell 1 Cell 2 Cell 3
Cell 5
Battery
Cell 6Cell 4
Cell 8 Cell 9Cell 7
10303051-6532
3TITLE=LINKABBREV=DRAWINGLAST_MODIFIED=Mon Feb 23 18:35:54 2004
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
2/19/04
2/11/042/12/04
2/23/04
42) changed C3676 to 10uF 20% 6.3V to adjust the Tdiode range43) changed R3677 to 40.2K 0.1% to adjust the Tdiode range44) mirrored FL9020 and FL9021 to fix layout45) changed L970 to 152S0154 (10uH) to reduce size46) removed 197S0703 as alternate for 197S0037 (25MHz Vesta crystal)47) changed all references to SMU_MANUAL_RESET_L to SMU_RESET_L
48) removed DC current limit circuit (U870 and associated discretes)49) added BOMOPTION for 2.8V CPU Avdd LDO51) changed R1610 (series R on SMU_ONEWIRE output) to 0 ohm
54) added NO_TEST properties to CPUVCORE_GNDSENSE and CPUVCORE_SENSE
41) changed R3676 to 100K 0.1% to adjust the Tdiode range
14) changed C2150 to 20%
*** sync with Logic *** 2/2/04
2/3/042/6/04
2/7/04
2/10/04
*** sync with Gila ***1/20/04
1/14/04
35) sync with Gila (Q45) to fix several power disconnects37) sync with Logic (Q43) to get DVO contraints38) changed R3671 to 100K 0.1% to adjust the Tdiode range39) changed C3671 to 10uF 20% 6.3V to adjust the Tdiode range40) changed R3672 to 40.2K 0.1% to adjust the Tdiode range
31) changed R1102 to 20K 1% 40230) changed C1121 to 680pF 40229) changed L1115 to 2.2uH IHLP5050CE (152S0152)28) removed Q1117 and C111427) changed C1068 to NO STUFF26) changed R800 and R810 to 1/2W 1206 10mohm25) changed C720 to 0.22uF24) changed PPVCORE_RUN_CPU connection to XW592 to _PP1V5_RUN_FET23) added alias from TP_SATA_CLK25M to SATA_CLK25M22) added R1620 and R1621 to divide ALS output down to 2.5V21) changed SMU_ADAPTER_ID to SMU_ONEWIRE20) changed Q2113 to second FET in Q590919) changed R2150 to 8.25 to reduce LED drive current to 20mA18) added pg 73 to alias PCI_SB nets back to PCI to reconnect
12) moved BS510 to page 18 for syncing with Logic
9) moved ZT9900-ZT9903 (EMI vias) to page 18 for syncing with Logic7) moved J1600 (BT/USB connector) to page 18 for syncing with Logic5) changed MIN_LINE_WIDTH of PP5V4_CHGR_LDO to 10 mils4) added 10 mil MIN_LINE_WIDTH and MIN_NECK_WIDTH to BKFD_PROT_EN_L
3) changed R2191 to pulldown on SYS_LED
53) changed C8160-C8160 (SATA AC coupling caps) to 0.01uF per Marvell recommendation52) added R1611 (1k pullup to PP3V3_ALL) on ADAPTER_ID to power SMU_ONEWIRE interface50) changed R4800 to 2.2 ohm 603, C4811 to 1uF 402, and C4816 to 0.1uF 402 in U3Lite AGP Avdd filter.
36) added aliases on page 5 to set unused CKE, CS, and MUX controls back to TP34) changed R5019 to 26.7K 1% to increase GPU Vcore current limit (rdar://3510721)33) added MIN_LINE_WIDTH and MIN_NECK_WIDTH properties to ALS1_PHOTODIODE and ALS1_OP_IN32) added MIN_LINE_WIDTH and MIN_NECK_WIDTH properties to CPUVCORE_CM_N and CPUVCORE_CS_N
17) changed PCI from shasta to PCI_SB to allow desktops to insert series R’s
16) changed C2115 to R2116 (3.32K 1% 402) to divide ALS output to 2.5V15) added 10 mil MIN_LINE_WIDTH and MIN_NECK_WIDTH to KBDLED_ANODE and KDBLED_RETURN13) moved J2130 (trackpad connector) to page 18 for syncing with Logic11) moved ZT500-ZT505, ZT510, and ZT511 (plated screw holes) to page 18 for syncing with Logic10) moved SP500-SP505 and SP9900 to (speaker wire clips) to page 18 for syncing with Logic8) moved C860-C865 (PBus hold-up caps) to page 18 for syncing with Logic6) moved J790 (backup battery/R USB connector) to page 18 for syncing with Logic
2) moved AGP Vref (R4802,R4803,C4818) circuit to M11 specific page (49)1) moved Q3001-Q3004,D3001,D3002,R3044,R3046,R3048,R3070,R3050,R3052,R3054 from Page 27 to page 16 to allow sync with Gila
Revision Notes
4 10303051-6532
Preliminary
www.vinafix.vn
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ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
More Test Point Aliasing
ONLY ONE CAN BE CLOSED Between XW590/XW591!!!
USB Signal Aliasing
N/A (Most aliases are on this page)
Signal aliases required by this page:
BOM options provided by this page:
USB "0": Left USB Port
Power aliases required by this page:
(NONE)
N/A (Most aliases are on this page)
Page Notes
AGP Signal Aliasing
_RUN PWR
Graphic PWR
PBUS PWR
2.5V SMU VRef
USB "3": MicroDash Modem
_PWRON PWR
CPU/GPU Core PWR
Power Connections
USB "2": BlueTooth
USB "4": Trackpad/Keyboard
ONLY ONE CAN BE CLOSED Between XW550/XW551!!!
XW552 Always close
Chassis GroundsTest Point Aliasing
SMU Signal Aliasing
USB "1": Right USB Port
GPU is D3cold
PCI Signal AliasingCardBus is D3cold
ONLY ONE CAN BE CLOSED Between XW560/XW561!!!
PP3V3_ALL
PP3V3_RUN
PP5V_PWRON
PP3V3_PWRON
PP5V_RUN
PP1V5_RUN
PP1V5_PWRON
PP1V2_PWRON
21XW510
OPEN
21XW518
OPEN
21XW530
OPEN
PP1V2_RUN
21XW520
OPEN
21XW540
OPEN
21XW560
OPEN
XW561
OPEN
21XW552
OPEN
2
1R5015%1/4W
0
ATI_MEMIO_2V5
1210FF
2
1R5031/4W
0
1210FF
5%
ATI_MEMIO_1V8
2
1R5041/10W
5%0
FF805
2
1R5021/10W
805
5%
FF
0
2
1R5001/10W
805FF
05%
2
1R5051/10W
05%
805FF
PP1V8_RUN
21XW590
OPEN
21XW591
OPEN
21XW592
OPEN
2
1R5995%100K1/16WMF402
PP3V3_PWRON
PP2V5_PWRON
PP2V5_RUN
051-65325
03
103
VOLTAGE=0VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
GND
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=3.3V
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=3.3V
MIN_LINE_WIDTH=25 milVOLTAGE=5VMIN_NECK_WIDTH=10 mil
VOLTAGE=3.3VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
VOLTAGE=5VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=1.5V
MIN_NECK_WIDTH=10 milVOLTAGE=1.5VMIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 milVOLTAGE=1.2VMIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=1.2V
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=1.8V
VOLTAGE=2.5VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil VOLTAGE=2.5V
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
PP2V5_PWRON_RAM
PP1V5_PWRON_NB_AVDD
PPVCORE_PWRON_PULSAR_PP1V5_PWRON_1V5RUN
PP1V5_PWRON_REG
VOLTAGE=1.5VMAKE_BASE=TRUEMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
_PP1V5_PWRON_REG
PCI_CLK_GP0
PCI_CLK_P4
MAKE_BASE=TRUEPCI_CLK33M_CBUS
_PCI_CLK33M_CBUSPCI_CLK_GP1
MAKE_BASE=TRUEPCI_CLK33M_AIRPORT
_PCI_CLK33M_AIRPORTPCI_CLK_P3
MAKE_BASE=TRUEPCI_RESET_L _PCI_CBUS_RESET_L
MAKE_BASE=TRUEPCI_RESET_L _GPU_RESET_L
PPVCORE_NB_REGMAKE_BASE=TRUEMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 milVOLTAGE=1.3V
_PPVCORE_NB_REG
PP1V2_PWRON_REG
VOLTAGE=1.2VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
MAKE_BASE=TRUE
PPBUS_ALL_A
MIN_LINE_WIDTH=25 milVOLTAGE=18.5VMIN_NECK_WIDTH=10 mil
_PP3V3_PWRON_1V8RUN
_PP2V5_PWRON_1V8RUN_PP2V5_PWRON_2V5RUN
_PP3V3_RUN_SI_PP3V3_RUN_FAN
_PP1V2_PWRON_1V2RUN
SYS_WARM_RESET_LMAKE_BASE=TRUE
MAKE_BASE=TRUEPP1V5_GPU
VOLTAGE=1.5VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
_PP1V5_GPU_AGP
PP1V5_RUN
MAKE_BASE=TRUEPPVCORE_GPUFB
VOLTAGE=1.8VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
MAKE_BASE=TRUEPP1V8_GPU
VOLTAGE=1.8VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
_PP1V8_GPU
PP2V5_RUNPP1V8_RUN
PP1V8_RUN
USB2_PWREN<0>
USB2_OC<1>
MAKE_BASE=TRUEUSB_BT_N
MAKE_BASE=TRUEUSB2_OC3_PU
_PPVIN_5V3VPWRON
_PP5V_RUN_HD_FET
MAKE_BASE=TRUETP_FAN_TACH3MAKE_BASE=TRUE
TP_FAN_TACH2MAKE_BASE=TRUE
TP_FAN_RPM2
TP_EXT_LED_LMAKE_BASE=TRUE
FAN_TACH3
FAN_TACH2
FAN_RPM2
EXT_LED_L
_GND_CHASSIS_SVIDEO_GND_CHASSIS_DVI_BOTTOM
_GND_CHASSIS_FW_PORT1_GND_CHASSIS_FW_PORT2
_GND_CHASSIS_ENET
VOLTAGE=0VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
GND_CHASSIS_LVDS _GND_CHASSIS_LVDS
MIN_NECK_WIDTH=10 milVOLTAGE=0VMIN_LINE_WIDTH=25 mil
GND_CHASSIS_INVERTER _GND_CHASSIS_INV
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 milVOLTAGE=0V
GND_CHASSIS_DVI _GND_CHASSIS_DVI_TOP
MIN_NECK_WIDTH=10 milVOLTAGE=0VMIN_LINE_WIDTH=25 mil
GND_CHASSIS_IO
MIN_NECK_WIDTH=10 mil
MAKE_BASE=TRUEPPVCORE_PWRON_NB
MIN_LINE_WIDTH=25 milVOLTAGE=1.3V
_PPVCORE_PWRON_NB
_PP1V2_PWRON_REG
_PPVCORE_PWRON_SB
_PP1V2_PWRON_DISK_SB_PP1V2_PWRON_HT
PP2V5_HT
SMU_WARM_RESET_L
PPVCORE_PULSAR
_PP3V3_ALL_LDO
MIN_LINE_WIDTH=25 milMAKE_BASE=TRUE
PP2V5_PWRON_REG
MIN_NECK_WIDTH=10 milVOLTAGE=2.5V
SATA_TXD_N2 TP_SATA_TXD_N2MAKE_BASE=TRUE
SATA_RXD_N2_C TP_SATA_RXD_N2MAKE_BASE=TRUE
SATA_TXD_P2MAKE_BASE=TRUE
TP_SATA_TXD_P2
SATA_RXD_P2_CMAKE_BASE=TRUE
TP_SATA_RXD_P2
NB_THMOMAKE_BASE=TRUE
TP_NB_THMO
NB_THMI TP_NB_THMIMAKE_BASE=TRUE
NB_PMR_OBSV TP_NB_PMR_OBSVMAKE_BASE=TRUE
I2C_SMU_D_SCL TP_I2C_SMU_D_SCLMAKE_BASE=TRUE
FAN_TACH5MAKE_BASE=TRUE
TP_FAN_TACH5
FAN_TACH4 TP_FAN_TACH4MAKE_BASE=TRUE
SMU_SLEEP SYS_SLEEPMAKE_BASE=TRUE
USB2_OC4_PUMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_LT_P
_PP3V3_ALL_DCILIM
PPVCORE_GPU
PPVCORE_CPU
MIN_LINE_WIDTH=25 milVOLTAGE=1.2V
PPVCORE_GPU_REGMAKE_BASE=TRUE
MIN_NECK_WIDTH=10 mil
PPVCORE_RUN_CPU
MIN_NECK_WIDTH=10 milVOLTAGE=1.1VMAKE_BASE=TRUEMIN_LINE_WIDTH=25 mil
_PPVCORE_GPU_REG
_PPVCORE_CPU_REG
_PPBUSB_BBATT
_PPVIN_2V5_NBVCORE_PWRON_PPBUS_FW
_PPBUS_ALL_B
VOLTAGE=18.5VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
PPBUS_ALL_B
_PPSPD_DIMM
_PP2V5_ENET_PP2V5_PWRON_DIMM_PP2V5_PWRON_HT_PP2V5_PWRON_SB
_PP3V3_PWRON_3V3RUN
_PP3V3_PWRON_ALS1_PPVIN_1V5PWRON
_PP3V3_PWRON_BT_PP3V3_PWRON_USB_PPPCI32_PWRON_SB
_PP3V3_PWRON_SB_PPPCI64_PWRON_SB
_PP3V3_PWRON_MODEM_PP3V3_PWRON_AUDIO
PP3V3_PWRON_REG
MIN_LINE_WIDTH=25 milMAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=10 mil
_PP3V3_PWRON_REG
_PP2V5_PWRON_REG
USB_TPAD_PMAKE_BASE=TRUE
MAKE_BASE=TRUETP_USB2_PWREN3
_PPVREF_SMU
_PP3V3_ALL_HALLEFFECT
USB2_N<4>
USB2_P<4>
USB2_P<2>
USB2_P<3>
USB2_PWREN<2>
USB2_OC<2>
USB2_N<3>
USB2_OC<3>
_PP3V3_ALL_ACIN
_PP3V3_ALL_RTC_PP3V3_ALL_SMU
USB2_LT_NMAKE_BASE=TRUE
USB2_N<0>
USB2_P<0>
MAKE_BASE=TRUELTUSB_OVERCURRENTUSB2_OC<0>
MAKE_BASE=TRUEUSB2_RT_N
RTUSB_PWRENMAKE_BASE=TRUE
USB2_P<1>
USB2_N<2>
MAKE_BASE=TRUEUSB2_OC2_PU
USB_MODEM_NMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB_MODEM_P
USB2_PWREN<3>
USB_TPAD_NMAKE_BASE=TRUE
USB2_OC<4>MAKE_BASE=TRUE
TP_USB2_PWREN4USB2_PWREN<4>
MAKE_BASE=TRUETP_USB2_PWREN2MAKE_BASE=TRUE
USB_BT_P
PP3V3_RUNPP2V5_RUN
MIN_LINE_WIDTH=25 milMAKE_BASE=TRUEVOLTAGE=2.5VMIN_NECK_WIDTH=10 mil
PP2V5_GPU
_PP2V5_GPU
PP1V2_RUN_GPU
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milMAKE_BASE=TRUEVOLTAGE=1.2V
_PP2V5_RUN_FET
_PP1V8_RUN_LDO
_PP3V3_RUN_FET
_PP1V5_RUN_FET
MIN_NECK_WIDTH=10 mil
MAKE_BASE=TRUEMIN_LINE_WIDTH=25 milVOLTAGE=1.8V
PP1V8_RUN_LDO
_PP3V3_SATABR_PP3V3_PATA
_PP3V3_PCI
_PPVIO_PCI_USB2_PPVIO_PCI_CBUS
_PP3V3_CPUVCORE_PP3V3_SB_PCI
_PP2V5_PCI
_PP1V8_SATABR
PP1V5_AGP
PP2V5_RUN_CPU
MAKE_BASE=TRUEPP2V5_SMU_VREF
_PP5V_PWRON_REG
MAKE_BASE=TRUEMIN_LINE_WIDTH=25 milVOLTAGE=5V
PP5V_PWRON_REG
MIN_NECK_WIDTH=10 mil
_PP5V_PWRON_MODEM_PP5V_PWRON_AUDIO
_PP5V_PWRON_LTUSB
_PP5V_PWRON_SLEEPLED_PP5V_PWRON_RTUSB
_PP5V_PWRON_FAN_PP5V_PWRON_3V3ALL_PP5V_PWRON_TPAD
_PP5V_PWRON_GPUVCORE
_PP5V_PWRON_5VRUN_PP5V_CBUS
_PPVIN_1V2PWRON
_PP5V_CPUVCORE_VDD_PP5V_CPUTHERM
_PP3V3_CPUTHERM_PP3V3_CBUS
_PP5V_RUN_KBDLED_PP5V_UATA
PP5V_RUN_CPU_PPBU_RUN_FW
USB2_PWREN<1>
USB2_N<1>
RTUSB_OVERCURRENTMAKE_BASE=TRUE
USB2_RT_PMAKE_BASE=TRUE
PP3V3_GPUMAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
_PP3V3_GPU
VOLTAGE=3.3VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
PP3V3_AGP
_PP3V3_PWRON_THERM
_PP5V_RUN_FET_PP5V_PWRON_SERIAL
_PP5V_PATA
VOLTAGE=5VPP5V_RUN_HD
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
_PP5V_RUN_AUDIO
_PP1V2_PWRON_SB
LTUSB_PWRENMAKE_BASE=TRUE
_PPVCORE_GPUFB
_PPVIN_GPUVCORE_PPVIN_CPUVCORE
_PPBUS_INV
_PPBUS_ALL_A
_PPBUSA_BBATT
_PP1V5_RUN_FET
PP1V2_HTPP1V2_PULSAR
_PP1V2_RUN_FET
VOLTAGE=1.2VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
PP1V2_EI_CPU
VOLTAGE=1.2VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
PP1V2_EI_NB
PCI_CLK_P1MAKE_BASE=TRUE
PCI_CLK33M_SB_EXT
PCI_CLK33M_USB2MAKE_BASE=TRUE
_PCI_CLK33M_USB2
MAKE_BASE=TRUESATA_CLK25M
_SATA_CLK25M
CPU1_HTBEN_R
EI_CPU1_SYNC_R
EI_CPU1_CLK_P_R
EI_CPU1_CLK_N_R
TP_CPU1_HTBEN_RMAKE_BASE=TRUE
MAKE_BASE=TRUETP_EI_CPU1_SYNC_R
MAKE_BASE=TRUETP_EI_CPU1_CLK_N
MAKE_BASE=TRUETP_EI_CPU1_CLK_P
TP_RAM_CKE_R<3>
TP_RAM_CKE_R<2>
TP_RAM_CKE_R<7>
TP_RAM_CKE_R<6>
RAM_CKE_R<2>
RAM_CKE_R<3>
RAM_CKE_R<7>
RAM_CKE_R<6>
TP_RAM_CS_L_R<3>
TP_RAM_CS_L_R<2>
TP_RAM_CS_L_R<11>
TP_RAM_CS_L_R<10>
RAM_CS_L_R<2>
RAM_CS_L_R<3>
RAM_CS_L_R<11>
RAM_CS_L_R<10>
TP_RAM_MUXEN4
TP_RAM_MUXEN0RAM_MUXEN0
RAM_MUXEN4
49
48
48
32
48
43
47
47
48
41
31
56
45
47
29
36
46
46
45
40
40
25
30
45
23
18
46
40
42
28
33
33
45
45 41
23
39
39
6 6
59
59
17
22
11
39
29
32
17
23
21
59
59
59
59
59
16
59
59
59
59
59
9
45
37
29
59
59
39
40
17
9
43
27
26
45
24
26
24
9
9
25
25
49
25
6
47
25
5 49
5 37
11
6
9
9
11
41
15
9
22
37
37
5
5 5
6
6
17
10
10
13
13
13
42
42
58
58
55
6 42
17 42
17 42
6
20
9
21
50
44
43
13
24
11
50
50
50
50
22
22
22
13
13
13
13 10
17 37
27
6
38
31
17
11
12
8
6
35
55
35
44
21
10
19
9
17
59
21
18
21
60
61
10
11
17
13
17
6
6
6
6
59
59
6
59
7
13
13
17 6
6
17 6
17
17
6
6
60
60
59
17
59
59
17
6 5
40
6
11
9
10
5
51
52
23
48
49
31
45
49
51
36
29
32
10
60
61
17
19
17
15
11
17
38
10
49
9
31
32
32
49
19
52
16
12
6
6
17
17
37
36
15
10
16
52
6
61
23
17
37
38
31
42
8
17
5
22
24
9
18
18
25 25
48
51
25
25
25
25
33
33
33
33
33
33
33
33
33
33 Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Firewire A
Within 1" of connector
(SMU_BOOT_CE)
(SMU_BOOT_SCLK)
(SMU_BOOT_BUSY)
(USB_MODEM_N)
BT/USB Flex
PP3V3_PWRON x 1PP5V_PWRON x 1GND x 1
Backup Battery/USB Flex
(SYS_LID_OPEN)
GND x 5
Within 2" of connector
Wireless Within 1" of connector
(I2C_MODEM_SDA)
x4
x3
x2
MISC
ROM ControlWithin 2" of U7500
Within 2" of connector
INVERTER
1 x GND
(LTUSB_PWREN)
GND x 2 - one by each fan
(USB_BT_N)
Within 1" of connector
(I2C_BATT_SDA)
(I2C_BATT_SCL)
(I2C_DS1775_SCL)
(I2C_DS1775_SDA)
(RTUSB_PWREN)
(RTUSB_OVERCURRENT)
(USB2_RT_P)
(USB2_RT_N)
(USB2_LT_N)
GND x 3X 4
LVDS
x4
UATA (Optical)
Within 1" of connector
S-Video
Within 1" of connector
x4
x3
x 2
x 3
Battery Conn
x2
GND x 1
Firewire BWithin 1" of connector
one by each fan GND x 2
Modem Connector
FUNCTIONAL TEST POINTS
(USB_MODEM_P)
DVI/VGA
GND x 4
Within 1" of connector
GND x 5
GND x 1
Within 1 of connector
Fan Connectors
2 x GND
Sound Connector
PP5V_PWRON x 1
(LTUSB_OVERCURRENT)
Within 2" of connector
(USB_BT_P)
(USB2_LT_P)
Within 2" of connector
Within 3" of connector
TrackpadWithin 3" of connector
Within 1" of connector
x2
Within 1" of connectorDC-in Connectors
PATA (SATA Bridge)
Within 2" of connector
(I2C_MODEM_SCL)
Functional Testpoints
10303051-6532
6
FUNC_TEST=YESPP1V2_RUN_GPU
FUNC_TEST=YESCPU_VID<5>
FUNC_TEST=YESSYS_POWERUP_L
SMU_BOOT_RXDFUNC_TEST=YES
CPU_VID<4>FUNC_TEST=YES
FUNC_TEST=YESPP1V8_RUN
FUNC_TEST=YESPP2V5_PWRON
FUNC_TEST=YESPP3V3_ALL
PPVCORE_RUN_CPUFUNC_TEST=YES
FUNC_TEST=YESI2S1_SYNC
ROM_OE_LFUNC_TEST=YES
FUNC_TEST=YESFW_PORT1_TPA_N_FL
TV_GND1FUNC_TEST=YES
FUNC_TEST=YESTV_Y
FUNC_TEST=YESTV_COMP
FUNC_TEST=TRUE
PATA_DA<2>
FUNC_TEST=TRUE
PATA_HSTROBE
FUNC_TEST=YESI2C_SMU_E_SDA
PP5V_RUN
FUNC_TEST=TRUE
FUNC_TEST=YESAUDIO_LO_OPTICAL_PLUG_L
PPFW_PORT2_VPFUNC_TEST=YES
KBDLED_RETURNFUNC_TEST=YES
SYS_DOOR_AJARFUNC_TEST=YES
USB2_N<1>FUNC_TEST=YES
FW_PORT2_TPA_N_FLFUNC_TEST=YES
FUNC_TEST=YESI2S0_BITCLK_F
FUNC_TEST=YESI2S0_DEV_TO_SB_DTI_F
I2S2_RESET_L_FFUNC_TEST=YES
I2S0_RESET_L_FFUNC_TEST=YES
USB2_PWREN<0>FUNC_TEST=YES
USB2_PWREN<1>FUNC_TEST=YES
I2S2_SYNC_FFUNC_TEST=YES
I2S0_SB_TO_DEV_DTO_FFUNC_TEST=YES
FUNC_TEST=YESI2S0_SYNC_F
I2S0_MCLK_FFUNC_TEST=YES
GND_CHASSIS_IOFUNC_TEST=YES
PP5V_RUN_DDCFUNC_TEST=YES FUNC_TEST=TRUE
PATA_DD<9>
UATA_DD<11>
FUNC_TEST=TRUE
FUNC_TEST=YESVGA_B
FUNC_TEST=YES
PCI_SLOTA_IDSEL
PCI_PAR
FUNC_TEST=YES FUNC_TEST=TRUE
PATA_STOP
PP3V3_RUNFUNC_TEST=YES
FUNC_TEST=YESPCI_SLOTA_INT_L
JTAG_CPU_TRST_LFUNC_TEST=YES
FUNC_TEST=YESJTAG_CPU_TDO
ROM_ONBOARD_CS_LFUNC_TEST=YES
JTAG_NB_TDOFUNC_TEST=YES
FUNC_TEST=YESI2S1_MCLK
I2S1_SB_TO_DEV_DTOFUNC_TEST=YES
FUNC_TEST=YESSYS_POWER_BUTTON_L
FUNC_TEST=YESUSB2_N<0>
KBDLED_ANODEFUNC_TEST=YES
FUNC_TEST=TRUE
UATA_DSTROBE_R
UATA_DD<3>FUNC_TEST=TRUE
FUNC_TEST=YESPPFW_PORT1_VP
UATA_DD<2>
FUNC_TEST=TRUE
FUNC_TEST=TRUE
UATA_INTRQ_R
FUNC_TEST=YESFW_PORT2_TPB_N_FL
FUNC_TEST=YESI2C_SMU_B_SCL
FUNC_TEST=YESI2C_SMU_B_SDA
FUNC_TEST=YESSYS_OVERTEMP_L
FUNC_TEST=YESUSB2_N<4>
FUNC_TEST=YESSYS_POWER_BUTTON_L
PP3V3_PWRONFUNC_TEST=YES
PP5V_PWRONFUNC_TEST=YES
PP3V3_ALLFUNC_TEST=YES
FUNC_TEST=YESPP3V3_RUN
PATA_DD<15>
FUNC_TEST=TRUE
FUNC_TEST=TRUEPPLOGIC_PATA
PPBATT_ALL_FFUNC_TEST=YES
FUNC_TEST=YESI2C_SMU_E_SCL
BATT_DET_LFUNC_TEST=YES
GND_BATTFUNC_TEST=YES
FUNC_TEST=YESPP18V5_ALL_DCIN
FW_PORT1_TPB_P_FLFUNC_TEST=YES
FW_PORT1_TPB_N_FLFUNC_TEST=YES
FW_PORT1_AREFFUNC_TEST=YES
GND_FW_PORT1_VGFUNC_TEST=YES
FUNC_TEST=YESUSB2_P<2>
FUNC_TEST=YESUSB2_P<0>
ADAPTER_IDFUNC_TEST=YES
PPBUS_ALL_BFUNC_TEST=YES
FUNC_TEST=YESSYS_POWERUP
USB2_P<1>FUNC_TEST=YES
USB2_OC<1>FUNC_TEST=YES
PCI_AD<11>FUNC_TEST=TRUE
PCI_AD<10>FUNC_TEST=TRUE
FUNC_TEST=TRUEPCI_AD<9>
TMDS_DN<1>FUNC_TEST=TRUE
FUNC_TEST=TRUE
PATA_DSTROBE_R
FUNC_TEST=TRUEPATA_CS1_L
FUNC_TEST=TRUE
PATA_CS0_L
FUNC_TEST=TRUE
PATA_DA<1>
FUNC_TEST=TRUEPATA_DA<0>
FUNC_TEST=TRUE
PATA_DMACK_L
FUNC_TEST=TRUE
PATA_DMARQ_R
PATA_DD<14>
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PATA_DD<13>
FUNC_TEST=TRUE
PATA_DD<12>
FUNC_TEST=TRUEPATA_DD<11>
FUNC_TEST=TRUE
PATA_DD<10>
FUNC_TEST=TRUE
PATA_DD<8>
FUNC_TEST=TRUEPATA_DD<7>
FUNC_TEST=TRUE
PATA_DD<6>
FUNC_TEST=TRUE
PATA_DD<5>
FUNC_TEST=TRUE
PATA_DD<4>
FUNC_TEST=TRUE
PATA_DD<3>
FUNC_TEST=TRUE
PATA_DD<2>
FUNC_TEST=TRUEPATA_DD<0>
TV_CFUNC_TEST=YES
UATA_HSTROBEFUNC_TEST=TRUE
FUNC_TEST=TRUE
UATA_RESET_L
FUNC_TEST=TRUE
UATA_CS1_L
UATA_DA<1>
FUNC_TEST=TRUEUATA_DA<0>
FUNC_TEST=TRUE
UATA_DD<15>
FUNC_TEST=TRUEUATA_DD<14>
FUNC_TEST=TRUEUATA_DD<13>
FUNC_TEST=TRUE
FUNC_TEST=TRUE
UATA_DD<12>
UATA_DD<10>
FUNC_TEST=TRUEUATA_DD<9>
FUNC_TEST=TRUE
UATA_DD<5>
FUNC_TEST=TRUE
UATA_DD<6>
FUNC_TEST=TRUE
UATA_DD<7>FUNC_TEST=TRUE
UATA_DD<8>
FUNC_TEST=TRUE
FUNC_TEST=TRUE
UATA_DD<4>
UATA_DD<1>
FUNC_TEST=TRUE
PP3V3_LCDFUNC_TEST=YES
LVDS_DDC_CLKFUNC_TEST=YES
FUNC_TEST=YESCLKLVDS_UP
CLKLVDS_UNFUNC_TEST=YES
FUNC_TEST=YESLVDS_U2P
FUNC_TEST=YESLVDS_U2N
FUNC_TEST=YESLVDS_U1P
FUNC_TEST=YESLVDS_U1N
FUNC_TEST=YESLVDS_U0P
FUNC_TEST=YESLVDS_U0N
FUNC_TEST=YESCLKLVDS_LP
FUNC_TEST=YESCLKLVDS_LN
LVDS_L2PFUNC_TEST=YES
FUNC_TEST=YESLVDS_L2N
FUNC_TEST=YESLVDS_L1P
FUNC_TEST=YESLVDS_L1N
FUNC_TEST=YESLVDS_L0P
LVDS_L0NFUNC_TEST=YES
DVI_HPD_UFFUNC_TEST=YES
DVI_DDC_DATA_UFFUNC_TEST=YES
FUNC_TEST=YESDVI_DDC_CLK_UF
VGA_HSYNCFUNC_TEST=YES
FUNC_TEST=YESVGA_VSYNC
FUNC_TEST=YESVGA_R
TMDS_CONN_CLKPFUNC_TEST=YES
FUNC_TEST=YESTMDS_CONN_CLKN
TMDS_DN<2>FUNC_TEST=TRUE
FUNC_TEST=TRUETMDS_DP<1>
TMDS_DP<0>FUNC_TEST=TRUE
FUNC_TEST=YES
AIRPORT_CLKRUN_L_PD
TP_AIRPORT_RF_DISABLE
FUNC_TEST=YES
FUNC_TEST=YES
TP_AIRPORT_PME_L
FUNC_TEST=YES
PCI_CLK33M_AIRPORT
FUNC_TEST=YES
PCI_SLOTA_GNT_L
FUNC_TEST=YES
PCI_SLOTA_REQ_L
FUNC_TEST=TRUE
PCI_CBE_L<3>
PCI_CBE_L<2>FUNC_TEST=TRUE
PCI_CBE_L<1>
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PCI_CBE_L<0>
PCI_STOP_LFUNC_TEST=YES
FUNC_TEST=YESPCI_DEVSEL_L
FUNC_TEST=YESPCI_IRDY_L
FUNC_TEST=YESPCI_TRDY_L
PCI_FRAME_LFUNC_TEST=YES
FUNC_TEST=TRUEPCI_AD<31>
FUNC_TEST=TRUEPCI_AD<30>
FUNC_TEST=TRUEPCI_AD<29>
FUNC_TEST=TRUEPCI_AD<28>
FUNC_TEST=TRUEPCI_AD<27>
PCI_AD<26>FUNC_TEST=TRUE
FUNC_TEST=TRUEPCI_AD<25>
FUNC_TEST=TRUEPCI_AD<24>
FUNC_TEST=TRUEPCI_AD<23>
FUNC_TEST=TRUEPCI_AD<22>
FUNC_TEST=TRUEPCI_AD<21>
FUNC_TEST=TRUEPCI_AD<20>
FUNC_TEST=TRUEPCI_AD<19>
FUNC_TEST=TRUEPCI_AD<18>
FUNC_TEST=TRUEPCI_AD<17>
FUNC_TEST=TRUEPCI_AD<16>
FUNC_TEST=TRUEPCI_AD<15>
PCI_AD<14>FUNC_TEST=TRUE
FUNC_TEST=TRUEPCI_AD<13>
PCI_AD<12>FUNC_TEST=TRUE
FUNC_TEST=TRUEPCI_AD<8>
FUNC_TEST=TRUEPCI_AD<7>
PCI_AD<6>FUNC_TEST=TRUE
PCI_AD<5>FUNC_TEST=TRUE
PCI_AD<4>FUNC_TEST=TRUE
PCI_AD<3>FUNC_TEST=TRUE
FUNC_TEST=TRUEPCI_AD<1>
FUNC_TEST=TRUEPCI_AD<0>
FUNC_TEST=TRUE
PATA_RESET_L
TMDS_DP<2>FUNC_TEST=TRUE
FUNC_TEST=YESLVDS_DDC_DATA
FUNC_TEST=YESGND_CHASSIS_LVDS
FUNC_TEST=TRUE
PP5V_RUN_HD
FUNC_TEST=TRUE
PATA_INTRQ_R
FUNC_TEST=YESFW_PORT1_TPA_P_FL
FW_PORT2_TPA_P_FLFUNC_TEST=YES
UATA_DA<2>
FUNC_TEST=TRUE
GND_FW_PORT2_VGFUNC_TEST=YES
FAN_RPM0FUNC_TEST=YES
FAN_TACH0FUNC_TEST=YES
FAN_TACH1FUNC_TEST=YES
FUNC_TEST=YESPP5V_PWRON
UATA_CS0_L
FUNC_TEST=TRUE
UATA_STOP
FUNC_TEST=TRUE
UATA_DD<0>
FUNC_TEST=TRUE
FUNC_TEST=YESVGA_G
FUNC_TEST=YESPP5V_INVERTER
FUNC_TEST=YESBRIGHT_PWM
FAN_RPM1FUNC_TEST=YES
FUNC_TEST=YESROM_CS_L
ROM_WE_LFUNC_TEST=YES
JTAG_NB_TMSFUNC_TEST=YES
JTAG_NB_TDIFUNC_TEST=YES
JTAG_NB_TRST_LFUNC_TEST=YES
FUNC_TEST=YESJTAG_SB_TMS
JTAG_SB_TDIFUNC_TEST=YES
FUNC_TEST=YESJTAG_SB_TDO
JTAG_SB_TCKFUNC_TEST=YES
FUNC_TEST=YESJTAG_SB_TRST_L
FUNC_TEST=YESJTAG_VESTA_TMS
FUNC_TEST=YESJTAG_VESTA_TDI
JTAG_VESTA_TDOFUNC_TEST=YES
FUNC_TEST=YESJTAG_VESTA_TCK
FUNC_TEST=YESJTAG_VESTA_TRST_L
FUNC_TEST=YESJTAG_CPU_TMS
FUNC_TEST=YESJTAG_CPU_TDI
FUNC_TEST=YESJTAG_CPU_TCK
FUNC_TEST=YESSMU_RESET_L
FUNC_TEST=YESSYS_RESET_BUTTON_L
FUNC_TEST=YESPPBUS_ALL_B
FUNC_TEST=YESAUDIO_GPIO_11
AUDIO_EXT_MCLK_SELFUNC_TEST=YES
AUDIO_SPKR_MUTE_LFUNC_TEST=YES
AUDIO_LO_DET_LFUNC_TEST=YES
AUDIO_LI_DET_LFUNC_TEST=YES
FUNC_TEST=YESAUDIO_LI_OPTICAL_PLUG_L
SLEEPLED_ANODEFUNC_TEST=YES
GND_AUDIOFUNC_TEST=YES
FUNC_TEST=YESPP5V_PWRON_AUDIO
FUNC_TEST=YESPP3V3_PWRON_AUDIO
I2S1_RESET_LFUNC_TEST=YES
FUNC_TEST=YESI2S1_DEV_TO_SB_DTI
USB2_N<3>FUNC_TEST=YES
FUNC_TEST=YESUSB2_P<3>
UDASH_SDOWNFUNC_TEST=YES
I2C_SB_SCLFUNC_TEST=YES
I2C_SB_SDAFUNC_TEST=YES
TMDS_DN<0>FUNC_TEST=TRUE
USB2_P<4>FUNC_TEST=YES
ALS_GAIN_BOOSTFUNC_TEST=YES
FUNC_TEST=YESUSB2_OC<0>
FUNC_TEST=YESALS0_OUT
USB2_N<2>FUNC_TEST=YES
FUNC_TEST=TRUE
UATA_DMACK_L
I2S1_BITCLKFUNC_TEST=YES
SMU_BOOT_TXDFUNC_TEST=YES
FUNC_TEST=YESSMU_BOOT_CNVSS
FUNC_TEST=YESMODEM_RING2SYS_L
FUNC_TEST=YESPPBUS_ALL_A
PPBUS_ALL_AFUNC_TEST=YES
PCI_AD<2>FUNC_TEST=TRUE
TV_GND2FUNC_TEST=YES
FUNC_TEST=TRUE
PATA_DD<1>
FUNC_TEST=YESAUDIO_LO_MUTE_L
FUNC_TEST=TRUE
UATA_DMARQ_R
JTAG_NB_TCKFUNC_TEST=YES
I2S2_DEV_TO_SB_DTI_FFUNC_TEST=YES
I2S2_BITCLK_FFUNC_TEST=YES
FUNC_TEST=YESFW_PORT2_TPB_P_FL
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
42
25
42
49
49
49
62
62
62
62
62
62
62
62
62
49
49
49
49
49
49
49
49
62
62
62
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
17
23
17
48
48
48
49
49
49
49
49
49
49
49
49
48
48
48
48
48
48
48
48
49
49
49
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
60
47
48
28
60
60
16
17
16
47
47
47
62
62
62
62
48
48
48
48
48
48
48
48
48
47
47
47
47
47
47
47
47
48
48
48
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
62
47
47
28
28
28
19
60
60
62
19
60
47
14
16
31
23
46
52
52
18
61
19
59
59
59
17
52
52
47 52
6
47
28
27
47
23
23
13
59
19
52
52
18
18
15
59
13
25
11
6
52
18
11
59
59
6
59
59
46
46
46
42
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
62
62
42
42
42
47
47
47
47
47
47
47
47
47
47
47
46
46
46
46
46
46
46
46
47
47
47
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
52
42
42
52
15
15
15
11
52
52
52
15
46
46
23
23
23
23
27
27
27
16
16
6
61
61
61
61
61
61
61
23
23
59
59
60
23
23
42
59
17
59
17
59
52
23
16
16
60
6
6
46
52
61
5
13
13
13
13
5
6
5
16
45
58
42
42
42
51
51
13
23
58
17
5
58
61
61
61
61
5
5
61
61
61
61
5
42 51
50
42
47
45 51
5
23
27
18
46
22
16
16
6
5
17
52
50
58
50
52
58
13
13
13
5
6
17
6
6
5
51
52
7
13
7
7
7
58
58
58
58
5
5
17
5
14
5
5
45
45
45
41
52
51
51
51
51
51
52
51
51
51
51
51
51
51
51
51
51
51
51
51
42
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
42
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
42
42
42
42
42
42
42
42
41
41
41
47
47
47
5
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
51
41
39
5
5
52
58
58
50
58
13
13
13
6
50
50
50
42
42
42
13
45
45
22
22
22
18
18
23
18
18
12
12
12
12
12
18
18
18
13
13
5
23
23
23
23
23
23
19
61
61
61
16
16
5
5
23
18
18
41
5
13
5
13
5
50
16
13
13
23
5
5
45
42
51
23
52
22
61
61
58
Preliminary
www.vinafix.vn
G
D
S G
D
S
D1D2D3D4S3
S2
GATE
S1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Place L759 as close to J750 as possible
518S0117
Main Battery Connector
<R1a>
DC Power Input(DC-In jack and associated circuit are on separate baord)
Vref = 3.3V * (R2a / (R1a + R2a))
ACIN Detection
<R2b>
<R1b>
Power Connectors
DC Inrush Limiter
<R2a>
Vth = 13.4VVth = Vref / (R2b / (R1b + R2b))
(BATT_IN_PD)(GND_BATT)
(PPBATT_F)1K resistor to protect SMU pins
518S0064
2
1R705
402MF
1/16W5%
10K
2
1R708
MF1/16W1%102K
402
2
1R709
MF1/16W1%10K
402
2
1R7101/16W
402MF
1%102K
2
1R711
MF
1%57.6K
402
1/16W
2
1 C70050V
0.1uF10%
X7R603-1
NO STUFF
2
5
1
3
4U710LMC7211SM
CRITICAL
2
1R713470K5%1/16WMF402
21
R712
MF1/16W5%
402
1M
4
5
3
Q715SOT-3632N7002DW
1
2
6
Q7152N7002DWSOT-363
2
1R7191/16W
5%
MF
470K
4022
1R715
MF402
1/16W5%
10K2
1 C7100.01uF20%
402
16VCERM
2
1R720
402
5%330K1/16W
MF 2
1 C7200.22uF25V20%
CERM805
21
L751
SM
FERR-50-OHM
CRITICAL
21
L755FERR-EMI-100-OHM
SM
21
L756FERR-EMI-100-OHM
SM
21
R755
5%
1K
402
1/16WMF
2
1R754
402
470K5%1/16WMF
2
1R7065%
402MF
1/16W
10K
PP3V3_ALL
9
8
7
6
5
4
3
2
10
1
J750M-RT-SM
CRITICAL
87438-1033
21
L759
SM
FERR-EMI-100-OHM
21
L750FERR-50-OHM
SMCRITICAL
3
2
1
4
8
7
6
5
Q720SI4405DY
SO-8
CRITICAL
4
3
2
1
J70087438-0433
M-RT-SM
CRITICAL
7 103051-6532 03
I2C_BATT_SCL
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=0V
GND_BATT
MIN_NECK_WIDTH=10 mil
PPBATT_ALL_VSNSVOLTAGE=12.8VMIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=25 milVOLTAGE=12.8V
PPBATT_ALL
MIN_NECK_WIDTH=10 mil
BATT_DET_LI2C_BATT_SDA_FI2C_BATT_SCL_F
ACIN_DIVADAPTER_PD
SMU_BATT_DET_L
MIN_LINE_WIDTH=8 milACIN_ENABLE_L
MIN_NECK_WIDTH=8 mil
I2C_BATT_SDA
MIN_LINE_WIDTH=8 milACIN_ENABLE_L_DIV
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=25 milVOLTAGE=18.5V
PP18V5_ALL_INRUSH
MIN_NECK_WIDTH=10 mil
_PP3V3_ALL_ACIN
PP18V5_ALL_DCINVOLTAGE=18.5VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
ACIN_1V20_REF
MAKE_BASE=TRUESMU_ACIN
SMU_ACIN_L
MIN_LINE_WIDTH=25 milVOLTAGE=12.8VMIN_NECK_WIDTH=10 mil
PPBATT_ALL_F
13
11
12
18
6
8
8
6
13
18
8
5
6
8
8
6 Preliminary
www.vinafix.vn
S2
GATE
S1
S3 D4D3D2D1
S2
GATE
S1
S3D4D3D2D1
S D
G
SD
G
G
D
S
G
D
SG
D
S
G
D
S
CSSP
CSSN
ACIN
DCIN
SCLSDA
INT*
IMAXVMAX
CCS
CCI
CCV
CSIPCSIN
VDD LDOSRC
PDL
PDS
REF
DHIV
DHI
DLO
PGNDPADTHM
GND
DAC
ACOK*
THM
BATT
I.C.
DLOV
G
D4
D2
S3S2
D1
D3
S1
D1D2D3D4 S3
S2
GATE
S1
G
D
S DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DC-IN Input Current LimiterPlace U800 and U870 near R800
NC
SMBus Battery Charger
Battery Charge PathBattery charge FET is open when not charging
Keep short and route as pair
RC time is 480K * 10uF @ 3.3VNC
NC
NC
(PP18V5_ALL)
NC
SMBus Battery Charger
(PP18V5_ALL_SENSE)
FETs are quickly turned off (diode)When AC is connected, P-channel
When AC is disconnected, P-channel FETs turn on
Battery Switch-over Circuit
2
1 C826
603CERM10V
1UF20%
2
1R821169K
1%1/16W
MF402
2
1R8201/16W
100K1%
MF402
2
1R8014.7
5%1/16W
402MF
2
1R8025%1/16W
402MF
4.7
2
1C80150V
0.47UF
1206
20%
CERM
2
1
D810MBRS140T3
SM
21
R8000.010
MF
1%
CRITICAL
1/2W
1206
2
1 C8020.47UF
CERM50V20%
1206
2
1R896
402MF
1/16W5%
100K
3
2
1
4
8
7
6
5
Q890CRITICAL
SOISI4435DY
3
2
1
4
8
7
6
5
Q880CRITICAL
SI4435DYSOI
2
1R881
402MF
5%1/16W
330K
2
1R891100K
5%
402
1/16WMF
2
1R890470K
MF
5%
402
1/16W
3
1
4
Q895SUD45P03TO-252
CRITICAL
2
1R895470K
MF1/16W
5%
402
3
1
4
Q899SUD45P03
TO-252
CRITICAL
4
5
3
Q800SOT-3632N7002DW
2
1C897
CERM805
6.3V20%
10uF
2
1R8971/16W
402
1%158K
MF
43
DP800BAS16TW
SOT-363
2
1R898
402MF1/16W5%100K
2
1
F899SM-25AMP-125V
2
1
F8955AMP-125V
SM-2
2
1R8995%1/16W
402
470K
MF
2
1 C81220%25VCERM1206
4.7uF
2
1C8134.7uF
1206CERM25V20%
2
1C8154.7uF
1206CERM25V20%
2
1 C8144.7uF
1206CERM25V20%
2
1C8174.7uF
1206CERM25V20%
2
1 C8164.7uF
1206CERM25V20%
2
1 C818CRITICAL
20%25VELECSM1
33uF
2
1R812
603MF
5%1/16W
1
21
R810
1%
MF
0.010
CRITICAL
1/2W
1206
21
L810
SM1
10uH
CRITICAL
2
1R8111
1/16W5%
603MF
2
1R825
402
20.5K1%1/16WMF
2
1R824
MF
1%100K
402
1/16W
2
1 C8251uF
CERM
20%
603
10V
2
1 C823
402
16V
0.01uF
CERM
20%
2
1R805NO STUFF
100K1%
402MF
1/16W
2
1R806NO STUFF
13K1%
402MF
1/16W
3
1D800SOT231N914
2
1 C800
805CERM25V20%1uF
2
1R850
MF402
1/16W
49.9K1%
2
1R8511/16W
402
5%
MF
68K
2
1C851
CERM
20%0.1uF
25V
603
1
2
6
Q8002N7002DWSOT-363
2
1R8801/16W5%
MF402
470K
52
DP800SOT-363
BAS16TW
2
1C88216V10%
CERM402
0.01UF
2
1R882
MF
100K5%
402
1/16W
2
1C81110%50V
402CERM
0.001uF
NO STUFF
1
2
6
Q882SOT-3632N7002DW
4
5
3
Q882SOT-3632N7002DW
2
1 C80525V
1206
4.7uF20%
CERM 2
1 C80625V
1206
20%
CERM
4.7uF2
1 C807
1206
4.7uF20%25VCERM 2
1 C8084.7uF
1206CERM
20%25V
2
1 C8291UF
603CERM
20%10V
2
1C82420%16V
CERM402
0.01UF2
1C8270.1UF
CERM25V20%
603
2
1R8265%
1/16WMF402
332
1C830
402
10V
0.1UF
CERM
20%
2
1C8310.1UF
402
10V20%
CERM
9
12
33
13
27
1415
4
22
31
30
2
16
10
17
185
24
23
25
26
1
11
2928
2120
8
6
7
19
32
3 U800MAX1535A
CRITICAL
QFN
2
1R8285%1/16WMF
0
402
2
1 C8280.1UF20%
603CERM25V
2
1R8275%
1/16WMF
0
402
2
1R8921/16W
100K5%
402MF
21
R8230
1/16WMF
5%
402
2
1C8200.1UF
402CERM10V20%
321
4
8765
Q810
SOI
CRITICAL
SI4835BDY
2
1R829100K
5%1/16W
MF402
3
2
1
4
8
7
6
5
Q850CRITICAL
SI4405DYSO-8
2
1R830100K5%1/16WMF402
4
5
3
Q8772N7002DWSOT-363
321
4
8765
Q811SI4336DY
CRITICAL
SO-8
2
1R8225%
402MF
1/16W
30K
2
1C82216V
0.01uF20%
CERM402
21
XW800SM
03051-65321038
PP18V5_ALL_INRUSH
VOLTAGE=18.5VMIN_NECK_WIDTH=10 mil
PP18V5_ALL_SENSE
MIN_LINE_WIDTH=25 mil _PPBUS_ALL_B
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 milBKFD_PROT_EN_L_DIV
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=12.6V
PPBATT_ALL_FUSEA
CHGR_THM
_PPBUS_ALL_A
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 milCHGR_DLOV_RC
MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
PP5V4_CHGR_LDOVOLTAGE=5.4V
CHGR_DAC
CHGR_CSSPCHGR_CSSN
CHGR_VMAX
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 milVOLTAGE=0V
GND_CHGR
CHGR_CCS
CHGR_IMAX
_PPBUS_ALL_A _PPBUS_ALL_B
CHGR_ACIN_RC
PPBATT_ALL
CHGR_DCIN
MIN_NECK_WIDTH=10 mil
CHGR_DHIMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
CHGR_DHIVMIN_LINE_WIDTH=20 mil
CHGR_DLOV
PPBATT_ALL_VSNS
I2C_CHGR_SCLI2C_CHGR_SDA
MIN_NECK_WIDTH=10 mil
BATT_PBUSA_EN_LMIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
BATT_PBUSB_EN_L
CHGR_CHARGE_EN_L
SMU_ACIN_L
_PPBUS_ALL_A
MIN_NECK_WIDTH=10 mil
PPBATT_ALL_FUSEBVOLTAGE=12.6VMIN_LINE_WIDTH=25 mil
CHGR_PBUS_EN_L
MIN_LINE_WIDTH=10 milCHGR_PBUS_EN_L_DIV
MIN_NECK_WIDTH=10 mil
SMU_ACIN
CHGR_CCV
PPBATT_CHGR_RSNSMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
CHGR_CCS_RCCHGR_CCI_RC
CHGR_CCV_RC
CHGR_CHARGE_EN_L_DIV
PPBATT_CHGR_OUT
BATT_ACIN_L_RC
BATT_PBUS_EN_L
SMU_ACIN
CHGR_CCI
SMU_CHARGE_BATT
CHGR_ACIN
CHGR_REF
SMU_CHARGE_BATT
CHGR_CSIP
SMU_CHARGE_BATT_L
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
BKFD_PROT_EN_L
CHGR_CSIN
MIN_LINE_WIDTH=25 mil
PPBATT_CHGR_OUTVOLTAGE=12.6VMIN_NECK_WIDTH=10 mil
CHGR_REF
MIN_LINE_WIDTH=25 milCHGR_DLO
MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
PPBATT_CHGR_SWMIN_LINE_WIDTH=25 mil
42
42
42
13
13
17
17
17 17
17
12
12
8
8
8 8
8
8
8
13
13
7
5
11
5
5 5
7
7
18
18
7
5
7
8
7
8
8
8
8
8
Preliminary
www.vinafix.vn
SW
SGND PGND PADTHERM
SVIN PVIN
PGOOD
VFB
ITHSYNC/MODE
RUN/SSRT
GNDSET
SHDN*
OUT1
FAULT*
OUT2
CC
IN
VIN
LBO
PG
SW
FB
SYNC
GND
PGND
LBI
EN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.8V/1.5V/1.2V MAIN SUPPLIES
1.8V/1.5V Supplies
NC
for fix voltage part
Burst
Continuous
powers up with PP5V_PWRON
SET internally disconnected
300mA output
LB - low battery - NOT USED
2
1 C981
CERM50V
0.0022uF10%
402
4
36
5
2
1
Q980SI3446DV
TSOP
CRITICAL
2
1C980
CERM805
6.3V20%
10UF
2
1 C95620%22uF6.3VCERM1206
2
1C95522uF
20%6.3VCERM1206
2
1 C952
CERM6.3V
1206
20%22uF
2
1C951
CERM6.3V20%
1206
22uF
2
1R9581/16WMF402
5%100K
2
1 C95022pF
402
5%
CERM50V
2
1R950470K
1%1/16W
MF402
21
L9501.0uH-3.5A
SM
CRITICAL
21
XW950SM
4
17
6
15
1411
10
1
8
7
516
9
2
13
12
3
U950
CRITICAL
LTC3412TSSOP
2
1R954309K1%1/16WMF402
2
1R951
402
1%1/16W
MF
511K
2
1R9521%
1/16WMF402
422K
2
1R955NO STUFF
5%1/16W
0
402MF
2
1R9565%1/16WMF402
0
2
1C95710%50V
CERM402
470pF
2
1R953
402
1/16WMF
15K1%
2
1 C954
402
50V5%
CERM
100pF
2
1C95310%50V
CERM402
0.001uF
2
1R9575%
MF402
1/16W
5.1M
2
1 C961
402
50VCERM
10%0.0022uF
4
36
5
2
1
Q960TSOP
SI3446DV
CRITICAL
2
1C960
805
6.3VCERM
20%10UF
7
5
4
12
3
8
6
U940LP3982
MSOP
21
R940
MF603
0
1/16W5%
NO STUFF
21
R941
1/16W
0
5%
603MF
2
1 C9402.2uF20%6.3VCERM1603
2
1 C941
402
10VX7R
20%0.033uF
2
1 C94210UF20%6.3VCERM805
21
L97010uH
CRITICAL
CDRH4D28C-SM
2
1R9701%
100K1/16W
MF402
2
1R97149.9K
402MF
1/16W1%
2
1 C97050VCERM
6.8pF0.5pF%
402
2
1 C97222uF6.3VCERM
20%
1206
2
1C971
CERM
10UF20%
6.3V
805
1
7
9
10
4
2
6
3
5
8
U970TPS62050
MSOP
CRITICAL
1039051-6532 03
_PP1V5_PWRON_REG_PPVIN_1V5PWRONMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
1V5PWRON_SW
1V2PWRON_VFB_DIV
_PP1V8_RUN_LDO
1V8RUN_SHDN_L
MIN_NECK_WIDTH=8 mil
1V8RUN_CCMIN_LINE_WIDTH=8 mil
1V8RUN_PGOOD
1V2PWRON_RUNSS
1V2PWRON_SGNDVOLTAGE=0VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
_PP3V3_PWRON_1V8RUN
1V2PWRON_RT
1V2PWRON_ITH1V2PWRON_MODE
_PP1V5_PWRON_1V5RUN
1V5RUN_EN
_PP1V5_RUN_FET
1V2PWRON_ITH_RC
1V2PWRON_VFB
1V2PWRON_PGOOD
_PP1V2_PWRON_1V2RUN
1V2RUN_EN
_PP1V2_RUN_FET
_PP1V2_PWRON_REG
1V2PWRON_SWMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
_PP2V5_PWRON_1V8RUNPPVIN_1V8RUN
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 mil
_PPVIN_1V2PWRON
1V5PWRON_VFB_DIV
5 5
5
14 14
5
5
14
5
5
14
5
5
5
5
Preliminary
www.vinafix.vn
GND
FLT
POWERGOOD CT
REF
REG5V_IN
STBY2 STBY1
TRIP1TRIP2
LH2 LH1
OUT1_UOUT2_U
LL1LL2
OUT2_D OUT1_D
OUTGND1OUTGND2
FB2 FB1
INV1INV2
SOFTSTART1SOFTSTART2
PWM/SKIP
VCCVREF55V_STBY
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DIODE WILL ENSURE DCDC_EN_L IS QUICKLY DISCHARGED DURING SHUT-DOWN
(GND)
5V START TO TURN ON ~12.5MS AFTER DCDC_EN_L
3V START TO TURN ON ~25MS AFTER DCDC_EN_L
(PP5V_PWRON)
is 10% necessary?
another 0.1uF needed?
POWERDOWN DELAY IS AROUND 4MS-15.6MS
3.3V/5V REGULATOR
(GND)
>2V = SKIP
3.3V/5V MAIN SUPPLY
<0.5V = PWM
4
3 6
5
2
1
Q1007
CRITICAL
TSOPSI3443DV
21
C1009
402
10%
0.0022uF
50VCERM
22 24
23 25
10 9
13 3
21
84
12
20 26
17
19
29
27
18 28
16 30
15 1
7
11
14 2
5
6
U1000
CRITICAL
TSOP
TPS5120
2
1C10500.1uF
CERM
20%25V
603
2 1
R1050
402MF
1/16W5%
10
2
1C105110V20%
4.7UF
CERM12063
1D1030SOT2330V-200MA
3
1D103530V-200MA
SOT23
2
1
D1031SM
MBR0540
2
1
D1036MBR0540SM
21
R10313.3
5%
MF402
1/16W
2
1 C103120%0.1uF10VCERM402
21
R1035
5%1/16WMF402
3.3
2
1C1035
402
20%
CERM10V
0.1uF
2
1C1052
CERM
0.01uF
402
20%16V
2
1R10531/16W
402MF
1%15K
2
1 C105316V
0.01uF20%
CERM402
2
1 C1065
CERM1206
25V20%4.7uF
2
1 C1066
1206CERM25V20%4.7uF
2
1 C1067
1206CERM25V20%4.7uF
2
1C10624.7uF
CERM
20%25V
12062
1C10614.7uF
20%25V
CERM1206
2
1C1060
1206CERM25V20%
4.7uF
2
1 C1063
CERM402
50V
0.001uF10%
NO STUFF
2
1C106850V
402CERM
10%0.001uF
NO STUFF
21
L1060CRITICAL
4.7UH
IHLP-5050
2
1 C107722uF6.3VCERM1206
20%
2
1C1076
1206
6.3V20%
CERM
22uF
2
1 C10756.3V20%330uF
POLYCASE-D
CRITICAL
2
1C105410%25V
CERM402
0.0047uF2
1R107320.5K
402MF
1/16W1%
21
L1065
SM1
10uH
CRITICAL
2
1R108110K
1%
402MF
1/16W
2
1C1081
CERM50V
0.001uF
402
10%2
1 C108720%6.3V
330uF
POLYCASE-D
CRITICAL
2 1
XW1003SM
2
1C1086
CERM
20%22uF
6.3V
1206
2
1 C1085
1206CERM
20%22uF6.3V
2
1R108334.8K1%
402MF1/16W
2
1R1080100K1%
MF402
1/16W
2
1 C105810%25VCERM402
0.0047uF2
1C1057
402
10V20%
0.1uF
CERM2
1 C10565%47pF
402CERM50V2
1C10550.1uF
CERM402
10V20%
2
1 C1059
CERM25V5%
402
220pF
2
1
D1060SM
MBRS140T3
1
2R1036
MF
05%1/16W
402
12
C1080
5%
100pF
402CERM50V
12
R1082
5%1/16WMF
10K
402
12
C1082
10%16VCERM
0.01uF
402
21
R1033
5%1/16W
402MF
100K
3
2
4
1
7
6
5
8
Q1065CRITICAL
SI4816DYSOI
2
1R10320
MF
5%
402
1/16W
2
1C107150V10%
402
0.001uF
CERM
2
1R107117.4K
MF402
1%1/16W
2
1R1070
MF
1%
402
1/16W
100K
21
C107047pF
CERM50V
402
5%
21
C1072
CERM
0.01uF
16V10%
402
21
R1072
402
5%
MF
10K
1/16W
2
1 C1074100uF6.3V20%
TANTCASE-B2
CRITICALNO STUFF
2
1 C1013CRITICAL
CASE-B2
6.3VTANT
100uF20%
2
1C1012
CERM
20%6.3V
805
10UF
2
1C100320%
402
16VCERM
0.01uF
2
1 C1001CRITICAL
CASE-B-3528POLY
20%100uF6.3V
2
1 C1004CRITICAL
CASE-B-3528POLY6.3V20%100uF
4
3 6
5
2
1
Q1003
CRITICAL
TSOPSI3443DV2
1C1011
CERM
20%6.3V
805
10uF
2
1C10050.1uF
10V
402CERM
20%4
3 6
5
2
1
Q1004
CRITICAL
SI3443DVTSOP
2
1C1006
CERM
20%6.3V
805
10UF
3 2 1
4
8 7 6 5
Q1060SO-8
CRITICAL
IRF7821
3 2 1
4
8 7 6 5
Q1061SO-8
CRITICAL
SI4336DY
2
1R105211K
MF402
1/16W1%
03051-653210310
_PP5V_PWRON_REG
5VPWRON_INV
5V3VPWRON_CT
3V3PWRON_SS
MIN_LINE_WIDTH=15 mil
GND_5V3VVOLTAGE=0VMIN_NECK_WIDTH=10 mil
5V3VPWRON_PGOOD
3V3RUN_EN_L
_PP3V3_PWRON_3V3RUN
_PP3V3_RUN_FET
5VRUN_EN_L
_PP5V_PWRON_5VRUN
5VRUNHD_EN_L
_PP5V_RUN_FET
_PP5V_RUN_HD_FET
5VPWRON_FB
VOLTAGE=5VPP5V_5V3V_VREF5
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 mil
PPVCC_ALL_3V5VVOLTAGE=18.5V
5VPWRON_TRIP
3V3PWRON_LH
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
3V3PWRON_TRIP
5VPWRON_SS
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
5VPWRON_OUT_U
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
3V3PWRON_OUT_D
SYS_SLEEP
3V3PWRON_LL
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
5VPWRON_FB_RC
3V3PWRON_FB_RC
3V3PWRON_INV_RC
5VPWRON_LH
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
5V3VPWRON_SKIP
5V3VPWRON_FLT
5VPWRON_LL
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
5VPWRON_BOOST_ESR
_PP3V3_PWRON_REG
3V3PWRON_FB
3V3PWRON_INV
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
3V3PWRON_SW
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
3V3PWRON_OUT_U
5V3VPWRON_REF
5VPWRON_INV_RC
MIN_LINE_WIDTH=20 mil3V3PWRON_BOOST_ESR
MIN_NECK_WIDTH=10 mil
_PPVIN_5V3VPWRON
3V3_STBY_L5V_STBY_L
MIN_NECK_WIDTH=10 mil
5VPWRON_OUT_DMIN_LINE_WIDTH=25 mil
5VPWRON_SWMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
25 11
5
14
14
5
5
14
5
14
5
5
5
5
5
14 14
Preliminary
www.vinafix.vn
GND
FLT
POWERGOOD CT
REF
REG5V_IN
STBY2 STBY1
TRIP1TRIP2
LH2 LH1
OUT1_UOUT2_U
LL1LL2
OUT2_D OUT1_D
OUTGND1OUTGND2
FB2 FB1
INV1INV2
SOFTSTART1SOFTSTART2
PWM/SKIP
VCCVREF55V_STBY
VTAP
IN OUTSENSE
GNDFDBKERR
LP2951
SHUTSHUT
PLUS5VTAP
LP2951
ERRFDBK
GND
SENSEOUTIN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.328V
Bootstrap system from adapter or battery
PP3V3_ALL LDO
PP4V6_ALL Generation
NC
NCNC NC
> 2V = SKIP
(GND)(GND)
< 0.5V = PWM
2.5V/NBVCORE/PMU SUPPLIES
2.5V/NBVCORE MAIN SUPPLIES
2
1 C1117
1206CERM25V20%4.7uF
2
1 C11164.7uF20%25VCERM1206
2
1 C111520%25VCERM1206
4.7uF
2
1 C114820%6.3VPOLYCASE-D
330uF
CRITICAL
2
1C1125330uF
POLYCASE-D
20%6.3V
CRITICAL
2
1 C1126
1206
6.3V
22uF20%
CERM
2
1C1127
CERM
20%22uF6.3V
1206
2
1C11410.001uF
50V
402CERM
10%
2
1R114117.4K
1%
402MF
1/16W
2 1
XW1104SM
21
L1110CRITICAL
4.7UH
IHLP-5050
2
1R1140100K
402MF
1/16W1%
2
1R114351.1K
MF402
1%1/16W
2
1R114210K
402MF
1/16W1%
2
1C114216V
0.01uF
402
10%
CERM
2
1C114047pF
CERM402
50V5%
3
1D113530V-200MASOT23
2
1 C110316V
0.01uF
CERM
20%
402
21
R1136
402
0
5%
MF1/16W
2
1R1103
402MF
1%1/16W
11K
2
1 C11000.1uF20%25VCERM603
2 1
R1100
402
1/16WMF
5%
10
2
1C110120%
4.7UF
1206
10VCERM
2
1R1102
402
1/16WMF
1%20K
2
1C11020.01uF
16V
402CERM
20%
21
R1132
1/16W
402MF
5%
02
1D1130MBR0540
SM
2
1C11124.7uF
1206CERM25V20%
2
1C11180.001uF
10%50V
CERM402
NO STUFF
2
1 C11350.1uF10V
402CERM
20%
21
R11351.8
1/16W5%
MF402
2
1 C11080.0047uF10%25VCERM402
2
1 C11070.1uF20%10VCERM402
2
1 C1106
402-1
68pF5%50VCERM
2
1
D1136MBR0540SM
2
1C11050.1uF
20%10V
402CERM
22 24
23 25
10 9
13 3
21
84
12
20 26
17
19
29
27
18 28
16 30
15 1
7
11
14 2
5
6
U1100
TSOP
TPS5120
CRITICAL
2
1
D1131SM
MBR0540
2
1C1104
402CERM25V10%
0.0047uF
2
1C1131
402
0.1uF20%10V
CERM
21
R11311.8
1/16WMF
5%
402
2
1 C11130.001uF10%50VCERM402
NO STUFF
3 2 1
4
5
Q1115SO-8-PWRPK
SI7392DP
CRITICAL
2
1 C1120
402
150pF5%50VCERM
2
1R11225.36K
402MF1/16W1%
2
1 C11220.01uF10%16VCERM402
2
1C1111
CERM1206
4.7uF25V20%
2
1C111025V
CERM1206
20%4.7uF
21
L1115
IHLP
CRITICAL
2.2uH-16A
2
1R112051.1K1%
402MF1/16W
2
1R1121
402MF
1%1/16W
17.4K
2
1 C1121
402CERM50V10%680pF
2
1C1145
1206
6.3V20%
CERM
22uF
2
1R11231%
402MF
1/16W
90.9K
2
1 C1146
1206
6.3V
22uF
CERM
20%
2
1C1147
CASE-DPOLY
330uF6.3V20%
CRITICAL
2
1 C1109
402CERM25V
220pF5%
2
1
D1110SMMBRS140T3
2
1
D1115B340LB
SMB
21
R1133
402MF
1/16W
100K
5%
7
6
3
2
4
8
5
1
Q1190SI6467BDQ
TSSOP
CRITICAL
2
1C119010UF
20%
CERM6.3V
805
21
C11920.0022uF
402
10%50VCERM
2
1R1171
MF
5%1/16W
603
1
6
3
2
18
4
7
5
U1170
CRITICAL
SOI-3.3V
2
1 C1171
805CERM
20%10uF6.3V
21
D1164SM
MBR0520LT
NO STUFF
21
D1163NO STUFF
SM
MBR0520LT
2
1 C11700.1uF
402CERM10V20%
2
1R11641
603MF1/16W5%
2
1R1162
402MF1/16W1%294K
2
1C1162
402CERM50V10%
470pF
2
1 C1164
805CERM10V20%2.2uF
2
1R1163
402MF1/16W1%100K
2
1C1161
402CERM10V20%
0.1uF
3
2
6
18
4
7
5
U1160
CRITICAL
SOI
2
1 C1160
603
25V
0.1uF20%
CERM
21
R1166
1210
137
1%1/4WFF
2
1D1162SM
MBR05403
1D11611N914
SOT23
21
D1160SM
MBR0540
3 1
D1165SOT231N5228B
21
R11610
5%1/10WFF805
321
4
8765
Q1110SO-8
CRITICAL
IRF7821
2
1 C1193100uF20%6.3VPOLYCASE-B-3528
321
4
8765
Q1111SO-8
CRITICAL
SI4336DY
3 2 1
4
8 7 6 5
Q1116SO-8
CRITICAL
SI4336DY
1031103051-6532
2V5_ITRIP
2V5PWRON_SW
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil2V5_LO_GATENBVCORE_LO_GATE
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
SYS_SLEEP 2V5_NBVCORE_PWM
MIN_LINE_WIDTH=25 milNBVCORE_HI_GATE
MIN_NECK_WIDTH=10 mil
_PPVIN_2V5_NBVCORE_PWRON
MIN_NECK_WIDTH=10 mil
2V5_NBVCORE_VCC
MIN_LINE_WIDTH=10 milVOLTAGE=18.5V
2V5NBVCORE_STBY_L
2V5_NBVCORE_FLT
2V5_NBVCORE_CT
2V5_NBVCORE_REF
2V5_SS
2V5_INV
2V5_FB
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil2V5_BST_HI
NBVCORE_ITRIP
MIN_LINE_WIDTH=25 milNBVCORE_BST_HI
MIN_NECK_WIDTH=10 mil
2V5_NBVCORE_VREF5
MIN_NECK_WIDTH=10 milVOLTAGE=5VMIN_LINE_WIDTH=20 mil
VOLTAGE=18.5VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
PP18V5_ALL_4V85ALL
PPBATT_ALL_FUSEA_ZENERVOLTAGE=16.3VMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 milVOLTAGE=18.5VMIN_LINE_WIDTH=10 mil
PP18V5_ALL_DCIN_R
MIN_LINE_WIDTH=15 mil4V85ALL_ESR
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
2V5_BST_LO
NBVCORE_BOOST_ESRMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
2V5_FB_RC
2V5_INV_RC
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 mil3V3ALL_ESR4V85ALL_FB
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=8 mil
MIN_LINE_WIDTH=8 milMIN_NECK_WIDTH=8 mil
3V3ALL_FB
PP4V85_ALL_LDO
MIN_LINE_WIDTH=15 milVOLTAGE=4.85VMIN_NECK_WIDTH=10 mil
PP18V5_ALL_DCIN
_PP5V_PWRON_3V3ALL
PP4V6_ALLVOLTAGE=4.6VMIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 mil
_PP3V3_ALL_LDO
PPBBATT_BOOST_OUT
PPBATT_ALL_FUSEA
_PP2V5_PWRON_REG
MIN_LINE_WIDTH=20 mil2V5_BOOST_ESRMIN_NECK_WIDTH=10 mil
2V5RUN_EN_L
_PP2V5_RUN_FET
_PP2V5_PWRON_2V5RUN
NBVCORE_BST_LOMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
2V5_HI_GATE
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
NBVCORE_FB_RC
NBVCORE_SS
NBVCORE_FB
PP5V_PWRON
2V5_NBVCORE_PGOOD
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 milVOLTAGE=0VGND_2V5_NBVCORE
MIN_LINE_WIDTH=25 milNBVCORE_SW
MIN_NECK_WIDTH=10 mil
_PPVCORE_NB_REG
NBVCORE_INV_RCNBVCORE_INV2
25 10
7
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5
5
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5
Preliminary
www.vinafix.vn
S
D
G
VESTA MISC
1 OF 3
PVDDDVDD AVDDL AVDD
GNDAGNDOVDD
REGSUP1REGSEN1REGCTL1
REGSUP2REGSEN2REGCTL2
2.5V_EN
NC
DNCDNCDNC
NC
TDOTCKTMSTRST*
TDI
RESET*
PVINSVIN
SHDN/RT
SYNC/MODE
SW
VFB
ITHPGOODPGND SGND
G
D
S
G
D
S
GND
VOUTVIN
NOISECONT
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ON/OFFGNDVOUT
FBVIN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DRAWING
N9/N10
Ethernet LowPwr
Signal aliases required by this page:
(Repeater mode on portables)whenever port power is disabled.
Pulse Mode
Vout = 2.5V @ 150 mA
Port Power Switch regulator will be in continuous mode.
3.3V Regulator
- VESTA1V2_BURST / VESTA1V2_PULSE
regulator. If both options are off the
Vout = 0.8V * (1 + (R2 / R1))
Controls operating mode of Vesta 1.2V
1.2V Regulator
<R1>
<R2> Vout = 1.199V @ 1.2 A
Page NotesPower aliases required by this page:
machine is running orwhen asleep on AC.
Ethernet portion in low power mode
- _PP12V_RUN_FW (backup PHY power)
2.5V LDO
NCNC
N5/N6
Schmitt trigger
L6/M6
Reset RC values per
To keep Vesta from being held
Broadcom recommendation
NOTE: Reset GPIO is active HIGHin reset when system is off
(NONE)
ContinuousMode
Vout = 3.3V @ 500mA
L9/M9
Burst Mode
- _PPBUS_FW (system supply for bus power)
BOM options provided by this page:
Vesta Core / Misc
Master: Link
Enables port power when
2
1 C121020%10VCERM402
0.1uF2
1 C12110.1uF
402CERM10V20%
2
1 C1212
402CERM10V20%0.1uF
2
1 C121320%10VCERM402
0.1uF
2
1 C12030.1uF
CERM402
10V20%
2
1 C12020.1uF
402CERM10V20%
2
1 C12010.1uF
402CERM
20%10V2
1 C120020%10VCERM402
0.1uF
2
1C122220%10V
CERM402
0.1uF2
1C122510V20%
CERM402
0.1uF2
1C122120%10V
CERM402
0.1uF2
1C12240.1uF
20%10V
CERM402
2
1C12310.1uF
402CERM10V20%
2
1C123020%10V
CERM402
0.1uF
2
1C122020%10V
CERM402
0.1uF2
1C12230.1uF
20%10V
CERM402
2
1C12430.1uF
402CERM10V20%
2
1C124220%10V
CERM402
0.1uF2
1C124110V
0.1uF
402CERM
20%2
1C12400.1uF
402CERM10V20%
2
1 C1250
CERM10V
1uF20%
6032
1
3
Q12502N7002SM
2
1R12505%
1/16WMF402
10K
D8
E8
E10
D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1
F15A7
A1
M13
C3
K2
J2
F14
C14
B7B2
A2
J1
C15
B15
B1
E9
C9B9
N10
N9N6
N5
M9M6
L9
L6
R12
R3
P11
P10
P5
P4
N8
N7M8
M7
L8L7
J12
J11
P9
P8
P7P6
H12
H11
M3U8600OMIT
BCM5462FBGA-2002
1R125182K
5%1/16W
MF402
2
1 C120820%
CERM
10uF6.3V
805
21
L1200FERR-EMI-600-OHM
SM
92
4
7
1
3
6
8
5
10
U1290LTC3411
MSOP
CRITICAL
2
1 C1293100pF
402CERM50V5%
2
1R1296
402MF
1/16W
4.99K1%
2
1C1294
402
0.0033uF10%50V
CERM
21
L12902.2uH
SM1
CRITICAL
2
1C12925%
22pF
402
50VCERM
2
1R12971%
MF
4.99K1/16W
402
2
1R12981%1/16WMF402
10K
2
1 C1295
CERM
22uF20%
1206
6.3V
2
1C1291
CERM
1uF10V
603
20%
21
R129010
1/16W5%
MF402
2
1 C12906.3VCERM
20%10uF
805
2
1R12951/16WMF402
324K1%
2
1R12945%1M
402MF
1/16W
2
1R12911/16W5%1M
402MF
2
1R1293VESTA1V2_PULSE
10K1/16W
5%
402MF
2
1R1292VESTA1V2_BURST
5%10K
402MF
1/16W
21
XW1290SM
2
1C128120%
0.01uF
402CERM16V2
1C12801uF
603
10V20%
CERM 2
1 C128220%10uF
805CERM6.3V
2
1R1266
402
1/16WMF
330K5%
2
1 C1265
402CERM16V20%0.01uF
2
1R12655%
MF402
1/16W
470K
43
DP1260SOT-363
BAS16TW
5 2
DP1260SOT-363
BAS16TW
61
DP1260BAS16TWSOT-363
21
R1261
402MF
1/16W5%
10K
PP3V3_RUN
2
1R1260100K
402
5%1/16W
MF
4
5
3
Q1260SOT-3632N7002DW
1
2
6
Q12602N7002DWSOT-363
2
1R12625%
MF402
1/16W
100K
2
1R1263
402MF
5%1/16W
470K
51
4
2
3
U1280CRITICAL
SOT-25AMM1572FN
21
D1265
B340B
CRITICAL
SMB
3
2
1
4
8
7
6
5
Q1265NDS9407
SOI
CRITICAL
21
F12651.5A-24V
SM
3
2
1
D1270SC-59
SDM20E40C
8
7
56
4
U1270LM2594
SM
CRITICAL
2
1C127010uF
50V
2320
N20P20%
CERM2
1 C1271CRITICAL
CASE-B-3528POLY
20%100uF6.3V
21
L1270CRITICAL
PLFC
100uH-1A
2
1
D1271MBRS140T3SM
1031203051-6532
TITLE=FIZZYABBREV=DRAWING
MIN_LINE_WIDTH=20 mil
PP3V3_VESTAVOLTAGE=3.3VMIN_NECK_WIDTH=10 mil
FWPWR_RUN
VESTA_RESET_L
PP3V3_VESTA
PP2V5_VESTA
_PPBUS_FW
FWPWR_EN_LMIN_LINE_WIDTH=8 milMIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 milVOLTAGE=33V
PPVIN_FWLM2594
VESTA1V2_ITH_RC
_PPFW_PHY
_PP1V2_ENETFW
_PP3V3_FW
MIN_LINE_WIDTH=20 mil
PPVOUT_VESTA1V2VOLTAGE=3.3VMIN_NECK_WIDTH=10 mil
ENETFW_RESETTP_VESTA_REGSEN2TP_VESTA_REGSUP2
TP_VESTA_REGSEN1TP_VESTA_REGSUP1
TP_VESTA_REGCTL1
TP_VESTA_2_5V_EN
TP_VESTA_DNC_B9
TP_VESTA_DNC_E9
PP1V2_VESTA
JTAG_VESTA_TRST_L
PP3V3_VESTA
_PP2V5_ENETFW_PPBU_RUN_FW
PPFW_COMBINED
SMU_ACIN
_PPFW_PORT1
VESTA1V2_SWMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
_PP3V3_ENET
FWPWR_ACIN
PP3V3_VESTA
MIN_NECK_WIDTH=10 milVOLTAGE=0VVESTA1V2_SGND
MIN_LINE_WIDTH=15 mil
_PP3V3_ENETFW
VESTA1V2_ITH
VESTA1V2_VFB
MIN_LINE_WIDTH=20 milFWLM2594_VOUT
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.2VPP1V2_VESTA
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
_PPFW_PORT2
MIN_LINE_WIDTH=25 mil
PPFW_COMBINEDVOLTAGE=33VMIN_NECK_WIDTH=10 mil
PP3V3_VESTA
VESTA_ENET_LOWPWR
FWPWR_EN_L_DIVMIN_LINE_WIDTH=8 milMIN_NECK_WIDTH=8 mil
PP3V3_VESTA
VOLTAGE=2.5VPP2V5_VESTA
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 mil
VESTA2V5_NOISE
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=8 mil
FWPWR_PWRON
VESTA1V2_MODE
VESTA1V2_RT
PP1V2_VESTA_AVDDL
MIN_LINE_WIDTH=20 milVOLTAGE=1.2VMIN_NECK_WIDTH=10 mil
TP_VESTA_DNC_C9
JTAG_VESTA_TMSJTAG_VESTA_TCKJTAG_VESTA_TDO
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=19VPPBUS_FW_FUSE
FWPWR_EN
PPFW_SWITCH
MIN_NECK_WIDTH=10 milVOLTAGE=19VMIN_LINE_WIDTH=25 mil
TP_VESTA_REGCTL2
JTAG_VESTA_TDI
LAST_MODIFIED=Mon Feb 23 19:03:46 2004
13
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57
8
12
12
12
5
57
54
57
23
12
6
12
54 5
12
7
58
54
12
57
12
58
12
12
54
12
12
14
6
6
6
6 Preliminary
www.vinafix.vn
P9[7]P9[6]P9[5]
P8[7]P8[6]P8[5]
P3[7]P3[6]P3[5]P3[4]
P2[6]P2[7]
P2[4]P2[5]
P1[4]P1[3]P1[2]P1[1]P1[0]
P0[4]
P0[0]
P0[2]P0[3]
P0[1]
P0[7]P0[6]P0[5]
P3[3]P3[2]P3[1]P3[0]
P2[3]P2[2]P2[1]P2[0]
P1[5]P1[6]P1[7]
PCNVSSRESET*XOUT
VREFXIN
P7[7]P7[6]P7[5]P7[4]P7[3]P7[2]P7[1]P7[0]
P6[7]P6[6]P6[5]P6[4]P6[3]P6[2]P6[1]P6[0]
P10[0]P10[1]
P9[3]P9[2]P9[1]P9[0]
P8[4]P8[3]P8[2]P8[1]P8[0]
P10[6]P10[7]
P10[2]P10[3]P10[4]P10[5]
VCC
AVSSVSS
AVCC
SQW/OUT
VBAT
SDA
SCL
X1X2
GND
VCC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Y
KI1*
NOTE: Pinout matches SMU pinout v1.51.
NOTE: All analog inputs to SMU should have a 100pF capacitor to the SMU AVSS signal (GND_SMU_AVSS). None of
Signal aliases required by this page:
- _PPVREF_SMU (SMU AVCC or 2.5V reference)
Page Notes
S = Spare
Y = Primary functionN = Alternate function
CLK3
TA2out
AN00
AN02AN03
AN01
TXD0
KI3*
S
Keep crystal subcircuit close to SMU.
Y1300’s load capacitance is 12pF
SSYY
SDAmm
INT5*INT4*Y
AN20
AN06
CTS0*
IOC7
TA2in
AN04
INT2*
CE*
Y
AN27
AN23
AN21
TA3in
AN0
(BUSY)
TB0inSin3
Master: Link
System Management Unit
provided on another page.
reference used by monitoring
(NONE)
(NONE)
- _PP3V3_PWRON_SMU- _PP3V3_ALL_RTC- _PP3V3_ALL_SMU
ELECTRICAL_CONSTRAINT_SET
BOM options provided by this page:
NOTE: CPU current/voltage monitoring
Real Time Clock
NC
provided on this page. Please. reuire pull-ups that are not.
RTS0*/
TXD1
CLK1
RTS1*
RXD0CLK0
RXD1AN07
AN05
SDA
TA4out
TA1in
AN24
TB1in
NMI*
INT1*
AN25
SCLmm
Y
Y
YY
YY
YY
Sout3
AN1AN2AN3
KI0*
KI2*
YY
IOC4
Y
SCL
this page.
TB2in
to ensure missing pull-ups are review the latest SMU specification
Power aliases required by this page:
IOC6
TA4in
TA3out
(CPU_SENSE_I/CPU_SENSE_V) requires
Caps should connect to GND_SMU_AVSS.
those capacitors are provided on
affect other analog inputs such as AC adapter ID.
NOTE: Some primary and alternate functions
SS
TA1out
DIFFERENTIAL_PAIR
System Management Unit
NET_SPACING_TYPE
SMU Pull-ups / pull-down
Server
Y
Desktop
Portable
Y
YY
YYY
NN
YY
S
YY
YY
Y
YY
Y
YY
NN
YYY
YY
S
Y
SSY
Consumer
SS
S SSS
Y Y Y YY
Y
YNSYY
Y
YYY
YY
S
YY
YYY
Y
YYYSS
N
S
Y
YYY
YY
Y
Y
YY
YY
Y
YY
Y
YY
YY
Y
S
YYYYS
YYY
Y
YYYY
S
Server
N
NN
Consumer
NNN
SS
NY
YSS
YY
Y
SSYY
NY
YYY
Y
YY
Y
S
Y
Y
Y
Y
Y
YS
Y
Y
Y
Y
Y
SY
YS
YS
Y
Y
Y
Y
Y
SY
Y
YS
Y
Y
Y
SYY
YYY
YYYYY
Portable
YYY
Y
YYYY
YY
YY
Y
YNY
Y
Y
YY
Y
YY
YY
YY
YY
SYYY
Y
YY
Y
Y
S
Desktop
Entry Desktop
Entry Desktop
YY
YY
Y
Y
YY Y
Y
Y
YY
YY
YY
Y
Y
Y
YY
S S
N N
Y Y
YY
YYSYY
Y Y
YY
YY
YY
SINT0*
S
YYYY
YY Y
Y
YYY
YY
AN26SS
YY Y
SYY
YY
YY
YY
SY Y
S
YY
Y
YY
S S
(see aliases below)
NNN
YYY
Y
YY
YYY
Y
YYY
Y
YYY
Y
AN22
INT3*
IOC5
YY
YYYY
Y
YS S
IOC3IOC2
Y
Y
Tower & Server
7.47.2
6.0
6.26.1
PortConsumer
2.5Port
2.62.7
Alternate FunctionsPortable
0.4Port
0.50.6
1.71.61.5
7.6
circuit, but be aware that this will
SMU_VREF should be same signal or
100K/10uF RC filter at SMU pins.
21
Y1300
8X4.5MM-SM
10.0000M
CRITICAL
1012
11
77
13
9
798012345
78141516171819
2021222324252627
2829303140414243
3233343536373839
4445464748495051
52535455565758
6869707172737476
59
6061626364656667
6
75
78
U1300QFP-80
M30280F8
OMIT
21
8
37
5
6
4
U1301MSOP
DS1338
PP3V3_PWRON
PP3V3_RUN
PP2V5_PWRON
21
R1399
5%1/16WMF402
NO_SMU_I2C_D
0
3
1
D1310SOT23
1N914
2
1 C13251uF
CERM6.3V10%
4022
1R132510K
5%
MF1/16W
402
2
1R1322100K5%1/16WMF402
2
1C131020%
0.22uF
402
6.3VCERM
2
1C130450V5%
12pF
402CERM 2
1C130550V5%
12pF
402CERM
2
1R1317
402
1/16WMF
5%0
21
R131610M
5%
MF1/16W
402
NO STUFF
2
1R1327
402
1/16WMF
5%10K
21
R1312100K
5%1/16WMF402
21
R1311
402MF
1/16W5%
100K
21
R1313
402MF
1/16W5%
100K
21
R1310100K
5%1/16WMF402
21
R1302
402MF
1/16W5%
10K
21
R1300
5%1/16WMF402
10K
12
R1304
5%1/16WMF
10K
402
2
1 C130910V20%
CERM
0.1uF
402
2
1C130810V20%
0.1uF
CERM402
2
1C130210V20%
0.1uF
CERM402
2
1C130110V20%
0.1uF
CERM402
2
1C13006.3V
10uF20%
CERM805
2
1 C1303
402CERM
1uF10%6.3V
21
R1315
402MF
1/16W5%
4.7
21
XW1300SM
4
1Y130132.768KSM-1
CRITICAL
051-65321031303FAN_PWM8 SYS_KBDLED
SYS_DOOR_AJAR_L SYS_LID_OPENSYS_DRIVE_BAY_INT_L SMU_BATT_DET_LSYS_POWERFAIL_L SMU_ACINFAN_RPM5 ALS_GAIN_BOOSTFAN_RPM4 ALS1_OUTFAN_RPM3 ALS0_OUT
FAN_TACH5 SYS_LED_BLUEFAN_TACH4 SYS_LED_GREENFAN_TACH3 SYS_LED_RED
I2C_SMU_CPU_SDA_IN FAN_PWM6I2C_SMU_CPU_SCL_IN FAN_PWM7
CPU_VID<1> FAN_TACH7CPU_VID<2> FAN_TACH8
CPU_VID<0> FAN_TACH6
SYS_SLOT_PWR
TP_SMU_SPARE_P10_0
SYS_RESET_BUTTON_L
SB_SUSPENDACK_LNB_SUSPENDACK_LSMU_WARM_RESET_L
SMU_PWRSEQ_P9_6
SB_STOPXTALS_L
I2C_SMU_CPU_SDA_OUT
FAN_PWM8
I2C_SMU_B_SCL
CPU_VID<3>
CPU_VID<1>CPU_VID<0>
CPU_VID<2>
I2C_SMU_A_SDA_INI2C_SMU_A_SDA_OUT
FAN_TACH4
FAN_RPM3
15 MIL SPACING SMU_CLK10M_XOUT_R
SMU_PWRSEQ_P9_5
CPU_TEMP
SYS_COLD_RESET_L
SYS_POWER_BUTTON_LSMU_SUSPENDREQ_L
SB_TO_SMU_INT_L
CLOCK_RESET_L
SMU_SLEEP
SYS_SLEWING_L
I2C_SMU_CPU_SCL_OUT
CPU_HRESET_L
FAN_RPM1
SYS_LED
I2C_SMU_CPU_SDA_IN
FAN_RPM2
SYS_PME_LTP_SMU_SPARE_P8_3
I2C_SMU_CPU_SCL_INFAN_RPM0
I2C_SMU_B_SDA
SMU_BOOT_TXD
SMU_TO_SB_INT_L
FAN_TACH5
FAN_TACH3FAN_TACH2
SYS_DOOR_AJAR_L
FAN_TACH0I2C_SMU_E_SCLI2C_SMU_E_SDA
SMU_PWRSEQ_P1_3SMU_PWRSEQ_P1_4
SMU_ONEWIREFAN_RPM5
I2C_SMU_D_SDA
CPU_SENSE_ICPU_SENSE_V
SYS_DRIVE_BAY_INT_L
SMU_PWRSEQ_P1_0SMU_PWRSEQ_P1_1
CPU_BYPASS_L
FAN_RPM4
SMU_PWRSEQ_P1_2
SMU_CHARGE_BATTI2C_SMU_D_SCL
I2C_SMU_A_SCL_INI2C_SMU_A_SCL_OUT
15 MIL SPACINGSMU_CLK10M_XTAL SMU_CLK10M_XIN
RTC_CLK32K_X215 MIL SPACING
I2C_RTC_SDA
I2C_RTC_SCL
15 MIL SPACINGRTC_CLK32K_XTAL RTC_CLK32K_X1
SMU_CLK10M_XOUT15 MIL SPACING
FAN_TACH1
SYS_OVERTEMP_L
SYS_POWERFAIL_L
_PPVREF_SMU
SMU_BOOT_CNVSS
_PP3V3_ALL_SMU
SMU_RESET_L
SMU_CLK10M_XOUT
SMU_CLK10M_XOUT_RSMU_CLK10M_XIN
SMU_BOOT_RXD
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SYS_COLD_RESET_L
SMU_SLEEP
SYS_POWERUP_L
_PP3V3_ALL_SMU
SYS_POWER_BUTTON_L
SYS_PME_L
GND_SMU_AVSS
SMU_BOOT_CE
MAKE_BASE=TRUESYS_POWERUP_L
CPU_VID<5>
SMU_BOOT_SCLKSMU_BOOT_BUSY
CPU_VID<4>
_PP3V3_ALL_SMUVOLTAGE=3.3VMIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 mil
PP3V3_ALL_SMU_AVCC
VOLTAGE=0VMIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 mil
GND_SMU_AVSS
_PP3V3_ALL_SMU_PP3V3_ALL_RTC
RTC_CLK32K_X1
RTC_CLK32K_X2
42
25
42
17
31
23
18 31
18
17
32
18
32
18
12
19
51
16
23
25
48
17
16
19
25
23
51
14
16
16
48
19
14
16
19
16
8
17
17
13
13
13
18
18
31
31
31
16
22
18
31
31
31
13
22
13
22
13
23
28
15
18
23
18
15
18
16
13
13
15
18
18
28
15
15
16
13
16
16
23
22
22
13
13
13
13
23
17
13
31
13
17
13
13 19
13 17
13 7
13 7
13 6
13 19
13 6
5
5
5
13
13
13
13
13
6
23
22
5
14
23
18
13
6
31
13
13
13
18
18
5
13
13
14
32
13
6
13
23
25
5
13
18
27
6
19
13
5
13
13
6
6
6
23
5
5
5
13
6
6
6
14
14
17
13
32
32
13
14
14
27
13
14
8
5
18
18
13
13
18
18
13
13
6
6
13
5
6
5
6
13
13
13
6
13
13
13
5
6
5
6
13
13
16
6
6
16
16
6
5
13
5
5
13
13
Preliminary
www.vinafix.vn
ALIAS
G
D
S
ALIAS
G
D
S
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
G
D
S
G
D
S
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TPS5120 needs a pull-up stronger than 82.5K
ACTIVE-HIGH, OUTPUT, PUSH-PULL
ACTIVE-HIGH, OUTPUT, PUSH-PULL
ACTIVE-LOW, OUTPUT, PUSH-PULL
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR
100K pull-up to 3.3V_ALL on pg 13
ACTIVE-LOW, OUTPUT, PUSH-PULL
ACTIVE-LOW, OUTPUT, PUSH-PULL
POWER-UP
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR
SHUT-DOWN
SLEEP
WAKE
Power Sequencing
Used to see if last rail is up
ANALOG INPUT, SENSE > 1.7V
21
R1411
1/16W
0
402MF
5%
21
R1420
402
1/16WMF
5%
100K
21
R1421100K
402MF
1/16W5%
21
R1422
5%1/16WMF402
100K
21
R1430
5%
MF402
0
1/16W
2
1R14355%
1/16WMF
100K
402
4
5
3
Q14352N7002DW
SOT-363
PP5V_RUN
21
R1436
5%1/16WMF402
100K
21
R1437
402MF
1/16W
100K
5%
21
R1440
5%
MF
100K
1/16W
402
21
R1441
5%
MF402
100K
1/16W
21
R14500
1/16WMF402
5%
21
R14510
5%
MF402
1/16W
PP5V_RUN
2
1R14655%1/16WMF402
100K
1
2
6
Q14352N7002DW
SOT-363
21
R1466
5%1/16WMF402
100K
21
R1467
5%1/16WMF402
0
2
1R1449
MF1/16W
05%
402
2
1R14595%0
1/16W
402MF
21
XW1470SM
21
R1469
402MF
1/16W5%
0
2
1R14581/16W
402
5%
MF
100K
2
1R1448100K5%1/16WMF402
PP3V3_RUN
PP3V3_RUN
1
2R1412100K1/16W
5%
MF402
2
1R14015%
MF402
68K1/16W
PP3V3_ALL
1
2
6
Q1400SOT-3632N7002DW
4
5
3
Q1400SOT-3632N7002DW
2
1R1429
MF
100K1/16W
5%
402
PP5V_PWRON
21
R1402
5%
0
1/16WMF402
21
R14030
1/16W5%
MF402
21
R1400
402MF
5%1/16W
0
21
R1410
5%
MF402
0
1/16W
14 10303051-6532
SYS_POWERUP_L_R
5VRUNHD_EN_L
SYS_POWERUP_L
GPUVCORE_SHDN_L
CPU_AVDD_EN
GPUVDD15_EN
3V3RUN_EN_L
1V5RUN_EN
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P9_6MAKE_BASE=TRUE
SYS_PWRSEQ_7 PP1V8_GPU_PVDD
GPUVCORE_PGOOD
CPUVCORE_SHDN_L
1V8RUN_SHDN_L
GPUPVDD_EN
VCORE_SWITCHING
1V2RUN_EN
1V8RUN_PGOOD
2V5RUN_EN_L
3V3_STBY_L
2V5NBVCORE_STBY_L
SMU_PWRSEQ_P1_4
2V5_NBVCORE_PGOOD
SMU_PWRSEQ_P9_5 SYS_PWRSEQ_6_LMAKE_BASE=TRUE
MAKE_BASE=TRUESYS_PWRSEQ_6_LS5
MAKE_BASE=TRUESYS_PWRSEQ_5
5V3VPWRON_PGOOD
5VRUN_EN_L
MAKE_BASE=TRUESYS_PWRSEQ_1
SMU_PWRSEQ_P1_2
MAKE_BASE=TRUESYS_PWRSEQ_4
PWRON_REGS_PGOODMAKE_BASE=TRUE
SYS_PWRSEQ_3_LS5
SYS_PWRSEQ_3_LMAKE_BASE=TRUE
SMU_PWRSEQ_P1_0
SYS_PWRSEQ_2_L
SYS_PWRSEQ_2MAKE_BASE=TRUE
SMU_PWRSEQ_P1_1
SYS_POWERUP
FWPWR_PWRON
5V_STBY_L
13
10
6
38
29
39
10
9
13
13 40
38
31
9
40
31
9
9
11
10
11
13
11
13
10
10
13
13
13
6
12
10
Preliminary
www.vinafix.vn
GND
DXN3
DXN4
DXP4
DXP3
DXP1
DXN1
DXP2DXN2
ADD0
ADD1
ALERT*
STBY*
SMBDATA
SMBCLK
VCC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ELECTRICAL_CONSTRAINT_SET
Fan 1
Fan 2
Thermal Sensor / Fans
(NONE)
- _PP5V_PWRON_FAN
thermal sensors for each of the available remote sensor locations.
- THERM_x / THERM_xBBOM options provided by this page:
Signal aliases required by this page:
- _PP3V3_PWRON_THERM
Page NotesPower aliases required by this page:
DIFFERENTIAL_PAIR
(PWM)
Remote 3 Remote 3 (Backup)
Remote 2 (Backup)
(GND)
(TACH)(PWR)
GPU Thermal DiodeRemote 4
Addr=0x30(Wr)/0x31(Rd)
(GND)(PWM)
Remote 1 (Backup) minimizing stubs.
to two different sensors. These
Sensor Selection
Remote 1
Place each cap close to associated transistorRemote Temperature Sensors
Selects between primary and backup
NET_SPACING_TYPE
resistors should be close to MAX1668,
First 3 MAX1668 inputs can connect
MAX1989 Thermal Sensor
(TACH)(PWR)
Remote 2
Place close to CPU_VCORE Place close to 5V/3.3V
Place close to U3Lite
Place close to Shasta/GPU_Vcore Place close to bottom RAM
Place close to CPU
2
3
1Q1510THERM_1
2N3904SM
2
1 C151020%50VCERM402
THERM_1
0.001uF
2
1 C1520
402
0.001uF
CERM50V20%
THERM_2
2
3
1Q1520SM
2N3904
THERM_2
2
1 C1515
CERM50V20%
402
0.001uF
THERM_1B
2
3
1Q1515SM
2N3904
THERM_1B
2
1 C1525
402
0.001uF
CERM50V20%
THERM_2B
2
3
1Q1525SM
2N3904
THERM_2B
21
R1510THERM_1
0
402MF
1/16W5%
21
R1515THERM_1B
5%1/16WMF402
0
21
R1511
5%
MF402
0
THERM_1
1/16W
21
R1516
402
1/16W5%
0
MF
THERM_1B
21
R1520
5%1/16WMF402
0
THERM_2
21
R15250
402MF
1/16W5%
THERM_2B
21
R1526
5%1/16WMF402
0
THERM_2B
21
R1521THERM_2
0
402MF
1/16W5%
2
1R159210K
402MF
1/16W5%
2
1C159220%10V
CERM1206
4.7uF
9
15
13
14
16
7
5
3
1
8
6
4
2
12
1011
U1500MAX1668
QSOP
CRITICAL
2
1 C1505NO STUFF
20%50VCERM402
0.001uF2
1 C15070.001uF
402CERM50V20%
NO STUFF
2
1C15060.001uF
402CERM50V20%
NO STUFF
2
1C1508NO STUFF
20%50V
CERM402
0.001uF
2
1 C1500
402
0.1uF
CERM10V20%
21
R1500
402MF
1/16W5%
200
2
1 C150150V20%
CERM402
0.001uF
NO STUFF
2
1C15020.001uF
402CERM50V20%
NO STUFF
2
1 C1503NO STUFF
0.001uF
402CERM50V20%
2
1C15040.001uF
402CERM50V20%
NO STUFF
21
R1535THERM_3B
5%1/16WMF402
0
21
R1536THERM_3B
0
402MF
1/16W5%
21
R1530THERM_3
0
402MF
1/16W5%
21
R1531THERM_3
5%1/16WMF402
0
2
1 C1535THERM_3B
20%50VCERM
0.001uF
4022
3
1Q1535SM
THERM_3B
2N39042
1 C1530
402
0.001uF
CERM50V20%
THERM_3
2
3
1Q1530SM
2N3904
THERM_3
2
1 C154020%50VCERM
0.001uF
402
4
3
2
1
6
5
J1592SM-2MT
CRITICAL
4
3
2
1
6
5
J1591SM-2MT
CRITICAL
2
1R15915%
1/16WMF
10K
402
2
1C159120%10V
CERM1206
4.7uF
03051-653215 103
THERM_1_N
THERM_2_N
_PP3V3_RUN_FAN
_PP3V3_RUN_FAN
_PP5V_PWRON_FAN
_PP5V_PWRON_FAN
PP3V3_PWRON_MAX1989
MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 milVOLTAGE=3.3V
MAX1989_D4 MAX1989_D4_NTHERM
MAX1989_D1 MAX1989_D1_PTHERMMAX1989_D1 MAX1989_D1_NTHERMMAX1989_D2 MAX1989_D2_PTHERM
THERM THERM_3_PTHERM_3
THERM THERM_1 THERM_1_NTHERM THERM_1_PTHERM_1
MAX1989_D4 MAX1989_D4_PTHERMMAX1989_D3 MAX1989_D3_NTHERM
THERM_1_P
THERM THERM_2_NTHERM_2
FAN_TACH0
I2C_MAX1989_SDA
MAX1989_D4_N
MAKE_BASE=TRUEGPU_THMDIODE_P
MAKE_BASE=TRUEGPU_THMDIODE_N MAX1989_D4_N
MAX1989_D4_P
FAN_TACH1
FAN_RPM0
FAN_RPM1
THERM_1B_P
THERM_1B_N
THERM_2B_N
THERM_3B_P
THERM_3B_N
THERM_2_P
THERM_3_P
THERM_3_N
THERM_2B_P
MAX1989_D1_P
MAX1989_D1_N
MAX1989_D2_P
MAX1989_D2_N
MAX1989_D3_P
MAX1989_D3_N
THERM_1B_P
THERM_1_P
THERM_1_N
THERM_2_P
THERM_2B_P
THERM_2_N
THERM_3B_P
THERM_3_P
THERM_3_N
THERM_3B_N
MAX1989_D2 MAX1989_D2_NTHERM
THERM THERM_2_PTHERM_2
THERM THERM_3B_PTHERM_3BTHERM THERM_2B THERM_2B_NTHERM THERM_2B_PTHERM_2BTHERM THERM_1B_NTHERM_1B
THERM THERM_3_NTHERM_3
_PP3V3_PWRON_THERM
MAX1989_D2_P
MAX1989_D3_PSYS_OVERTEMP_L
MAX1989_D4_P
MAX1989_D1_P
I2C_MAX1989_SCL
THERM_2B_N
THERM_1B_N
MAX1989_D3_N
MAX1989_D2_N
MAX1989_D1_NTHERM THERM_1B_PTHERM_1B
THERM THERM_3B_NTHERM_3B
MAX1989_D3 MAX1989_D3_PTHERM
25 23 17
15
15
15
15
13
13
13
13
13
15
15
5
5
5
5
15
15
15
15
15
15
15
15
15
15
15
6
18
15
37
37 15
15
6
6
6
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
5
15
15 6
15
15
18
15
15
15
15
15
15
15
15
Preliminary
www.vinafix.vn
S
D
G
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Debug LEDs
Debug "Buttons"
"RESET"
Add silkscreen:
"POWER"
(GPIO#)
(TRXC)
516S0143
(RXD)
(SCCA)
(DTR#)
(RTS#)(TXD#)
allow serial debug flex to use either connectorSCC same pins have pinout as modem connector to
SMU Download / Serial Debug Connector
INTERNAL I/O CONNECTORS
21
R1690NO STUFF
5%1/16WMF
0
603
21
R1691
1/16W
603
5%
MF
0
NO STUFF
9
8 7
6 5
4 3
2
16 15
14 13
12 11
10
1
J1699DEVELOPMENT
QT510166-L010F-ST-SM1
CRITICAL
2
1R3054DEVELOPMENT
5%1801/16WMF402
2
1D3002SMRED
DEVELOPMENT
2
1
3
Q3004DEVELOPMENT
Q3004_D
SM2N7002
2
1R3052DEVELOPMENT
5%
402MF1/16W
180
2
3
1 Q3003DEVELOPMENT
SMQ3003_B 2N3904
2
3
1
Q3002SM
DEVELOPMENT
2N3906
2
1R3048DEVELOPMENT
5%1801/16WMF402
21
R3050
5%
DEVELOPMENT
402MF
1/16W
180
2
1
D3001GREENSM
DEVELOPMENT
2
1R3070DEVELOPMENT
1/16W5%
402MF
180
2
1R3046DEVELOPMENT
5%1K1/16WMF402
2
3
1 Q3001DEVELOPMENT
SM2N3904
21
R3044
5%
DEVELOPMENT
402MF
1/16W
180
03051-653210316
_PP5V_PWRON_SERIAL_PP3V3_ALL_SMU
I2S1_SB_TO_DEV_DTOI2S1_MCLK
I2S1_RESET_LSMU_BOOT_TXDSMU_BOOT_RXDSMU_BOOT_BUSY
I2S1_SYNCI2S1_DEV_TO_SB_DTII2S1_BITCLKSMU_RESET_LSMU_BOOT_CESMU_BOOT_SCLKSMU_BOOT_CNVSS
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
D3002_1
PP5V_RUN_CPU
Q3004_G
Q3002_E
CHKSTOP_L
D3001_1
PP5V_RUN_CPU
Q3002_B
Q3001_C
Q3001_BPLLLOCK
42
18
60
60
60
60
60
60
19
17
29
29
13
23
23
23
13
13
23
23
23
13
13
13
13
16
16
5 5
6
6
6
6
6
13
6
6
6
6
13
13
6
6
6
5
27
5
27 Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
series resistors to protect SMU pins
overtemp may need pull-up resistor
USB Trackpad Connector
For EMI around ENET magnetic
Speaker Clips
for EMI testing only
Graphic Heat SinkCPU Heat Sink Right I/O area
PPBUS Hold-Up CapsBlueTooth / Left USB Flex Connector
Place cap close to SMU
battery circuit. _PPBUSA_BBATT is an output only.
NC
NC
Backup Battery / Right USB Flex Connector
_PPBUSB_BBATT is both an input and an output for backup
Q51 Specific connectors
Place cap close to SMU
21
D790SM
MBR0530
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J1600CRITICAL
F-RT-SM54550-1490
2
1 C862CRITICAL
ELEC25V20%33uF
SM12
1 C861CRITICAL
SM1
33uF20%25VELEC
2
1 C865CRITICAL
ELEC25V20%33uF
SM12
1 C864CRITICAL
ELEC25V20%33uF
SM1
2
1 C860CRITICAL
ELEC25V20%33uF
SM1
2
1 C863CRITICAL
ELEC25V20%33uF
SM1
1
ZT511146R126
1
ZT510146R126
1
BS510STDOFF-217ODX150IDX35H-TH
1
ZT503255R158
1
ZT504255R158
1
ZT502255R158
1
ZT500255R158
1
ZT501255R158
1
ZT505255R158
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J79054550-1490
CRITICAL
F-RT-SM
1
SP9900OMIT
SPKR_CLIP_P84
1
SP503SPKR_CLIP_P84
1
SP504SPKR_CLIP_P84
1
SP505SPKR_CLIP_P84
1
SP500SPKR_CLIP_P84
1
SP501SPKR_CLIP_P84
1
SP502SPKR_CLIP_P84
1
ZT9901HOLE-VIA-20R10
OMIT
2
1 C1610
CERM402
5%50V
100pF
1
ZT9903HOLE-VIA-20R10
OMIT
1
ZT9900HOLE-VIA-20R10
OMIT
1
ZT9902OMIT
HOLE-VIA-20R10
2
1R2132100K
402
5%
MF1/16W
98765432
1413121110
1
16
15
J2130CRITICAL
F-RT-SM54550-1490
2
1R21315%1/16WMF402
15K
2
1R21305%
MF402
15K1/16W
21
R16201K
MF
5%1/16W
402
21
R1610
MF
5%1/16W
402
0
2
1R16213.32K1%1/16WMF402
2
1R16111K5%1/16WMF402
PP3V3_ALL
2
1 C1605
CERM50V5%
402
100pF
2
1R16015%1/16W
15K
MF4022
1R16005%
1/16WMF402
15K
18 103
03051-6532
ALS0_OUT
GND_SMU_AVSS
ALS0_OUT_R
SMU_ONEWIREMAKE_BASE=TRUE
GND_SMU_AVSS
_PPBUSA_BBATTPPBBATT_BOOST_OUT
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 milVOLTAGE=6.3V
RTUSB_PWREN
USB2_RT_N
RTUSB_OVERCURRENT
USB2_RT_P
_PP5V_PWRON_RTUSB_PPBUSB_BBATT
USB_BT_NUSB_BT_P
_PP5V_PWRON_LTUSB
ALS_GAIN_BOOSTMAKE_BASE=TRUE
LTUSB_OVERCURRENT
USB2_LT_P
LTUSB_PWREN
USB2_LT_N
_PP3V3_PWRON_BT
_PPBUS_ALL_A
_PPBUS_ALL_B
GND_CHASSIS_DVI
GND_CHASSIS_IOGND_CHASSIS_INVERTER
_PP3V3_ALL_HALLEFFECT
USB_TPAD_N
SYS_LID_OPENMAKE_BASE=TRUE
_PP5V_PWRON_TPAD
PP3V3_PWRON
USB_TPAD_P
KBDLED_RETURNKBDLED_ANODE
SYS_OVERTEMP_L
SYS_POWER_BUTTON_L
I2C_DS1775_SDAI2C_DS1775_SCL
ADAPTER_ID
25
32
32
23
42
19
19
19
42
15
16
13
17
17
13
8
8
6
25
19
19
13
13
6
13
13
13
5 11
5
5
5
5
5
5
5
5
5
6
5
5
5
5
5
5
5
5
5 5
5
5
13
5
6
5
6
6
6
6
18
18
6
Preliminary
www.vinafix.vn
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIASALIAS
ALIAS
ALIAS
ALIAS
LM339AV+
GND
LM339AV+
GND
LM339AV+
GND
LM339AV+
GND
G
D
S
G
D
S
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(MASTER)U1300SMU U3
(MASTER)
NorthBridge I2C "B" Bus
I2C CONNECTIONS
I2C "A" Bus
U3LiteU3
(MASTER)U1300SMU
(Write: 0x?? Read: 0x??)U2900CPU
Power aliases required by this page:(NONE)
(NONE)
(NONE)BOM options provided by this page:
(I2C_CPU_A_SDA)
(I2C_CPU_A_SCL)
(Write: 0x?? Read: 0x??)
ELECTRICAL_CONSTRAINT_SET DIFFERENTIAL_PAIRNET_SPACING_TYPE
(Write: 0xAC Read: 0xAD)(Address set on modem flex)
MicroDash
Audio Board(Write: 0x?? Read: 0x??)
J9500
J9400
SouthBridge I2C Bus
(MASTER)U2300
ShastaRTCU1301
J790
U800
(Write: 0x?? Read: 0x??)
(Write: 0x?? Read: 0x??)
(Write: 0x?? Read: 0x??)
Battery Charger
Battery Conn
I2C "E" Bus
SMUU1300
(MASTER)
PulsarU2600
On Trackpad FlexDS1775
(Write: 0x?? Read: 0x??)
(Write: 0x30 Read: 0x31)
(Write: 0x?? Read: 0x??)
I2C "B" Bus
SMU(MASTER)U1300
U3Lite
(Write: 0xA0 / 0xA2,J4010 / J4020DIMMs
Read: 0xA1 / 0xA3)
NorthBridge I2C "C" Bus
U3(MASTER)
U3Lite
MAX1989U1500
Signal aliases required by this page:
Page Notes
U3 Lite I2C inversion
2
1R20295%1/16WMF402
2K
PP2V5_PWRON
2
1R2028
402MF
1/16W5%2K
2
1R20517.15K1/16W1%
MF4022
1R20501%
7.15K1/16W
MF402
2
1R20195%1/16WMF402
200
2
1R2018
MF402
5%2001/16W
2
1R20155%
1/16WMF402
4.7K
PP5V_PWRON
2
1C201520%10V
CERM402
0.1uF
3
13
11
10
12
U2015SOI
CRITICAL
PP3V3_PWRON
2
1R2011
402MF1/16W5%2K
2
1R20105%
1/16WMF402
2K
2
1 C2016
CERM10V20%
402
0.1uF
2
1R2016
MF1/16W
1%576
402
3
14
9
8
12
U2015SOI
CRITICALPP3V3_PWRON
2
1R20811/16W
402MF
5%2K
2
1R20801/16W
MF402
5%2K
3
1
7
6
12
U2015SOI
CRITICAL
2
1R2083
MF1/16W5%1K
4022
1R2082
MF
1K1/16W
5%
402
3
2
5
4
12
U2015SOI
CRITICAL
5
6
7
8
4
3
2
1
RP20850K5%
1/16WSM1
SMU_CPU_JTAG
5
6
7
8
4
3
2
1
RP2080
SM11/16W
5%0K
SMU_CPU_I2C
4
5
3
Q2000SOT-3632N7002DW
1
2
6
Q20002N7002DWSOT-363
PP3V3_RUN
2
1R20411K
402MF1/16W5%
2
1R20405%1K
1/16WMF402
72
RP20604.7K
SM11/16W5%
81
RP2060
5%1/16WSM1
4.7K
54
RP2060
5%1/16W
4.7K
SM1
63
RP20604.7K
SM11/16W5%
PP2V5_PWRON
2
1R20302K5%
1/16WMF402 2
1R20312K
402
1/16W5%
MF
PP3V3_PWRON
2
1R20215%1/16WMF402
1K
2
1R20201K
402MF
1/16W5%
03
20 103051-6532
I2C_0V546_REF
MAKE_BASE=TRUEI2C_SMU_A_SDA_IN
SMU_CPU_JTAG_OR_I2C
MAKE_BASE=TRUEI2C_SMU_CPU_SDA_OUT
I2C_SMU_A_SDA_OUTMAKE_BASE=TRUE
I2C_SMU_A_SCL_OUTMAKE_BASE=TRUE
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SCL_OUT_L
I2C_NB_C I2C I2C_NB_C I2C_NB_C_SDA
I2C_SBI2CI2C_SB I2C_SB_SCL
I2C I2C_SMU_A_OUTI2C_SMU_A_OUT I2C_SMU_A_SDA_OUT
I2C I2C_NB_CI2C_NB_C I2C_NB_C_SCL
I2C_DIMM_SDA
I2C_DIMM_SCL
MAKE_BASE=TRUEI2C_NB_C_SDAMAKE_BASE=TRUE
I2C_NB_C_SCL
I2C_DS1775_SDA
I2C_DS1775_SCL
I2C_MAX1989_SDA
I2C_MAX1989_SCL
I2C_CLOCK_SDA
I2C_CLOCK_SCL
I2C_CHGR_SCL
I2C_CHGR_SDA
I2C_BATT_SDA
I2C_BATT_SCL
I2C_RTC_SDA
I2C_RTC_SCL
MAKE_BASE=TRUEI2C_SMU_B_SDAMAKE_BASE=TRUE
I2C_SMU_B_SCLMAKE_BASE=TRUE
I2C_SMU_E_SCL
MAKE_BASE=TRUEI2C_SMU_E_SDA
_PP3V3_ALL_SMU
I2C_AUDIO_SDA
I2C_AUDIO_SCL
I2C_MODEM_SDA
I2C_MODEM_SCL
MAKE_BASE=TRUEI2C_SB_SDAMAKE_BASE=TRUE
I2C_SB_SCL
I2C I2C_SMU_CPU_OUTI2C_SMU_CPU_OUT I2C_SMU_CPU_SCL_OUT
I2C SMU_CPU_JTAG_OR_I2CI2C I2C_CPU_A_SDA
I2C I2C_SMU_BI2C_SMU_B I2C_SMU_B_SDAI2C I2C_SMU_BI2C_SMU_B I2C_SMU_B_SCL
I2C I2C_CPU_A_SDA_TO_SMU
I2C I2C_CPU_A_SCL
I2C I2C_SMU_A_INI2C_SMU_A_IN I2C_SMU_A_SDA_INI2C I2C_SMU_A_INI2C_SMU_A_IN I2C_SMU_A_SCL_IN
I2C I2C_SMU_A_OUTI2C_SMU_A_OUT I2C_SMU_A_SCL_OUT
I2C I2C_SMU_CPU_OUTI2C_SMU_CPU_OUT I2C_SMU_CPU_SDA_OUT
I2C I2C_NB_BI2C_NB_B I2C_NB_B_SDA
I2C I2C_SMU_CPU_INI2C_SMU_CPU_IN I2C_SMU_CPU_SCL_IN
I2C I2C_SMU_CPU_INI2C_SMU_CPU_IN I2C_SMU_CPU_SDA_IN
I2C I2C_NB_BI2C_NB_B I2C_NB_B_SCL
MAKE_BASE=TRUEI2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT_L
PP1V2_EI_NB
I2C_CPU_A_SDA
JTAG_CPU_TDO
PP1V2_EI_CPU
I2C_NB_A_SCL
I2C_NB_A_SDA
JTAG_SB_TCK
JTAG_SB_TDI
JTAG_SB_TRST_L
JTAG_SB_TMS
_PP3V3_PWRON_SB
MAKE_BASE=TRUEI2C_NB_B_SCL
MAKE_BASE=TRUEI2C_NB_B_SDA
I2C_SMU_A_SDA_OUT_L
JTAG_CPU_TDIJTAG_CPU_TMSJTAG_CPU_TCK
I2C_SMU_CPU_SCL_INMAKE_BASE=TRUE
I2C I2C_SBI2C_SB I2C_SB_SDA
I2C_CPU_A_SCLI2C_CPU_A_SDA_TO_SMU
MAKE_BASE=TRUEI2C_SMU_CPU_SCL_OUT
MAKE_BASE=TRUEI2C_SMU_CPU_SDA_IN
29
45
23
18
18
16
23
23
18
18
28
28
23
28
28
28
23
18
18
18
18
22
18
18
22
22
22
13
13 13
13
13
18
18
18
27
13
13
27
18
18
18
18
22
18
18
22
18
26
27
27
27
23
23
23
23
21
22
22
27
27
27
18
18
27
18
18
13
18
13
13
13
18
18
18
6
13
18
35
35
18
18
17
17
15
15
25
25
8
8
7
7
13
13
6
6 6
6
5
61
61
60
60
6
6
13
18
18
6
6
18
18
13
13
13
13
18
13
13
18
13
18
5
18
6
5
22
22
6
6
6
6
5
18
18
18
6
6
6
13
6
18
18
13
13
Preliminary
www.vinafix.vn
V+
V-
G
D
SPGND
EP
GND
COMP
CTRL
CS
OUTLXIN
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Ambient Light Sensor #1
SMU ALS/LEDs
Keyboard LED Driver
Sleep LED Circuit
SMU / System Reset Button
Keep inductor close to cap
Place R2115,R2116 and C2115 close to SMU
2
6
5
1
4
3
U2110CRITICAL
SOT23-6MAX4236EUTT
2
1 C211020%
CERM402
0.1uF10V
2
1R21101K
402
1%
MF1/16W
2
1R21115%1/16WMF402
5.1M
2
1C2111
CERM402
16V20%
0.01uF
2
1
RD2111CRITICAL
TH
BS520
2
1R2112120K
402MF1/16W5%
2
1C21120.22uF
20%6.3V
402X5R
2
1R21131K
402
1%
MF1/16W
2
1R211415K
402
1%
MF1/16W
21
R21151K
402
1%
MF1/16W
2
1R2199100
402MF1/16W5%
2
1
L2199SM-1400-OHM-EMI
2
1 C2199
402CERM50V10%470pF
2
3
1 Q2199SM2N3906
2
1R21931/16W
2.2K
402MF
5%
2
1R2192
402
1/16W5%
MF
4.7K
4
5
3
Q2191SOT-3632N7002DW
2
1R21915%
1/16WMF402
100K
7
1
82
69
3
45
U2150CRITICAL
QFNMAX1561
21
L2150CRITICAL
22uH
SMA-2
2
1C215120%10V
CERM402
0.1uF2
1 C21520.22uF10%
CERM50V
12102
1C2150
CERM16.3V
603
2.2uF20%
2
1D2150SMMBR0540
2
1R21508.251%1/10WFF805
43
21
SW2100SM
2
1R21163.32K1%1/16WMF402
2
1 C2115
402CERM50V5%100pF
1
2
6
Q5909SOT-3632N7002DW
21 103051-6532 03
GND_SMU_AVSS
ALS1_OUT
SYS_LED
ALS1_OUT_DIV
ALS1_OUT_R
SLEEPLED_EN_L_DIV
SLEEPLED_ANODE
SLEEPLED_ANODE_F
SLEEPLED_ANODE_F_Q
SLEEPLED_EN_L
ALS1_PHOTODIODE
MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
SMU_RESET_L
KBDLED_COMP
MAKE_BASE=TRUESYS_KBDLED
KBDLED_LX_PP5V_RUN_KBDLED
_PP3V3_PWRON_ALS1
_PP5V_PWRON_SLEEPLED
KBDLED_RETURNMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
KBDLED_ANODEMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
ALS_GAIN_BOOST
ALS1_GAIN_BOOST_L
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
ALS1_OP_IN
32
16
17
17
61
13
17
17
13
13
13
13
6
6
13
5
5
5
6
6
6
Preliminary
www.vinafix.vn
GNDGND
VDD
(SYM 6 OF 7)
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
U3Lite Core Power
Page NotesPower aliases required by this page:- _PPVCORE_PWRON_NB
BOM options provided by this page:(NONE)
(NONE)Signal aliases required by this page:
Master: Link
R14
T16
T11
U18
U13
U10
V15
K15
V12
K12
L17
L14
M16
M11
N18
N13
P15
P12
R17
W17
W14
AC13
B22
B16
B13B4
AC7
D25
D19D10
D7
D2F22
F16F13
G27
G23
AE25
G4
H19
H10J14
J9
K25K21
K16K11
K6
AE19
K2L18
L13
L10M20
M15
M12N27
N23N17
AE10
N14
N9N8
N4
P19P16
P11
R18
R13
R10
AE4
T27T23
T20
T15T12
T6
T2U17
U14U9
AG22
V19
V16V11
W25
W21W18
W13
W8W4
Y20
AG16
Y15
Y12
AA19AA10
AB27
AB23AB6
AB2
AC22AC16
AG13
AG7
U3
PBGA
OMIT
U3LITEV1.0-300MM
2
1 C2222
402
0.1UF20%10VCERM 2
1 C2223
CERM10V20%0.1UF
4022
1 C2224
402
0.1UF20%10VCERM 2
1 C2226
CERM10V20%
402
0.1UF2
1 C2225
402
0.1UF20%10VCERM 2
1 C2228
CERM10V20%0.1UF
4022
1 C2227
402
0.1UF20%10VCERM
2
1 C2230
CERM10V20%0.1UF
4022
1 C2229
402
0.1UF20%10VCERM 2
1 C2232
402
0.1UF20%
CERM10V2
1 C223120%
402
0.1UF10VCERM 2
1 C2234
402
0.1UF20%10VCERM2
1 C2233
CERM10V20%0.1UF
402
2
1 C2236
402
0.1UF20%10VCERM
2
1 C2235
402
0.1UF20%10VCERM
2
1 C2238
402
0.1UF20%10VCERM2
1 C2237
CERM10V20%
402
0.1UF2
1 C2240
402
0.1UF20%10VCERM2
1 C223910V20%0.1UF
402CERM 2
1 C2242
CERM10V20%0.1UF
4022
1 C2241
CERM10V20%0.1UF
402
2
1 C2243
CERM10V20%0.1UF
4022
1 C2244
402
0.1UF20%10VCERM 2
1 C2245
402
0.1UF20%10VCERM 2
1 C2246
402
0.1UF20%10VCERM 2
1 C2247
402
0.1UF20%10VCERM
ABBREV=DRAWINGTITLE=FIZZY
1032203051-6532
_PPVCORE_PWRON_NB
LAST_MODIFIED=Mon Feb 23 19:04:04 2004
5
Preliminary
www.vinafix.vn
VIO1
POWER
VDDO33
VDDO25
VIO2
VDDP_KL
VDDC
GND
GND
GND
(1 OF 8)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DRAWING
Master: Link
other Shasta supplies.
- _PP2V5_PWRON_SB
- _PPPCI32_PWRON_SB (to 5V or 3.3V)- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
different drive timing
PCI, otherwise 3.3V.
Connect _PPPCI32_PWRON_SB to spec for 5V vs. 3.3V operation.
appropriate PCI bus voltage and
Signal aliases required by this page:(NONE)
(NONE)BOM options provided by this page:
Power Sequencing:
- _PPVCORE_PWRON_SB (1.2V)NOTE: PCI pads use the VIO supply to meet
characteristics required by the PCI
_PPPCI64_PWRON_SB to same if 64-bit
Must power Shasta VCore rail before any
Page NotesPower aliases required by this page:
Shasta Core Power
Shasta max (est 06/30/03) current:
VDDPs - 2.5V - 100 mA ( 250 mW)I/O 2.5 - 2.5V - 20 mA ( 60 mW)
Total: 3015 mW
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
ANALOG12 - 1.2V - 600 mA ( 760 mW)DIGITAL - 1.2V - 950 mA (1175 mW)
For PCI_AD<31..0>
For PCI_AD<63..32>
2
1 C230420%10VCERM402
0.1uF
2
1 C230510VCERM402
0.1uF20%
2
1 C23060.1uF
402CERM10V20%
2
1 C230720%10VCERM402
0.1uF2
1 C23080.1uF
402
20%
CERM10V 2
1 C230920%10V
402CERM
0.1uF
2
1 C23020.1uF
402CERM10V20%
2
1 C23010.1uF
402CERM10V20%
2
1 C230020%10VCERM402
0.1uF
2
1 C23140.1uF
402CERM10V20%
2
1 C23130.1uF
402CERM10V20%
2
1 C2312
402
20%10VCERM
0.1uF2
1 C231120%10VCERM402
0.1uF2
1 C2310
402CERM
20%10V
0.1uF
2
1 C233420%10VCERM402
0.1uF2
1 C23330.1uF
402CERM10V20%
2
1 C23390.1uF
402CERM10V20%
2
1 C233820%10VCERM402
0.1uF
2
1 C233220%10VCERM402
0.1uF2
1 C23310.1uF
402CERM10V20%
2
1 C23370.1uF
402CERM10V20%
2
1 C233620%10VCERM402
0.1uF
2
1 C233020%10VCERM402
0.1uF
2
1 C23350.1uF
402CERM10V20%
2
1 C23240.1uF
402CERM10V20%
2
1 C23230.1uF
402CERM10V20%
2
1 C232920%10VCERM402
0.1uF2
1 C232820%10VCERM402
0.1uF
2
1 C232220%10VCERM402
0.1uF2
1 C2321
CERM
20%10V
402
0.1uF
2
1 C23270.1uF
402CERM10V20%
2
1 C23260.1uF
402CERM10V20%
2
1 C23200.1uF
402CERM10V20%
2
1 C232520%10VCERM402
0.1uF
2
1 C235120%10VCERM
0.1uF
4022
1 C23500.1uF
402
10V20%
CERM
2
1 C23570.1uF
402
20%10VCERM2
1 C235620%10VCERM402
0.1uF2
1 C23550.1uF
402CERM10V20%
2
1 C2362
CERM402
0.1uF10V20%
2
1 C236120%
CERM402
0.1uF10V2
1 C23600.1uF10V
402CERM
20%
2
1 C23650.1uF
402CERM10V20%
Y19
W22
L21
K21
H17
H18
V8
D1
B5B2
B1
AB6AB2
AB10AA3
W4V7
U9
U12R2
M1L7
H1
F8F4
AA2
AA1
G15
D19
P15
N8
M15
L8
L15
K8
J15
J12
T15
T10
R9
R12
R10
H8
H15
D2C19
AB22
AB1
W5W19
U22
U13U10
T12R19
P9
P4
AA6
P14
P13
P12P10
N9
N22N13
N12N11
N10
AA10
M2
M14
M13
M12
M11
M10
L9
L16
L14
L13
A5
L12
L11
L10
K9
K7
K13
K12
K11
K10
J22
A22
J16
J14
J13J11
J10H9
H2
F7F3
E22
A2A1
U2300
OMIT
BGAV1.0
SHASTA
2
1 C230320%10VCERM402
0.1uF
23 103051-6532 03
TITLE=FIZZYABBREV=DRAWING
_PP2V5_PWRON_SB
_PPPCI64_PWRON_SB
_PPPCI32_PWRON_SB
_PP3V3_PWRON_SB
_PP2V5_PWRON_SB
_PPVCORE_PWRON_SB
LAST_MODIFIED=Mon Feb 23 19:04:08 2004
56
56
45
45
45
23
23
23
21
18
21
5
5
5
5
5
5
Preliminary
www.vinafix.vn
G
D
SG
D
S
S
D
G
G
D
SG
D
SG
D
SG
D
S
SYS_ISCL0SYS_ISCA0
SYS_ISCA1
SYS_ISCL1
API_ISCA
API0_ISCL
THMO
DUMMY_ADUMMY_B
PMR_OBSV
IRQ0
THMI
(SYM 7 OF 7)
HRESET*PURESET*
SUSPENDACK*SUSPENDREQ*
CE1_B_TDOCE1_A_TDI
CE1_LT_TCK
VSP_CLKNVSP_CLKP
CE1_DI1_TMS
CE1_DI2_TRSTCE1_RI
CEO_TEST
PM_SLEEP0
CE0_RE
CE0_MC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
MASTER: GILA
JTAG_NB_TRST_L
JTAG_NB_TDOJTAG_NB_TMS
U3LITE MISC
JTAG_NB_TDIJTAG_NB_TCK
U3LITE REQUIRES ALL JTAG SIGNALSHIGH FOR NORMAL OPERATION
PP3V3_PWRON
PP3V3_PWRON PP3V3_PWRON
PP3V3_PWRON PP2V5_PWRON
PP2V5_PWRONPP2V5_PWRON
PP2V5_PWRON
I109
I110
2
1R2435
MF1/16W5%4.7K
402
2
1 C24000.1UF
402CERM10V20%
2
1R2418100MF1/16W5%
402
2
1R2419
402MF1/16W5%100
NOSTUFF
4
5
3
Q2404SOT-3632N7002DW
NOSTUFF
2
1R24201/16W402
10K5%MF
NOSTUFF
2
1R2400
MF
1001/16W
402
1%
1
2
6
Q24042N7002DWSOT-363
NOSTUFF
2
1
3
Q24072N7002SM
2
1R2421
MF1/16W5%10K
4022
1R2422
402
4.7K5%1/16WMF
2
1
3
Q2408SI2302DSSM
4
5
3
Q2409SOT-3632N7002DW
2
1R24231/16W
10K
MF5%
402
1
2
6
Q24092N7002DWSOT-363
4
5
3
Q2412NOSTUFF
2N7002DWSOT-363
2
1R2438NOSTUFF
MF
10K
402
5%1/16W
1
2
6
Q2412NOSTUFF
SOT-3632N7002DW
2
1R2403
402MF1/16W1%100
2
1R2424
402
10K5%1/16WMF
2
1R2426
402MF1/16W5%10K
2
1R2429
402
10K5%1/16WMF
2
1R2431
MF1/16W5%10K
402 2
1R2433
402
10K5%1/16WMF
2
1R2436
MF1/16W
402
10K5%
2
1R244210K
MF1/16W5%
4022
1R2443
MF1/16W5%10K
4022
1R2444
402
10K5%1/16WMF
2
1R2405NOSTUFF
5%1/16WMF402
4.7K
21
R2406
402MF
1/16W5%
0
21
R2407NOSTUFF
0
5%1/16WMF402
21
R2408
402MF
1/16W5%
0
P4
R4
J18J17
C21
C20
E21
B21
D21D20
E20
D15
Y9
E9
A21
AB28
AC28
AH3
AC2
R25
F20M26
AA25V25
AD3AD5
B20
A20
U3V1.0-300MM
U3LITE
OMIT
PBGA
2
1R2402
402
1211%1/16WMF
2
1R2401
MF1/16W1%121
402
21
R2409NOSTUFF
0
5%1/16WMF402
2
1 C2401
CERM
NOSTUFF
1000PF5%25V
603
051-65321032403
NB_RST_L
PP1V2_HT
SYS_COLD_RESET_L
NB_RESETNB_PU_RST_L
NB_MC_PDNB_TEST_PD
JTAG_NB_TCKJTAG_NB_TDI
JTAG_NB_TRST_LJTAG_NB_TMS
NB_RI_PU
VSP_NB_CLK_PVSP_NB_CLK_N
I2C_NB_B_SCL
JTAG_NB_TDO
TP_NB_PM_SLEEP0
NB_RE_PD
PMU_SUSPEND_REQ
SMU_SUSPENDREQ_L
NB_SUSPEND_REQ_L
VOLTAGE=0.6VNB_VSP_CLK_VREF
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MIL
NB_SUSPEND_ACK_L
I2C_NB_A_SDA
I2C_NB_B_SDA
I2C_NB_A_SCL
NB_SUSPEND_REQ_L
NB_PU_RST_LNB_RST_L
I2C_NB_C_SDAI2C_NB_C_SCL
TP_DUMMY_ATP_DUMMY_B
NB_INT_L
NB_PMR_OBSV
NB_THMINB_THMO
NB_PU_RESETNB_SUSPENDACK_L
NB_SUSPEND_ACK
NB_SUSPEND_ACK_L
SMU_WARM_RESET_L
SMU_RESET SYS_COLD_RESET_L10 MIL SPACING10 MIL SPACINGSMU_RESET SYS_WARM_RESET_L 48
51
51
45
43
22
23
13
22
23
22
5
13
22
6
6
6
6
25
25
18
6
13
22
22
18
18
18
22
22
22
18
18
23
5
5
5
13
22
5
13
5 Preliminary
www.vinafix.vn
GNDPLL_49
GNDXTAL_18 PLL_45
GND
VIOPME
PLL_49VDD
PLL_45VDD
XGI
XTALS
TEST
PWR_MGT
PCI
GPIO
I2C
I2S2
I2S1
I2S0
(2 OF 8)
PCI1C_BE_4_L
PCI1C_BE_5_LPCI1C_BE_6_L
PCI1C_BE_7_L
PCI1PAR64_H
XGI_DTI_H
XGI_DTO1_H
XGI_CLK_H
XGI_DTO0_H
PCI1ACK64_LPCI1REQ64_L
PCI1AD_60_H
PCI1AD_63_H
PCI1AD_62_HPCI1AD_61_H
PCI1AD_50_H
PCI1AD_52_H
PCI1AD_53_H
PCI1AD_51_H
PCI1AD_59_HPCI1AD_58_H
PCI1AD_57_H
PCI1AD_56_HPCI1AD_55_H
PCI1AD_54_H
PCI1AD_40_H
PCI1AD_41_H
PCI1AD_42_HPCI1AD_43_H
PCI1AD_44_H
PCI1AD_49_H
PCI1AD_48_HPCI1AD_47_H
PCI1AD_46_H
PCI1AD_45_H
PCI1AD_39_H
PCI1REQ_5_L
PCI1AD_32_H
PCI1AD_34_H
PCI1AD_38_H
PCI1AD_37_HPCI1AD_36_H
PCI1AD_33_H
PCI1AD_35_H
PCI1GNT_5_L
PCI1GNT_4_L
PCI1REQ_4_L
PCI1GNT_3_L
PCI1REQ_3_L
XTAL_18XTALVDD VDD
FSTEST
XTAL_18_I
XTAL_18_O
XTALI
XTALO
PLLTESTTEST_MODE_H
TDI
TCK
TMS
TDO
INTRWD_H
I2CDATA_H
I2CCLK_H
PCI_SEL32BIT_HGPIO_H_3
GPIO_H_2
GPIO_H_1I2S2SYNC_H
I2S2BITCLK_H
I2S2MCLK_HI2S2DTO_H
I2S2DTI_H
GPIO_H_0
I2S1DTO_HI2S1MCLK_H
I2S1BITCLK_HI2S1SYNC_H
I2S1DTI_H
I2S0BITCLK_H
I2S0SYNC_H
I2S0DTI_H
I2S0DTO_H
I2S0MCLK_H
RESET_L
STOPXTALS_LSUSPENDREQ_L
SUSPENDACK_L
PCI1PME_L
TRST_L
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE: It is the responsibility of
AUDIO GPIOS
necessary pull-ups & pull-downs.
the audio circuit to provide the
<- To CPU
-> From NorthBridge
NorthBridge / SouthBridge MPIC Routing
From SouthBridge <-
To SouthBridge ->
interrupt controller. SouthBridge MPIC will be used for Selects whether NorthBridge or- MPIC_NB/MPIC_SB
Configures Shasta for 64-bit PCI- PCI_64BIT
AUDIO GPIO - see note on right
Shasta Serial / Misc
- _PP3V3_PWRON_SB
- _PP1V2_PWRON_SB
Signal aliases required by this page:
35
32
21
DO NOT swap between RPAKs
"Slot F" - AD22
"Slot E" - AD21 6
NOTE: XGC required for Shasta GPIOs
(NONE)
- _PP2V5_PWRON_SB
- _PP3V3_PCI
29
(I2S2_RESET_L)
4849
5251
50
5453
4039
4647
4544
41
43
383736
34
28
30
33
31
(SCCB)
(SCCA)
2524
20
1819
27
2322
12
9
16151413
17
8
11
7
10
(I2S0_DEV_TO_SB_DTI)
26
Power aliases required by this page:
BOM options provided by this page:
NC
GPIO
Page Notes
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
I2S1: Soft Modem
I2S0: Audio DAC
Master: Link
REDUNDANT - NEED TO ADDRESS THIS
REDUNDANT - NEED TO ADDRESS THIS
(I2S2_DEV_TO_SB_DTI)
1 = 32-bit PCI & GPIOs
Re-pin within each RPAK as necessary
(I2S1_RESET_L)
(I2S1_DEV_TO_SB_DTI)
0 = 64-bit PCI & XGC
PCI 32-bit select
I2S2: S/P-DIF
42
2
1 C250010uF20%6.3V
1206CERM 2
1 C2501
402CERM
1uF10%6.3V
2
1 C2511
402
10%
CERM
1uF6.3V2
1 C251020%6.3VCERM1206
10uF
2
1C252020%
6.3VCERM1206
10uF2
1C2521
402
10%
CERM
1uF6.3V
2
1C253010uF
CERM1206
20%6.3V2
1C2531
CERM402
10%1uF6.3V
2
1R2500
402MF
1/16W5%
10K
2
1R25011/16W
MF402
PCI_64BIT
5%1K
21
Y2590
8X4.5MM-SM
18.432M
CRITICAL 2
1R25901%1/16WMF402
200
2
1 C2591
402CERM50V5%22pF
2
1C259022pF
402CERM50V5%
2
1R2580
MF402
5%1/16W
4.7K
Y13
V13W13
AB12
W14
V15
U15
T9
U7
W2
Y4
W17
W12
Y11
A3
W11
AA11
AB11
U11
V11
W10E9
Y12
AA12
AA13
AB13
U14
W6
U16
AB21
U17
K17
W18
E18
Y20
AA20
AA19
K20
K22
H22J20
H21
G22
F22J19
H20G21
F21
J17H19
K18
D22G20
D21
C22G19
F20C21
E20
D20F19
E19
G18G17
C20
B21A21
F16G16
F17
F18A20
D18
L17
V12
W9
Y7Y8
AA5
AB4
AA7
V9
AB5V10
AA8
Y6
U8
Y5
W7
AA4
AB7
Y9
W8
AB3
Y2
V5
V14
U2300V1.0BGA
SHASTAOMIT
2
1 C25400.1uF
402CERM10V20%
63
RP2551
SM1
10K
5%1/16W
81
RP2550
SM1
5%1/16W
10K
54
RP2550
1/16WSM1
5%
10K
72
RP2550
SM1
10K
5%1/16W
81
RP2551
SM11/16W
10K
5%
72
RP2551
SM11/16W5%
10K
54
RP2551
SM1
10K
1/16W5%
81
RP255210K
SM1
5%1/16W
63
RP2550
SM11/16W5%
10K
72
RP2552
5%1/16WSM1
10K
54
RP2552
SM11/16W5%
10K
63
RP2552
5%
SM1
10K
1/16W
72
RP2553
SM1
5%1/16W
10K
54
RP255310K
5%
SM11/16W
81
RP2553
5%1/16WSM1
10K
63
RP2553
SM1
10K
5%1/16W
21
R255010K
MF1/16W5%
40221
R255110K
MF1/16W5%
40221
R2552
402
1/16W5%
10K
MF
21
R2553
5%1/16WMF
10K
40221
R2556
5%1/16WMF
10K
40221
R2557
5%1/16WMF
10K
40221
R255810K
MF1/16W5%
40221
R255910K
MF1/16W5%
402
21
R256410K
402MF
1/16W5%
21
R256310K
402MF
1/16W5%
21
R2560
402MF
1/16W5%
1K
21
R2561
5%
MF402
10K
1/16W
21
R256610K
402
5%
MF1/16W
21
R2565NO STUFF
5%1/16WMF402
10K
21
R2567
5%1/16WMF402
10K
21
R2568
5%
MF402
10K
1/16W
21
R2562NO STUFF
402MF
1/16W5%
1K
21
R255510K
MF1/16W5%
NO STUFF
402
21
R25541K
5%1/16WMF402
PP3V3_RUN
2
1R2576
402
1/16W5%10K
MF
2
3
1 Q2576SM2N3904
MPIC_SB21
R2575
5%1/16WMF402
10K
MPIC_SB
2
1R2579MPIC_NB
5%1/16W
MF402
0
21
R2578
5%1/16WMF402
0
MPIC_SB
7
8
6
5
2
1
3
4RP2510
5%33
SM11/16W
8
7
6
5
1
2
3
4RP2530
SM1
335%
1/16W
6
5
8
7
3
4
1
2RP2520
1/16W5%33
SM1
21
R25053.3
805FF
1/10W5%
21
R2510
5%1/10WFF805
3.3
21
R25203.3
805FF
1/10W5%
21
R2530
5%1/10WFF805
3.3
TITLE=FIZZYABBREV=DRAWING 25 103
03051-6532
I2S1_RESET_L
_PP3V3_PWRON_SB
I2S2_SYNC
SB_CLK18M_XTALI
TP_SB_FSTEST
SB_PCI_SEL32BIT
JTAG_SB_TRST_L
I2S2_BIDIR I2S2_SYNC
I2S1_BITCLKI2S1_BIDIR
I2S0_BITCLK
JTAG_SB_TMS
I2S2_MCLK
SB_GPIO52
SB_GPIO50
SMU_TO_SB_INT_L
SB_GPIO51
SB_GPIO47
SB_GPIO45
SB_GPIO49
SB_GPIO46
SB_GPIO25
SB_GPIO23
SB_GPIO30
SB_GPIO24
SB_GPIO12
PCI_SLOTC_INT_L
PCI_SLOTF_INT_L
PCI_SLOTB_INT_L
ENET_ENERGYDET
ENETFW_RESET
FW_LOWPWR
SB_SATABR_RESET_L
SYS_SLEWING_L
MODEM_RING2SYS_L
UDASH_RESET_L
SB_TO_SMU_INT_L
SYS_OVERTEMP_L
CPU_SRESET_L
_PP3V3_PWRON_SB
I2S0_BIDIR I2S0_BITCLK
I2S1_TO_DEV I2S1_SB_TO_DEV_DTO
SB_TEST_MODE_PD
15 MIL SPACING SB_CLK18M_XTALO
_PP3V3_PWRON_SB
I2S1_RESET_L
I2S1_DEV_TO_SB_DTI
I2S2_RESET_L
I2S0_DEV_TO_SB_DTI
I2S0_SYNC
I2S0_MCLKI2S0_SB_TO_DEV_DTO
I2S1_SYNCI2S1_BITCLKI2S1_MCLKI2S1_SB_TO_DEV_DTO
I2S2_SB_TO_DEV_DTO
I2S2_SYNC_RI2S2_BITCLK_R
I2S2_SB_TO_DEV_DTO_R
I2S1_SYNC_RI2S1_BITCLK_RI2S1_MCLK_RI2S1_SB_TO_DEV_DTO_R
I2S0_SYNC_RI2S0_BITCLK_RI2S0_MCLK_RI2S0_SB_TO_DEV_DTO_R
I2S2_SB_TO_DEV_DTOI2S2_TO_DEV
I2S1_TO_SB I2S1_DEV_TO_SB_DTI
I2S1_SYNCI2S1_BIDIR
SB_CLK18M_XTALISB_CLK18M_XTAL 15 MIL SPACING
I2S2_TO_SB I2S2_DEV_TO_SB_DTI
I2S0_BIDIR I2S0_SYNC
I2S2_BITCLKI2S2_BIDIR
I2S0_SB_TO_DEV_DTOI2S0_TO_DEV
I2S2_MCLKI2S2_TO_DEV 10 MIL SPACING
15 MIL SPACING SB_CLK18M_XTALO_R
SYS_PME_L
I2C_SB_SCL
SB_SUSPENDACK_LSMU_SUSPENDREQ_LSB_STOPXTALS_L
SB_INT_LMODEM_RING2SYS_L
I2C_SB_SDA
TP_SB_WATCHDOG
JTAG_SB_TCK
JTAG_SB_TDI
TP_SB_PLLTEST
SB_CLK25M_ATA
_PP3V3_PWRON_SB
_PP3V3_PCI
PCI_SLOTE_REQ_L
PCI_SLOTF_REQ_L
PCI_SLOTE_GNT_L
PCI_SLOTF_GNT_L
PCI_SLOTA_INT_L
PCI_SLOTE_INT_L
PCI_SLOTD_INT_L
PCI_SLOTG_INT_L
JTAG_SB_TDO
SYS_WARM_RESET_L
SB_CLK18M_XTALO_R
I2S2_BITCLK
SB_CLK18M_XTALO
15 MIL SPACING SB_CLK25M_ATASB_CLK25M_ATA
I2S2_DEV_TO_SB_DTI
I2S2_MCLK_R
MIN_NECK_WIDTH=15 milMIN_LINE_WIDTH=20 milVOLTAGE=2.5V
PP2V5_PWRON_SB_XTAL18VDD
MIN_NECK_WIDTH=15 milVOLTAGE=2.5V
PP2V5_PWRON_SB_XTALVDD
MIN_LINE_WIDTH=20 mil
_PP2V5_PWRON_SB
MIN_NECK_WIDTH=15 milMIN_LINE_WIDTH=20 milVOLTAGE=1.2V
PP1V2_PWRON_SB_PLL49VDD
MIN_NECK_WIDTH=15 milMIN_LINE_WIDTH=20 milVOLTAGE=1.2V
PP1V2_PWRON_SB_PLL45VDD_PP1V2_PWRON_SB
NB_TO_SB_INT
NB_INT_L
CPU_INT_L
NB_INT_L_R
SB_INT_L
I2S0_TO_DEV I2S0_MCLK10 MIL SPACING
I2S0_DEV_TO_SB_DTII2S0_TO_SB
I2S1_MCLKI2S1_TO_DEV 10 MIL SPACING
SB_GPIO47
SYS_SLEWING_L
SB_GPIO50SB_GPIO49
SB_GPIO51SB_GPIO52NB_TO_SB_INTSMU_TO_SB_INT_L
AUDIO_SPKR_DET_LAUDIO_LO_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_GPIO_12
AUDIO_LO_OPTICAL_PLUG_LAUDIO_LO_DET_L
AUDIO_LI_DET_LAUDIO_LI_OPTICAL_PLUG_LAUDIO_HP_DET_L
AUDIO_HP_MUTE_L
AUDIO_EXT_MCLK_SELAUDIO_GPIO_11
PCI_SLOTG_INT_LFW_LOWPWRENETFW_RESETSB_GPIO30
SB_GPIO45SB_GPIO46
ENET_ENERGYDET
I2S0_RESET_L
SYS_OVERTEMP_L
PCI_SLOTF_REQ_L
CPU_SRESET_L
PCI_SLOTF_GNT_L
UDASH_SDOWNUDASH_RESET_LAGP_INT_LPCI_SLOTA_INT_LPCI_SLOTB_INT_LPCI_SLOTC_INT_LPCI_SLOTD_INT_LPCI_SLOTE_INT_LPCI_SLOTF_INT_LSB_GPIO23SB_GPIO24SB_GPIO25SB_SATABR_RESET_L
SB_TO_SMU_INT_L
SB_GPIO12
PCI_SLOTE_GNT_LPCI_SLOTE_REQ_L
LAST_MODIFIED=Mon Feb 23 19:04:13 2004
25
49
25
45
23
45
45
45
48
23
60
23
60
31
17
23
60
23
60
60
60
60
60
60
60
60
23
47
48
56
60
31
17
23
21
23
25
60
15
28
21
23
21
23
23
23
23
23
23
23
23
60
21
46
47
45
45
23
25
15
28
47
16
18
61
18
61
16
61
18
23
54
23
57
51
23
23
23
13
27
18
61
16
18
16
16
61
61
61
61
16
16
16
16
16
16
61
61
61
61
48
18
22
23
18
18
18
25
18
45
49
49
23
49
48
22
61
25
61
21
28
61
61
16
23
23
61
61
61
61
61
61
61
61
48
57
23
54
13
27
60
23
49
51
23
49
49
6
5
23
23
6
23
6
23
6
23
23
23
13
23
23
23
23
23
23
23
23
23
23
23
23
23
23
12
23
23
13
6
23
13
6
23
5
23
6
23
5
6
6
61
23
23
23
23
6
6
6
6
23
23
6
6
23
23
23
23
23
23
23
13
6
13
13
13
23
6
6
6
6
23
5
5
23
23
23
23
6
23
23
23
6
5
23
23
23
23
23
5
5
23
22
27 23
23
23
6
23
13
23
23
23
23
23
13
61
6
6
61
6
6
6
6
61
61
6
6
23
23
12
23
23
23
23
61
6
23
23
23
6
23
37
6
23
23
23
23
23
23
23
23
23
13
23
23
23
Preliminary
www.vinafix.vn
SYM 2 OF 2
VDD33
VDD25
VDD25
VDD_PLL3VDD_PLL2
VDD_PLL1
C4_VDDC3_VDD
C2_VDD
VDD_PLL4
VDD_I2CVDD_NBSYNC
VDD_PCLK
VDD33_BC
VDD33_BC1
VDD_HCLK0
VDD_HSYNC
VDD_HCLK2
VDD_HCLK0
VDD_HCLK1
VDD_HCLK2
VDD_HSYNC
VDD15_HSYNC
VDD15_PCLK
VDD_XTALVDD_VCLK
VSS_XTALVSS_VCLK
VSS_HSYNC
VSS_HCLK2
VSS_HCLK0VSS_HCLK1
VSS_HCLK2
VSS_HSYNC
VSS_HCLK0
VSS33_BC1
VSS33_BCVSS33
VSS_PCLK
VSS_NBSYNC
VSS25
VSS25
VSS_I2C
VSS_CML
VSS_PLL4
VSS_PLL3VSS_PLL2
C2_VSS
C3_VSSC4_VSS
VSS_PLL1
C1_VSSC1_VDD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
MASTER: GILA
IF 603 CAN BE PLACED CLOSE TO PULSAR
402 CAPS NOT NEEDED
PLACE NEAR PIN L8 K8
PLACE NEAR PIN M3 M2
PLACE NEAR PIN D2 D1
PULSAR POWER
CAN BE TURNED OFF IN SLEEP
PINS G12, M12, H3, K1, L5, M9, A11, A9A8, C5, B4, K10, H12 J11, M11, A1
PLACE NEAR PIN D10 D12
21
R26014.7
MF1/16W5%
402
PP3V3_RUN
PP3V3_PWRON
2
1 C2601
CERM20%10V402
0.1UF
21
R2603
402
4.75%
1/16WMF
21
R2605
402
4.75%
1/16WMF
2
1 C26050.1UF
40210V20%CERM
21
L2601
0603
180-OHM-1.5A
2
1 C2609
CERM40210V0.1UF20%
2
1 C2611
40210V20%CERM
0.1UF
21
L2603
0603
180-OHM-1.5A
2
1 C26130.1UFCERM20%10V402
21
L2605
0603
180-OHM-1.5A
2
1 C26150.1UFCERM20%10V402
21
L2607
0603
180-OHM-1.5A
2
1 C2617
402CERM20%10V0.1UF
2
1 C26190.1UFCERM20%10V402
2
1 C26220.1UF
40210V20%CERM
21
R2607
MF1/16W5%
4.7
402
21
L2609180-OHM-1.5A
0603
2
1 C262010V20%CERM
0.1UF
402
2
1 C2627
CERM20%10V402
0.1UF2
1 C26280.1UF
40210V20%CERM 2
1 C2629
CERM20%10V402
0.1UF2
1 C2630
CERM20%10V402
0.1UF
2
1 C2651
CERM20%10V402
0.1UF
2
1 C26230.1UF
40210V20%CERM 2
1 C26240.1UF
40210V20%CERM 2
1 C26250.1UF
40210V20%CERM 2
1 C26260.1UF
40210V20%CERM
2
1 C26310.1UF
40210V20%CERM 2
1 C26320.1UF
40210V20%CERM 2
1 C26330.1UF
40210V20%CERM 2
1 C26340.1UF
40210V20%CERM 2
1 C26350.1UF
40210V20%CERM 2
1 C26360.1UF
40210V20%CERM 2
1 C26370.1UF
40210V20%CERM 2
1 C26380.1UF
40210V20%CERM
2
1 C266510V402
20%0.1UFCERM 2
1 C2667
CERM20%10V402
0.1UF2
1 C2671
CERM20%10V402
0.1UF
2
1 C2640
402
0.1UF10V20%CERM2
1 C2639
402CERM
0.1UF20%10V
21
R2609
402
4.75%
1/16WMF
2
1 C2645
603
20%
CERM16.3V
2.2UF
2
1 C2669
603
20%2.2UF6.3VCERM1
2
1 C2603
603
20%
CERM16.3V
2.2UF
2
1 C2607
603
20%2.2UF6.3VCERM1
2
1 C2621
603
20%
CERM16.3V
2.2UF
C12A3
M2
K8D1
D12
L12
F11
C2
K12
H10
A7A4
B7
B11C10
A6
M5
L7E2
H2L2
A12A1
M3
L8D2
D10
M12
G12
B2
H12
K10
B4C5
A8
A9A11
M9
L5E1
K1H3
M11
J11
C9B9
E10E12M4L3
G1F1
U2600PULSAR
OMIT
FSBGA
PP3V3_PWRON
PP3V3_PWRON
PP3V3_PWRON
PP3V3_RUN
1032603051-6532
PULSAR, PBGA U26001359S0076
PPVCORE_PWRON_PULSAR
MIN_NECK_WIDTH=10MIL
PP3V3_PSL_XTAL
MIN_LINE_WIDTH=25MILVOLTAGE=3.3V
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL1VOLTAGE=1.5VMIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL3VOLTAGE=1.5VMIN_LINE_WIDTH=25MIL
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
PP1V2_PULSAR
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL2VOLTAGE=1.5VMIN_LINE_WIDTH=25MIL
PPVCORE_PULSAR
PP1V2_PULSAR
PPVCORE_PWRON_PULSAR
PPVCORE_PWRON_PULSAR
PPVCORE_PULSAR
PPVCORE_PULSAR
PP1V2_PULSAR
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL4VOLTAGE=1.5VMIN_LINE_WIDTH=25MIL
33
33
24
24
24
24
24
24
24
24
24
24
24
5
5
5
5
5
5
5
5
5
5
5
Preliminary
www.vinafix.vn
REFCLK_1
SYM 1 OF 2
SCLK
SDATA
RESET*
XIN
XOUT
REF25REF15
TEST3TEST2
TEST1
ADDRSEL
REF33
REF_CML
PRES_CML
FORCESPO*
PD
VCLKNVCLKP
HCLKN_0
HCLKN_1HCLKN_2
GPCLK33_1
GPCLK33_0
HCLKP_0
HCLKP_2HCLKP_1
PCLK33_1PCLK33_0
PCLK25_1
PCLK25_0
GPCLK25_0
GPCLK25_1
PCLK33_2PCLK33_3
PCLK33_4
HTBEN_0
HTBEN_1
NBSYNC
HSYNC_0HSYNC_1
REFCLK_0
ERROR*SLEWING*
PCLK12
PCLK15
SCAN_MODE
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.2V
MASTER: GILA
ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE DIFFERENTIAL_PAIR
33MHZ
33MHZ
1=IIC ADDR D4/D5
PULSAR CLOCKS
66MHZ
66MHZ33MHZ66MHZ
66MHZ66MHZ
3.3V
1.2V
1.2V
1.2V1.5V 66MHZ
66MHZ
NET
TYPESPACING
(SLEEP)
66MHZ
NET_SPACING_TYPE
3.3V
3.3V
2.5V
2.5V2.5V
25MHZ25MHZ
EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY
DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHERALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP
3.3V3.3V
2.5V
2.5V2.5V
3.3V 33MHZ
0=IIC ADDR D2/D3
33MHZ
21
R27015%0
I100
I101
I102
I103
21
R2704
4025%
0
21R2706 1%402249
B12
C11
B3
A2
D11E11
K3
K9
B1
C1
M1
D3
H1
G2
A5
M6
J2
G11
B6
C3
M10
L9M7
L6
K5
L1K2
L10
L11
F12
J12K11
H11
J10
B5B8
A10
C4C8
B10
K4L4
J1
J3
F2
M8
E3
U2600PULSAR
OMIT
FSBGA
1
2
3
J2700F-ST-SM
NOSTUFF
U.FL-R_SMT
21
Y270125.0000M
8X4.5MM-SM
CRITICAL
2
1R2722
MF1/16W5%1K
402
21
R2748
MF1/16W5%
0
NOSTUFF
402
I116
I117
I118
I119
21R2703
5% 402
20
21R2705
5%
0
402
21R2707
5% 402
0
21R2709
5% 402
20
21R2711
5%
0
402
21R27150
4025%
21R2717
5% 402
0
21R2719
5%
0
402
21R2720
402
0
5%
21R2724 1K 402 5%NOSTUFF
21
R2738NOSTUFF
1K
5% 402
21R2740 1K 1%402
21R2742 402806 1%
21R2744 1%402681
21R2746 1%1K 402
21R2750 0 5%402
21
R2752NO STUFF
402MF5%
0
1/16W21
R2754
MF1/16W
05%
402
21
R2756
MF1/16W5%
0
402
21
R2758
MF1/16W5%
330KNO STUFF
402
21
R2761
402
0
5%
2
1R276224MF5%
402
NOSTUFF
1/16W
2
1R27645%241/16W402MF
NOSTUFF
2
1 C2705
402
33PFCERM50V5%
2
1C2707
402
33PF5%50V
CERM
21R2768
5% 402
0
21R2770
4025%
20
21R2772
5% 402
0
21
C27080.001UF
50V CERM
40210%
21
C2710
10% 402
CERM50V0.001UF
21
C2713
10% 402
CERM50V0.001UF
21
C27150.001UF
50V CERM
40210%
21
C2700
10% 402
CERM50V0.001UF
21
C2702
40210%
CERM50V0.001UF
21R27750
5% 402 21R2776
5%
0
402
21R2702
5%
0
402 21R2779
402
0
5%
21R2700
5%
22
402
NOSTUFF
I86
I87
I90
I91
I94
I95
I96
I97
I98
I99
10327
03051-6532
EI_CPU_CLK_N CLOCKS EI_CPU_CLKEI_CPU_CLK
EI_CPU_CLK_NEI_CPU_CLK_P
EI_CPU_CLK_P CLOCKS EI_CPU_CLKEI_CPU_CLK
EI_CPU_SYNC
EI_CPU_SYNC EI_SYNC CLOCKS
EI_CPU_CLK_N_C CLOCKS
EI_CPU_CLK_P_C CLOCKS
SYS_SLEEP
CLOCKSEI_NB_SYNC_R
SB_CLK25M_ATA
PCI_CLK66M_SB_INT_R CLOCKS
PCI_CLK_P3_R CLOCKS
SB_CLK25M_ATA_R CLOCKS
HT_CLK66M_SB
AGP_CLK66M_GPU_R CLOCKSCLOCKSPCI_CLK_P1_R
PLS_X_OUT_BPLS_X_IN_B
PLS_FORCE_P0_L_R
PLS_X_IN
EI_NB_SYNC CLOCKS
HT_SB_CLKHT_CLK66M_SB CLOCKSHT_NB_CLKHT_CLK66M_NB CLOCKS
AGP_CLK66M_GPU
TP_PLS_CLK_66M_0
EI_NB_CLK_N
PCI_CLK_P3
PCI_CLK_P1
TP_PLS_CLK_66M_1CLOCKSPLS_CLK_66M_1_R
EI_NB_CLK_P
PLS_XTAL CLOCKSPLS_EXTCLK
PCI_CLK33M_SB_EXT CLOCKSCLOCKS_PCICLOCKS_PCI CLOCKSPCI_CLK66M_SB_INT
EI_NB_CLK_N EI_NB_CLK CLOCKS EI_NB_CLK
VSP_NB_CLKVSP_NB_CLKVSP_NB_CLK_N CLOCKS
TP_SATA_CLK25M
RAM_CLK66M_NBCLOCKSHT_CLK66M_NB_R
PCI_CLK66M_SB_INT
CPU_HTBEN
CLOCKSPCI_CLK_GP0_R
CLOCKSEI_CPU1_CLK_P_R
CLOCKSEI_CPU1_CLK_N_R
CLOCKSPCI_CLK_GP1_R
CLOCKSEI_CPU1_SYNC_R
HT_CLK66M_NB
CPU1_HTBEN_R CLOCKS
PLS_POWER_DOWN
VSP_NB_CLK_N
PCI_CLK_GP1
EI_NB_SYNC
PLS_RESET_L
I2C_CLOCK_SDA
PLS_X_ADDRSEL
I2C_CLOCK_SCL
SYS_SLEWING_L
CLOCKSAGP_CLK66M_NB_R
PLS_PRES_CML
PLS_REF33PLS_REF25PLS_REF15
PLS_SCAN_MODE
CLOCKSSLEWING_L_R
CLOCKSSATA_CLK25M_R
CLOCK_ERROR_L
TP_PLS_REF_CML
TP_PLS_TEST1TP_PLS_TEST2TP_PLS_TEST3
AGP_CLK66M_NB
PLS_INTERM
CLOCK_RESET_L
PP3V3_PWRON
VSP_NB_CLK_P
PCI_CLK_GP0
VSP_NB_CLK_N_C CLOCKS
AGP_NB_CLKAGP_CLK66M_NB CLOCKS
EI_NB_CLK_P EI_NB_CLK CLOCKS EI_NB_CLK
VSP_NB_CLK VSP_NB_CLKCLOCKSVSP_NB_CLK_P
AGP_CLK66M_GPU AGP_GPU_CLK CLOCKS
CLOCKSEI_CPU_SYNC_R
CLOCKSCPU_HTBEN_R
PCI_CLK_P4_R CLOCKS
CLOCKSRAM_CLK66M_NB_R
EI_NB_CLK_P_C CLOCKS
CLOCKSHT_CLK66M_SB_R
PCI_CLK_P4
CLOCKSVSP_NB_CLK_P_C
CLOCKSPLS_CLK_66M_0_R
EI_NB_CLK_N_C CLOCKS
PLS_X_OUT
SYS_OVERTEMP_L
PLS_EXTCLK
CLOCKSEI_CPU1_SYNC EI_CPU1_SYNC
CLOCKSEI_CPU1_CLK_P EI_CPU1_CLK EI_CPU1_CLKCLOCKSEI_CPU1_CLK_N EI_CPU1_CLK EI_CPU1_CLK
23 17
11
31
15
27
27
27
27
27
27
10
44
26
44
43
37
26
26
45
45
26
25
45
28
43
25
26
23
36
17
25
36
26
25
37
13
25
25
25
25
25
25
5
23
25
25
25
25
25
25
5
5
25
25
5
25
25
22
33
25
27
5
5
5
25
5
22
5
25
18
18
13
25
13
6
22
5
25
25
22
25
5
6
25 Preliminary
www.vinafix.vn
API_APCLKPAPI_APCLKN
API0_SRIP1
API0_SRIN0
API0_SROP1
API0_SRON0
API0_BCLKINAPI0_BCLKIP
INTERFACEAPPLE PI
API_APCLK_AVSS
(SYM 1 OF 7)
API0_ADO35API0_ADO36
API0_ADO37
API0_ADO38API0_ADO39
API0_ADO40
API0_ADO41
API0_ADO43
API0_ADO42
API0_SROP0
API0_SRON1
API_QREQ0
API_CSTP
API0_ADO34
API0_ADO0
API0_ADO1
API0_ADO2API0_ADO3
API0_ADO4
API0_ADO5
API0_ADO8
API0_ADO7
API0_ADO6
API0_ADO10
API0_ADO9
API0_ADO12
API0_ADO11
API0_ADO13
API0_BCLKONAPI0_BCLKOP
API0_ADO14
API0_ADO15
API0_ADO18
API0_ADO17API0_ADO16
API0_ADO19API0_ADO20
API0_ADO21API0_ADO22
API0_ADO23
API0_ADO24API0_ADO25
API0_ADO26
API0_ADO28API0_ADO27
API0_ADO29
API0_ADO30API0_ADO31
API0_ADO33API0_ADO32
VDD_APIAPCLK_AVDD
API
API0_ADI3API0_ADI2
API0_ADI1
API0_ADI0
API0_ADI5
API0_ADI4
API0_ADI13
API0_ADI12
API0_ADI11API0_ADI10
API0_ADI9API0_ADI8
API0_ADI7
API0_ADI6
API0_ADI15
API0_ADI14
API0_ADI17
API0_ADI18
API0_ADI19API0_ADI20
API0_ADI21API0_ADI22
API0_ADI23
API0_ADI16
API0_ADI24
API0_ADI33API0_ADI32
API0_ADI31
API0_ADI25
API0_ADI26
API0_ADI30
API0_ADI29
API0_ADI28API0_ADI27
API0_ADI34
API0_SEAPI0_APSYNC
API0_ADI42
API0_ADI43
API0_ADI37
API0_ADI38API0_ADI39
API0_ADI40
API0_ADI41
API0_SRIP0
API0_SRIN1
API_QACK0
API0_ADI36API0_ADI35
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
U3LITE APPLE PI
NEAR U3LITEPLACE R2805 AND R2806
DIFFERENTIAL_PAIRNET_SPACING_TYPEELECTRICAL_CONSTRAINT_SET
EI_NB_CLK_N
EI_NB_CLK_P
C2820, R2803, R2804 CHANGED TO 603 FOR FMAX
MASTER: GILA
1
ZT2800OMIT
HOLE-VIA-20R10
1
ZT2801OMIT
HOLE-VIA-20R10
1
ZT2802OMIT
HOLE-VIA-20R10
1
ZT2803OMIT
HOLE-VIA-20R10
1
ZT2804OMIT
HOLE-VIA-20R10
2
1 C2813
CERM10V20%0.1UF
402
1
ZT2805OMIT
HOLE-VIA-20R10
1
ZT2806OMIT
HOLE-VIA-20R10
1
ZT2807OMIT
HOLE-VIA-20R10
1
ZT2808OMIT
HOLE-VIA-20R10
1
ZT2809HOLE-VIA-20R10
OMIT
2
1 C2812
402
0.1UF20%10VCERM
1
ZT2810OMIT
HOLE-VIA-20R10
1
ZT2811OMIT
HOLE-VIA-20R10
1
ZT2812OMIT
HOLE-VIA-20R10
1
ZT2813OMIT
HOLE-VIA-20R10
1
ZT2814OMIT
HOLE-VIA-20R10
2
1 C2811
CERM10V20%0.1UF
402
1
ZT2815OMIT
HOLE-VIA-20R10
1
ZT2816OMIT
HOLE-VIA-20R10
1
ZT2817OMIT
HOLE-VIA-20R10
1
ZT2818OMIT
HOLE-VIA-20R10
1
ZT2819OMIT
HOLE-VIA-20R10
2
1 C2810
402
0.1UF20%10VCERM
1
ZT2820OMIT
HOLE-VIA-20R10
1
ZT2821OMIT
HOLE-VIA-20R10
1
ZT2822OMIT
HOLE-VIA-20R10
1
ZT2823OMIT
HOLE-VIA-20R10
1
ZT2824OMIT
HOLE-VIA-20R10
2
1 C2809
CERM10V20%0.1UF
402
1
ZT2825OMIT
HOLE-VIA-20R10
1
ZT2826OMIT
HOLE-VIA-20R10
1
ZT2827OMIT
HOLE-VIA-20R10
1
ZT2828OMIT
HOLE-VIA-20R10
1
ZT2829HOLE-VIA-20R10
OMIT
2
1 C2808
402
0.1UF20%10VCERM
1
ZT2830OMIT
HOLE-VIA-20R10
1
ZT2831OMIT
HOLE-VIA-20R10
1
ZT2832OMIT
HOLE-VIA-20R10
1
ZT2833OMIT
HOLE-VIA-20R10
1
ZT2834OMIT
HOLE-VIA-20R10
2
1 C2807
CERM10V20%0.1UF
402
1
ZT2835OMIT
HOLE-VIA-20R10
1
ZT2836OMIT
HOLE-VIA-20R10
1
ZT2837OMIT
HOLE-VIA-20R10
1
ZT2838OMIT
HOLE-VIA-20R10
1
ZT2839OMIT
HOLE-VIA-20R10
2
1 C2806
402
0.1UF20%10VCERM
1
ZT2840OMIT
HOLE-VIA-20R10
1
ZT2841OMIT
HOLE-VIA-20R10
1
ZT2842OMIT
HOLE-VIA-20R10
1
ZT2843OMIT
HOLE-VIA-20R10
1
ZT2844OMIT
HOLE-VIA-20R10
2
1 C2805
CERM10V20%0.1UF
402
1
ZT2845OMIT
HOLE-VIA-20R10
21
R2805
402
0
21
R2806NOSTUFF
402
0
2
1 C2804
402
0.1UF20%10VCERM
D13
D4
F10
F7G2
H16
H13
J13
B19
B10
B7
D16
K8K4
E14D14
F14
G20
F21
D18
C18
B5
A3
B6
A4
E17
D17
B18
A19
H17
D6E6
F15E15
E8
H2
G1H4
J4
F2
B8
A7
B3A2
E1
C8
A6C1
B1D1
B2
C6C5
C3
C2
K1
A5
D8
E4D5
E5F6
J8
F3J7
H6
J1
F5E2
F4
E3J6
J5J3
H3
H5F1
H1
J2
C9
D9G14
H14
H12
C17
B17
A18A17
G12
E18
F18H18
G18G17
F17
G15H15
C15
B15
H11
A15
A16
C14B14
A14A13
E12
D12C12
B12
G11
A12A11
B11
C11B9
A8A9
A10
E11D11
F12
F11
U3U3LITE
PBGA
OMIT
V1.0-300MM
2
1R2803
MF
NOSTUFF
1211/16W1%
402 2
1R28041%1211/16WMF
NOSTUFF
402
2
1 C2821
402
0.001UF50VCERM
NOSTUFF
10%
2
1 C2803
CERM10V20%0.1UF
402
I212
I213
I214
I215
I216
I217
I218
I219
2
1 C2802
402
0.1UF20%10VCERM
I220
I221
I222
I223
I224
I225
2
1 C2801
CERM10V20%0.1UF
4022
1 C28000.1UF
CERM402
20%10V 2
1 C2814
402
0.1UF20%10VCERM 2
1 C2815
CERM10V20%0.1UF
4022
1 C2816
CERM10V20%0.1UF
4022
1 C2817
CERM10V20%0.1UF
402
2
1R28011001%1/16WMF402
NOSTUFF
2
1 C2820NOSTUFF
0.1UF20%
CERM10V
402
2
1R2802NOSTUFF
1001%1/16WMF402
2
1 C28190.1UF20%
CERM402
10V2
1 C2818
CERM6.3V10%1UF
402
21
R28002.2
1/16W5%
MF603
1
ZT2846HOLE-VIA-20R10
OMIT
1
ZT2847HOLE-VIA-20R10
OMIT
1
ZT2848HOLE-VIA-20R10
OMIT
1
ZT2849HOLE-VIA-20R10
OMIT
1
ZT2850HOLE-VIA-20R10
OMIT
1
ZT2851HOLE-VIA-20R10
OMIT
1
ZT2852HOLE-VIA-20R10
OMIT
1
ZT2853HOLE-VIA-20R10
OMIT
1
ZT2854HOLE-VIA-20R10
OMIT
1
ZT2855OMIT
HOLE-VIA-20R10
1
ZT2856OMIT
HOLE-VIA-20R10
1
ZT2857OMIT
HOLE-VIA-20R10
1
ZT2858OMIT
HOLE-VIA-20R10
1
ZT2859OMIT
HOLE-VIA-20R10
1
ZT2860OMIT
HOLE-VIA-20R10
1
ZT2861OMIT
HOLE-VIA-20R10
1
ZT2862OMIT
HOLE-VIA-20R10
1
ZT2863OMIT
HOLE-VIA-20R10
1
ZT2864OMIT
HOLE-VIA-20R10
1
ZT2865OMIT
HOLE-VIA-20R10
1
ZT2866HOLE-VIA-20R10
OMIT
1
ZT2867OMIT
HOLE-VIA-20R10
1
ZT2868OMIT
HOLE-VIA-20R10
1
ZT2869OMIT
HOLE-VIA-20R10
051-6532 03
28 103
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR1EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR0EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR1EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR0EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_P<0>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR1EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR0EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR1EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR0EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_P<0>
EI_SYNC_FROM_NB
EI_NB_CLK_P
PP1V2_EI_NB
PP1V5_PWRON_NB_AVDD
EI_NB_CLK_N
PP1V5_PWRON_EI_NB_AVDDVOLTAGE=1.5V
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_ADEI_NB_TO_CPU_AD<0..43>EI_CPU_TO_NB_CAD EI_CPU_TO_NB_ADEI_CPU_TO_NB_AD<0..43>
PP1V2_EI_NB
EI_QACK_L
NB_APSYNC
EI_SE
EI_QREQ_L
CPU_CHKSTOP_L
EI_NB_SYNC
PP1V2_EI_NB
VOLTAGE=0.6VEI_APCLK_VREF
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLKEI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLKEI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_CLK_NEI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLKEI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLKEI_CPU_TO_NB_CLK_N
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_AD<43>EI_NB_TO_CPU_AD<42>EI_NB_TO_CPU_AD<41>EI_NB_TO_CPU_AD<40>EI_NB_TO_CPU_AD<39>EI_NB_TO_CPU_AD<38>EI_NB_TO_CPU_AD<37>EI_NB_TO_CPU_AD<36>EI_NB_TO_CPU_AD<35>EI_NB_TO_CPU_AD<34>EI_NB_TO_CPU_AD<33>EI_NB_TO_CPU_AD<32>EI_NB_TO_CPU_AD<31>EI_NB_TO_CPU_AD<30>EI_NB_TO_CPU_AD<29>EI_NB_TO_CPU_AD<28>EI_NB_TO_CPU_AD<27>EI_NB_TO_CPU_AD<26>EI_NB_TO_CPU_AD<25>EI_NB_TO_CPU_AD<24>EI_NB_TO_CPU_AD<23>EI_NB_TO_CPU_AD<22>EI_NB_TO_CPU_AD<21>EI_NB_TO_CPU_AD<20>EI_NB_TO_CPU_AD<19>EI_NB_TO_CPU_AD<18>EI_NB_TO_CPU_AD<17>EI_NB_TO_CPU_AD<16>EI_NB_TO_CPU_AD<15>EI_NB_TO_CPU_AD<14>EI_NB_TO_CPU_AD<13>EI_NB_TO_CPU_AD<12>EI_NB_TO_CPU_AD<11>EI_NB_TO_CPU_AD<10>EI_NB_TO_CPU_AD<9>EI_NB_TO_CPU_AD<8>EI_NB_TO_CPU_AD<7>EI_NB_TO_CPU_AD<6>EI_NB_TO_CPU_AD<5>EI_NB_TO_CPU_AD<4>EI_NB_TO_CPU_AD<3>EI_NB_TO_CPU_AD<2>EI_NB_TO_CPU_AD<1>EI_NB_TO_CPU_AD<0>
EI_CPU_TO_NB_AD<43>EI_CPU_TO_NB_AD<42>EI_CPU_TO_NB_AD<41>EI_CPU_TO_NB_AD<40>EI_CPU_TO_NB_AD<39>EI_CPU_TO_NB_AD<38>EI_CPU_TO_NB_AD<37>EI_CPU_TO_NB_AD<36>EI_CPU_TO_NB_AD<35>EI_CPU_TO_NB_AD<34>EI_CPU_TO_NB_AD<33>EI_CPU_TO_NB_AD<32>EI_CPU_TO_NB_AD<31>EI_CPU_TO_NB_AD<30>EI_CPU_TO_NB_AD<29>EI_CPU_TO_NB_AD<28>EI_CPU_TO_NB_AD<27>EI_CPU_TO_NB_AD<26>EI_CPU_TO_NB_AD<25>EI_CPU_TO_NB_AD<24>EI_CPU_TO_NB_AD<23>EI_CPU_TO_NB_AD<22>EI_CPU_TO_NB_AD<21>EI_CPU_TO_NB_AD<20>EI_CPU_TO_NB_AD<19>EI_CPU_TO_NB_AD<18>EI_CPU_TO_NB_AD<17>EI_CPU_TO_NB_AD<16>EI_CPU_TO_NB_AD<15>EI_CPU_TO_NB_AD<14>EI_CPU_TO_NB_AD<13>EI_CPU_TO_NB_AD<12>EI_CPU_TO_NB_AD<11>EI_CPU_TO_NB_AD<10>EI_CPU_TO_NB_AD<9>EI_CPU_TO_NB_AD<8>EI_CPU_TO_NB_AD<7>EI_CPU_TO_NB_AD<6>EI_CPU_TO_NB_AD<5>EI_CPU_TO_NB_AD<4>EI_CPU_TO_NB_AD<3>EI_CPU_TO_NB_AD<2>EI_CPU_TO_NB_AD<1>EI_CPU_TO_NB_AD<0>
43
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
26
36 62
62
26
26
62
62
62
62
62
62
62
62
62
62
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62
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62
62
62
62
62
62
62
62
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62
62
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62
62
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62
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62
62
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62
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62
62
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
18
33 27
27
18
28
28
18
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
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27
27
26
26
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26
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26
26
26
26
26
26
26
26
26
26
27
25
5
5
25
26
26
5
27
27
27
27
25
5
26
26
26
26
26
26
26
26
26
26
26
26
26
26
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Preliminary
www.vinafix.vn
(1 OF 3)
EI_ADI3EI_ADI2
EI_ADI0
EI_CLKI
EI_ADI1
EI_CLKI*
EI_ADI11EI_ADI10
EI_ADI8
EI_ADI4
EI_ADI9
EI_ADI7EI_ADI6EI_ADI5
EI_ADI12
EI_ADI21
EI_ADI18
EI_ADI20EI_ADI19
EI_ADI16EI_ADI17
EI_ADI15EI_ADI14EI_ADI13
EI_ADI22EI_ADI23EI_ADI24
EI_ADI28EI_ADI29
EI_ADI31EI_ADI30
EI_ADI25EI_ADI26EI_ADI27
EI_ADI32
EI_ADI42
EI_ADI38
EI_ADI35
EI_ADI39
EI_ADI41EI_ADI40
EI_ADI34
EI_ADI37EI_ADI36
EI_ADI33
EI_ADI43
EI_SRI0*
EI_SRI1*
CHKSTOP*
EI_SRI1
EI_SRI0
SRESET*
HRESET*
THERM_INT*
APSYNCOUT
TBEN
QACK*
PROCID0
TRIGGER_OUTTRIGGER_IN
PROCID2PROCID1
AVPRESET*
C1UNDGLOBALC2UNDGLOBAL
LSSDMODELSSDSCANENABLELSSDSTOPC2ENABLELSSDSTOPC2STARENABLELSSDSTOPENABLE
BIMODE*
AFN
MCP*
DI2*
SYNCENABLE*
RAMSTOPENABLEPULSESEL2PULSESEL1PULSESEL0
PSRO1PSRO2
RI*
INT*
QREQ*
I2CGO
APSYNCIN
CKTERMDIS
IIC_SDAIIC_SCL
TMSTRST*
TCK
TDOTDI
ATTENTION
BUSCFG0BUSCFG1BUSCFG2
EI_DISABLE
GPUL_DBGJTAGMODE
PLLMULT
BYPASS*PLLLOCK
PLLRANGE0
SPARE
PLLTESTOUT
PLLRANGE1PLLTEST
EI_SRO1*EI_SRO1
EI_SRO0*EI_SRO0
EI_ADO11EI_ADO10
EI_ADO12EI_ADO13EI_ADO14EI_ADO15
EI_ADO17EI_ADO16
EI_ADO18EI_ADO19EI_ADO20EI_ADO21
EI_ADO23EI_ADO22
EI_ADO24EI_ADO25
EI_ADO28EI_ADO29EI_ADO30EI_ADO31
EI_ADO27EI_ADO26
EI_ADO32
EI_ADO43
EI_ADO38EI_ADO37EI_ADO36EI_ADO35
EI_ADO42EI_ADO41EI_ADO40EI_ADO39
EI_ADO34EI_ADO33
EI_ADO3EI_ADO2EI_ADO1EI_ADO0
EI_ADO9EI_ADO8EI_ADO7
EI_ADO4
EI_ADO6EI_ADO5
EI_CLKO*EI_CLKO
SYSCLKSYSCLK*
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PLACE AT PROCESSOR PINS.
PROCESSOR IIC ADDRESS:
ON PAGES 31 & 32MORE PROCESSOR DECOUPLING
PROCESSOR LOGIC I/O
PLACE BY PROCESSOR PIN.
(SEE TABLE)
80,84
NEO APPLE PI
MATCH TO SYSCLK
PLACE NEAR PROCESSOR.
MASTER: GILA
2
1 C29001UF10%6.3VCERM402
2
1C2902
402CERM6.3V10%1UF
2
1 C2903
402CERM6.3V10%1UF
2
1 C2904
402CERM6.3V10%1UF
2
1 C2905
402CERM6.3V10%1UF
2
1 C29066.3V
402CERM
10%1UF
2
1 C2907
402CERM6.3V10%1UF
2
1 C290810%
CERM402
6.3V
1UF2
1 C2909
CERM6.3V10%1UF
4022
1 C2910
402
6.3V10%1UF
CERM2
1 C2911
402CERM6.3V10%1UF
2
1R2909
402MF1/16W1%100
NOSTUFF
2
1 C290120%0.22UF
NOSTUFF
X5R6.3V
402 2
1R2907
402
1001%1/16WMF
NOSTUFF
21
R2910
402MF
0
1/16W5%
W20
N19
N21
AD22
V22
AD13
AB21
AD21
AD17
T22R22
AB24
AB4
AA13
AA5
AB6
AB12V21
AC10
AB11
AC9
V5
V23
M18
M19
L19
T19
W22
AA9
AB7
AA8
T20
AD18
AD11
AD7
AD8
U19
AB5
W4
AB19
Y21
AA20
N22
V20
AA22
F1
G1
L2
L3
L22
L21
K24
L24
P20
E3
D3
D24E24
G4
H1
H3
K2
K4
A6
A8
C10
A10
M3
C9
A9
A4
C6
C8
A7
C7
C4
B4
B6
L1
A12
C12
D8
D2
A2
A5
D6
B2
C5
C1
K3
C11
B10
A11
E12
D11
B8
G3
E2
F4
F2
H2
N3
G20
J24
H23
K22
A13
A19
C16
A17
A15
C13
A18
A20
A23
A21
C18
C19
A22
D20
B21
D18
J22
C17
C14
B19
B17
F21
B24
B23
E21
E20
C22
H22
A16
D15
C15
A14
B15
G19
G24
D22
G21
F23
J21
H21
U24
AA14
R20
AC15
AC16
V24
AB16
AC19
AA19
AC24
W23
AD12
AD14 AA10
AA12
U2900
CBGA
GPUL
CRITICALOMIT
21
R2901NOSTUFF
46.4
1%
MF402
1/16W
21
R2903
1/16W
46.4
NOSTUFF
402MF
1%
21
R2905NOSTUFF
1/16W
49.9
1%
402MF 21
R2902
5%
0
1/16W
402MF
21
R2904NOSTUFF
1/16W5%
402MF
0
2
1R2906
402
1/16W
1K
MF
5%
2
1R2908
402
1/16W5%1K
MF
21
R2911
402MF
0
NOSTUFF
1/16W5%
2
1 C2912
402CERM
1UF10%6.3V
2
1 C29131UF10%6.3VCERM402
2
1 C29141UF10%6.3VCERM402
2
1 C29151UF10%6.3VCERM402
2
1 C29161UF10%6.3VCERM402
2
1 C29171UF10%6.3VCERM402
2
1 C29181UF10%6.3VCERM402
2
1 C29191UF10%6.3VCERM402
2
1 C29201UF10%6.3VCERM402
2
1 C29211UF10%6.3VCERM402
2
1 C29221UF10%6.3VCERM402
2
1 C29231UF10%6.3VCERM402
2
1 C29241UF10%6.3VCERM402
2
1 C29251UF10%6.3VCERM402
2
1 C29261UF10%6.3VCERM402
2
1 C29271UF10%6.3VCERM402
2
1 C29281UF10%6.3VCERM402
2
1 C29291UF10%6.3VCERM402
2
1 C29301UF10%6.3VCERM402
2
1 C29311UF10%6.3VCERM402
2
1 C29321UF10%6.3VCERM402
2
1 C29331UF10%6.3VCERM402
2
1 C29341UF10%6.3VCERM402
2
1 C29351UF10%6.3VCERM402
2
1 C29361UF10%6.3VCERM402
2
1 C29371UF10%6.3VCERM402
2
1 C29381UF10%6.3VCERM402
2
1 C29391UF10%6.3VCERM402
2
1 C29401UF10%6.3VCERM402
2
1 C29411UF10%6.3VCERM402
2
1 C29421UF10%6.3VCERM402
2
1 C29431UF10%6.3VCERM402
2
1 C29441UF10%6.3VCERM402
2
1 C29451UF10%6.3VCERM402
2
1 C29461UF10%6.3VCERM402
2
1 C29471UF10%6.3VCERM402
2
1 C29481UF10%6.3VCERM402
2
1 C29491UF10%6.3VCERM402
2
1 C295010%1UF6.3VCERM402
2
1 C29511UF10%6.3VCERM402
2
1 C2952
CERM6.3V10%1UF
402
2
1 C29531UF10%6.3VCERM402
2
1 C29541UF10%6.3VCERM402
2
1 C29551UF10%6.3VCERM402
2
1 C29561UF10%6.3VCERM402
2
1 C29571UF10%6.3VCERM402
2
1 C29581UF6.3V
402CERM
10%2
1 C2959
402
1UF10%6.3VCERM2
1 C2960
CERM
1UF10%6.3V
402
03051-6532
29 103
EI_CPU_TO_NB_AD<9>
EI_CPU_SYNC
CPU_APSYNC EI_SYNC_FROM_NB
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<2>
PLLRANGE0PLLRANGE1PLLTESTPLLTESTOUT
MCP_LLSSDSTOPENABLE
LSSDSCANENABLELSSDMODE
DI2_LC2UNDGLOBALC1UNDGLOBAL
AVPRESET_L
PROCID2PROCID1
PROC_THERM_INT_L
CPU_SRESET_L
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<4>
PP1V2_EI_CPU
CPU_INT_L
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<43>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<11>
PPVCORE_CPU
JTAGMODE_SPARE2
CPU_HTBEN
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_SR_P<0>
CHKSTOP_L
EI_NB_TO_CPU_AD<43>
EI_NB_TO_CPU_SR_P<1>
PROCID0
PP1V2_EI_CPU
EI_CPU_CLK_P
EI_CPU_CLK_N
CPU_CHKSTOP_L
CPU_SPARE
CPU_BYPASS_LPLLLOCKPLLMULT
JTAG_CPU_TRST_L
JTAG_CPU_TDOJTAG_CPU_TMS
JTAG_CPU_TDIJTAG_CPU_TCK
BUSCFG2
TP_ATTENTIONGPUL_DBG
BUSCFG1
EI_DISABLE
CKTERMDIS_L
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<26>EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<23>EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<20>EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<15>EI_CPU_TO_NB_AD<16>EI_CPU_TO_NB_AD<17>EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<14>EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_CLK_P
RAMSTOPENABLE
SYNCENABLERI_L
PULSESEL1PULSESEL2
TP_PSRO1TP_PSRO2
PULSESEL0
LSSDSTOPC2ENABLELSSDSTOPC2STARENABLE
BIMODE_L
TP_AFN
EI_SETP_PROC_TRIGGER_OUT
CPU_HRESET_L
TP_PSYNCOUT
CPU_HTBEN
EI_NB_TO_CPU_SR_N<1>
EI_QACK_L
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_AD<41>EI_NB_TO_CPU_AD<40>EI_NB_TO_CPU_AD<39>EI_NB_TO_CPU_AD<38>EI_NB_TO_CPU_AD<37>EI_NB_TO_CPU_AD<36>EI_NB_TO_CPU_AD<35>EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<32>EI_NB_TO_CPU_AD<33>
EI_NB_TO_CPU_AD<31>EI_NB_TO_CPU_AD<30>EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<27>EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<26>EI_NB_TO_CPU_AD<25>EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<22>EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_AD<21>EI_NB_TO_CPU_AD<20>EI_NB_TO_CPU_AD<19>EI_NB_TO_CPU_AD<18>EI_NB_TO_CPU_AD<17>EI_NB_TO_CPU_AD<16>EI_NB_TO_CPU_AD<15>EI_NB_TO_CPU_AD<14>EI_NB_TO_CPU_AD<13>EI_NB_TO_CPU_AD<12>EI_NB_TO_CPU_AD<11>EI_NB_TO_CPU_AD<10>EI_NB_TO_CPU_AD<9>EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<6>EI_NB_TO_CPU_AD<5>
EI_NB_TO_CPU_AD<2>EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_AD<1>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_SR_P<0>
EI_QREQ_L
I2C_CPU_A_SCLI2C_CPU_A_SDA
BUSCFG0
CHKSTOP_L
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_AD<7>
EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<0>
EI_NB_TO_CPU_CLK_P
MCP_L
I2CGO
EI_CPU_TO_NB_AD<1>
VOLTAGE=0.6VSYSCLK_TERM
29
32
29
28
31
28
27
30
28
27
28 28
28 28
28
62
62
62
62
28
62
62
62
62
62
62
62
62
62
18
28
62
62
62
62
62
62
62
62
62
62
62
62
29
27
62
62
27
62
62
18
28
28
18 18
18 18
62
62
62
62
62 62
62
62
62 62
62 62
62 62 62 62
62 62
62
62
62
28
28
27
62
62
62 62 62 62 62 62 62 62
62 62
62 62 62
62 62
62 62 62
62 62
62 62 62 62 62 62 62 62 62 62 62 62 62 62
62 62
62 62
62
62
62
62
28
27
62
62
62
62
62
62
26
25
26
26
26
26
28 28 28 28
27 28
28 28
28 28 28
28
28 28
28
23
26
26
26
26
26
26
26
26
26
5
23
26
26
26
26
26
26
26
26
26
26
26
26
5
28
25
26
26
16
26
26
28
5
25
25
26
28
13 16 28
6
6 6
6 6
28
28
28
28
28
26
26
26
26
26 26
26
26
26 26
26 26
26 26 26 26
26 26
26
26
26
28
28 28
28 28
28
28 28
28
26
13
25
26
26
26
26 26 26 26 26 26 26 26
26 26
26 26 26
26 26
26 26 26
26 26
26 26 26 26 26 26 26 26 26 26 26 26 26 26
26 26
26 26
26
26
26
26
26
18 18
28
16
26
26
26
26
26
27
28
26
Preliminary
www.vinafix.vn
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
SYSTEM CONFIGURATION
SYSCLK * 8
SYSCLK * 12
PROC / 3
PROC / 8
PROC / 16
SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.
AVPRESET ON
SELECT ELASTIC MODE OR BYPASS.
* STUFF THESE ON Q45.
*BYPASS MODE
PROC / 4
PROC / 6
PROC / 12
PROC / 2
CPU STRAPS
RESERVED
AVPRESET OFF
MASTER: GILA
SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.
*
*
SELECT PLL FREQUENCY RANGE.
*
21
R3001
402MF
1/16W
0
5%
21
R30031K
5%1/16WMF402
21
R3005
402
1K
5%1/16WMF
21
R3007
402MF
1/16W5%
1K
2 1
R30091K
5%1/16WMF402
21
R30021K
5%1/16WMF402
21
R30041K
5%1/16WMF402
21
R3006
402MF
1/16W5%
1K
2
1R3008OMIT
402MF1/16W5%1K
2
1R3024OMIT
402MF1/16W5%1K
2
1R3026OMIT
402MF1/16W5%1K
2
1R3028OMIT
402MF1/16W5%1K
2
1R3030OMIT
MF1/16W5%1K
402 2
1R3032OMIT
1K5%1/16WMF402 2
1R3034
402
OMIT
MF1/16W5%1K
2
1R3012OMIT
1K5%1/16WMF402 2
1R3018OMIT
1K5%1/16WMF4022
1R3016OMIT
402MF1/16W5%1K
2
1R3014OMIT
1K5%
MF402
1/16W
2
1R3010OMIT
1K5%1/16WMF402 2
1R3020OMIT
402MF1/16W5%1K
2
1R3022OMIT
402
1K5%1/16WMF
21
R3040
402
1K
5%
MF1/16W
21
R3042
MF
5%
1K
402
1/16W
NOSTUFF
2
1R3036OMIT
402
1K5%1/16WMF
2
1R3038OMIT
402MF1/16W5%1K
2
1R306810K5%1/16WMF402
21
R3031
402MF
1/16W5%
1K
21
R30331K
5%1/16WMF402
21
R30351K
5%1/16WMF402
21
R3037
402MF
1/16W5%
1K
21
R30390
5%1/16WMF402
21
R3041
402MF
1/16W5%
1K
21
R3043
402MF
5%
1K
1/16W
21
R3045
402MF
1/16W5%
1K
21
R3047
1/16W
402MF
5%
1K
21
R3049
402MF
1/16W5%
1K
21
R3051
402
5%
MF1/16W
1K
21
R3053NOSTUFF
402MF
1/16W5%
10K
21
R30551K
402MF
1/16W5%
21
R3057
402
1K
5%1/16WMF
NOSTUFF
21
R3059
1/16W
402
1K
5%
MF
21
R3061
402
1K
5%1/16WMF
21
R3063
402
1K
5%1/16WMF
NOSTUFF
21
R30651K
5%1/16WMF402
21
R3067NOSTUFF
1K
5%
MF402
1/16W
21
R3069
MF402
1/16W5%
1K
21
R3071NOSTUFF
MF
5%
1K
402
1/16W
21
R3073
402
1K
5%1/16WMF
21
R3075
402
1K
5%1/16WMF
NOSTUFF
21
R3077
402
NOSTUFF
MF1/16W5%
1K
21
R3079
1/16W
NOSTUFF
402MF
5%
1K
21
R30811K
402MF
1/16W5%
21
R3083
402
1K
5%1/16WMF
21
R3085
402
1K
5%1/16WMF
21
R3087
402MF
1K
5%1/16W
21
R3089
402MF
1/16W5%
1K
21
R3091
402
1K
5%1/16WMF
21
R3093
5%
1K
1/16WMF402
21
R309510K
402MF
1/16W5%
21
R3097
402
5%1/16WMF
10K
21
R3099
402MF
1/16W5%
10K
21
R30000
5%
MF402
1/16W
NOSTUFF
CPU_PLL_HIGH114S1103 2 R3030,R3016RES,1K OHM,1/16W,5%,0402
RES,1K OHM,1/16W,5%,0402 R30341114S1103 EI_3TO1
CPU_PLL_MEDIUM114S1103 2 R3014,R3032RES,1K OHM,1/16W,5%,0402
114S1103 2 R3014,R3016RES,1K OHM,1/16W,5%,0402 NOSTUFF
CPU_PLL_LOWRES,1K OHM,1/16W,5%,0402 R3030,R3032114S1103 2
03051-6532
10330
R3008,R3010,R3012114S1103 3 RES,1K OHM,1/16W,5%,0402 NOSTUFF
1114S1103 RES,1K OHM,1/16W,5%,0402 R3036
1 RES,1K OHM,1/16W,5%,0402114S1103 R3020 NOSTUFF
114S1103 RES,1K OHM,1/16W,5%,04021 R3022
R3024,R3010,R30123 RES,1K OHM,1/16W,5%,0402114S1103 NOSTUFF
R3008,R3026,R3012RES,1K OHM,1/16W,5%,04023114S1103 NOSTUFF
114S1103 RES,1K OHM,1/16W,5%,0402 R3008,R3026,R30283 NOSTUFF
RES,1K OHM,1/16W,5%,0402 R3008,R3010,R3028114S1103 3 NOSTUFF
R3024,R3026,R3012114S1103 3 RES,1K OHM,1/16W,5%,0402 EI_3TO1
114S1103 RES,1K OHM,1/16W,5%,04021 R3038 NOSTUFF
R3024,R3010,R30283 RES,1K OHM,1/16W,5%,0402114S1103 NOSTUFF
RES,1K OHM,1/16W,5%,04021114S1103 R3018 EI_2TO1
R3024,R3026,R30283 RES,1K OHM,1/16W,5%,0402114S1103 EI_2TO1
LSSDSTOPENABLE
PLLRANGE0
BUSCFG0
PLLRANGE1PLLMULTEI_DISABLE
BUSCFG1
AVPRESET_L
PP1V2_EI_CPUPP1V2_EI_CPU
PP1V2_EI_CPU
CPU_SPARE
LSSDSTOPC2STARENABLE
EI_QREQ_L
RI_L
LSSDMODE
JTAG_CPU_TCK
JTAG_CPU_TDI
JTAG_CPU_TMS
PULSESEL1
PULSESEL0
C1UNDGLOBAL
C2UNDGLOBAL
CPU_BYPASS_L
PLLTEST
JTAGMODE_SPARE2
LSSDSCANENABLE
LSSDSTOPC2ENABLE
SYNCENABLE
RAMSTOPENABLE
PULSESEL2
PROCID0
PROCID1
PROCID2
JTAG_CPU_TDO
BIMODE_L
DI2_L
CPU_INT_L
PROC_THERM_INT_L
CPU_HRESET_L
CPU_SRESET_L
I2CGO
CPU_HTBEN
CKTERMDIS_L
BUSCFG2
PLLTESTOUT
JTAG_CPU_TRST_L
JTAG_SEL
GPUL_DBG
EI_SE
PP1V2_EI_CPU
29
29
29
29
28
28
28
28
27
27
27
27
27
27
27
27
18
18
18
27
18
18
18
27
18
27
27
27
27
27
27
18
27
27
27
27
27
27
27
27
5
5
5
27
27
26
27
27
6
6
6
27
27
27
27
13
27
27
27
27
27
27
27
27
27
27
6
27
27
23
27
13
23
27
25
27
27
27
6
27
26
5
Preliminary
www.vinafix.vn
X100 X99GNDVCORE
(3 OF 3)GND
VOUTVIN
NOISECONT
KPGND2
KPVDD2KPVDD1AVDD
X105 X105VCORE GND
(2 OF 3)
AGND KPGND1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#TABLE_5_ITEM
PLACE ALL THESE PARTS VERY CLOSE TO U2900
0805
MASTER: GILA
CPU POWER AND BYPASS
21
R3101
1/16WMF
5%
603
2.2
2
1 C31000.22UF6.3V20%
402X5R
2
1 C3101NOSTUFF
20%0.22UF
402
6.3VX5R
21
R3103
5%
MF402
0
NOSTUFF
1/16W
21
R3105NOSTUFF
0
5%1/16WMF402
2
1 C310220%6.3VCERM805
10UF
21
L310160-OHM-EMI
SM
21
R3127
5%
MF1/16W
402
0
21
R3129
5%
0
1/16WMF40221
R3131
MF
0
402
5%1/16W
2
1 C310310%1UF
402
6.3VCERM
2
1 C3104
CERM6.3V10%
402
1UF
2
1 C3105
402CERM6.3V10%1UF
2
1 C3106
402CERM6.3V10%1UF
2
1 C3107
402CERM6.3V10%1UF
2
1 C3108
CERM6.3V10%
402
1UF
2
1 C3109
402CERM
10%1UF6.3V
2
1 C3110
402CERM6.3V10%1UF
2
1 C3111
402CERM6.3V10%1UF
2
1 C3112
402CERM6.3V
1UF10%
2
1 C3113
402CERM6.3V10%1UF
2
1 C3114
805
20%6.3VCERM
10UF2
1 C311510UF6.3V20%
805CERM2
1 C3116
CERM6.3V20%
805
10UF2
1 C3117
805CERM6.3V20%10UF
NO STUFF
2
1 C3118
402CERM6.3V10%1UF
2
1 C3119
402CERM6.3V10%1UF
2
1 C3120
402CERM6.3V10%1UF
2
1 C3121
CERM6.3V10%1UF
402
2
1 C3122
402CERM6.3V10%1UF
2
1 C3123
402CERM6.3V10%1UF
2
1 C3124
402
6.3V10%1UF
CERM
2
1 C3125
402CERM6.3V10%1UF
2
1 C3126
402CERM6.3V10%1UF
2
1 C3127
402CERM6.3V10%1UF
2
1 C31286.3V10%1UF
CERM402
2
1 C3129
402CERM6.3V10%1UF
2
1 C3130
402CERM6.3V10%1UF
2
1 C3131
402CERM
10%1UF6.3V
2
1 C3132
402CERM6.3V10%1UF
2
1 C3133
402CERM
10%1UF6.3V
2
1 C3134
402CERM6.3V10%1UF
2
1 C3135
402
6.3V10%1UF
CERM
2
1 C3136
CERM6.3V
1UF10%
402
2
1 C3137
402CERM6.3V10%1UF
2
1 C3138
402CERM6.3V10%1UF
2
1 C31396.3V10%1UF
CERM402
2
1 C3140
402CERM6.3V
1UF10%
2
1 C3141
402CERM6.3V10%1UF
2
1 C3142
402
10%1UF
CERM6.3V
2
1 C3143
402CERM
10%1UF6.3V2
1 C31441UF
402CERM
10%6.3V
2
1 C3145
402CERM6.3V10%1UF
2
1 C31466.3V10%1UF
CERM402
2
1 C31476.3V10%1UF
402CERM
AD9AD5AD3
AD23AD19AD15AD1AC8AC6AC4
AC22AC20AC2
AC18AC14AC12AB9AB3
AB23AB17AB15AB13AB1AA6AA4
AA24AA2
AA18AA16
Y9Y7Y5Y3
Y23Y22Y19Y17Y15Y13Y11W8W6
W24W2
W18W16W14W12W10V9V7V3
V19V17V15V13V11V1U8U6U4
U22U20U2
U18U16U14U12U10T9T7T5T3
T23T21T17T15T13T11T1R8R6R4
R18R16R14R12R10P9P7P5P3
P23P21P19P17P15P13P11P1
AD6AD4AD24AD20AD2AD16AD10AC7AC5AC3AC23AC21AC17AC13AC11AC1AB8AB22AB20AB2AB18AB14AB10AA7AA3AA23AA21AA17AA15AA11Y8Y6Y4Y24Y20Y2Y18Y16Y14Y12Y10W9W7W5W3W21W19W17W15W13W11W1V8V6V4V2V18V16V14V12V10U9U7U5U3U23U21U17U15U13U11U1T8T6T4T24T18T16T14T12T10R9R7R5R3R23R21R19R17R15R13R11R1P8P6P4P22P2P18U2900
CBGA
GPUL
21
R3132
1/16W
603
5%
MF
2.2
NOSTUFF
51
4
2
3
VR3100OMIT
MM1572FNSOT-25A
2
1 C315020%6.3VCERM805
10UF2
1 C31491UF10VCERM603
20%
2
1 C314816VCERM
20%0.01UF
402
2
1 C31991UF10%
CERM402
6.3V
2
1
XW3100SM
OMIT
N18N16N14N12N10M9M7M5
M23M21
C2
M17M15M13M11M1L8L6L4
L20L18
B7
L16L14L12L10K9K7K5
K23K21K19
B3
K17K15K13K11J8J6J4
J20J2
J18
B20
J16J14J12J10J1H9H7H5
H24H19
B16
H17H15H13H11G8G6
G22G18G16G14
B13
G12G10F9F7F5F3
F19F17F15F13
B11
F11E8E6E4
E22E18E16E14E10E1
A24
D9D7D5
D23D21D19D17D13C24
N8N6N4
N24N20N2
C20
A1
R2Y1
T2AA1
N5N23N17N15N13N11N1M8M6M4
C21
M24M22M20M2M16M14M12M10L9L7
B9
L5L23L17L15L13L11K8K6K20K18
B5
K16K14K12K10K1J9J7J5J3J23
B22
J19J17J15J13J11H8H6H4H20H18
B18
H16H14H12H10G9G7G5G23G2G17
B14
G15G13G11F8F6F24F22F20F18F16
B12
F14F12F10E9E7E5E23E19E17E15
B1
E13E11D4D16D14D12D10D1C3
P16P14P12P10N9N7
C23
A3
P24
R24
U2900GPUL
CBGA
051-6532 03
10331
CRITICAL CPU_AVDD_2V8VREG MM1572FN 2.8V353S0807 1 VR3100
CRITICAL CPU_AVDD_2V6VR3100VREG MM1572FN 2.6V1353S0806
PP5V_RUN_CPU
VOLTAGE=2.5V
PP2V5_RUN_CPU_AVDDMIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
MIN_NECK_WIDTH=8MILNET_SPACING_TYPE=PROC_DIFF
KPGND2
DIFFERENTIAL_PAIR=P_KP2
MIN_LINE_WIDTH=10MIL
NET_SPACING_TYPE=PROC_DIFFMIN_NECK_WIDTH=8MIL
KPVDD2
DIFFERENTIAL_PAIR=P_KP2
MIN_LINE_WIDTH=10MIL
PPVCORE_CPU PP1V2_EI_CPU
GND_CPU_AVDD
PP2V5_RUN_CPU_AVDD_R_LVOLTAGE=2.5VMIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
PP2V5_RUN_CPU
CPU_AVDD_EN CPU_AVDD_NOISE
VOLTAGE=2.5VMIN_NECK_WIDTH=10MIL
PP2V5_RUN_CPU_AVDD_R
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=8MIL
MIN_LINE_WIDTH=10MILDIFFERENTIAL_PAIR=P_TDDNET_SPACING_TYPE=PROC_DIFF
TDIODE_POS
GND_SPARE_GND
GND_Z_OUT
GND_Z_SENSE
GND_Z_OUT
GND_Z_SENSE
PPVCORE_CPU
GND_SPARE_GND
TDIODE_NEGDIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MILMIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF
32
32
31
31
30 28
30
29 27
29
16
27 18
27
5
5 5
5
14
32
29
29
29
29
29
5
29
32
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
MASTER: GILA
PROC DECOUPLING
2
1 C32001UF10%
CERM402
6.3V
2
1 C32011UF10%
CERM402
6.3V
2
1 C32021UF10%
CERM402
6.3V
2
1 C3203
402
1UF10%
CERM6.3V
2
1 C32041UF10%
CERM402
6.3V
2
1 C32051UF10%
CERM402
6.3V
2
1 C32061UF10%
CERM402
6.3V
2
1 C32071UF10%
CERM402
6.3V
2
1 C32081UF10%
CERM402
6.3V
2
1 C32091UF10%
CERM402
6.3V
2
1 C32101UF10%
CERM402
6.3V
2
1 C32111UF10%
CERM402
6.3V
2
1 C32121UF10%
CERM402
6.3V
2
1 C3213
402
1UF10%
CERM6.3V2
1 C3214
402
1UF10%
CERM6.3V
2
1 C32151UF10%
CERM402
6.3V2
1 C32161UF10%
CERM402
6.3V2
1 C32171UF10%
CERM402
6.3V2
1 C32181UF10%
CERM402
6.3V2
1 C32191UF10%
CERM402
6.3V2
1 C32201UF10%
CERM402
6.3V2
1 C32211UF10%
CERM402
6.3V2
1 C32221UF10%
CERM402
6.3V
2
1 C32231UF10%
CERM402
6.3V2
1 C32241UF10%
CERM402
6.3V
2
1 C32251UF10%
CERM402
6.3V
2
1 C32261UF10%
CERM402
6.3V
2
1 C32271UF10%
CERM402
6.3V
2
1 C32281UF10%
CERM402
6.3V
2
1 C32291UF10%
CERM402
6.3V
2
1 C32301UF10%
CERM402
6.3V
2
1 C32311UF10%
CERM402
6.3V
2
1 C32321UF10%
CERM402
6.3V
2
1 C32331UF10%
CERM402
6.3V 2
1 C32341UF10%
CERM402
6.3V
2
1 C32351UF10%
CERM402
6.3V
2
1 C32361UF10%
CERM402
6.3V
2
1 C32371UF10%
CERM402
6.3V
2
1 C32381UF10%
CERM402
6.3V
2
1 C32391UF10%
CERM402
6.3V
2
1 C32401UF10%
CERM402
6.3V
2
1 C32411UF10%
CERM402
6.3V
2
1 C32421UF10%
CERM402
6.3V
2
1 C32431UF10%
CERM402
6.3V
2
1 C32441UF10%
CERM402
6.3V
2
1 C32451UF10%
CERM402
6.3V
2
1 C32461UF10%
CERM402
6.3V
2
1 C32471UF10%
CERM402
6.3V
2
1 C32481UF10%
CERM402
6.3V
2
1 C32491UF10%
CERM402
6.3V
2
1 C32501UF10%
CERM402
6.3V
2
1 C32511UF10%
CERM402
6.3V
2
1 C32521UF10%
CERM402
6.3V
2
1 C32531UF10%
CERM402
6.3V
2
1 C32541UF10%
CERM402
6.3V
2
1 C32551UF10%
CERM402
6.3V
2
1 C32561UF10%
CERM402
6.3V
2
1 C32571UF10%
CERM402
6.3V
2
1 C32581UF10%
CERM402
6.3V
2
1 C32591UF10%
CERM402
6.3V
2
1 C32601UF10%
CERM402
6.3V
2
1 C32611UF10%
CERM402
6.3V
2
1 C32621UF10%
CERM402
6.3V
2
1 C32631UF10%
CERM402
6.3V
2
1 C32641UF10%
CERM402
6.3V
2
1 C32651UF10%
CERM402
6.3V
2
1 C32661UF10%
CERM402
6.3V
2
1 C32671UF10%
CERM402
6.3V
2
1 C32681UF10%
CERM402
6.3V
2
1 C32691UF10%
CERM402
6.3V
2
1 C32701UF10%
CERM402
6.3V
2
1 C32711UF10%
CERM402
6.3V
2
1 C32721UF10%
CERM402
6.3V
2
1 C32731UF10%
CERM402
6.3V
2
1 C32741UF10%
CERM402
6.3V
2
1 C32751UF10%
CERM402
6.3V
2
1 C32761UF10%
CERM402
6.3V
2
1 C32771UF10%
CERM402
6.3V
2
1 C32781UF10%
CERM402
6.3V
2
1 C32791UF10%
CERM402
6.3V
2
1 C32801UF10%
CERM402
6.3V
2
1 C32811UF10%
CERM402
6.3V
2
1 C32821UF10%
CERM402
6.3V
2
1 C32831UF10%
CERM402
6.3V
2
1 C32841UF10%
CERM402
6.3V
2
1 C3285
402
1UF10%
CERM6.3V2
1 C3286
402
1UF10%
CERM6.3V2
1 C3287
402
1UF10%
CERM6.3V2
1 C3288
402
1UF10%
CERM6.3V
2
1 C32891UF10%
CERM402
6.3V
2
1 C3290
402
1UF10%
CERM6.3V2
1 C3291
402
1UF10%
CERM6.3V2
1 C3292
402
1UF10%
CERM6.3V
2
1 C32931UF10%
CERM402
6.3V
2
1 C32941UF10%
CERM402
6.3V
2
1 C32951UF10%
CERM402
6.3V
2
1 C32961UF10%
CERM402
6.3V
2
1 C32971UF10%
CERM402
6.3V
2
1 C32981UF10%
CERM402
6.3V
2
1 C32991UF10%
CERM402
6.3V
051-6532
10332
03
PPVCORE_CPU32 31 29 27 5
Preliminary
www.vinafix.vn
PGNDGNDTHMPAD
VDDVCC
VROK
V+
ILIM
TIME
BSTS
BSTM
LXMLXS
CCI
CCV
DHS
DLM
DLS
REF
DHMD2
D3
S1
S0
D4
D1D0
SUS
CMN
OFS
TON
SKIP*
SHDN*
CMP
OVP
CSN
OAIN-OAIN+
CSP
FB
GNDS
S
D
G
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
VID4 = 0, VID3 = 1
0.850V
(CPUVCORE_CM_P)
NCNC
(_PPVIN_CPUVCORE)
Output
1
1.350V0
VID0VID4 = 1, VID3 = 0
VID2VID1 VID0VID2VID10
NET_SPACING_TYPE DIFFERENTIAL_PAIR
CPU VCore Regulator
1.100V
(CPUVCORE_DLM)
(CPUVCORE_OAIN_N)
Output0.875V
0.900V
0.925V
0.950V
1.050V
1.025V
1.000V
0.975V
REF
GND
S0
OPEN
S1OPEN
OPEN
OPEN
VCCOPEN
OPEN
GND
REF
VCCVCC
VCC
VCC
VCC
SUS > 2.7V
0.850V
0.825V
0.800V
0.775V
0.750V
0.725V
0.700V
0.675V
OutputS0GND
REF
GND
S1
GND VCC
VCC
OPEN
REF
GNDREF
REF
REF
REF
Output0.950V
0.925V
0.900V
VID0
1
0
0
1 0.875V
SHDN
0
0
1
1
0.800V
0.825V
VID10
0
1
1
0
0
1
1
1.150V
1.125V
0
0
0
1.075V 0
1
1
1
1
1.050V
1.025V
1.000V
0.975V
0
0
0
1
0
0
0
110
0
0
1
1
1
1
1
1
0
0
1
1
SUS = GND
1.325V
1.300V
OutputVID0
0
1
1.275V1
1.175V
1.200V
1.225V
1.250V
0
0
1
1
VID2
0 1
0
00
0
10
0
0
1
1
1
1
1
11.450V
1.425V
1.400V
1.500V
Output
1.475V
1.375V
0
0
1
VID10
0
1
11
0
0
1
1 1
1
0
0
VID2
0
0
0
0
1
1
1
1
(CPUVCORE_LXM)(CPUVCORE_LXS)
(CPUVCORE_BSTM)
(CPUVCORE_DLS)
(CPUVCORE_VREF)
1.525V
1.550V
(CPUVCORE_DHS)
(CPUVCORE_CS_P)
ELECTRICAL_CONSTRAINT_SET
GND
OPEN
GND
VID4 = 1, VID3 = 1
(GND_CPUVCORE)
VID4 = 0, VID3 = 0
(CPUVCORE_FB)
(CPUVCORE_DHM)
(CPUVCORE_SUS)
2
1 C33504.7uF20%25VCERM1206
2
1 C33514.7uF
1206CERM25V20%
2
1 C3352NO STUFF
20%
1206
25VCERM
4.7uF2
1 C33534.7uF
1206CERM25V20%
2
1 C3354
1206
25V20%
CERM
4.7uF2
1 C335525V
1206CERM
20%4.7uF
2
1 C3356NO STUFF
4.7uF20%25VCERM1206
2
1 C335725V
4.7uF
1206CERM
20%
25
30
10
36
2
1
41
3
18
6
54
8
31
19
7
16
17
34
27
9
13
11
15
32
29
33
28
20
21
2223
24
4039
37
38
12
14
3526
U3300MAX1544
QFN
CRITICAL
21
R3300
1/16W
402MF
5%
10
2
1 C3302
402X5R
0.22uF20%6.3V
2
1 C3300
CERM805
2.2uF20%10V2
1C3301
CERM603
10V20%1uF
2
1R3340
402MF
1/16W5%0
2
1R3307100K
5%
MF402
1/16W
NO STUFF
2
1C33335%
100pF
402CERM50V
2
1R3302
402
5%1/16W
MF
0
NO STUFF
2
1R3301
402
1/16W
05%
MF
2
1R3303
402
1%
MF1/16W
100K
2
1R3304
402
1%
MF1/16W
51.1K
2
1C3312
402
10%0.001uF
50VCERM
NO STUFF
2
1C3313
402
10%0.001uF
CERM50V
NO STUFF
21
L33100.36uH
SM-FDH1040CRITICAL
21
L3320
SM-FDH1040
0.36uH
CRITICAL
2
1C332310%
402
0.001uF50V
CERM
NO STUFF
2
1C33220.001uF
402
10%50V
CERM
NO STUFF
2
1 C331025V
1uF
805CERM
20%2
1 C3311
CERM805
20%25V
1uF
2
1 C332120%25VCERM
1uF
8052
1 C332020%25V
805
1uF
CERM
21
R3316
5%1/16WMF
10
402
2
1 C3315
CERM10V20%1uF
6032
1D3315SM
MBR0540
2
1C3316
CERM
20%
805
0.22uF25V
2
1 C332520%10VCERM
1uF
6032
1D3325MBR0540
SM
2
1C332620%25V
CERM805
0.22uF
21
R3326
402
5%1/16WMF
10
2
1C3304100pF
50V5%
402CERM
2
1 C330350V
402
10%
CERM
470pF
2
1R3310
2512
1WMF
1%0.001
CRITICAL
1
2R3320
2512
1%
MF1W
0.001
CRITICAL
2
1R33051%
1/16WMF402
20K
2
1R33065%
1/16WMF402
220K
2
1 C3306470pF
CERM50V10%
402
2
1C337010uF
CERM
20%
805
6.3V 2
1C3371
805
6.3V20%
10uF
CERM 2
1C337220%
10uF6.3V
805CERM 2
1C3373
805
6.3V
10uF20%
CERM 2
1C3374NO STUFF
20%10uF6.3V
805CERM 2
1C3375
805
6.3V
10uF20%
CERM 2
1C337620%
CERM
10uF6.3V
8052
1C3377
805
6.3V
10uF
CERM
20%2
1C337820%
CERM
10uF6.3V
8052
1C337920%
10uF6.3VCERM805
2
1C3389NO STUFF
805
6.3V
10uF
CERM
20%2
1C3388NO STUFF
805
10uF
CERM
20%6.3V2
1C338720%
CERM6.3V
805
10uF2
1C3386NO STUFF
6.3VCERM
20%
805
10uF2
1C338520%
10uF6.3V
805CERM2
1C338410uF
20%
CERM6.3V
8052
1C3383NO STUFF
6.3V20%
805
10uF
CERM2
1C338220%
CERM
10uF
805
6.3V2
1C3381
805
6.3V
10uF
CERM
20%2
1C3380
805
6.3V
10uF
CERM
20%
2
1C3394
805
NO STUFF
10uF20%
6.3VCERM2
1C3393NO STUFF
CERM6.3V
805
10uF20%
2
1C33926.3VCERM
10uF20%
8052
1C3391
CERM805
6.3V20%
10uF2
1C3359
805
6.3V
10uF
CERM
20%
2
1C3363330uF
2.5V-ESR9V20%
POLYCASE-D2E
CRITICAL
2
1C33622.5V-ESR9V
330uF20%
POLYCASE-D2E
CRITICAL
2
1C33612.5V-ESR9V
330uF20%
POLYCASE-D2E
CRITICAL
2
1C33602.5V-ESR9V
330uF20%
POLYCASE-D2E
CRITICAL
2
1C33652.5V-ESR9V
330uF20%
POLYCASE-D2E
CRITICAL
2
1C33672.5V-ESR9V
20%330uF
POLYCASE-D2E
CRITICAL
2
1C3364330uF
20%2.5V-ESR9V
POLYCASE-D2E
CRITICAL
2
1C336620%
330uF
POLY
CRITICAL
CASE-D2E
2.5V-ESR9V
2
1
XW3360SM
2
1
XW3361SM
21
R3360
5%1/16WMF402
10
21
R3361
5%1/16WMF402
10
21
R3318
5%1/16WMF
0
402
21
R3319
5%1/16WMF
0
402
2
1C331910%
NO STUFF
402
0.001uF50V
CERM
21
R3329
402
0
MF1/16W5%
21
R3328
402MF
1/16W5%
02
1C332910%
NO STUFF
402
0.001uF50V
CERM
2
1R33211/16WMF
1K
402
1%
2
1R33111/16W
MF
1K1%
4022
1R33661%
402
2K
MF1/16W
2
1R33335%
1/16WMF402
100
2
1 C333010%50VCERM
470pF
402
2
1R33305%1/16WMF402
0
2
1R33311/16W
5%
MF
1M
402
2
1 C3332470pF10%50VCERM
NO STUFF
4022
1R33321%
1/16WMF
2K
4022
1R3312
MF
1K1%
402
1/16W
2
1R33221/16W
MF
1K
402
1%
2
1
3
Q3309SM
2N7002
21
XW3300SM
2
1R33091/16W
402
30.1K
MF
1%
21
XW3320SM
21
XW3310SM
3
2 1
D3320
SBM540
PWRMITE
3
2 1
D3310
PWRMITE
SBM540
2
1C3399
CERM6.3V
805
NO STUFF
10uF20%
2
1C3398
805CERM6.3V
10uF20%
2
1C3397NO STUFF
6.3V
805CERM
20%10uF
2
1C3396
805
6.3VCERM
20%10uF
2
1C33956.3V
10uF
CERM
20%
805
NO STUFF
21
R3399
1/16W
10K
MF402
5%
1
2
3
4
8
7
6
5
RP3300
SM1
5%
1/16W
10K
321
4
5
Q3320SI7392DPSO-8-PWRPK
CRITICAL
321
4
5
Q3310CRITICAL
SO-8-PWRPKSI7392DP
21
R3398
MF402
5%1/16W
0
21
R33970
1/16W5%
402MF
2 1
R3341
1%
30.1K
1/16WMF402
2
1R33705%
402MF
01/16W
2
1R3371
402
1/16W5%
MF
0
NO STUFF
321
4
8765
Q3323SI4336DY
CRITICAL
SO-8
321
4
8765
Q3312CRITICAL
SO-8SI4336DY
321
4
8765
Q3313CRITICAL
SO-8SI4336DY
321
4
8765
Q3322CRITICAL
SO-8SI4336DY
051-6532 03
10333
CPUVCORE_TON
CPUVCORE_OVP
CPUVCORE_FB
CPUVCORE_OFS
CPUVCORE_VREF
CPUVCORE_SKIP_L
GND_CPUVCORE
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 milVOLTAGE=0V
CPUVCORE_CM_P_R
CPUVCORE_OAIN_NCPUVCORE_OAIN_P
CPUVCORE_CS_N_RCPUVCORE_CS_P_R
CPU_VID<1>MAKE_BASE=TRUE
CPUVCORE_DLM
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
CPUVCORE_CM_P
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
CPUVCORE_LXMMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
CPUVCORE_LXS
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milCPUVCORE_DLS
_PPVIN_CPUVCORE
CPUVCORE_GNDS
CPUVCORE_GNDS_RC
CPUVCORE_SNS
CPUVCORE_CM_N_R
CPUVCORE_SHDN_L
MIN_LINE_WIDTH=15 mil
PP5V_CPUVCORE_VCCVOLTAGE=5VMIN_NECK_WIDTH=10 mil
CPUVCORE_VID<4>
CPUVCORE_TIME
CPUVCORE_SW_TIME
CPUVCORE_SNSCPUVCORE_GNDSTHERM
CPUVCORE_CS_P
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 milCPUVCORE_CS_PCPUVCORE_CSTHERM
CPUVCORE_CS_NCPUVCORE_CSTHERM
CPUVCORE_CM_NCPUVCORE_CMTHERM
CPUVCORE_CM_PCPUVCORE_CMTHERM
CPUVCORE_GNDS CPUVCORE_GNDSTHERM
CPUVCORE_CCI
MIN_LINE_WIDTH=20 milCPUVCORE_BSTM_R
MIN_NECK_WIDTH=10 mil
CPU_VID<2>CPU_VID<1>
CPU_VID<0>
SYS_SLEWING_L
CPUVCORE_BSTS_RMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
CPUVCORE_CCI_C
CPU_VID<4>MAKE_BASE=TRUE
CPUVCORE_VID<4>
MAKE_BASE=TRUECPU_VID<3> CPUVCORE_VID<3>
CPUVCORE_DHMMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
_PP3V3_CPUVCORE
CPUVCORE_VID<3>CPUVCORE_VID<4>
CPUVCORE_CCV
CPUVCORE_VID<3>CPU_VID<2>MAKE_BASE=TRUE
MAKE_BASE=TRUECPU_VID<0>
VCORE_SWITCHING
_PP5V_CPUVCORE_VDD
MIN_LINE_WIDTH=25 milCPUVCORE_DHS
MIN_NECK_WIDTH=10 mil
PPVCORE_CPU
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 milCPUVCORE_BSTS
MIN_LINE_WIDTH=20 milCPUVCORE_BSTM
MIN_NECK_WIDTH=10 mil
CPUVCORE_ILIM
CPUVCORE_CS_N
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
_PPVCORE_CPU_REG
CPUVCORE_GNDSENSENO_TEST=TRUE
CPUVCORE_SENSENO_TEST=TRUE
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
CPUVCORE_CM_N
32 30
25
29
31
32
32
32
32
31
31
31
23
13
31
31
27
32
13
31
5
31
31
14
31
31 31
31
31
31
31
31
13
13
13
13
6 31
13 31
5
31
31
31
13
13
14
5
5
31
5
31 Preliminary
www.vinafix.vn
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Place close to SMU
For U3670For U3669For U3660
Place close to CPU
Place close to SMU
BUFFER
100UA CURRENT SOURCE
Place close to R3320
Place close to R3310
CPU Temp Monitoring
CPU Thermal Diode Circuit
For U3630
Place close to SMU
Place close to SMU
Place close to R3320
SMU Voltage Reference
DC GAIN = 80
CPU Current Monitoring
Place near center of CPU
CPU Voltage Monitoring
Place close to CPU Power Supply
Place XW3600 close to SMU
Place close to R3310
2
1 C36702.2UF
805
20%
CERM10V
21
C3671
20%
805CERM
10uF
6.3V
21
R3671
603MF
1/16W
100K
0.1%
21
R3670
1/16W0.1%
10K
FF603
CRITICAL
2
5
1
4
3
U3669SOT23-5LMV2011
CRITICAL
2
5
1
4
3
U3670LMV2011SOT23-5
CRITICAL
21
C3676
6.3V
805CERM
20%
10uF
21
R3676
MF603
1/16W
100K
0.1%
21
R3672CRITICAL
603
1/16WFF
40.2K
0.1%
21
R3675
FF
10K
603
1/16W0.1%
CRITICAL
21
R3677CRITICAL
603
1/16WFF
TD440.2K
0.1%
2
1 C366910VCERM
20%
805
2.2UF2
1 C36602.2UF10VCERM
20%
805
21
R366210K
FF603
1/16W0.1%
2
1 C36302.2UF20%
805
10VCERM
21
R3600
5%1/16W
603MF
2.2
21
XW3600SM
21
R3661
1/16W
10K
FF603
0.1%
CRITICAL
2
1R366912.7K1/16W1%
603MF
2
5
1
4
3
U3660LMV2011SOT23-5
CRITICAL
21
R366610K
603
1/16W0.1%
FF
CRITICAL
21
R366020K
1/16W0.1%
603FF
CRITICAL
21
R366520K
FF603
0.1%1/16W
CRITICAL
2
1R3655NOSTUFF
1/16W1%
MF402
1K
2
1R365605%
MF1/16W
402
2
1 C3651
402
10%50VCERM
0.0022UF2
1 C3650
402
10%50VCERM
0.0022UF
21
XW3630SM
21
C3631
20%
0.22UF
402
6.3VX5R
21
R3631
1%
MF1/16W
806K
603
2
5
1
4
3
U3630SOT23-5LMV2011
CRITICAL
21
C3636
6.3V
0.22UF
X5R
20%
402
21
R3636
1/16W
806K
MF603
1%
21
R3630CRITICAL
1/16W0.1%
603FF
10K
21
R363510K
FF603
0.1%1/16W
CRITICAL
21
R3679
1/16W5%
MF402
1K
2
1 C36795%50VCERM402
100pF
21
XW3640SM
21
R36401K
402MF
1/16W5%
2
1 C3640100pF
402CERM50V5%
21
R3610
1%1/16WMF402
10
21
R362010
1%1/16W
402MF
21
R3621
1/16W
10
1%
MF402
21
R3611
1/16W1%
10
402MF
2
1 C3639100pF
402CERM50V5%
21
R3639
5%
MF402
1K
1/16W
21
XW3621SM
21
XW3611SM
21
XW3620SM
21
XW3610SM
2
1C36982.2UF
20%10V
CERM805
2
1 C36992.2UF20%10VCERM805
2
1R36992001/16WMF603
1%
31
2
D36992.5VSSOT-23
CRITICAL
21
XW3650SM
21
XW3651SM
3603051-6532103
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 milCORE_ISNS_N
MIN_NECK_WIDTH=10 milISNS0MIN_LINE_WIDTH=10
MIN_NECK_WIDTH=10 milCPU_SENSE_I_RMIN_LINE_WIDTH=10
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 milADC_REF
PP2V5_SMU_VREF
DAGND
_PP3V3_CPUTHERM
TD_CURRENT
DAVDD
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10TD_BUFFERED
DAGND
ADC_REF
DAGNDMIN_LINE_WIDTH=15
MIN_NECK_WIDTH=10 mil
DAGND
MIN_NECK_WIDTH=10 mil
CPU_SENSE_VMIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=10TP_PROC_SENSE_COMMON
MIN_NECK_WIDTH=10 mil
_PP5V_CPUTHERM
GND_SMU_AVSS
DAVDD
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10ISNS1
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 milCORE_ISNS_P
DAGNDCPUVCORE_CM_P CPUIMON_PHASE1_P
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
_PPVCORE_CPU_REG
_PPVCORE_CPU_REGMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
CPUIMON_PHASE1_N
CPUVCORE_CS_P
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
CPUIMON_PHASE2_P
GND_SMU_AVSS
CPU_SENSE_V_R
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
GND_SMU_AVSS
DAVDD
DAVDD
MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
CPU_TEMP
MIN_NECK_WIDTH=10 mil
TD110
MIN_NECK_WIDTH=10 mil10CPU_TEMP_R
ADC_REF
TD310
MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
10
10
MIN_NECK_WIDTH=10 mil
TD2
DAGND
DAGND
DAGND
ADC_REF
DAGND
DAGND
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 DAVDD
PPVCORE_CPU
PPVCORE_CPU
CPUIMON_PHASE2_N
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
CPU_SENSE_I
TDIODE_POS
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=10 mil
CPU_TDIODE_POS
TDIODE_NEG CPU_TDIODE_NEGMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=8 mil
32
32
31
31
32
32
32
30
30
19
32
32
19
19
29
29
17
31
31
17
17
27
27
32
5
32
5
32
32
32
32
32
13
5
13
32
32
31
5
5
31
13
13
32
32
13
32
32
32
32
32
32
32
32
5
5
13
29
29
Preliminary
www.vinafix.vn
INTERFACEDATA
MEMORY
DDR_DQ5
DDR_DQ0DDR_DQ1
DDR_DQ2
DDR_DQ3DDR_DQ4
DDR_DQ6DDR_DQ7
DDR_DQ8DDR_DQ9
DDR_DQ10
DDR_DQ11DDR_DQ12
DDR_DQ13
DDR_DQ14DDR_DQ15
DDR_DQ16
DDR_DQ26DDR_DQ25
DDR_DQ24
DDR_DQ23DDR_DQ22
DDR_DQ21
DDR_DQ20DDR_DQ19
DDR_DQ18DDR_DQ17
DDR_DQ36
DDR_DQ35
DDR_DQ34DDR_DQ33
DDR_DQ32
DDR_DQ31DDR_DQ30
DDR_DQ29DDR_DQ28
DDR_DQ27
DDR_DQ46
DDR_DQ45DDR_DQ44
DDR_DQ43
DDR_DQ42DDR_DQ41
DDR_DQ40DDR_DQ39
DDR_DQ38
DDR_DQ37
DDR_DQ47DDR_DQ48
DDR_DQ49
DDR_DQ50DDR_DQ51
DDR_DQ52DDR_DQ53
DDR_DQ54
DDR_DQ55DDR_DQ56
DDR_DQ57
DDR_DQ58DDR_DQ59
DDR_DQ60
DDR_DQ61DDR_DQ62
DDR_DQ63
VDD_DDR
(SYM 2 OF 7) DDR_DQ64DDR_DQ65
DDR_DQ69
DDR_DQ68DDR_DQ67
DDR_DQ66
DDR_DQ70
DDR_DQ74
DDR_DQ73DDR_DQ72
DDR_DQ71
DDR_DQ75
DDR_DQ79DDR_DQ78
DDR_DQ77
DDR_DQ76
DDR_DQ80
DDR_DQ81DDR_DQ82
DDR_DQ83
DDR_DQ85
DDR_DQ84
DDR_DQ90DDR_DQ89
DDR_DQ88
DDR_DQ87DDR_DQ86
DDR_DQ95DDR_DQ94
DDR_DQ93DDR_DQ92
DDR_DQ91
DDR_DQ99
DDR_DQ98DDR_DQ97
DDR_DQ96
DDR_DQ100
DDR_DQ104
DDR_DQ105DDR_DQ106
DDR_DQ107
DDR_DQ108DDR_DQ109
DDR_DQ110
DDR_DQ103
DDR_DQ102
DDR_DQ101
DDR_DQ111DDR_DQ112
DDR_DQ113
DDR_DQ114DDR_DQ115
DDR_DQ116DDR_DQ117
DDR_DQ118
DDR_DQ119DDR_DQ120
DDR_DQ121
DDR_DQ127
DDR_DQ126DDR_DQ125
DDR_DQ124
DDR_DQ123DDR_DQ122
DDR_VREF7
DDR_VREF6DDR_VREF5
DDR_VREF4
DDR_VREF3
INTERFACECONTROLMEMORY
DDRCLK_AVDD
VDD_DDR
(SYM 3 OF 7)
DDR_CK_DDDR_CK_CN
DDR_CK_C
DDR_CK_BNDDR_CK_B
DDR_CK_ANDDR_CK_A
DDR_CK_DN
DDR_CK_EN
DDR_CK_FN
DDR_CK_F
DDR_CK_E
DDR_CLKP
DDR_CKE7DDR_CKE6
DDR_CKE5
DDR_CKE4DDR_CKE3
DDR_CKE1
DDR_CKE2
DDR_CKE0
DDR_VREF1
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA1DDR_BA0
DDR_MUXEN0
DDR_MAD5
DDR_MAD4DDR_MAD3
DDR_MAD2
DDR_MAD1DDR_MAD0
DDR_MUXEN4
DDR_MAD9DDR_MAD8
DDR_MAD6
DDR_MAD7
DDR_MAD13
DDR_MAD12DDR_MAD11
DDR_MAD10
DDR_CS1
DDR_CS0
DDR_CS2
DDR_CS8
DDR_CS3
DDR_CS11
DDR_CS10
DDR_CS9
DDR_DQSP1
DDR_DQSP0
DDR_DQSP2
DDR_DQSP3
DDR_DQSP8
DDR_DQSP7DDR_DQSP6
DDR_DQSP9DDR_DQSP10
DDR_DQSP11
DDR_DQSP12
DDR_DQSP4
DDR_DQSP5
DDR_DQSP13
DDR_DQSP15DDR_DQSP14
DDR_CLK_AVSS
DDR_VREF2
DDR_VREF0
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
MASTER: GILA
U3LITE MEMORY
U3TWINS DO NOT HAVE MASKS
2
1 C3713
402
0.1UF20%10VCERM2
1 C3712
CERM10V20%0.1UF
4022
1 C3711
402
0.1UF20%10VCERM2
1 C3710
CERM10V20%0.1UF
4022
1 C3709
402
0.1UF20%10VCERM2
1 C3708
CERM10V20%0.1UF
4022
1 C3707
402
0.1UF20%10VCERM2
1 C3706
CERM10V20%0.1UF
4022
1 C3705
402
0.1UF20%10VCERM2
1 C3704
CERM10V20%0.1UF
4022
1 C3703
402
0.1UF20%10VCERM2
1 C3702
CERM10V20%0.1UF
4022
1 C3701
402
0.1UF20%10VCERM2
1 C370010V20%
402CERM
0.1UF2
1 C3714
CERM10V20%0.1UF
402
2
1 C3729
CERM10V20%0.1UF
4022
1 C3728
402
0.1UF20%10VCERM2
1 C3727
CERM10V20%0.1UF
4022
1 C3726
402
0.1UF20%10VCERM2
1 C3725
CERM10V20%0.1UF
4022
1 C3724
402
0.1UF20%10VCERM2
1 C3722
402
0.1UF20%10VCERM2
1 C3721
CERM10V20%0.1UF
4022
1 C3720
402
0.1UF20%10VCERM2
1 C3719
CERM10V20%0.1UF
4022
1 C3718
402
0.1UF20%10VCERM2
1 C3717
CERM10V20%0.1UF
4022
1 C3716
402
0.1UF20%10VCERM2
1 C371510V20%
402CERM
0.1UF
2
1 C3731
402
0.1UF20%10VCERM 2
1 C3732
CERM10V20%0.1UF
4022
1 C3733
CERM10V20%0.1UF
4022
1 C3734
CERM10V20%0.1UF
4022
1 C3735
CERM10V20%0.1UF
402
2
1 C3730
CERM10V20%0.1UF
402
2
1 C3736
CERM10V20%0.1UF
4022
1 C3737
CERM10V20%0.1UF
402
2
1 C3738
402
0.1UF20%10VCERM2
1 C3739
402
0.1UF20%10VCERM2
1 C3740
402
0.1UF20%10VCERM2
1 C3742
402
0.1UF20%10VCERM2
1 C3743
402
0.1UF20%10VCERM
21
R3702
5%
603MF
1/16W
2.2
2
1 C37440.1UF20%10VCERM402
2
1R3700
402MF
1%1K
1/16W
2
1 C3745
CERM6.3V10%1UF
402
2
1 C3746
402
20%10VCERM
0.1UF2
1 C3747
402
0.1UF20%10VCERM 2
1 C3748
402
0.1UF20%10VCERM
2
1R3701
MF1/16W
1%1K
402
AA16
AA13
AB25
AC19
AE27
AE22
AE16
AE13
V20
W27
W23
Y19
Y16
AG25
AG19
P27
R28R26
R27
U26T28
V28
U27W28
V24
AH25
V27V26
Y24Y28
Y25
Y26AA28
AA24
AA26AA27
AH26
AD27
AC27AC25
AC26AF27
AD26
AE28AF28
AG28
AD25
AD21
AD24
AF26
AG26AE24
AF24AG27
H22
G21
H21J21
AD23
H23
E23J22
F24A26
B28
A28A27
A24
A23
AC21
B23
B24
C23C24
A25A22
C27
C26D24
D23
AB20
J23L23
L22
M24P22
P21M23
M25
P23P24
AG21
R24
P26U23
R21
R22P25
U22V22
V23
U24
AH21
AA22
Y22
AA23U25
AH28
AF23AG24
E24
E25
C28D28
E26
F26E27
E28
AH27
H26
F27
H24H25
G28
J26J24
J25
L24J27
AH23
H28H27
K28
L27L26
L25
P28L28
N28
M28
AH24
AH22AF20
U3
PBGA
OMIT
V1.0-300MMU3LITE
B25
D27
D22
F19
G25
K27
K23
K19
M19
N25
N21
P20
T25
T21
T19
AC23
J20
V21M21
AA21
H20L21
U21
Y21
AE21
AH18AH16
AF15AG15
AC12
AD12AE12
AF12
AH15AH14
AG17
AH17
AG14AF14
AH13
AG12
AD28AE23
F23B27
B26
M22R23
Y23
F25F28
J28
M27U28
Y27
AG23AC24
AD18AC18
AH20
AG20
AH19AG18
AE18
AF18
AA20
AB21
AC20
AB15AA15
AC15
AD15AD14
AC14AE14
AE15
AA14AB14
AB12
AA12
AA18
AB18AA17
AB17AF17
AE17
AD17AC17
AD20
AE20AF21
U3
OMIT
V1.0-300MMU3LITE
PBGA
03
37 103
051-6532
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
VOLTAGE=1.25VPP1V25_PWRON_RAM_VREF_NB
RAM_CLK_E_N_R
PP1V5_PWRON_RAM_NB_AVDDVOLTAGE=1.5V
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MIL
RAM_DQ_R<64>
RAM_DQ_R<71>
RAM_DQ_R<75>
RAM_DQS_R<15>RAM_DQS_R<14>
RAM_DQS_R<12>RAM_DQS_R<13>
RAM_DQS_R<11>
RAM_DQS_R<9>RAM_DQS_R<10>
RAM_DQS_R<8>RAM_DQS_R<7>RAM_DQS_R<6>RAM_DQS_R<5>RAM_DQS_R<4>RAM_DQS_R<3>RAM_DQS_R<2>RAM_DQS_R<1>RAM_DQS_R<0>
RAM_CS_L_R<9>RAM_CS_L_R<8>
RAM_CS_L_R<1>RAM_CS_L_R<0>
RAM_A_R<13>RAM_A_R<12>RAM_A_R<11>RAM_A_R<10>RAM_A_R<9>RAM_A_R<8>RAM_A_R<7>
RAM_A_R<3>RAM_A_R<4>
RAM_A_R<2>RAM_A_R<1>RAM_A_R<0>
RAM_BA_R<0>
RAM_WE_L_R
RAM_CAS_L_R
RAM_RAS_L_R
RAM_DQ_R<127>RAM_DQ_R<126>
RAM_DQ_R<124>RAM_DQ_R<125>
RAM_DQ_R<121>
RAM_DQ_R<123>RAM_DQ_R<122>
RAM_DQ_R<119>RAM_DQ_R<120>
RAM_DQ_R<117>RAM_DQ_R<118>
RAM_DQ_R<116>
RAM_DQ_R<114>RAM_DQ_R<115>
RAM_DQ_R<111>
RAM_DQ_R<113>RAM_DQ_R<112>
RAM_DQ_R<110>RAM_DQ_R<109>RAM_DQ_R<108>RAM_DQ_R<107>RAM_DQ_R<106>
RAM_DQ_R<104>RAM_DQ_R<105>
RAM_DQ_R<103>
RAM_DQ_R<101>RAM_DQ_R<102>
RAM_DQ_R<99>RAM_DQ_R<98>
RAM_DQ_R<100>
RAM_DQ_R<96>RAM_DQ_R<97>
RAM_DQ_R<94>RAM_DQ_R<95>
RAM_DQ_R<93>
RAM_DQ_R<91>RAM_DQ_R<92>
RAM_DQ_R<89>RAM_DQ_R<90>
RAM_DQ_R<88>
RAM_DQ_R<86>RAM_DQ_R<87>
RAM_DQ_R<85>RAM_DQ_R<84>RAM_DQ_R<83>
RAM_DQ_R<81>RAM_DQ_R<80>
RAM_DQ_R<82>
RAM_DQ_R<79>
RAM_DQ_R<76>RAM_DQ_R<77>
RAM_DQ_R<74>RAM_DQ_R<73>
RAM_DQ_R<70>
RAM_DQ_R<72>
RAM_DQ_R<69>RAM_DQ_R<68>
RAM_DQ_R<65>
RAM_DQ_R<67>
RAM_DQ_R<59>
RAM_DQ_R<0>
RAM_DQ_R<5>
RAM_DQ_R<3>RAM_DQ_R<2>
RAM_DQ_R<4>
RAM_DQ_R<10>
RAM_DQ_R<6>RAM_DQ_R<7>RAM_DQ_R<8>RAM_DQ_R<9>
RAM_DQ_R<11>
RAM_DQ_R<15>
RAM_DQ_R<12>RAM_DQ_R<13>RAM_DQ_R<14>
RAM_DQ_R<16>
RAM_DQ_R<21>RAM_DQ_R<20>RAM_DQ_R<19>
RAM_DQ_R<17>RAM_DQ_R<18>
RAM_DQ_R<26>
RAM_DQ_R<22>RAM_DQ_R<23>RAM_DQ_R<24>RAM_DQ_R<25>
RAM_DQ_R<31>
RAM_DQ_R<27>RAM_DQ_R<28>RAM_DQ_R<29>RAM_DQ_R<30>
RAM_DQ_R<36>
RAM_DQ_R<32>RAM_DQ_R<33>RAM_DQ_R<34>RAM_DQ_R<35>
RAM_DQ_R<41>
RAM_DQ_R<37>RAM_DQ_R<38>RAM_DQ_R<39>RAM_DQ_R<40>
RAM_DQ_R<46>RAM_DQ_R<45>RAM_DQ_R<44>RAM_DQ_R<43>RAM_DQ_R<42>
RAM_DQ_R<51>
RAM_DQ_R<47>RAM_DQ_R<48>RAM_DQ_R<49>RAM_DQ_R<50>
RAM_DQ_R<52>
RAM_DQ_R<56>RAM_DQ_R<55>RAM_DQ_R<54>RAM_DQ_R<53>
RAM_DQ_R<57>
RAM_DQ_R<60>
RAM_DQ_R<58>
RAM_DQ_R<61>RAM_DQ_R<62>RAM_DQ_R<63>
RAM_DQ_R<1>RAM_DQ_R<66>
RAM_CKE_R<7>
RAM_BA_R<1>
RAM_MUXEN4RAM_MUXEN0
RAM_CS_L_R<3>RAM_CS_L_R<2>
RAM_CS_L_R<11>RAM_CS_L_R<10>
RAM_CKE_R<5>
RAM_CKE_R<1>
RAM_CLK_F_P_R
RAM_CLK_E_P_R
RAM_CKE_R<0>
RAM_CKE_R<4>
RAM_CKE_R<6>
RAM_CKE_R<3>
RAM_CLK_D_N_R
RAM_CLK_C_N_RRAM_CLK_D_P_R
RAM_CLK_C_P_R
RAM_CLK_A_N_R
RAM_CLK_B_N_RRAM_CLK_B_P_R
PP1V5_PWRON_NB_AVDD
RAM_CKE_R<2>
RAM_CLK_F_N_R
RAM_DQ_R<78>
RAM_A_R<5>
RAM_CLK_A_P_R
RAM_CLK66M_NB
RAM_A_R<6>
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
43 36
33
33
33
33
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
26
62
62
62
62
24
24
24
24
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
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34
34
34
34
34
34
34
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34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
5
34
5
5
5
5
5
5
34
34
34
34
34
34
5
5
34
34
34
34
34
34
34
5
5
34
34
34
34
25
34
5
5
5
5 Preliminary
www.vinafix.vn
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ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
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ALIAS
ALIAS
ALIAS
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ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
into self refresh during sleepCKE pulldowns to put RAM
Series Termination for Clock/Control Signals
RPAKs can be swapped if the 3rd number in reference designator (RP38x0) is the same.
BA
CNTL
CS
CKE
ADDR
CLOCKS
DIMM "B"
No series termination on data signals
DIMM "A"
No series termination on strobe signals
NOTE: SO-DIMMs only use 2 of the 3 clocks
(NONE)
Signal aliases required by this page:
(NONE)
Page NotesPower aliases required by this page:
Memory Series Term
(NONE)
Unused clocks renamed below. provided for each DIMM module.
BOM options provided by this page:
63
RP3801
SM1
22
1/16W5%
54
RP3801
5%1/16WSM1
22
81
RP3801
1/16W
22
SM1
5%
72
RP380122
SM1
5%1/16W
72
RP3810
1/16W
22
SM1
5%
81
RP381022
SM11/16W5%
63
RP3810
SM1
5%1/16W
22
54
RP3810
SM1
5%1/16W
22
54
RP3820
SM1
5%1/16W
22
63
RP3820
SM1
5%1/16W
22
81
RP3820
5%1/16WSM1
22
72
RP3820
SM1
22
1/16W5%
72
RP383022
SM11/16W5%
54
RP3830
5%1/16WSM1
22
81
RP3830
1/16W5%
SM1
22
63
RP383022
SM11/16W5%
72
RP3831
5%1/16WSM1
22
81
RP383122
SM11/16W5%
63
RP3831
SM1
22
1/16W5%
54
RP3831
SM1
5%1/16W
22
63
RP3832
SM1
5%1/16W
22
54
RP3832
SM1
22
1/16W5%
81
RP3832
SM1
22
1/16W5%
72
RP3832
SM1
22
1/16W5%
54
RP3833
SM11/16W5%
22
72
RP3833
SM1
5%1/16W
22
81
RP3833
SM1
22
5%1/16W
21
R3841
5%1/16WMF402
22
21
R3842
402
22
MF1/16W5%
63
RP383322
SM11/16W5%
21
R3840
5%1/16WMF402
22
72
RP3850
SM11/16W5%
10K
54
RP385010K
5%1/16WSM1
81
RP3850
1/16WSM1
5%
10K
63
RP385010K
5%1/16WSM1
81
RP3800
SM1
5%1/16W
22
72
RP3800
SM1
22
1/16W5%
54
RP3800
SM1
22
1/16W5%
63
RP3800
5%1/16WSM1
22
38 103051-6532 03
RAM_CKE<5>
RAM_CKE<4>
RAM_CLK_E_N_R
RAM_CLK_A_N
RAM_CLK_A_P_R
RAM_CLK_B_P_R
RAM_CS_L_R<9>
RAM_CLK_C_N_RMAKE_BASE=TRUE
TP_RAM_CLK_C_N
RAM_CLK_F_P_RMAKE_BASE=TRUE
TP_RAM_CLK_F_P
RAM_CLK_F_N_RMAKE_BASE=TRUE
TP_RAM_CLK_F_N
RAM_CLK_C_P_RMAKE_BASE=TRUE
TP_RAM_CLK_C_P
RAM_DQS<1>MAKE_BASE=TRUE
RAM_DQS_R<1>
RAM_DQS<0>MAKE_BASE=TRUE
RAM_DQS_R<0>
MAKE_BASE=TRUERAM_DQS<2>RAM_DQS_R<2>
MAKE_BASE=TRUERAM_DQS<3>RAM_DQS_R<3>
RAM_DQS<4>MAKE_BASE=TRUE
RAM_DQS_R<4>
RAM_DQS<5>MAKE_BASE=TRUE
RAM_DQS_R<5>
RAM_DQS<6>MAKE_BASE=TRUE
RAM_DQS_R<6>
RAM_DQS<8>MAKE_BASE=TRUE
RAM_DQS_R<8>
RAM_DQS<7>MAKE_BASE=TRUE
RAM_DQS_R<7>
RAM_DQS<9>MAKE_BASE=TRUE
RAM_DQS_R<9>
RAM_DQS<10>MAKE_BASE=TRUE
RAM_DQS_R<10>
RAM_DQS<11>MAKE_BASE=TRUE
RAM_DQS_R<11>
RAM_DQS<12>MAKE_BASE=TRUE
RAM_DQS_R<12>
RAM_DQS<13>MAKE_BASE=TRUE
RAM_DQS_R<13>
RAM_DQS<14>MAKE_BASE=TRUE
RAM_DQS_R<14>
RAM_DQS<15>MAKE_BASE=TRUE
RAM_DQS_R<15>
MAKE_BASE=TRUERAM_DQ<62>RAM_DQ_R<62>
MAKE_BASE=TRUERAM_DQ<63>RAM_DQ_R<63>
MAKE_BASE=TRUERAM_DQ<61>RAM_DQ_R<61>MAKE_BASE=TRUE
RAM_DQ<60>RAM_DQ_R<60>MAKE_BASE=TRUE
RAM_DQ<59>RAM_DQ_R<59>MAKE_BASE=TRUE
RAM_DQ<58>RAM_DQ_R<58>
MAKE_BASE=TRUERAM_DQ<55>RAM_DQ_R<55>
MAKE_BASE=TRUERAM_DQ<57>RAM_DQ_R<57>MAKE_BASE=TRUE
RAM_DQ<56>RAM_DQ_R<56>
MAKE_BASE=TRUERAM_DQ<53>RAM_DQ_R<53>
MAKE_BASE=TRUERAM_DQ<54>RAM_DQ_R<54>
MAKE_BASE=TRUERAM_DQ<52>RAM_DQ_R<52>MAKE_BASE=TRUE
RAM_DQ<51>RAM_DQ_R<51>
MAKE_BASE=TRUERAM_DQ<49>RAM_DQ_R<49>MAKE_BASE=TRUE
RAM_DQ<48>RAM_DQ_R<48>
MAKE_BASE=TRUERAM_DQ<50>RAM_DQ_R<50>
MAKE_BASE=TRUERAM_DQ<45>RAM_DQ_R<45>
MAKE_BASE=TRUERAM_DQ<47>RAM_DQ_R<47>MAKE_BASE=TRUE
RAM_DQ<46>RAM_DQ_R<46>
MAKE_BASE=TRUERAM_DQ<44>RAM_DQ_R<44>MAKE_BASE=TRUE
RAM_DQ<43>RAM_DQ_R<43>MAKE_BASE=TRUE
RAM_DQ<42>RAM_DQ_R<42>MAKE_BASE=TRUE
RAM_DQ<41>RAM_DQ_R<41>
MAKE_BASE=TRUERAM_DQ<39>RAM_DQ_R<39>MAKE_BASE=TRUE
RAM_DQ<38>RAM_DQ_R<38>
MAKE_BASE=TRUERAM_DQ<40>RAM_DQ_R<40>
MAKE_BASE=TRUERAM_DQ<37>RAM_DQ_R<37>MAKE_BASE=TRUE
RAM_DQ<36>RAM_DQ_R<36>MAKE_BASE=TRUE
RAM_DQ<35>RAM_DQ_R<35>MAKE_BASE=TRUE
RAM_DQ<34>RAM_DQ_R<34>
MAKE_BASE=TRUERAM_DQ<31>RAM_DQ_R<31>
MAKE_BASE=TRUERAM_DQ<32>RAM_DQ_R<32>
MAKE_BASE=TRUERAM_DQ<33>RAM_DQ_R<33>
MAKE_BASE=TRUERAM_DQ<29>RAM_DQ_R<29>
MAKE_BASE=TRUERAM_DQ<30>
MAKE_BASE=TRUERAM_DQ<27>RAM_DQ_R<27>
RAM_DQ_R<28>
MAKE_BASE=TRUERAM_DQ<25>RAM_DQ_R<25>MAKE_BASE=TRUE
RAM_DQ<24>RAM_DQ_R<24>
MAKE_BASE=TRUERAM_DQ<26>RAM_DQ_R<26>
MAKE_BASE=TRUERAM_DQ<21>RAM_DQ_R<21>
MAKE_BASE=TRUERAM_DQ<23>RAM_DQ_R<23>MAKE_BASE=TRUE
RAM_DQ<22>RAM_DQ_R<22>
MAKE_BASE=TRUERAM_DQ<20>RAM_DQ_R<20>MAKE_BASE=TRUE
RAM_DQ<19>RAM_DQ_R<19>MAKE_BASE=TRUE
RAM_DQ<18>RAM_DQ_R<18>
RAM_DQ_R<17>
RAM_DQ<14>MAKE_BASE=TRUE
RAM_DQ_R<14>
RAM_DQ_R<16>MAKE_BASE=TRUE
RAM_DQ<15>RAM_DQ_R<15>
MAKE_BASE=TRUERAM_DQ<13>RAM_DQ_R<13>MAKE_BASE=TRUE
RAM_DQ<12>RAM_DQ_R<12>MAKE_BASE=TRUE
RAM_DQ<11>RAM_DQ_R<11>MAKE_BASE=TRUE
RAM_DQ<10>RAM_DQ_R<10>
MAKE_BASE=TRUERAM_DQ<7>RAM_DQ_R<7>
MAKE_BASE=TRUERAM_DQ<8>RAM_DQ_R<8>
MAKE_BASE=TRUERAM_DQ<9>RAM_DQ_R<9>
MAKE_BASE=TRUERAM_DQ<4>RAM_DQ_R<4>
MAKE_BASE=TRUERAM_DQ<6>RAM_DQ_R<6>MAKE_BASE=TRUE
RAM_DQ<5>RAM_DQ_R<5>
MAKE_BASE=TRUERAM_DQ<3>RAM_DQ_R<3>MAKE_BASE=TRUE
RAM_DQ<2>RAM_DQ_R<2>
MAKE_BASE=TRUERAM_DQ<0>RAM_DQ_R<0>
MAKE_BASE=TRUERAM_DQ<1>RAM_DQ_R<1>
MAKE_BASE=TRUERAM_DQ<127>RAM_DQ_R<127>MAKE_BASE=TRUE
RAM_DQ<126>RAM_DQ_R<126>MAKE_BASE=TRUE
RAM_DQ<125>RAM_DQ_R<125>MAKE_BASE=TRUE
RAM_DQ<124>RAM_DQ_R<124>MAKE_BASE=TRUE
RAM_DQ<123>RAM_DQ_R<123>MAKE_BASE=TRUE
RAM_DQ<122>RAM_DQ_R<122>
MAKE_BASE=TRUERAM_DQ<119>RAM_DQ_R<119>
MAKE_BASE=TRUERAM_DQ<121>RAM_DQ_R<121>MAKE_BASE=TRUE
RAM_DQ<120>RAM_DQ_R<120>
MAKE_BASE=TRUERAM_DQ<116>RAM_DQ_R<116>
MAKE_BASE=TRUERAM_DQ<117>RAM_DQ_R<117>
MAKE_BASE=TRUERAM_DQ<118>RAM_DQ_R<118>
MAKE_BASE=TRUERAM_DQ<115>RAM_DQ_R<115>
MAKE_BASE=TRUERAM_DQ<112>RAM_DQ_R<112>
MAKE_BASE=TRUERAM_DQ<113>RAM_DQ_R<113>
MAKE_BASE=TRUERAM_DQ<114>RAM_DQ_R<114>
MAKE_BASE=TRUERAM_DQ<111>RAM_DQ_R<111>MAKE_BASE=TRUE
RAM_DQ<110>RAM_DQ_R<110>MAKE_BASE=TRUE
RAM_DQ<109>RAM_DQ_R<109>MAKE_BASE=TRUE
RAM_DQ<108>RAM_DQ_R<108>
MAKE_BASE=TRUERAM_DQ<105>RAM_DQ_R<105>
MAKE_BASE=TRUERAM_DQ<106>RAM_DQ_R<106>
MAKE_BASE=TRUERAM_DQ<107>RAM_DQ_R<107>
MAKE_BASE=TRUERAM_DQ<104>RAM_DQ_R<104>MAKE_BASE=TRUE
RAM_DQ<103>RAM_DQ_R<103>MAKE_BASE=TRUE
RAM_DQ<102>RAM_DQ_R<102>
MAKE_BASE=TRUERAM_DQ<98>RAM_DQ_R<98>
MAKE_BASE=TRUERAM_DQ<100>RAM_DQ_R<100>
MAKE_BASE=TRUERAM_DQ<101>RAM_DQ_R<101>
MAKE_BASE=TRUERAM_DQ<99>RAM_DQ_R<99>
MAKE_BASE=TRUERAM_DQ<97>RAM_DQ_R<97>MAKE_BASE=TRUE
RAM_DQ<96>RAM_DQ_R<96>MAKE_BASE=TRUE
RAM_DQ<95>RAM_DQ_R<95>
MAKE_BASE=TRUERAM_DQ<92>RAM_DQ_R<92>MAKE_BASE=TRUE
RAM_DQ<91>RAM_DQ_R<91>
MAKE_BASE=TRUERAM_DQ<94>RAM_DQ_R<94>MAKE_BASE=TRUE
RAM_DQ<93>RAM_DQ_R<93>
MAKE_BASE=TRUERAM_DQ<90>RAM_DQ_R<90>
MAKE_BASE=TRUERAM_DQ<88>RAM_DQ_R<88>
MAKE_BASE=TRUERAM_DQ<89>RAM_DQ_R<89>
MAKE_BASE=TRUERAM_DQ<85>
MAKE_BASE=TRUERAM_DQ<87>RAM_DQ_R<87>MAKE_BASE=TRUE
RAM_DQ<86>RAM_DQ_R<86>
MAKE_BASE=TRUERAM_DQ<84>RAM_DQ_R<84>MAKE_BASE=TRUE
RAM_DQ<83>RAM_DQ_R<83>
MAKE_BASE=TRUERAM_DQ<81>RAM_DQ_R<81>
MAKE_BASE=TRUERAM_DQ<82>RAM_DQ_R<82>
MAKE_BASE=TRUERAM_DQ<79>RAM_DQ_R<79>
MAKE_BASE=TRUERAM_DQ<80>RAM_DQ_R<80>
MAKE_BASE=TRUERAM_DQ<78>RAM_DQ_R<78>
MAKE_BASE=TRUERAM_DQ<75>RAM_DQ_R<75>
MAKE_BASE=TRUERAM_DQ<77>RAM_DQ_R<77>MAKE_BASE=TRUE
RAM_DQ<76>RAM_DQ_R<76>
MAKE_BASE=TRUERAM_DQ<74>RAM_DQ_R<74>
MAKE_BASE=TRUERAM_DQ<71>RAM_DQ_R<71>
MAKE_BASE=TRUERAM_DQ<72>RAM_DQ_R<72>
MAKE_BASE=TRUERAM_DQ<73>RAM_DQ_R<73>
MAKE_BASE=TRUERAM_DQ<70>RAM_DQ_R<70>MAKE_BASE=TRUE
RAM_DQ<69>RAM_DQ_R<69>MAKE_BASE=TRUE
RAM_DQ<68>RAM_DQ_R<68>
RAM_DQ<67>MAKE_BASE=TRUE
RAM_DQ_R<67>
MAKE_BASE=TRUERAM_DQ<65>RAM_DQ_R<65>
RAM_DQ<64>MAKE_BASE=TRUE
RAM_DQ_R<64>
MAKE_BASE=TRUERAM_DQ<66>RAM_DQ_R<66>
RAM_CLK_E_N
RAM_CLK_E_P_R RAM_CLK_E_P
RAM_CLK_D_N_R RAM_CLK_D_N
RAM_CLK_B_N_R RAM_CLK_B_N
RAM_CLK_A_N_R
RAM_CLK_D_P_R RAM_CLK_D_P
RAM_CLK_A_P
RAM_A_R<9> RAM_A<9>
RAM_A<12>
RAM_A_R<10> RAM_A<10>
RAM_A_R<8> RAM_A<8>
RAM_A_R<7> RAM_A<7>
RAM_A_R<5> RAM_A<5>
RAM_A_R<1> RAM_A<1>
RAM_A_R<6> RAM_A<6>
RAM_A_R<4> RAM_A<4>
RAM_A<2>
RAM_CS_L<9>
RAM_A_R<0> RAM_A<0>
RAM_CS_L_R<8> RAM_CS_L<8>
RAM_CS_L_R<1> RAM_CS_L<1>
RAM_CS_L_R<0> RAM_CS_L<0>
RAM_A_R<12>
RAM_A_R<11> RAM_A<11>
RAM_A_R<13>
RAM_BA_R<0> RAM_BA<0>
RAM_BA_R<1> RAM_BA<1>
RAM_WE_L_R RAM_WE_L
RAM_CAS_L_R
RAM_RAS_LRAM_RAS_L_R
RAM_A<3>
RAM_A_R<2>
RAM_CLK_B_P
MAKE_BASE=TRUERAM_DQ<16>
MAKE_BASE=TRUERAM_DQ<17>
RAM_DQ_R<85>
MAKE_BASE=TRUERAM_DQ<28>
RAM_DQ_R<30>
RAM_CAS_L
RAM_A<13>
RAM_CKE_R<5>
RAM_CKE_R<1>
RAM_CKE_R<4>
RAM_CKE_R<0>
RAM_A_R<3>
RAM_CKE<5>
RAM_CKE<1>
RAM_CKE<4>
RAM_CKE<0>
RAM_CKE<1>
RAM_CKE<0>
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34 Preliminary
www.vinafix.vn
DQ58
RFU18
KEY
VDD6VSS6
VSS8
VDD5
DQ15
DQ13
DQ14
VSS5
DM1
VDD3
VSS3
DQ7DQ12
DQ6
DM0
DQ4
DQ5
VSS1VREF1
VDD1
SA1SA2
RFU19
SA0
VDD32DQ63
DQ62VSS32
DQ61VDD30
DQ60
DQ55
DM7
VSS30
DQ54
DM6VDD28
DQ53DQ52
VDD25
CK1*CK1
VSS28
DQ47DQ46
VDD23
VSS25
DM5DQ45
DQ44
DM4
DQ39
VSS23DQ38
DQ37
RFU17
DQ36
VSS21
VDD21
VDD19
RAS*
BA1
CAS*S1*
A6
A4A2
A0
VSS19A8
A11
VDD17
RFU15
CKE0
VDD15
VSS17
RFU11VSS16
RFU9
VDD14
RFU3
VSS14RFU5
RFU7
RFU1VDD12
VSS12
DM3
DQ31
DQ30
DQ29
VSS10
VDD10
DQ28DQ23
DM2
DQ20
VDD8
DQ21
DQ22
VDDSPDSCL
SDA
VDD31
VSS31
DQ59
DQS7
DQ51
VDD29
DQ56
VSS29
DQ57
DQ48
DQS6VDD27
DQ49
DQ50
DQ43
VSS26VDD26
VDD24
VSS27
DQ41DQS5
VSS24
VDD22
DQ42
DQ34VSS22
DQ35
DQS4
DQ40
VDD20
RFU16
DQ32
VSS20
DQ33
S0*
VDD18
BA0
A10_AP
WE*
A1
A5A3
A9
A7
VSS18
CKE1
RFU14
RFU13VDD16
VDD13
VSS15RFU10
RFU8
RFU12
RFU0
RFU4VSS13
RFU2
RFU6
VSS11DQ26
DQ27
DQS3
VDD11
DQ19DQ24
VDD9
VSS9
DQ25
DQ18
DQ16
VDD7
DQ17
DQS2
DQ11
VDD4
VSS7
CK0*CK0
DQS1
VSS4
DQ10
VDD2
DQ9
DQ2
DQS0
DQ8DQ3
VSS2
VDD0
DQ0
DQ1
VSS0VREF0
A12
DQ58
RFU18
KEY
VREF0
VDD0
DQ0
DQ1
VSS0
DQS0
VSS2
DQ3DQ8
DQ2
VDD2
VSS4
DQS1
DQ10
DQ9
DQ11
CK0CK0*
VSS7
VDD4
DQ16
DQ18
VDD7
DQ17
DQS2
VSS9
DQ25VDD9
DQ24DQ19
DQS3
VDD11
DQ27
DQ26VSS11
RFU0
VDD13
RFU4VSS13
RFU2
RFU6
RFU13
RFU12
RFU8
RFU10VSS15
A9
CKE1
RFU14
VDD16
A1
A5
A7
VSS18
A3
BA0
VDD18
S0*WE*
A10_AP
DQ33
VSS20
DQ32
VDD20
RFU16
DQS4
DQ34VSS22
DQ35
DQ40VDD22
DQ41DQS5
VSS24
DQ42DQ43
DQ48
VSS26VDD26
VDD24
VSS27
VSS29
DQ50
DQ49
DQS6VDD27
DQS7
DQ51
VDD29
DQ56
DQ57
SDA
VDD31
VSS31
DQ59
VDDSPDSCL
RFU19
VDD32
VSS28
CK1
DQ52
VDD28DM6
DQ54
VSS30
DM7
DQ55
DQ60
VDD30DQ61
DQ53
SA1SA2
SA0
DQ63
DQ62
VSS32
VSS25
DM5DQ45
VDD23
VDD21
VSS21
DQ36
RFU17
DQ44
DM4
DQ39
VSS23DQ38
DQ37
RAS*CAS*
S1*
DQ46DQ47
CK1*
VDD25
RFU7
RFU5
VDD14
VSS17
VDD15
CKE0RFU15
VDD17
A11
A8
RFU11VSS16
RFU9
VSS19
A0
A2A4
A6
BA1VDD19
VDD12
VSS12
DQ31
DQ30
DM3
DQ22
DQ21
VDD8
DQ20
DQ29
VSS10
VDD10
DQ28
DQ23
DM2
VSS6
VSS8
RFU1
VSS14RFU3
VREF1
DQ5DQ4
DM0DQ6
DQ12DQ7
VSS3
VSS1
VDD1
VDD3
DM1
VSS5DQ14
DQ13
DQ15
VDD5VDD6
A12
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
Customer Slot
Slot "A"Standard
NC
NC
DDR SODIMM CONNS
DDR VRefOne 0.1uF per connector
NC
NC
NCNC
NCNC
NCNC
NCNCNC
NC
NCNC
NC
NC
NC
NC516S0029
NC
Addr=0xA2(Wr)/0xA3(Rd)
NC
Slot "B"Reversed
NCNC
NCNC
NCNC
NC
NC
Addr=0xA0(Wr)/0xA1(Rd)NC
NC
NCNC
NC
NCNC
NCNC
NC
Factory Slot
NC
516S0028
Power aliases required by this page:- _PP2V5_PWRON_DIMM
(NONE)Signal aliases required by this page:
(NONE)BOM options provided by this page:
- _PPSPD_DIMM (2.5V - 3.3V)
Page Notes
Slot "A"(For return current)
DDR Bypass Caps
Slot "B"
2
1 C403120%
CERM
10uF6.3V
805
2
1 C401420%10VCERM402
0.1uF2
1 C401320%10VCERM402
0.1uF2
1 C4012
402CERM10V20%0.1uF
2
1 C4009
805
6.3V
10uF
CERM
20%
2
1 C4011
402CERM10V20%0.1uF
2
1 C400820%
CERM
10uF6.3V
805
2
1 C4010
402CERM10V20%0.1uF
2
1 C4019
402CERM10V20%0.1uF
2
1 C4018
402CERM10V20%0.1uF
2
1 C401720%10VCERM402
0.1uF2
1 C401620%10VCERM402
0.1uF2
1 C401520%10VCERM402
0.1uF
119
51
4039
38
2827
186185
174
16
173
162161
159
150149
138137
126125
15
104103
90
8887
7675
6463
52
43
21
197
57
4645
36
3433
192191
180
22
179
168167
157
156155
144143
132131
21
114113
9493
92
8281
7069
58
109
193
195
198
196
194
122121
8483
8079
7877
7473
200199
124123
9897
91
89
8685
7271
118
202
201
183
169
147
133
61
47
25
11
23
19
18
190
188
182
178
14
189
187
181
177
176
172
166
164
175
171
8
165
163
154
152
146
142
153
151
145
141
6
140
136
130
128
139
135
129
127
68
66
17
60
56
67
65
59
55
54
50
44
42
13
53
49
43
41
32
30
24
20
31
29
7
5
184
170
148
134
62
48
26
12
95 96
158
160
37
35
120
116
117
101 102
105 106
107 108
109 110
99 100
115
111 112
J4010F-RT-SM
AS0A42-D2S
CRITICAL
119
51
40 39
38
28 27
186 185
174
16
173
162 161
159
150 149
138 137
126 125
15
104 103
90
88 87
76 75
64 63
52
4 3
2 1
197
57
46 45
36
34 33
192 191
180
22
179
168 167
157
156 155
144 143
132 131
21
114 113
94 93
92
82 81
70 69
58
10 9
193
195
198
196
194
122 121
84 83
80 79
78 77
74 73
200 199
124 123
98 97
91
89
86 85
72 71
118
202
201
183
169
147
133
61
47
25
11
23
19
18
190
188
182
178
14
189
187
181
177
176
172
166
164
175
171
8
165
163
154
152
146
142
153
151
145
141
6
140
136
130
128
139
135
129
127
68
66
17
60
56
67
65
59
55
54
50
44
42
13
53
49
43
41
32
30
24
20
31
29
7
5
184
170
148
134
62
48
26
12
9596
158
160
37
35
120
116
117
101102
105106
107108
109110
99100
115
111112
J4020F-RT-SM
AS0A42-D2R
CRITICAL
2
1R40001K1%1/16WMF402
2
1R4001
402MF1/16W1%1K
2
1 C40010.1uF
402CERM10V20%
2
1 C40020.1uF
402CERM10V20%
2
1 C40290.1uF20%10VCERM402
2
1 C40280.1uF20%10VCERM402
2
1 C40240.1uF
402CERM10V20%
2
1 C40230.1uF
402CERM10V20%
2
1 C40220.1uF20%10VCERM402
2
1 C40210.1uF20%10VCERM402
2
1 C40270.1uF
402CERM10V20%
2
1 C40260.1uF
402CERM10V20%
2
1 C40200.1uF20%10VCERM402
2
1 C4030
805
6.3V
10uF
CERM
20%
2
1 C40250.1uF
402CERM10V20%
03051-653240 103
_PP2V5_PWRON_DIMM
_PP2V5_PWRON_DIMM
RAM_DQ<63>RAM_DQ<62>
RAM_DQ<61>
RAM_DQ<60>RAM_DQ<55>
RAM_DQ<52>
RAM_DQ<53>RAM_DQ<54>
RAM_CLK_B_PRAM_CLK_B_N
RAM_DQ<44>RAM_DQ<46>
RAM_DQ<45>
RAM_DQ<39>RAM_DQ<47>
RAM_DQ<38>
RAM_DQ<36>RAM_DQ<37>
RAM_CS_L<1>
RAM_RAS_LRAM_CAS_L
RAM_BA<1>
RAM_A<0>
RAM_A<4>RAM_A<2>
RAM_A<6>
RAM_A<8>RAM_A<11>
RAM_CKE<0>
RAM_DQ<31>RAM_DQ<30>
RAM_DQ<29>
RAM_DQ<28>RAM_DQ<23>
RAM_DQ<22>
RAM_DQ<21>RAM_DQ<20>
RAM_DQ<15>RAM_DQ<14>
RAM_DQ<13>
RAM_DQ<7>RAM_DQ<12>
RAM_DQ<6>
RAM_DQ<5>RAM_DQ<4>
RAM_VREF_DIMM
_PPSPD_DIMMI2C_DIMM_SCLI2C_DIMM_SDA
RAM_DQ<59>RAM_DQ<58>
RAM_DQS<7>RAM_DQ<57>
RAM_DQ<56>RAM_DQ<51>
RAM_DQS<6>RAM_DQ<50>
RAM_DQ<49>RAM_DQ<48>
RAM_DQ<43>
RAM_DQS<5>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQS<4>
RAM_DQ<33>RAM_DQ<32>
RAM_CS_L<0>
RAM_BA<0>RAM_WE_L
RAM_A<10>
RAM_A<1>
RAM_A<5>RAM_A<3>
RAM_A<7>
RAM_A<9>
RAM_CKE<1>
RAM_DQ<27>
RAM_DQS<3>
RAM_DQ<24>
RAM_DQ<25>
RAM_DQ<19>
RAM_DQ<18>RAM_DQS<2>
RAM_DQ<17>RAM_DQ<16>
RAM_CLK_A_PRAM_CLK_A_N
RAM_DQ<11>
RAM_DQS<1>
RAM_DQ<10>
RAM_DQ<3>RAM_DQ<8>
RAM_DQ<2>RAM_DQS<0>
RAM_DQ<1>
RAM_VREF_DIMM RAM_VREF_DIMM
RAM_DQ<64>RAM_DQ<65>
RAM_DQS<8>RAM_DQ<66>
RAM_DQ<67>RAM_DQ<72>
RAM_DQ<73>RAM_DQS<9>
RAM_DQ<74>RAM_DQ<75>
RAM_CLK_D_PRAM_CLK_D_N
RAM_DQ<80>RAM_DQ<81>
RAM_DQS<10>RAM_DQ<82>
RAM_DQ<88>RAM_DQ<83>
RAM_DQ<89>RAM_DQS<11>
RAM_DQ<90>RAM_DQ<91>
RAM_CKE<5>
RAM_A<9>
RAM_A<7>RAM_A<5>RAM_A<3>RAM_A<1>
RAM_A<10>RAM_BA<0>
RAM_CS_L<8>RAM_WE_L
RAM_DQ<96>RAM_DQ<97>
RAM_DQS<12>RAM_DQ<98>
RAM_DQ<99>RAM_DQ<104>
RAM_DQ<105>RAM_DQS<13>
RAM_DQ<106>RAM_DQ<107>
RAM_DQ<112>RAM_DQ<113>
RAM_DQ<114>RAM_DQS<14>
RAM_DQ<120>RAM_DQ<115>
RAM_DQS<15>RAM_DQ<121>
RAM_DQ<122>RAM_DQ<123>
I2C_DIMM_SDAI2C_DIMM_SCL_PPSPD_DIMM
_PPSPD_DIMM
RAM_DQ<124>
RAM_DQ<127>
RAM_DQ<125>
RAM_DQ<126>RAM_DQ<119>
RAM_DQ<118>
RAM_DQ<116>
RAM_CLK_E_PRAM_CLK_E_N
RAM_DQ<109>
RAM_DQ<108>RAM_DQ<103>
RAM_DQ<110>RAM_DQ<111>
RAM_DQ<102>
RAM_DQ<101>RAM_DQ<100>
RAM_CAS_LRAM_RAS_L
RAM_CS_L<9>
RAM_A<4>
RAM_A<0>
RAM_A<6>
RAM_A<8>RAM_A<11>
RAM_A<2>
RAM_BA<1>
RAM_CKE<4>
RAM_DQ<95>RAM_DQ<94>
RAM_DQ<93>
RAM_DQ<92>RAM_DQ<87>
RAM_DQ<86>
RAM_DQ<85>RAM_DQ<84>
RAM_DQ<79>RAM_DQ<78>
RAM_DQ<77>
RAM_DQ<76>RAM_DQ<71>
RAM_DQ<70>
RAM_DQ<69>RAM_DQ<68>
RAM_VREF_DIMM
_PP2V5_PWRON_DIMM _PP2V5_PWRON_DIMM _PP2V5_PWRON_DIMM
RAM_VREF_DIMM
_PP2V5_PWRON_DIMM
RAM_A<12>RAM_A<13>
RAM_A<12>RAM_A<13>
RAM_DQ<0>
RAM_DQ<9>
RAM_DQ<26>
RAM_DQ<41>
RAM_DQ<34>
RAM_DQ<35>
RAM_DQ<117>
_PP2V5_PWRON_DIMM
62
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62 62
62
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18
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5
5
34
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34
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5
Preliminary
www.vinafix.vn
S
D
G
AGPREFCLK_AVDD
VDD_AGP
AGP_CBE2
AGP_AD_STBS0AGP_AD_STBF0
AGP_DBI_LO
AGP_CBE1
AGP_CBE0
AGP_SB_STBS
AGP_SB_STBF
AGP_AD_STBS1
AGP_AD_STBF1
AGP_DBI_HI
AGP_CBE3
AGP_STOP
AGP_REQ
AGP_DEVSELAGP_FRAME
AGP_GNTAGP_IRDY
AGP_TRDY
AGP_PAR
AGP_ST0
AGP_ST1
AGP_ST2
AGP_RBFAGP_WBF
AGP_GC_AGP8X_DETAGP_TYPEDET
AGP_AD0AGP_AD1
AGP_AD2
AGP_AD3AGP_AD4
AGP_AD5
AGP_AD6AGP_AD7
AGP_AD9AGP_AD8
AGP_AD15
AGP_AD16
AGP_AD12AGP_AD11
AGP_AD10
AGP_AD13
AGP_AD14
AGP_AD21AGP_AD20
AGP_AD19
AGP_AD18AGP_AD17
AGP_AD26
AGP_AD25
AGP_AD24AGP_AD23
AGP_AD22
AGP_AD27
AGP_SBA2
AGP_SBA3
AGP_AD31
AGP_AD30
AGP_AD29AGP_AD28
AGP_SBA1
AGP_SBA0
AGP_SBA4
AGP_STP_AGP*AGP_BUSY*
AGP_REFCLK
AGP_SBA5
AGP_SBA6AGP_SBA7
AGP_VREFCG
AGP_PVTREF2
AGP_PVTREF1
AGP_VREFGC
AGP_MB_AGP8X_DET
AGP_REFCLK_AVSS
(SYM 4 OF 7)
AGPINTERFACE
G
D
SG
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
AGP BUSY AND STOP ARE NOT USED IN ALL DESIGNS
LEVEL SHIFTER FOR U3LITE
FOR CONSTRAINTSGROUPS WITH STROBE1DBIHI AND DBILO
U3LITE AGP
DIFFERENTIAL_PAIRELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPENET_PHYSICAL_TYPE
MASTER: GILA
PVTREF RESISTOR
DBI_HI IS NOT A STROBE BUT SHARES THE SAME TOPOLOGY AS A STROBE
2
1 C4808
CERM10V20%0.1UF
402
2
1R4811
402MF1/16W5%10K
AGP_BUSYSTOP
2
1R48121/16W
402
10K5%
MF
2
1R48085%10K1/16WMF402
AGP_BUSYSTOP
2
1R4810
MF402
10K5%1/16W
2
3
1 Q48022N3904SM
AGP_BUSYSTOP
2
1
3
Q48032N7002SM
AGP_BUSYSTOP2
1R4809
MF
10K5%1/16W
402
2
1 C4807
402
0.1UF20%10VCERM
21
R4813
5%
402MF
1/16W
1K
AGP_BUSYSTOP
2
1R4807
402MF1/16W5%10K
2
1 C4806
CERM10V20%0.1UF
4022
1 C4805
402
0.1UF20%10VCERM2
1 C4804
CERM10V20%0.1UF
4022
1 C4803
402
0.1UF20%10VCERM2
1 C4802
CERM10V20%0.1UF
4022
1 C4801
402
0.1UF20%10VCERM2
1 C480010V20%
402CERM
0.1UF
21
R4800
603
5%
2.2
1/16WMF
2
1 C4811
4026.3V10%1UFCERM 2
1 C4816
40210V0.1UFCERM20%
21
R4801
1/16WMF
1821%
402
2
1 C481210V402
0.1UF20%CERM 2
1 C4813
CERM20%0.1UF
40210V 2
1 C4814
CERM20%0.1UF
40210V 2
1 C4815
CERM20%0.1UF
40210V
2
1 C48170.01UF
402
20%16VCERM
I46
I48
I49
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
W10
W6
W2Y11
AB4
AC10
AE7
AE2
V9
AG10
AG4
AD6
AA9AC5
AC9
AH5
AD4
AH4
AB1AC1AC4
AE1AD1
AF1AG1AF2AD2AG3AH1AF3AG2
AB9
AE5
AE6
AH2
AC6
AF5AG5
AH7
AA8
AG6AC3
AB8
AH6AF6
AA6
AA4
AA5Y8
AF8AG8
AC8
AA2
AD8
AA3
AE8
AH9AH8AF11AE11AD11AC11
AA7W1
AH12
V7V8V3V4V6V5Y7Y1Y2AA1
AG11
Y5Y6Y3Y4
AD9AE9AF9AG9AH11AH10
AA11AB11U3
V1.0-300MMPBGA
U3LITE
OMIT
2
1 C4810
CERM20%0.1UF
40210V
4
5
3
Q4801SOT-3632N7002DW
AGP_BUSYSTOP
1
2
6
Q4801SOT-3632N7002DW
AGP_BUSYSTOP
0348 103
051-6532
VOLTAGE=1.5VPP1V5_PWRON_AGP_NB_AVDD
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MIL
AGP_SBA_L<5>
AGP_SBA_L<7>
AGP_IRDY
TP_VREF_CG
AGP_AD_STBF<1>
PP1V5_PWRON_NB_AVDD
AGP_SBA_L<0>
AGP_PVTREF2AGP_PVTREF1
PP1V5_AGP
AGP_CBE<0>AGP_CBE<1>
AGP_DBI_HI
AGP_VREF_GC
TP_AGP_MB_AGP8X_DET_L
AGP_AD<24>AGP_AD<23>
AGP_AD<21>
AGP_AD<2>AGP_AD<3>
AGP_SBA AGP_DATAAGP_SBA_L<7..0>AGP_AD<7>
AGP_AD<29>
AGP_AD<31>
AGP_SBA_L<3>
AGP_AD<0>
AGP_AD<19>AGP_AD<18>
AGP_AD<16>
AGP_AD_STB_0 AGP_STROBE AGP_AD_STB0AGP_AD_STBF<0>
AGP_AD_1 AGP_DATAAGP_CBE<3..2>
AGP_SB_STBS AGP_STROBE AGP_SB_STBAGP_SB_STBF
AGP_AD_0 AGP_DATAAGP_CBE<1..0>
AGP_AD_1AGP_AD<31..16> AGP_DATA
AGP_AD<11>
AGP_AD_STB_1AGP_DBI_HI AGP_DATA
AGP_AD_STB_1 AGP_AD_STB1AGP_AD_STBS<1> AGP_STROBE
AGP_SB_STBS AGP_STROBE AGP_SB_STBAGP_SB_STBS
AGP_AD_STB_1AGP_AD_STBF<1> AGP_STROBE AGP_AD_STB1
AGP_AD_0 AGP_DATAAGP_DBI_LO
AGP_SBA_L<1>
NB_AGP_BUSY_L
AGP_SBA_L<2>
AGP_AD_STBS<1>
AGP_CBE<3>AGP_CBE<2>
AGP_AD_STBS<0>AGP_AD_STBF<0>
AGP_DBI_LO
AGP_AD<28>AGP_AD<27>
AGP_SB_STBFAGP_SB_STBS
AGP_AD<17>
AGP_WBF
AGP_AD<1>
AGP_ST<2>
AGP_RBF
AGP_DEVSEL
AGP_TRDY
AGP_AD<13>
AGP_REQ
AGP_PAR
AGP_SBA_L<4>
AGP_SBA_L<6>
AGP_CLK66M_NB
NB_STOP_AGP_L
AGP_AD<30>
AGP_AD<25>
AGP_AD_STB_0 AGP_STROBEAGP_AD_STBS<0> AGP_AD_STB0
AGP_AD_0AGP_AD<15..0> AGP_DATA
AGP_AD<5>AGP_AD<6>
AGP_AD<8>AGP_AD<9>AGP_AD<10>
AGP_AD<12>
AGP_AD<14>AGP_AD<15>
AGP_AD<20>
AGP_AD<22>
AGP_AD<26>
AGP_ST<1>AGP_ST<0>
AGP_STOP
AGP_GNT
NB_AGP_GCDET_LAGP_TYPEDET_L
AGP_FRAME
PP1V5_AGP
AGP_AD<4>
PP1V5_AGP
NB_AGP_BUSY_L
PP3V3_AGP
AGP_BUSY_L_F
AGP_BUSY_L
PP3V3_AGPPP3V3_AGP
PP1V5_AGP
STOP_AGP_LSTOP_AGP_L_F
NB_STOP_AGP_L STOP_AGP_L_R
43 33
37
37
37
37
37
37
37
26
37
36
37
37
37
37
37
37
37
37
37 37
37
37
37
37
37
37
37
37
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37
36
37
36
36
36
36
36
36
36
37
36
5
36
5
36
36
36
37
36
36
36
36
36
36 36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
37
36
37
37
37
37
36
37
37
36
36
25
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
37
37
37
37
37
37
37
5
36
5
36
5
37
5
5
5
37
36
Preliminary
www.vinafix.vn
OE
GND
OUT
VCC
OSC
XIN/CLKINSSCLK
VSSS0S1
FRSEL
XOUT
VDD
VSS VSS
VSSVSS
RAGE_MOBILITY
(2 OF 6)
VDDCI
VSS
(6 OF 6)
RAGE_MOBILITY
VSSVSS
(1 OF 6)
RAGE_MOBILITY
AGP_BUSYBAD_STBB1AD_STBB0
AD_STB0
AGPREF
AD_STB1AD30AD31
AD29AD28AD27AD26AD25AD24
AD17
AD14AD15
AD23AD22
AD19AD20AD21
AD16
AD18
AD6AD5AD4
AD13
AD11AD12
AD10AD9AD8AD7
AD3
CBEB1CBEB2CBEB3
AD0AD1AD2
CBEB0
PCICLKFRAMEB
PAR
IRDYBTRDYB
RSTBINTABGNTBREQB
DEVSELBSTOPB
MEMVMODE1MEMVMODE0
TEST_YCLKTEST_MLCK
D+D-
VREFVREFG
MEMTESTPLLTEST
WBF
ST0ST1ST2
SBA5SBA6
SBA3SBA4
SBA7
SBA2
STP_AGPB
RBFB
SB_STB
SBA1SBA0
SUS_STAT
AGPTESTAGP8X_DETB
RSTB_MSK
DBI_LODBI_HI
SB_STBS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
AGP 4X
S0=1;S1=M => -1.5% DOWN-SPREAD
NC
(PULL-UP to GPU_MEM_IO)
NC
NC
27MHz OSC CLOSE TO GPU PIN AJ29) (PLACE THE OSCILLATOR AND R4981 AND RR4982
(PLACE R4985 CLOSE TO OSC)
FOR 2.5 VDDR1MEMVMODE0=1.8VMEMVMODE1=GND
FOR 1.8 VDDR1MEMVMODE0=GNDMEMVMODE1=1.8V
CLOSE TO ATI M10 VREF PINPLACE VREF VOLTAGE DIVIDER
SPREAD SPECTRUM SUPPORT
M11 AGP INTERFACE
AGP 8X
U3LITE SIGNAL
U3LITE AGP I/O REFERENCE(PLACE CLOSE TO GPU AGP BALL)
(PLACE C4913 CLOSE TO AGPREF PIN)
21
R4900
1/16W
47
5%
MF402
2
1R4901
402
1/16W5%
MF
10K
21
L490060-OHM-EMI
SM
2
1 C49000.01uF20%
CERM402
16V
2
1 C4901
402CERM
20%16V
0.01uF
2
1 C4902
CERM
20%6.3V
805
10uF
2
1 C490316VCERM
20%
402
0.01uF
2
1 C490416V
402CERM
20%0.01uF
2
1R4902
MF1/16W
5%10K
402
2
1R490445.3
402MF1/16W1%
21
R4905
5%
0
1/16WMF402
2
1R4906NO STUFF
402
5%1/16WMF
10K
2
1R49075%1/16WMF402
4.7K
2
1R49084.7K
5%1/16W
MF402
2
1R49091/16WMF402
1%1K
2
1R49101/16WMF
1K1%
402
2
1R4911
MF402
1K1%1/16W
2
1R49121K1/16WMF402
1%
2
1 C4906
CERM
20%0.1uF10V
4022
1 C490720%6.3V
805CERM
10uF
14
81
7
G4980
SM-1
CRITICAL
27.0000M2
1R4980NO STUFF
100K5%
402MF
1/16W
2
1 C49804.7uF
805CERM
20%6.3V2
1C4981
CERM402
20%10V
0.1uF
21
L4980
SM
FERR-EMI-100-OHM
2
1R49901/16W
MF
5%
402
NO STUFF
0
21
L4990GPU_SS
SM
FERR-EMI-100-OHM
8
1
2
7
5
3
4
6
U4990
GPU_SS CRITICAL
SOICY25811
2
1 C49910.1uF
CERM10V
402
20%
GPU_SS
2
1 C4990
805CERM
20%6.3V
GPU_SS
10uF
2
1R4991GPU_SS
MF
01/16W5%
402
2
1R49930
NO STUFF
1/16WMF
5%
4022
1R49920
402
5%
MF1/16W
NO STUFF
2
1R4981
MF402
1%1/16W
287
2
1R49821621/16W
402MF
1%
2
1R4920475%
MF1/16W
402
2
1 C491220%10V
402CERM
0.1uF
2
1R4923NO STUFF
1/16W
4.7K
402MF
5%
2
1R4924NO STUFF
4.7K
402MF
5%1/16W
21
R4985GPU_SS
402MF
1/16W5%
0
2
1R4995GPU_SS
MF1/16W
335%
402
2
1 C491320%16V
402CERM
0.01uF
G30
N3N4
N1N2
M4
L3M3
L4
K3K4
J1
J2H1
H2
B27A27
D23
C23D22
C20
D20C21
D21
C22A25
B25A26
B26
AE4AE3
AD4AD3
AB4
AB3AA4
AA3
AD2AD1
AC2
AC1AA2
AA1Y2
Y1
Y4Y3
W4
W3U4
U3
T4T3
W2W1
V2
V1T2
T1
R2R1
G2
G1F2
F1D2
D1
C2C1
J4
J3H4
H3
F4F3
E3E4
B1
A1B2
A2
B4A4
B5
A5D3
C3D4
C4
D6C6
D7
C7A8
B8
A9B9
A11B11
A12
B12C9
D9
C10
D10C12
D12
C13D13
A13B13
A14
B14A16
B16
A17
B17
C14D14
C15
D15C17
D17
C18D18
C24
D24C25
D25
C27D27
C28D28
B28
A28A29
A30
C29C30
D29
D30E27
E28F27
F28
H27H28
J27
J28E29
E30
F29F30
H29H30
J29
J30AC3
AB1
V3U1
E1
G3B3
D5B10
D11
B15D16
D26
B30G28
U4900M10-CSP64
64MBBGA
OMIT
R19
R18
R17R16
T16U16
V16
W16T14
T13
T12T15
R15
P15N15
M15B19
A21
P3M2
P25
F18AE15
U6
U4900
64MBBGA
OMIT
M10-CSP64
AE27
L1A22
L2
B22K1
A23
K2
B23AC4
AB2V4
U2
E2G4
A3
C5A10
C11A15
C16
C26B29
G27
G29P1
D19
R4A18
R3A19
P4
B18P2
C19
AK3
D8
T28
E8
J6
AJ28
AG29
T27
AE29
AF28AF30
AD28AC29
AC28AB29
AC27
AC30AD27
AD30
AE28AD29
AD24
AH30
AF29
AE30
AC22
AG30
R28
B6B7 C8
T30
AH29AF27
U27
T29
Y25
Y27
AC11AC10
W28U29
R30
N27
AG28
K29
K30
U25
Y29
W29M28
N29
N28
N30M30
M27M29
L28
AB30
AB27
L30
AA29
AB28AA30
AA27
Y30AA28
W30
W27V30
V28
L27
V29V27
U30U28
R27
R29P28
P30
P27P29
L29
K28
U4900M10-CSP64
CRITICAL
OMIT
BGA64MB
2
1R491310K
402MF1/16W5%
2
1R49145%1/16W
0
402MF
2
1R48021/16W
3.32K1%
402MF
2
1 C4818
40216VCERM20%0.01UF
2
1R48031.02K1%1/16WMF402
051-65321034903
AGP_VREF_GCMIN_LINE_WIDTH=8 milMIN_NECK_WIDTH=8 mil
AGP_AD_STBS<1>
AGP_AD<2>
AGP_ATI_VREFG
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=8 mil
GPU_RESET_L_R
AGP_WBF
AGP_TRDY
AGP_DBI_HI
_PP3V3_GPU
AGP_SUS_STAT_L_PU
AGP_VREF_GC
GPU_AGP_TEST
_PP1V5_GPU_AGP
NB_AGP_GCDET_L
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
AGP_ATI_MVREF
_PP3V3_GPU
_GPU_RESET_L
_PP3V3_GPU
AGP_AD<30>
AGP_AD<31>
PP1V5_AGP
AGP_AD<13>
STOP_AGP_L
AGP_SBA_L<5>
GPU_MEMVMODE1
AGP_ST<0>
_PP1V8_GPU
GPU_MEMVMODE0
AGP_DBI_LO
AGP_AD<20>
AGP_BUSY_L
AGP_INT_L
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 milVOLTAGE=3.3VPP3V3_GPU_OSC
GPUSS_S1
GPUSS_S0
GPUSS_CLK27M
_PPVCORE_GPUFB
_PP3V3_GPU
_PP3V3_GPU
GPU_OSC_OE
GPUSS_CLK27M
GPU_SSCLK_UF
GPU_CLK27M_OSC
AGP_AD<28>
AGP_AD<27>
AGP_AD<25>
AGP_AD<22>
AGP_AD<23>
AGP_AD<21>
AGP_AD<19>
AGP_AD<18>
AGP_AD<17>
AGP_AD<16>
AGP_AD<15>
AGP_AD<12>
AGP_AD<11>
AGP_AD<10>
AGP_AD<7>
AGP_AD<6>
AGP_AD<5>
AGP_AD<4>
AGP_AD<3>
AGP_AD<1>
AGP_AD<0>
AGP_CBE<1>
AGP_CBE<2>
AGP_CLK66M_GPU
AGP_CBE<0>
AGP_FRAME
AGP_IRDY
AGP_DEVSEL
AGP_STOP
AGP_PAR
AGP_REQ
GPU_THMDIODE_P
GPU_MEMTEST
AGP_ST<2>
AGP_AD_STBF<1>
AGP_CBE<3>
GPU_CLK27M_DIV
_PPVCORE_GPUFB
MIN_NECK_WIDTH=10 mil
PP3V3_GPUSS_VDDVOLTAGE=3.3VMIN_LINE_WIDTH=10 mil
GPU_SSCLK_IN
AGP_AD_STBF<0>
AGP_ST<1>
AGP_SBA_L<7>
AGP_SB_STBF
AGP_AD<8>
AGP_AD<14>
AGP_SBA_L<2>
AGP_SBA_L<0>
AGP_SBA_L<4>
AGP_AD<29>
AGP_SBA_L<6>
AGP_SBA_L<3>
AGP_SBA_L<1>
ATI_RSTB_MSK
AGP_SB_STBS
AGP_RBFAGP_AD<9>
AGP_GNT
AGP_AD<26>
AGP_AD<24>
AGP_TYPEDET_L
AGP_AD_STBS<0>
PPVCORE_GPU
GPU_THMDIODE_N
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 mil
PPVCORE_GPU_VDDCIVOLTAGE=1.2V
40
40
40
41
40
40
39
40
39
39
40
40
39
39
40
37
37
37
39
37
41
37
36
39
37
37
37
37
39
36
36
36
36
36
36
5
36
5
36
5
5
5
36
36
5
36
36
36
36
5
36
36
36
23
37
5
5
5
37
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
25
36
36
36
36
36
36
36
15
36
36
36
39
5
39
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36 36
36
36
36
36
36
5
15 Preliminary
www.vinafix.vn
PADTHM
GND
V+TON
DL
LSAT
ILIM
LX
BSTDH
REF
REFINFB
OUTSHDN*
SKIP*
OVP/UVP
CSPCSN
ODGATEPGOODFBLANK
VCC VDD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
2V output reference
<R3a>
<R3b>
<R1>
OD is open drain output controlled by gate
Changed R5050 from 30.1K to 37.4Kto get 1.2V at the high input
REFIN is FB voltage
FAT
GPU VCore Regulator
open LSAT=1.75*Ilim
SHORT
FAT
SHORT
FAT
SHORT
Req = R3a + R3b
Vout = 2V * (R2 / (R1+R2)) = 1.0V
FAT
SHORT
When GPUVCORE_CNTL_L = 1, Vout = 1.0V
When GPUVCORE_CNTL_L = 0, Vout = 1.2VVout = 2V * (Req / (R1+Req)) = 1.2V
2
1C5038
1206
20%
CERM
22uF6.3V
2
1 C50372.5V-ESR9VPOLYCASE-D2E
330uF20%
CRITICALNO STUFF2
1C503620%
330uF
CRITICAL
2.5V-ESR9VPOLY
CASE-D2E
2
1 C503320%
1206
4.7uF25VCERM2
1 C503225V20%CERM1206
4.7uF2
1 C50314.7uF
1206CERM25V20%2
1 D5011MBR0540SM
2
1 C50110.1UF
402
20%CERM10V
21
R50110
5%
MF402
1/16W
2
1R5009
MF
5%100K1/16W
NO STUFF
402
2
1R5008
MF
5%201/16W
402
2
1 C50086.3V10%
402CERM
1uF
2
1R5007NO STUFF
MF
5%0
402
1/16W
2
1 C5035CRITICAL
20%330uF2.5V-ESR9VPOLYCASE-D2E
3
1 2
L50301.53uH
SM
CRITICAL
2
1
R50342.25%1/10WFF805
NO STUFF
2
1 C5034
CERM60350V0.0022UF
NO STUFF
10%
2
1R501890.9K
MF402
1%1/16W
2
1 C5019470PF
40250V10%CERM2
1 R501926.7K1/16W1%
402MF
2
1C5030
CERM
10%
402
0.001uF50V
NO STUFF
2
1 C50006.3V20%
805CERM
10UF
2
1R50141001%
MF402
1/16W
1922
14
1
25
13
23
7
6
4
24
10
8
16
3
5
20
21
29
18
15
11
12
17
U5000
CRITICAL
QFNMAX1993
21
C5012
402
6.3V20%
X5R
0.22uF
2
1 C5001
CERM10%50V402
0.0018UF
2
1 R50135%
MF402
01/16W
2
1R5012
MF1/16W
1%1.1K
402
2
1R5005NO STUFF
402MF
1/16W5%0
2
1R5003NO STUFF
402
05%
1/16WMF
2
1R5006NO STUFF
402
1/16WMF
5%0
2
1R50041/16W
0
402
5%
MF
2
1R5001
402MF
5%0
1/16W
2
1R5002NO STUFF
402MF
1/16W5%0
2
1 C5002
402
20%6.3V0.22uFX5R
2
1R50151/16WMF402
1%75K
2
1R5016
402MF1/16W1%75K
2
1 C50150.001uF50V10%
CERM402
2
1R5017
MF
1%37.4K1/16W
402
2
1
D5030SMB
B340LB
21
XW5001SM
321
4
5
Q5030SO-8-PWRPKSI7392DP
CRITICAL
321
4
8765
Q5031SI4336DY
CRITICAL
SO-8
2
1R5010NO STUFF
1/16WMF
5%0
402
50 10303051-6532
GPUVCORE_LX
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
_PPVCORE_GPU_REG
_PPVIN_GPUVCORE
PP5V_GPUVCORE_VCCVOLTAGE=5VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
GPUVCORE_BSTMIN_LINE_WIDTH=20 mil
GPUVCORE_BST_RCMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
GPUVCORE_FBLANK
GPUVCORE_CNTL_L
GPUVCORE_TON
GND_GPUVCORE
_PPVIN_GPUVCORE
MIN_LINE_WIDTH=25 milGPUVCORE_DH
MIN_NECK_WIDTH=10 mil
_PP5V_PWRON_GPUVCORE
GPUVCORE_DLMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 milGPUVCORE_SKIP_L
GPOVCORE_LX_RC
GPUVCORE_OVP_UVP
GND_GPUVCORE
GPUVCORE_PGOOD
GPUVCORE_CSPGPUVCORE_CSN
GPUVCORE_FB
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 mil
GND_GPUVCOREVOLTAGE=0V
GPUVCORE_SHDN_L
GPUVCORE_LSAT
GPUVCORE_REF
GPUVCORE_REFIN
GPUVCORE_ILIM
GPUVCORE_OD
38
38
5
5
39
38
5
5
38
14
38
14
Preliminary
www.vinafix.vn
HPD1
DDC3CLKDDC3DATA
DDC1CLKDDC1DATA
DDC2CLKDDC2DATA
BLON
GPIO16GPIO15
G
R
B
Y_G
R2SETRSET
H2SYNCHSYNC
V2SYNCVSYNC
ZV_LCDDATA5ZV_LCDDATA4ZV_LCDDATA3ZV_LCDDATA2
ZV_LCDDATA6
ZV_LCDDATA15ZV_LCDDATA14ZV_LCDDATA13ZV_LCDDATA12
ZV_LCDDATA7ZV_LCDDATA8ZV_LCDDATA9ZV_LCDDATA10ZV_LCDDATA11
ZV_LCDDATA16C_R
DIGON
COMP_B
AUXWIN
ZV_LCDDATA21ZV_LCDDATA20
ZV_LCDCNTL0ZV_LCDCNTL1
ZV_LCDDATA22ZV_LCDDATA23
ZV_LCDDATA17ZV_LCDDATA18ZV_LCDDATA19
ZV_LCDCNTL2ZV_LCDCNTL3
GPIO0GPIO1
GPIO5
GPIO7GPIO6
GPIO2GPIO3GPIO4
TXOUT_L3NTXOUT_L2PTXOUT_L2N
TXOUT_U3PTXCLK_UN
TXOUT_U2P
TXOUT_L0NTXOUT_L0PTXOUT_L1NTXOUT_L1P
TXOUT_U3N
TXCLK_UP
TXOUT_U2NTXOUT_U1P
TXOUT_U0PTXOUT_U0N
TXOUT_U1N
GPIO8
GPIO12
GPIO10GPIO11
GPIO9
GPIO14GPIO13
TX0M
TX2P
TX1PTX2M
TXCM
TX1MTX0P
TXCP
XTALINTXOUT_L3PTXCLK_LNTXCLK_LP
SSOUT
XTALOUT
TESTEN
SSIN
ROMCSBZV_LCDDATA1ZV_LCDDATA0
RAGE_MOBILITY
(3 OF 6)
VSSVSSVSS
VSSVSS
VDDC
(5 OF 6)
RAGE_MOBILITY
VSS
VDD15
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Length Tolerance: 50 mils
Page Notes
NC
NC
NC
NC
NC
NC
NC
NC
(NO ICT TEST)
(NO ICT TEST)
(NO ICT TEST)
(NO ICT TEST)
NC
NC
NC
M10 Power Shut down Sequencing
(PUT ALL CAPs BELOW ATI ASIC)
Secondary Max Sep: 100 mils
DIFFERENTIAL_PAIR
NOTE: Target differential impedance for
(NONE)
(NONE)
Line To Line: 15 mils
Net Spacing Type: LVDS
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
M11 CORE PWR/LVDS/TMDS
(500mA)
GPU VCORE - 1.2V
(GPIO2)
(GPIO0)(GPIO1)
(GPIO3)(GPIO4)(GPIO5)(GPIO6)
_PP1V5_GPU_AGP, _PP3V3_GPU, PPVCORE_GPU
Primary Max Sep: 10 mils
Secondary Length: 250 mils
LVDS data pairs is 100 ohms.
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE
2
1 C5120
X5R6.3V
402
20%0.22uF
2
1 C51006.3V20%
805CERM
10uF2
1 C510110uF20%6.3VCERM805
2
1 C5102
X5R
0.22uF6.3V20%
4022
1 C5103
X5R
0.22uF6.3V
402
20%2
1 C5104
X5R6.3V20%0.22uF
4022
1 C5105
X5R
0.22uF
402
6.3V20%
2
1 C5106
X5R402
20%6.3V
0.22uF
2
1 C5107
X5R
0.22uF20%
402
6.3V 2
1 C5108
X5R
20%0.22uF
402
6.3V 2
1 C5109
X5R6.3V
402
20%0.22uF
2
1 C5110
X5R
0.22uF
402
20%6.3V 2
1 C5111
X5R
20%6.3V
402
0.22uF2
1 C5112
X5R
20%
402
6.3V
0.22uF2
1 C5113
X5R
20%
402
6.3V
0.22uF2
1 C5114
X5R
20%
402
0.22uF6.3V
2
1 C5115
X5R6.3V
402
20%0.22uF
2
1 C5116
X5R
0.22uF6.3V20%
4022
1 C5117
X5R
0.22uF20%6.3V
402
2
1 C5118
X5R6.3V
402
20%0.22uF
2
1 C5119
X5R
0.22uF20%6.3V
4022
1 C5123
X5R6.3V
402
20%0.22uF
2
1 C5121
X5R6.3V
402
20%0.22uF
2
1 C5122
X5R6.3V20%
402
0.22uF
2
1R5123NO STUFF
5%1/16W
MF
10K
402
2
1R5100
MF402
5%1/16W
10K
2
1R51011/16W
5%10K
402MF
2
1R51021/16W
751%
MF402
2
1R5103
MF402
1%1/16W
75
2
1R51041/16W
402MF
1%75
2
1R51051/16W
751%
MF402
2
1R5106
402MF
1%751/16W
2
1R5107
MF1/16W1%75
402
2
1R51081%
MF1/16W
499
402
2
1R51091%
1/16W
715
MF402
2
1R51105%10K
MF1/16W
402
2
1R5111NO STUFF
10K
402
5%
MF1/16W
2
1R51125%
402MF
10K
NO STUFF
1/16W
2
1R5113NO STUFF
5%
MF
10K1/16W
402
2
1R51141/16W
10K
MF402
5%
NO STUFF
2
1R51151/16W
NO STUFF
5%
402MF
10K
2
1R5116NO STUFF
5%
402MF
10K1/16W
2
1R511710K
MF
5%
402
1/16W
NO STUFF
2
1R5118NO STUFF
1/16WMF402
5%10K
2
1R51191/16W5%
MF
10K
402
2
1R5120NO STUFF
5%1/16W
402
10K
MF
2
1R5121
402
5%10K
MF
NO STUFF
1/16W
2
1R512210K
NO STUFF
1/16WMF402
5%
2
1R5125NO STUFF
402MF
10K1/16W5%
2 1
R5124
1/16W
402
1K
MF
5%
2
1 C512510uF6.3V20%
CERM805
2
1 C51240.01uF20%16VCERM402
2
1 C513216VCERM
20%
402
0.01uF2
1 C512616V20%
CERM402
0.01uF2
1 C51270.01uF
402CERM
20%16V
2
1 C512820%0.01uF16V
402CERM2
1 C5129
402CERM16V20%0.01uF
2
1 C51300.01uF
CERM16V20%
4022
1 C5131
402CERM
20%16V
0.01uF
21
L5126FERR-220-OHM
0805
4
36
5
2
1
Q5100TSOP
SI3446DV
CRITICAL
2
1 C5133
CERM50V10%0.001uF
402
52
DP5190BAS16TWSOT-363
43
DP5190BAS16TWSOT-363
61
DP5190SOT-363
BAS16TW
PP2V5_RUN
21
XW5190SM
21
XW5191SM
21
XW5192SM
21
XW5193SM
21
XW5194SM
2
1R51261/16WMF
5%1K
402
2
1R5127
402MF
5%10K1/16W
2
1R5128EXT_TMDS
1/16W
10K
402MF
5%
AK7
AJ7
AH7AG7
AK6
AJ6AH6
AH11
AG11
AK10AJ10
AG6
AH10
AG10AK9
AJ9
AH9AG9
AK8AJ8
AH8
AG8
AK5
AJ5
AG5AH5
AK4
AJ4
AK23
AJ30
AJ29
AG27
B21A20
A24
B20B24
AG25
AG22
AH22AG20
AH20
AG19AH19
AG18
AH18
AJ20AK20
AJ18
AK18AJ17
AK17
AJ16AK16
AK12AJ12
AG21
AH21
AJ19AK19
AK15
AJ15AK14
AJ14
AK13AJ13
AH24
AJ25AJ26
AK25
AE5
AJ24
AK28
AG26
AF11
AG24
AF3
AG3AH1
AF4AJ1
AH2
AH3AK1
M1
AE1
AE2AF1
AG1
AF2AG2
AK2
AJ2
AK27
AE13
AH26AH25
AE12
AF12
AH28AH27
AK24
AK22
AF13
AK26
AJ27
U4900
64MBM10-CSP64
BGA
OMIT
G16
G15
AD23
G14
AD22
AD21
AD20AD19
AD18AD17
AD16
AD15AD14
AD13
G13
AD12AD11
AD10
AD9AD8
AD7AC24
AC23
AC8AC7
G12
AB24
AB7AA24
AA7
Y24Y7
W24W7
V24
V7
G11
U24
U7
T24T7
R24
R7P24
P7N24
N7
G10
M24M7
L24
L7K24
K7
J24J7
H24H23
G9
H8
H7G24
G23
G22G21
G20
G19G18
G17
G8G7
AD26
P6H6
G6
F6AF5
V25W25
N25
M25F25
AE24
F24
AH4
F23
AE18
AC25AE17
AF15W26
AF14
AE14F14
F13
AG4
AE11F11
AE10
F10F7
AE6AD6
AC6
W6V6
AF25
AJ3
AB25R25
G25
F17AB6
T6
L6F12 U4900
BGA64MB
M10-CSP64
OMIT
2
1R51295%
10K1/16W
MF402
INT_TMDS
10351051-6532 03
8 MIL SPACING GPU_DVOD<0..19>GPU_DVO_DATA
8 MIL SPACING GPU_DVO_CLKPGPU_DVO_CTL
GPU_DVO_DE8 MIL SPACINGGPU_DVO_CTL
GPU_DVO_VSYNC8 MIL SPACINGGPU_DVO_CTL8 MIL SPACING GPU_DVO_HSYNCGPU_DVO_DATA
GPU_DVOD<21..23>8 MIL SPACINGGPU_DVO_DATA
GPU_DVOD<20>8 MIL SPACINGGPU_DVO_DATA20
SI_DDC_DATA
LVDS_U1 LVDS_U1PLVDS
LVDS LVDS_L2 LVDS_L2N
CLKLVDS_UPLVDS LVDS_UCLKCLKLVDS_UNLVDS LVDS_UCLK
LVDS LVDS_U2 LVDS_U2N
LVDS_U0 LVDS_U0NLVDS
LVDS LVDS_LCLK CLKLVDS_LP
LVDS CLKLVDS_LNLVDS_LCLK
LVDS LVDS_L0 LVDS_L0P
LVDS LVDS_U1 LVDS_U1N
LVDS LVDS_U2 LVDS_U2P
LVDS_L1NLVDS_L1LVDSLVDS LVDS_L2PLVDS_L2
LVDS LVDS_L1PLVDS_L1
LVDS_L0NLVDS_L0LVDS
LVDS LVDS_U0 LVDS_U0P
GPU_X1CLK_SKEW<1>
GPU_BUS_CFG<0>
GPU_BUS_CFG<1>
GPU_BUS_CFG<2>
GPU_AGP_FBSKEW<0>
GPU_AGP_FBSKEW<1>
_PP3V3_GPU
GPU_X1CLK_SKEW<0>
PP1V5_GPU_VDD15
MIN_NECK_WIDTH=10milMIN_LINE_WIDTH=25milVOLTAGE=1.5V
GPUVDD15_EN
_PP1V5_GPU_AGP
VOLTAGE=1.5VMIN_NECK_WIDTH=10milMIN_LINE_WIDTH=25mil
PP1V5_GPU_VDD15_UF
PPVCORE_GPU
MIN_NECK_WIDTH=8milMIN_LINE_WIDTH=8mil
PP1V5_AGP_NECK
MIN_LINE_WIDTH=8milMIN_NECK_WIDTH=8mil
PP1V8_GPU_PVDD_NECK
MIN_NECK_WIDTH=8milMIN_LINE_WIDTH=8milPPVCORE_GPU_NECK
_PP1V5_GPU_AGP
MIN_NECK_WIDTH=8milMIN_LINE_WIDTH=8mil
PP2V5_RUN_NECK1PP1V8_GPU_PVDD_LDO
PPVCORE_GPU
PP1V5_GPU_VDD15
PP1V5_GPU_VDD15_NECK
MIN_NECK_WIDTH=8milMIN_LINE_WIDTH=8mil
_PP3V3_GPU
FP_PWR_EN
INV_ON_PWM
_PP3V3_GPU
GPU_AUXWIN
GPU_RSET
GPU_R
GPU_R2SET
GPU_Y
GPU_G
GPU_B
GPU_C
GPU_COMP
GPU_DVOD<1>GPU_DVOD<0>
GPU_CLK27M_DIV
GPU_TMDS_CLKP
GPU_TMDS_CLKN
GPU_TMDS_DP<2>
GPU_TMDS_DN<2>
GPU_TMDS_DP<1>
GPU_TMDS_DN<0>
GPU_TMDS_DN<1>
GPU_TMDS_DP<0>
HPD_PWR_SNS_EN
GPU_GPIO8_PD
SI_RESET_LGPU_BUS_CFG<2>
GPU_BUS_CFG<1>
GPU_BUS_CFG<0>
GPU_X1CLK_SKEW<1>
GPU_AGP_FBSKEW<1>
GPU_AGP_FBSKEW<0>
GPU_X1CLK_SKEW<0>
GPU_DVO_CLKPGPU_DVO_DE
GPU_DVOD<23>GPU_DVOD<22>
GPU_DVO_HSYNCGPU_DVO_VSYNC
GPU_DVOD<21>
GPU_DVOD<19>GPU_DVOD<18>
GPU_DVOD<16>GPU_DVOD<17>
GPU_DVOD<14>GPU_DVOD<15>
GPU_DVOD<11>
GPU_DVOD<13>GPU_DVOD<12>
GPU_DVOD<10>GPU_DVOD<9>GPU_DVOD<8>
GPU_DVOD<6>GPU_DVOD<7>
GPU_DVOD<5>GPU_DVOD<4>GPU_DVOD<3>GPU_DVOD<2>
CLKLVDS_LN
TP_LVDS_L3P
CLKLVDS_LP
TP_LVDS_L3N
LVDS_L2P
LVDS_L1P
LVDS_L2N
LVDS_L1N
LVDS_L0P
LVDS_L0N
CLKLVDS_UN
CLKLVDS_UP
TP_LVDS_U3P
LVDS_U2P
TP_LVDS_U3N
LVDS_U1P
LVDS_U1N
LVDS_U2N
LVDS_U0P
LVDS_U0N
GPU_HSYNC
GPU_VSYNC
GPUVCORE_CNTL_L
GPU_SSCLK_IN
LVDS_DDC_DATA
LVDS_DDC_CLK
GPU_DVI_DDC_DATA
GPU_DVI_DDC_CLK
SI_DDC_CLK
GPU_HPD
GPU_TESTEN
GPU_DVOD<20>
_PP3V3_GPU
_PP1V8_GPU
40
40
40
40
40
40
41
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
39
39
39
39
39
39
39
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
39
40
41
41
41
41
41
41
41
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
37
37
37
37
37
37
37
41
41
62
62
62
62
62
62
62
62
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
42
42
41
37
37
39
39
39
39
39
39
39
41
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
39
39
39
39
39
39
5
39
39
14
5
5
5
40
5
39
5
42
42
5
42
42
42
42
42
42
39
39
37
41
41
41
41
41
41
41
41
42
41
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
42
42
38
37
6
6
42
42
41
42
39
5
5
Preliminary
www.vinafix.vn
CONT NOISE
VIN VOUT
GND
CONT NOISE
VIN VOUT
GND
VDDR1
DVOVMODE
LVDDR_25LVDDR_25
VSS2DIVSS1DI
VDD2DIVDD1DI
(4 OF 6)
RAGE_MOBILITY
PVSSAVSSQ
AVSSN1AVSSN0A2VSSQ
A2VSSN0A2VSSN1
VSSRH0VSSRH1
VDDR1
A2VDD0A2VDD1
PVDD
AVDD1AVDD0
A2VDDQ
VDDRH0VDDRH1
VDDP
LPVSSTPVSSMPVSS
LVSSR0LVSSR1LVSSR2LVSSR3
VDDM
LVDDR_18LVDDR_18
LPVDDTPVDDMPVDD
TXVDDR3
TXVDDR0TXVDDR1TXVDDR2
TXVSSR3TXVSSR2TXVSSR1
VDDR3
VDDR4
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.8V DVO POWER (EXT. TMDS)
Notice this is FB_VIO as well!
M11 POWER
M10 SHUT DOWN POWER SEQUENCING
MEMORY I/O
AGP 4X I/O - 1.5V
(or 2.5V)
(21mA)
(or 2.5V)
(AVDD+VDDDI=75mA)
(100mA MAX)
(Total PVDD = 66mA)GPU PLL - 1.8V
(1200mA)(AVDD+VDDDI=75mA)
(2mA)
(20mA)
(40mA)
(140mA)
(20mA)
(350mA)
(180mA)
LVDS - 2.5V
MEMORY PLL - 1.8V
(1800mA)
LVDS PLL - 1.8V
MEMORY CORE - 1.8V/2.5V
LVDS/TMDS - 1.8V
2
1 C520020%0.1uF
CERM402
10V2
1 C52010.1uF
402
10V20%
CERM2
1 C5202
805
10uF20%6.3VCERM 2
1 C52030.1uF
402CERM
20%10V
2
1 C520420%
402CERM10V
0.1uF2
1 C520520%10V
402
0.1uF
CERM2
1 C52060.1uF20%10VCERM402
2
1 C520710V
402CERM
0.1uF20%
2
1 C5208
CERM402
0.1uF10V20%
2
1 C52096.3V20%10uF
805CERM
2
1 C521020%10V
402CERM
0.1uF
2
1C52116.3VCERM805
20%10uF
2
1C521220%10V
0.1uF
402CERM2
1C521316V
402CERM
20%0.01uF
2
1 C52140.1uF
CERM402
10V20%
2
1 C521520%10V
402CERM
0.1uF2
1 C5216
402
0.1uF20%
CERM10V2
1 C5217
CERM10V
402
20%0.1uF
2
1C521810V
0.1uF20%
CERM402
2
1C521920%
402
10VCERM
0.1uF2
1C522016V
CERM
20%
402
0.01uF2
1C52210.01uF
16V20%
402CERM 2
1C522210V
CERM402
0.1uF20%
2
1C52230.01uF
402
20%16V
CERM
2
1 C52240.1uF
CERM402
10V20%
2
1 C522520%
402CERM
0.1uF10V 2
1 C522620%10V
402CERM
0.1uF
2
1 C5227
402CERM
0.01uF16V20%
2
1C522820%
6.3V
805CERM
10uF2
1C522910V
402CERM
20%0.1uF
2
1C52300.01uF
CERM
20%
402
16V 2
1C5231
CERM402
0.1uF20%10V2
1C5232
402
0.01uF20%
CERM16V2
1C523320%
402
0.01uF
CERM16V 2
1C523420%10V
CERM402
0.1uF2
1C523510V20%
402
0.1uF
CERM2
1C523620%16V
CERM402
0.01uF
2
1C52370.1uF
CERM402
20%10V2
1C523820%
0.1uF
CERM10V
4022
1C5239
CERM402
0.01uF20%16V 2
1C52400.1uF
CERM402
10V20%
2
1C52410.01uF
16V20%
402CERM
2
1C52420.01uF
402CERM
20%16V2
1C52430.01uF
16VCERM
20%
402
2
1C52440.01uF
402
20%
CERM16V2
1C5245
CERM
20%16V
0.01uF
402
2
1 C5246
402
20%10VCERM
0.1uF2
1 C52470.1uF
CERM402
10V20%
2
1 C5248
402
20%
CERM10V
0.1uF2
1 C52490.1uF20%10V
402CERM
2
1 C5250
CERM10V20%0.1uF
402
2
1C5251
402
0.01uF20%
CERM16V
2
1C525220%
0.01uF16V
CERM402
2
1C5253
CERM
0.01uF20%16V
4022
1C5254
CERM16V20%
402
0.01uF
2
1C52550.01uF
CERM402
20%16V2
1C525616V20%
402CERM
0.01uF
2
1C52570.01uF
16V20%
402CERM2
1C52580.01uF
20%
402
16VCERM
2
1C525916V
0.01uF20%
CERM402
2
1C52600.01uF
20%
402CERM16V
2
1C52610.01uF
CERM
20%16V
402
2
1C526220%
10uF
805
6.3VCERM
2
1C5263
CERM
20%
805
10uF6.3V
2
1C52640.01uF
CERM402
16V20%
2
1C526510uF
20%
CERM6.3V
805
2
1C5266
CERM
20%6.3V
805
10uF
2
1C5267
CERM805
10uF20%
6.3V
2
1C5268
CERM
20%
805
6.3V
10uF
2
1C52696.3V
10uF
805
20%
CERM
2
1C5270
CERM
20%6.3V
805
10uF
2
1C5271
CERM10V
0.1uF
402
20%2
1C52726.3V
10uF20%
805CERM
2
1C527310uF
6.3VCERM805
20%
2
1C5274
CERM
0.1uF
402
10V20%
21
L5200FERR-220-OHM
0402
21
L5201
0402
FERR-220-OHM
21
L5202FERR-220-OHM
0402
21
L5203FERR-220-OHM
0402
21
L5204FERR-220-OHM
0402
21
L5205FERR-220-OHM
0402
21
L5206FERR-220-OHM
0402
21
L5207FERR-220-OHM
0402
21
L5208FERR-220-OHM
0402
2
1 C527520%
CERM6.3V
805
10uF
21
L5209FERR-220-OHM
0805
21
L5210
SM
FERR-10-OHM-500MA
21
L5211FERR-220-OHM
0805
2 1
L5212
SM
FERR-10-OHM-500MA
21
L5213
SM
FERR-10-OHM-500MA
43
DP5290SOT-363
BAS16TW
52
DP5290BAS16TWSOT-363
61
DP5290SOT-363
BAS16TW
21
XW5293SM
21
XW5290SM
PP2V5_GPU_NECK2
21
XW5291SM
PP1V8_GPU_NECK
21
XW5292SM
PP1V5_GPU_NECK
2
1C527620%
0.01uF16V
CERM402
2
1C5277
CERM
20%
805
6.3V
10uF
51
4
2
3
U5290MM1571J
GPUTPVDD_NOISE
SOT-25ACRITICAL
2
1C527810%
6.3VCERM
1uF
4022
1C5279
CERM402
16V10%
0.01UF2
1 C528010UF20%6.3VCERM805
21
L5214FERR-220-OHM
0402
51
4
2
3
U5280SOT-25ACRITICAL
MM1571J
2
1C5281
CERM
10%1uF6.3V
402
2
1 C528210uF
CERM6.3V20%
8052
1 C528320%
CERM10V
402
0.1uF2
1 C52840.1uF10VCERM
20%
402
M6
F20
AF19AG23
N6
F19
AE8AF7
AE7
AF6
AE25
AD25AF10
AF9
AE9AF8
AF26AE26
R5
P5
N5M5
L5
E25
E24
E23E22
E21
E17E16
K5
E15E14
E11
E10E9
H26
E7
J26J25
H25
J5
F22F21
F16
F15F9
F8AA6
Y6
R6K6
H5
G26
AD5AC5
AB5
AA5Y5
W5V5
U5
T5
G5
F5
N26
M26
L26K26
AA25K27
Y28
T25
AC26AB26
AA26Y26
V26
U26T26
R26
P26
L25
K25
F26E26
E20
E19E18
E13E12
E6
E5
AF20AH23
AH15
AH14AH13
AG15
AG14AG13
AG12
AJ11AK11
AK30AK29
A6A7
AF18
AH17AG17
AH16
AF17
AG16AF16
AE16
AJ21AK21
AH12
AF22
AE23AE22
AF24
AF23
AJ22
AE20
AE19AJ23
AF21AE21
U4900OMIT
M10-CSP6464MBBGA
2
1 C52920.1uF
CERM402
10V20%
2
1 C529510V
402CERM
0.1uF20%
2
1 C52980.1uF
CERM402
10V20%
2
1 C529320%10VCERM
0.1uF
4022
1 C52960.1uF
CERM402
10V20%
2
1 C529920%10V
402CERM
0.1uF
2
1 C52940.1uF
CERM402
10V20%
2
1 C529720%10V
402CERM
0.1uF
2
1R5201INT_TMDS
402MF1/16W5%0
21
R5200EXT_TMDS
0
5%1/16WMF402
2
1R5280INT_TMDS
603
05%1/16WMF
21
L5280FERR-10-OHM-500MA
EXT_TMDS
SM
03051-653252 103
MIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 milVOLTAGE=1.8VPP1V8_GPU_AVDD
MIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 milVOLTAGE=1.8VPPDVO_GPU_VDDR4
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 milVOLTAGE=1.8V
PPVIO_GPUFB
VOLTAGE=1.8VPPVCORE_GPUFB_VDDM
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=25 mil
_PP3V3_GPUVOLTAGE=3.3VMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
PP3V3_GPU_VDDR3
_PP2V5_GPU VOLTAGE=1.8VMIN_NECK_WIDTH=10 mil
PP1V8_GPU_TPVDD_LDO
MIN_LINE_WIDTH=15 mil
PP1V8_GPU_LVDDR
MIN_NECK_WIDTH=10 milVOLTAGE=1.8VMIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
PP1V8_GPU_TPVDD
MIN_LINE_WIDTH=15 milVOLTAGE=1.8V
PP1V8_GPU_VDDDI
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 milVOLTAGE=1.8V
PP1V8_GPU_PVDD_LDO
MIN_LINE_WIDTH=15 milVOLTAGE=1.8VMIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 milVOLTAGE=1.8VPP1V8_GPU_A2VDDQ
MIN_LINE_WIDTH=10 mil
_PPVCORE_GPUFB
GPUPVDD_NOISEMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
GPUPVDD_EN
_PP2V5_GPU
_PP1V8_GPU
_PP1V8_GPU
_PP1V8_GPU
PP1V8_GPU_PVDD_LDO
PP1V8_GPU_PVDD_LDO
GPUPVDD_EN
_PP2V5_GPU
_PP2V5_GPU
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=8 mil
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=8 mil
_PP3V3_GPU
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=8 mil
PP1V8_GPU_MPVDDVOLTAGE=1.8VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 mil
_PP1V8_GPU
PP1V8_GPU_PVDDVOLTAGE=1.8VMIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 mil
_PP1V5_GPU_AGP
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 milVOLTAGE=2.5VPP2V5_GPU_A2VDD
_PP1V5_GPU_AGP
_PPVCORE_GPUFB
_PP2V5_GPU
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=10 mil
_PPVCORE_GPUFB
PP1V5_GPU_VDDPVOLTAGE=1.5VMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
_PP1V8_GPU
MIN_NECK_WIDTH=8 milMIN_LINE_WIDTH=8 mil
PP3V3_GPU_NECK
PPVIO_GPUFB
PP1V8_GPU_LPVDDVOLTAGE=1.8VMIN_LINE_WIDTH=15 milMIN_NECK_WIDTH=10 mil
PP2V5_GPU_LVDDR
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 milVOLTAGE=2.5V
ATI_DVOVMODE
_PP1V8_GPU
_PP1V8_GPU
PPVCORE_GPUFB_VDDRHVOLTAGE=1.8VMIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 mil
41
41
41
41
41
41
41
40
40
40
40
40
40
40
40
40
40
40
39
40
39
39
39
39
39
39
39
40
40
39
39
39
37
40
40
37
40
40
37
37
37
40
40
40
40
40 37
37
37
37
37
40
37
37
37
37
40
5
5
39
5
14
5
5
5
5
39
39
14
5
5 5
5
14
5
5
5
5
5
5
40
5
5
Preliminary
www.vinafix.vn
PGND2
PGND1
PGND1
PGND2
MVREFSVREF
RSVD
STX2+STX2-
STX1-STX1+
STX0+STX0-
STXC-STXC+
MTX2+MTX2-
MTX1-MTX1+
MTX0+MTX0-
MTXC+MTXC-
MMSENSMSEN
PVCC1
PVCC1
AVCC VCC
PGND1
SSDASSCLMSDAMSCL
SRSET#MRSET#
MPDSPD
SEDGE/HTPMEDGE/HTP
SHSYNCMHSYNC
MIDCK+
MVSYNCSVSYNC
SIDCK+MIDCK-
SIDCK-
SDEMDE
SDK3SDK1MDK3MDK1
SD14/SYNCOSD13/MASTSD12/DUAL
MD14/SYNCOMD13/MASTMD12/DUAL
SD11
SD9SD10
MD11MD10MD9
SD8SD7SD6SD5SD4SD3SD2SD1SD0
MD8MD7MD6MD5MD4MD3MD2MD1MD0
PVCC1
PVCC2
PVCC2
SEXT_SWINGMEXT_SWING
AGND GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Page Notes
TRACE SO THAT IT MAY BE CUT BETWEEN CAPS
EXTERNAL TMDS TERMINATION
strap 1 -> I2C enabled
active-high HTP
NC
ATI TMDSBOM options provided by this page:
Net Spacing Type: TMDS
NCNC
Line To Line: 15 mils
NOTE: Target differential impedance for
Power aliases required by this page:
TMDS data pairs is 100 ohms.
Primary Max Sep: 10 milsLength Tolerance: 50 mils
Secondary Length: 250 milsSecondary Max Sep: 100 mils
Signal aliases required by this page:
(NONE)
(NONE)
(None)
strap 0 -> reset function
NC
/SYNCI
NC
SILICON IMAGE TMDS
ATI TMDS
TRACE SO THAT IT MAY BE CUT BETWEEN CAPSCMF LINE SHOULD BE ROUTED AS 4MIL SURFACE
INTERNAL TMDS TERMINATIONTERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN
TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWNCMF LINE SHOULD BE ROUTED AS 4MIL SURFACE
NC
NC
21
L5720
SM-1
400-OHM-EMI
EXT_TMDS
2
1 C572250V
100pF
402
5%
CERM
EXT_TMDS
2
1 C5723100pF5%50VCERM402
EXT_TMDS
2
1 C5724EXT_TMDS
402CERM50V5%100pF
2
1 C5725
402CERM50V
EXT_TMDS
100pF5%
2
1 C57215%
EXT_TMDS
100pF
402
50VCERM
2
1 C5734
CERM
100pF
EXT_TMDS
402
50V5%
2
1 C5733100pF5%50VCERM402
EXT_TMDS
2
1 C5732100pF
402CERM50V5%
EXT_TMDS
2
1 C5731100pF
EXT_TMDS
CERM
5%50V
4022
1 C5730EXT_TMDS
CERM6.3V20%10uF
805
2
1C5720EXT_TMDS
6.3V
10uF
805
20%
CERM
21
L5730400-OHM-EMI
SM-1
EXT_TMDS
2
1 C5738100pF5%50VCERM402
EXT_TMDS
2
1 C5737
CERM402
50V5%
EXT_TMDS
100pF2
1 C5736100pF5%50VCERM402
EXT_TMDS
21
L5739400-OHM-EMI
SM-1
EXT_TMDS
2
1 C572610uF
805CERM6.3V20%
EXT_TMDS
2
1 C5739
402CERM
5%100pF
EXT_TMDS
50V2
1 C5735
805CERM6.3V20%10uF
EXT_TMDS
41
RP5707EXT_TMDS
SM1
10
5%1/16W
32
RP5707
SM11/16W5%
10
EXT_TMDS
41
RP5708
1/16W5%
SM1
10
EXT_TMDS
32
RP5709
5%
SM11/16W
10
EXT_TMDS
32
RP5708
SM11/16W5%
10
EXT_TMDS
32
RP571010
EXT_TMDS
5%1/16WSM1
41
RP5709EXT_TMDS
SM11/16W5%
10
41
RP5710
SM1
EXT_TMDS
10
5%1/16W
2
1 C574020%10VCERM
0.1uF
402
EXT_TMDS
2
1R5740
402MF1/16W1%1K
EXT_TMDS
2
1R5741EXT_TMDS
1K1%1/16WMF402
2
1R5745330
5%1/16W
MF402
EXT_TMDS
2
1R57461/16W
402MF
5%330
EXT_TMDS
21
R570549.9
1%1/16WMF402
EXT_TMDS
21
R5704
1%
MF402
EXT_TMDS
1/16W
49.9
2
1 C5705EXT_TMDS
470PF10%
CERM402
50V2
1C570450V
402
10%
CERM
470PF
EXT_TMDS
21
R5703
402MF
1/16W1%
49.9
EXT_TMDS
21
R5702
402MF
1/16W1%
EXT_TMDS
49.9
2
1 C5703470PF10%50VCERM
EXT_TMDS
4022
1C5702EXT_TMDS
470PF10%50V
CERM402
21
R5700EXT_TMDS
402MF
1/16W1%
49.921
R570149.9
1%1/16WMF402
EXT_TMDS
2
1 C5701EXT_TMDS
CERM402
50V10%470PF
2
1C5700470PF
10%50V
402CERM
EXT_TMDS
41
RP5711
5%1/16WSM1
10
EXT_TMDS
32
RP5712
SM11/16W5%
10
EXT_TMDS
32
RP5711
SM11/16W5%
10
EXT_TMDS
41
RP5712
SM11/16W5%
10
EXT_TMDS
32
RP5713EXT_TMDS
5%1/16W
10
SM1
41
RP5713EXT_TMDS
10
5%1/16WSM1
2
1R575010K
EXT_TMDS
402MF
1/16W5%
2
1R5751EXT_TMDS
1/16W
402
5%10K
MF
H8
H4
D8
D4
L5
H3
K11
K10
G11
G10
H11H10
J11
J10
K8
L8
J8
J7
L7
J1H1
K5
K9
K6
J5
H6
J4
G2
H2K4
J2
L4K3
K2
K1
K7
L6J6
F2G1
L2
L3
C8
G3
E3
L10
F10
A10
G4E4
L9
F9
A9
B5
D3
E11
E10
B11B10
C11
C10
D11D10
B8
A8
C7
B7
A7
C1D1
A5
F8
A6
C5D6
C4
B3B2
B1
A4D2
B4E1
E2
F4
B6
C6A2
A3
C2F3
C3
E8E7
E6
E5D7
F1
L1
H7
D5
J3
H5
G8G7
G6
G5F7
F6
F5
A1
J9
G9
D9
B9
F11
L11
H9
E9C9
A11
U5700
BGASIL1178
EXT_TMDS
2
1R5754
MF
10K
EXT_TMDS
5%
402
1/16W
2
1R5753EXT_TMDS
5%1/16W
402
10K
MF2
1R57521/16W
MF402
10K5%
EXT_TMDS
2
1R57551/16W
10K
EXT_TMDS
402MF
5%
21
R5761EXT_TMDS
49.9
402
1%1/16WMF
21
R5760
MF402
1/16W1%
49.9
EXT_TMDS
2
1 C5761470PF
402
50V10%
CERM
EXT_TMDS
2
1C5760470PF
CERM402
50V10%
EXT_TMDS
21
R5763EXT_TMDS
49.9
1%1/16WMF402
2
1 C5763
402
470PF10%50VCERM
EXT_TMDS
2
1C576210%50V
CERM402
EXT_TMDS
470PF
21
R5765EXT_TMDS
49.9
1/16W
402
1%
MF
21
R5762
402MF
1/16W1%
49.9
EXT_TMDS
21
R5764
402MF
1/16W1%
49.9
EXT_TMDS
2
1 C5765470PF10%50VCERM402
EXT_TMDS
2
1C5764470PF
10%50V
CERM402
EXT_TMDS
21
R576749.9
1%1/16WMF402
EXT_TMDS
2
1 C5767
CERM402
50V10%470PF
EXT_TMDS
2
1C5766
CERM402
50V10%
470PF
EXT_TMDS
21
R5766
402MF
1/16W1%
49.9
EXT_TMDS
41
RP5714INT_TMDS
1/16W5%
SM1
0
32
RP57140
5%1/16WSM1
INT_TMDS
41
RP5715INT_TMDS
5%
0
SM11/16W
32
RP57160
INT_TMDS
SM11/16W5%
32
RP5715
5%1/16W
INT_TMDS
0
SM1
32
RP57170
5%1/16WSM1
INT_TMDS
41
RP5716INT_TMDS
5%
SM11/16W
0
41
RP5717INT_TMDS
SM11/16W5%
0
2
1R5756
402
5%1/16W
MF
10K
EXT_TMDS
2
1R5758EXT_TMDS
5%1/16W
MF402
10K 2
1R5757
MF
10K1/16W
402
EXT_TMDS
5%
41
RP5702
SM1
5%1/16W
INT_TMDS
10
41
RP570310
SM11/16W5%
INT_TMDS32
RP570210
5%1/16WSM1
INT_TMDS
32
RP5704INT_TMDS
SM11/16W5%
10
32
RP5703
5%
SM1
INT_TMDS
10
1/16W
41
RP5704
1/16WSM1
5%
10
INT_TMDS
32
RP5706
1/16W5%
10
SM1
INT_TMDS
41
RP570610
5%1/16WSM1
INT_TMDS
2
1C5710INT_TMDS
470PF10%50V
402CERM 2
1 C5711INT_TMDS
470PF10%50V
402CERM
21
R5707INT_TMDS
402MF
1/16W1%
49.921
R5708INT_TMDS
1%1/16WMF402
49.9
21
R570949.9
1%1/16WMF402
INT_TMDS
2
1 C5712
402CERM50V10%470PF
INT_TMDS
2
1C571310%
402CERM50V
470PF
INT_TMDS
21
R571049.9
1%
MF402
1/16W
INT_TMDS
21
R5711INT_TMDS
49.9
1%1/16WMF402
2
1 C5714INT_TMDS
470PF10%50VCERM402
2
1C571550V
470PF10%
CERM402
INT_TMDS
21
R5712INT_TMDS
49.9
1%1/16WMF402
21
R5713INT_TMDS
1%1/16WMF402
49.9
2
1 C5716INT_TMDS
402CERM50V10%470PF
2
1C5717INT_TMDS
470PF
CERM402
50V10%
21
R5714INT_TMDS
MF402
1/16W1%
49.9
03
57 103051-6532
SI_DDC_DATASI_DDC_CLK
SI_I2CSEL
_GPU_RESET_L
SI_RESET_L
GPU_DVO_HSYNC
SI_HTP
GPU_DVOD<22>
GPU_DVOD<7>
GPU_DVOD<4>
GPU_DVO_VSYNC
GPU_DVOD<19>
GPU_DVOD<17>
PP3V3_SI_AVCC
MIN_NECK_WIDTH=10 MILMIN_LINE_WIDTH=15 MIL
SI_PRIMARYSI_DUAL_MODEGPU_DVOD<11>GPU_DVOD<10>GPU_DVOD<9>GPU_DVOD<8>
GPU_DVOD<5>
GPU_DVO_CLKP
GPU_DVOD<21>GPU_DVOD<20>
GPU_DVOD<15>GPU_DVOD<14>GPU_DVOD<13>GPU_DVOD<12>SI_SYNC
SI_MEXTSWING
GPU_TMDS_DN_R<1>
TMDS_CLKN
TMDS_DN<0>
TMDS_DP<1>
TMDS_DP<2>
TMDS_CLKP
TMDS_DP<0>
TMDS_DN<1>
TMDS_DN<2>
GPU_TMDS_DP_R<2> GPU_TMDS_DN_R<2>
GPU_TMDS_DP_R<0> GPU_TMDS_DN_R<0>
GPU_TMDS_CLKP_R GPU_TMDS_CLKN_R
INT_TMDS_D2_CMF
INT_TMDS_D0_CMF
INT_TMDS_CLK_CMF
GPU_TMDS_DN<2>
GPU_TMDS_DN<1>
GPU_TMDS_DP_R<2>
GPU_TMDS_DP<0> GPU_TMDS_DP_R<0>
GPU_TMDS_DP<1> GPU_TMDS_DP_R<1>
GPU_TMDS_DN<0> GPU_TMDS_DN_R<0>
GPU_TMDS_CLKP
GPU_TMDS_CLKN
SI_TMDS_DN<5>
SI_TMDS_DN<5> TMDS_DN<5>
SI_TMDS_DP<5> TMDS_DP<5>
SI_TMDS_DN<4> TMDS_DN<4>
SI_TMDS_DP<3> TMDS_DP<3>
SI_TMDS_DP<4> TMDS_DP<4>
SI_TMDS_DN<2>
SI_TMDS_DN<3> TMDS_DN<3>
SI_TMDS_DP<2>
SI_TMDS_DN<1>
SI_TMDS_DP<0>
SI_TMDS_DP<1>
SI_TMDS_DN<0>
SI_TMDS_CLKN
_PP1V8_GPU
SI_TMDS_DP<5>
SI_TMDS_DN<4>SI_TMDS_DP<4>
SI_TMDS_DP<3>
SI_TMDS_DP<2>SI_TMDS_DN<2>
SI_TMDS_DN<1>SI_TMDS_DP<1>
SI_TMDS_DP<0>SI_TMDS_DN<0>
SI_TMDS_CLKPSI_TMDS_CLKN
SI_SEXTSWING
SI_VREFMIN_LINE_WIDTH=8 MILMIN_NECK_WIDTH=8 MIL
SI_MSEN_OC
SI_TMDS_DN<3>
GPU_TMDS_DP<2>
GPU_TMDS_DP_R<1>
GPU_TMDS_CLKP_R
_PP3V3_RUN_SI
GPU_TMDS_CLKN_R
GPU_TMDS_DN_R<1>
INT_TMDS_D1_CMF
EXT_TMDS_CLK_CMF
EXT_TMDS_D2_CMF
TMDS_CLKP
TMDS_DP<0>
TMDS_DP<1>
TMDS_DP<2>
TMDS_CLKN
EXT_TMDS_D0_CMF
TMDS_DN<0>
TMDS_DN<1>
TMDS_DN<2>
TMDS_D3_CMF
TMDS_D4_CMF
TMDS_D5_CMF
TMDS_DN<3>
TMDS_DN<4>
TMDS_DP<3>
TMDS_DP<4>
TMDS_DN<5>TMDS_DP<5>
TMDS_CLKNGPU_TMDS_CLKN_R
TMDS_DN<0>GPU_TMDS_DN_R<0>
TMDS_DP<1>GPU_TMDS_DP_R<1>
TMDS_CLKPGPU_TMDS_CLKP_R
TMDS_DP<0>GPU_TMDS_DP_R<0>
TMDS_DP<2>GPU_TMDS_DP_R<2>
TMDS_DN<1>GPU_TMDS_DN_R<1>
TMDS_DN<2>GPU_TMDS_DN_R<2>
PP3V3_SI_PVCCMIN_LINE_WIDTH=15 MILMIN_NECK_WIDTH=10 MIL
SI_TMDS_CLKP
GPU_TMDS_DN_R<2>
EXT_TMDS_D1_CMF
GPU_DVOD<6>
GPU_DVOD<16>
GPU_DVOD<23>
GPU_DVO_DE
SI_SECONDARY
GPU_DVOD<18>
PP3V3_SI_VCC
MIN_NECK_WIDTH=10 MILMIN_LINE_WIDTH=15 MIL
GPU_DVOD<3>GPU_DVOD<2>GPU_DVOD<1>GPU_DVOD<0>
62
62
62
62
62
62
40
62
62
62
62
62
62
62
62
62
62
62
62
62
42
42
42
62
42
42
42
62
62
62
62
62
62
39
62
42
42
42
62
42
42
42
62
62
62
62
62 62
62
42
42
62
42
42
42
42
37
62
42
41
41
41
42
41
41
41
62 62
62 62
62 62
62
62
62
62 62
62 62
62 62
62
62
62
62 42
62 42
62 42
62 42
62 42
62
62 42
62
62
62
62
62
62
37
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
42
41
41
41
42
41
41
41
42
42
42
42
42 42
42 62
41 62
41 62
42 62
41 62
41 62
41 62
41 62
62
62
39
39
5
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
41
41
6
6
6
41
6
6
6
41 41
41 41
41 41
39
39
41
39 41
39 41
39 41
39
39
41
41 41
41 41
41 41
41 41
41 41
41
41 41
41
41
41
41
41
41
5
41
41
41
41
41
41
41
41
41
41
41
41
41
39
41
41
5
41
41
41
6
6
6
41
6
6
6
41
41
41
41
41 41
41 41
6 41
6 41
41 41
6 41
6 41
6 41
6 41
41
41
39
39
39
39
39
39
39
39
39
Preliminary
www.vinafix.vn
G2
D2S2
G1
S1
D1
G
SD
G
SD
G
SD
G
D
S
G
DS
SYM_VER-1
MINIDIN
S
D
G
G
DS
D S
G
LCFILTER
LCFILTER
LCFILTER
SYM_VER-1
SYM_VER-1
32
32
32
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
LCD INTERFACE
LCD POWER SWITCH
100K pull-ups are for
Panel has 2K pull-upsno-panel case (development)
TMDS FILTERING PLACE CLOSE TO CONNECTOR
S-VIDEO/COMP OUT INTERFACE
EXTERNAL VIDEO (DVI) INTERFACE(55mA requirement per DVI spec)
GPU DURING SHUTDOWN. WHEN
device path into DDC_CLK.Isolation will be disabled as well.
will be low, TP0610 will turn
As host rails rise, TP0610will turn off, as will remote
on, driving SOFT_PWR_ON_L low.
Power key detect path when
is pressed, 5V will be drivenpower key on remote device
system is shutdown or asleep..
into DDC_CLK. Since host rails
DDC_CLK is isolated from
pullup.powered DDC clock
Pulldown prevents
has active, self-
3904 from turningon when DVI monitor
(LVDS DDC POWER)
PLACE NEAR C5A & C5B
VIDEO CONNECTORS
(+5V_DDC SLEEP)
3V LEVEL SHIFTERS
ANALOG FILTERING
NC
DVI POWER SWITCH
Isolation required for DVI power switch
PLACE CLOSE TO CONNECTOR
graphics controllerPlace GND shorts at
graphics controllerPlace GND shorts at
VGA VSYNC BUFFERS
NOTE: Pulldown for DVI_HPD provided by DVI power switch interface
DVI DDC CURRENT LIMIT
Q5909 shares with ALS sensor to save space
PLACE NEAR 3, 11 & 19
when system is running.HPD normally driven to
on remote device pressed,HPD will be driven to 5V.COMPARATOR ENABLED BY GPU’sGPIO.
Power key detect path
3.3V. When power key
NEED PULL-DOWN BECAUSE THISSIGNAL IS TRISTATED INITIALLY
INVERTER EXPECTS ACTIVE HIGH SIGNAL
INVERTER INTERFACE
PP5V_PWRON
2
1R5984
402MF
1/16W5%
100K
2
1 C5982
402
50VCERM
20%0.001UF
2
1 C59810.001UF
402
50V20%
CERM
2
1 C5980
402
0.001UF
CERM50V20%
2
1 C5984
CERM6.3V20%
805
10UF
12
L5980FERR-1K-OHM-EMI
SM
21
L5982400-OHM-EMI
SM-1
PP3V3_ALL
2
1C59830.1UF
402CERM10V20%
4
3
2
6
Q5984FDG6324L
SC70-6
1
5
6
Q5984FDG6324LSC70-6
2
1 C59103.3PF
CERM50V
402
0.25%
2
1 C59110.25%3.3PF
402
50VCERM
2
1 C5912
402
0.25%
CERM50V
3.3PF
2
1R5908
402MF1/16W5%10K
2
1R5907
MF
10K5%1/16W
402
1
2
6
Q5907SOT-363
2N7002DW
PP3V3_RUN
4
5
3
Q59072N7002DW
SOT-363
2
1R5909100K
MF1/16W
402
5%
2
1 C5905
CERM50V
402
5%100pF
2
1R5902
402MF
5%1/16W
4.7K
2
1R5903
402MF
5%4.7K1/16W
2
1 C590450VCERM
5%100pF
402
2
1 C59000.01UF50V
603CERM
20%
21
L5900400-OHM-EMI
SM-1
4
5
3
Q5909SOT-363
2N7002DW
21
F59000.5AMP-13.2V
SM21
D5900
MBR0530
SM
2
1 C5906100pF
402
5%50VCERM
2
3
1 Q5930SM2N3904
21
R593020K
402MF
1/16W5%
2
1 C59200.1UF
402CERM10V20%
2
1R5920
402MF
1%1/16W
68.1K
2
5
1
3
4U5920
CRITICALSMLMC7211
21
R5922
1/16W
10K
1%
MF402
2
1R5921100K
1%1/16W
MF402
2
1R5923
MF1/16W
1%10K
402
1
2
6
Q59252N7002DWSOT-363
2
1R59261/16W
100K
MF402
5%
2
3
1 Q5935SM2N3904
21
R5935
1/16WMF402
10K
5%
2
1R5934330
402MF
1/16W5%
2
1
3
Q5933TP0610
SM
2
1C59600.01UF
CERM50V20%
603
21
L5960FERR-10-OHM-500MA
SM
21
L5962
0603
3.3UH
21
L59633.3UH
0603
2
1C5961
CERM50V20%
603
0.01UF
21
L5964
0603
3.3UH
21
L5961FERR-10-OHM-500MA
SM
PP3V3_RUN
PP5V_RUN
21
XW5960SM
21
XW5961SM
2
1R59005%
1/16WMF402
0
2
1R5901
402
0
MF1/16W5%
21
R5904100
MF402
1/16W5%
21
R5905
5%1/16WMF402
100
21
R5906
5%1/16WMF
100
402
4
3
2
1
6
5
J5980CRITICAL
SM-2MT21
L5981400-OHM-EMI
SM-1
4
32
1
L5915CRITICAL
165-OHMSM
5
4 3
2 1
1110
98
J5960CRITICAL
RT-THMH1177
2
1C5970
CERM402
20%0.001uF
50V
2
1R5973100K
402MF
1/16W5%
2
1C597320%50V
CERM402
0.001uF
PP3V3_RUN
2
1R5972100K
402MF
1/16W5%
9
8
7
6
5
4
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
34
33
J5970F-RT-SM
CRITICAL
G-501973
2 1
C5971
20%50VCERM402
0.001uF
2
1C59750.001uF
402CERM50V20%
21
L5975
SM
FERR-250-OHM
PP3V3_PWRON
21
C5976
50VCERM
10%
402
0.0022uF4
3 6
5
2
1
Q5975TSOP
SI3443DV
21
R5976
402MF
1/16W
100K
5%
2
1R5977100K5%1/16WMF402
2
1
3
Q59772N7002SM
2 1
R5933
402MF
1/16W5%
680
21
C59990.01uF
603CERM50V20%
9
8
7
6
5
4
3
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
36
35
34
33
32
31
C5B C5A
C4
C3
C2
C1
J5900CRITICAL
QH1112F-RT-TH
21
R59990
5%1/16WMF402
2
1R592968K5%1/16WMF402
2
1
3
Q5926SM
TP06102
1R5928330
402
1/16W5%
MF
2
1C59296.3V20%
1210CERM
47UF
4
5
3
Q5925SOT-3632N7002DW
2
1R59275%
1/16WMF402
100K
2
1R5925100K
5%1/16W
MF402
2
1C5972NO STUFF
402CERM50V20%
0.001uF
2
1C5967
402
560PF10%50V
CERM
2
1C5968
402CERM50V10%
560PF
2
1C5969
402
560PF10%50V
CERM
2
1C5962560PF
10%50V
CERM402
2
1C5963
402
560PF10%50V
CERM
2
1C5964560PF
10%50V
CERM402
43
21
FL5910CRITICAL
SM-220MHZ
43
21
FL5911SM-220MHZ
CRITICAL
43
21
FL5912CRITICAL
SM-220MHZ
4
32
1
L5916CRITICAL
2012H90-OHM-300mA
4
32
1
L5917CRITICAL
90-OHM-300mA
TMDS_CONN_DN<1>
2012H
5
4
2
1
3
U5914CRITICAL
74AHC1G32SM
VGA_VSYNC_BUF
5
4
2
1
3
U591374AHC1G32SM
CRITICAL
VGA_HSYNC_BUF 21
R5913
402MF
1/16W5%
33
21
R5914
402MF
1/16W5%
33
PP3V3_PWRON
5
4
2
1
3
U5983CRITICAL
74AHC1G32SM
4
32
1
L59182012H
TMDS_CONN_DN<2>
TMDS_CONN_DP<2>
90-OHM-300mA
CRITICAL
4
32
1
L591990-OHM-300mA
2012H
CRITICAL
4
32
1
L59202012H
90-OHM-300mA
CRITICAL
TMDS_CONN_DN<4>
4
32
1
L5921CRITICAL
90-OHM-300mA2012H
TMDS_CONN_DP<5>
TMDS_CONN_DN<5>
051-653259
03
103
MIN_NECK_WIDTH=10 MILMIN_LINE_WIDTH=20 MIL
PPBUS_INVERTER_PPBUS_INV
BRIGHT_PWM
BRIGHT_PWM_UFINV_ON_PWM
_PPBUS_ALL_A
GPU_DVI_DDC_DATA
DVI_HPD_UF DVI_HPD_DIV
SYS_POWER_BUTTON_L
HPD_ON
HPD_PWR_SNS_EN
HPD_4V_REF
COMP_DISABLE
HPD_PWR_SW
COMP_ENABLE
HPD_ON_RC
HPD_BASE
TMDS_CONN_DP<2>
PP3V3_LCD
MIN_NECK_WIDTH=10 MILMIN_LINE_WIDTH=20 MIL
_GND_CHASSIS_LVDS
PP5V_RUN_DDC_FMIN_LINE_WIDTH=10 MILMIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=10 MILMIN_NECK_WIDTH=10 MIL
DDC_CLK_ISO
DVI_HPD_UF
LVDS_U0P
GPU_HPD
VGA_RVGA_VSYNC
VGA_HSYNC
GPU_VSYNC
GPU_HSYNC
FP_PWR_EN
GPU_TV_GND2MIN_LINE_WIDTH=15 MILMIN_NECK_WIDTH=10 MIL
GPU_TV_GND1MIN_LINE_WIDTH=15 MILMIN_NECK_WIDTH=10 MIL
GPU_COMP
_GND_CHASSIS_SVIDEO
TV_GND2
TV_COMP
GPU_C
GPU_Y
TV_C
TV_Y
TV_GND1
LCD_DIGON_L
LCD_PWREN_L
MIN_NECK_WIDTH=10 MILMIN_LINE_WIDTH=20 MIL
PP3V3_LCD_FET
LVDS_DDC_DATA
LVDS_L1P
LVDS_L1N
DVI_DDC_DATA
LVDS_U1P
LVDS_U2P
LVDS_U0N
LVDS_L0N
LVDS_DDC_CLK
TMDS_CONN_CLKN
VGA_B
CLKLVDS_UP
CLKLVDS_UN
LVDS_U2N
LVDS_U1N
LVDS_L0P
FP_PWR_EN_L
VGA_BGPU_B
GPU_G
GPU_R
VGA_G
PP5V_INVERTER
TMDS_CONN_DN<0> TMDS_CONN_DN<2>
VGA_GVGA_HSYNC
_GND_CHASSIS_LVDS
VGA_VSYNC
LVDS_L2N
LVDS_L2P
CLKLVDS_LN
CLKLVDS_LP
DVI_DDC_CLK GPU_DVI_DDC_CLK
_GND_CHASSIS_INV
MIN_NECK_WIDTH=10 MILMIN_LINE_WIDTH=10 MILPP5V_INVERTER_F
DVI_HPD
DVI_TURN_ON_BASE
DVI_TRUN_ON_ILIMDVI_TURN_ONDVI_DDC_CLK_UF
PP5V_RUN_DDC
FP_PWR_EN
_GND_CHASSIS_LVDS
PP5V_RUN_DDCMIN_LINE_WIDTH=10 MILMIN_NECK_WIDTH=10 MIL
DVI_DDC_DATA_UF
DVI_DDC_CLK_UF
VGA_R
TMDS_CONN_DP<0>
_GND_CHASSIS_DVI_TOP
_GND_CHASSIS_DVI_BOTTOM
TMDS_CONN_DN<5>
TMDS_CONN_DP<5>
TMDS_CONN_DP<1>
TMDS_CONN_DP<4>
TMDS_CONN_DP<3>
TMDS_CONN_DN<1>
TMDS_CONN_DN<3>
TMDS_CONN_DN<4>
TMDS_CONN_CLKP
TMDS_CONN_DN<3>
TMDS_CONN_DP<3>TMDS_DP<3>
TMDS_DN<3>
TMDS_CONN_DP<4>TMDS_DP<4>
TMDS_DN<4>
TMDS_DP<5>
TMDS_DN<5>
TMDS_CONN_DN<0>
TMDS_CONN_DP<0>TMDS_DP<0>
TMDS_DN<0>
TMDS_CONN_DP<1>TMDS_DP<1>
TMDS_DN<1>
TMDS_DP<2>
TMDS_DN<2>
TMDS_CONN_CLKP
TMDS_CONN_CLKNTMDS_CLKN
TMDS_CLKP
_GND_CHASSIS_INV
17
17
16
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
8
42
13
62
42
42
39
42 42
42
42
39
39
39
39
39
39
39
39
42
42
39
39
39
39
39
42
42
62 62
42 42
42
42
39
39
39
39
42
42
42
42
42
42
42
42
62
62
62
62
62
62
62
62
62
42
62
62 62
62
62 62
62
62
62
62
62 41
41
62 41
41
41
41
42
42 62
62
42
42
42
42
42
42
42
5
6
39
5
39
6
6
39
42
6
5
6
6
39
6 6
6
39
39
39
39
5
6
6
39
39
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6 39
39
39
6
6
42 42
6 6
5
6
6
6
6
6
39
5
6
6
39
5
6
6
6
6
42
5
5
42
42
42
42
42
42
42
42
6
42
42 41
41
42 41
41
41
41
42
42 6
6
42 6
6
6
6
6
6 41
41
5
Preliminary
www.vinafix.vn
HT_CTL_TXN0
HT_CTL_TXP0
HT_CTL_RXN0
HT_CTL_RXP0
HT_CLK_RXN0HT_CLK_RXP0
HT_CLK_TXN0HT_CLK_TXP0(SYM 5 OF 7)
INTERFACEHT
HT_LDTREQ*
HT_LDTSTOP*HT_RESET*
HT_PWROK
HT_CAD_RXN7
HT_CAD_RXP7HT_CAD_RXN6
HT_CAD_RXN1
HT_CAD_RXN5HT_CAD_RXP5
HT_CAD_RXP6
HT_CAD_RXN4HT_CAD_RXP4
HT_CAD_RXN3
HT_CAD_RXP3HT_CAD_RXN2
HT_CAD_RXP2
HT_CLK
HT_CAD_RXP0
HT_CAD_RXN0
HT_CAD_RXP1
HT_PVTREF1
HT_PVTREF0
HT_CAD_TXP7
HT_CAD_TXN7
HT_CAD_TXN6
HT_CAD_TXN1
HT_CAD_TXN5
HT_CAD_TXN4
HT_CAD_TXP2
HT_CAD_TXP3
HT_CAD_TXP4
HT_CAD_TXN2
HT_CAD_TXN3
HT_CAD_TXP5
HT_CAD_TXP6
HT_CAD_TXN0
HT_CAD_TXP1
HT_CAD_TXP0
HT_CLK_AVSS
AVDDHT_CLK VDD_HT VDD_HT
2_5 1_2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
MASTER: GILA
U3LITE HT
NET_SPACING_TYPE DIFFERENTIAL_PAIRELECTRICAL_CONSTRAINT_SET
8 MIL SPACING TO ANYTHING ELSE4 MIL SPACING IN GROUP
HT_2V5
10 MIL SPACING TO ANYTHING ELSE5 MIL SPACING FOR DIFF PAIR
HT_1V2
LENGTH TOLERENCE DOES NOT NEED TO BE SPECIFIEDMATCHED GROUP CONSTRAINT IS TIGHT ENOUGH
2
1 C6006
402
0.1UF20%10VCERM2
1 C6005
CERM10V20%0.1UF
4022
1 C6004
402
0.1UF20%10VCERM2
1 C6002
402
0.1UF20%10VCERM2
1 C6001
CERM10V20%0.1UF
4022
1 C60000.1UF
CERM402
20%10V 2
1 C6007
CERM10V20%0.1UF
4022
1 C6008
CERM10V20%0.1UF
402
2
1 C60120.1UF20%10VCERM402
21
R60002.2
603MF
1/16W5%
2
1 C6013
402
1UF
CERM
10%6.3V
2
1 C6011
402
0.1UF20%10VCERM2
1 C601010V20%
402CERM
0.1UF
2
1R6001
402MF1/16W1%200
2
1R6002
402MF1/16W5%1K
2
1R60031K5%1/16WMF4022
1R6004
402MF1/16W5%1K
2
1R6005
402MF1/16W5%1K
I46
I47
I48
I49
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
I60
I61
I62
I63
I64
I65
I66
I67
I68
I69
I70
I71
I72
I73
I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
G6
J10
L9
N10
N6N2
R9
T8T4
G9
F9
L8
L7H8
H7
L6
L5
V2
V1
R7
R8
N1
P1
G8
F8
H9
M7
M5
P6
P8
R5
U4
U6
U8
M8
M6
P5
P7
R6
U3
U5
U7
U1
R1
R3
P2
M2
M4
L3
L1
U2
T1
R2
P3
M1
M3
L4
L2
U3
OMIT
U3LITEV1.0-300MM
PBGA
03
60 103
051-6532
HT_NB_TO_SB HT_NB_TO_SB_CLKHT_NB_TO_SB_CLK_P HT_NB_TO_SB
HT_NB_TO_SB_CTLHT_NB_TO_SB_CTL_N HT_NB_TO_SB HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CAD1HT_NB_TO_SB_CAD_P<1> HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CAD4HT_NB_TO_SB_CAD_P<4> HT_NB_TO_SB
HT_SB_TO_NB HT_SB_TO_NB_CLKHT_SB_TO_NB_CLK_N HT_SB_TO_NB
HT_SB_TO_NB_CAD0HT_SB_TO_NB_CAD_P<0> HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<3> HT_SB_TO_NB_CAD3HT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB HT_NB_TO_SB_CAD0HT_NB_TO_SB_CAD_N<0> HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CLKHT_NB_TO_SB_CLK_N HT_NB_TO_SBHT_NB_TO_SB_CTLHT_NB_TO_SB_CTL_P HT_NB_TO_SB HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CAD0HT_NB_TO_SB_CAD_P<0> HT_NB_TO_SB
HT_CTLHT_RESET_L HT_2V5
HT_CTLHT_LDTREQ_L HT_2V5
HT_SB_TO_NB_CAD0HT_SB_TO_NB_CAD_N<0> HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CTL_N HT_SB_TO_NB_CTLHT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB HT_NB_TO_SB_CAD7HT_NB_TO_SB_CAD_N<7> HT_NB_TO_SBHT_NB_TO_SB HT_NB_TO_SB_CAD7HT_NB_TO_SB_CAD_P<7> HT_NB_TO_SBHT_NB_TO_SB HT_NB_TO_SB_CAD6HT_NB_TO_SB_CAD_N<6> HT_NB_TO_SB
HT_SB_TO_NB_CAD_P<6> HT_SB_TO_NB_CAD6HT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB HT_NB_TO_SB_CAD5HT_NB_TO_SB_CAD_N<5> HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CAD3HT_NB_TO_SB_CAD_P<3> HT_NB_TO_SBHT_NB_TO_SB HT_NB_TO_SB_CAD2HT_NB_TO_SB_CAD_N<2> HT_NB_TO_SBHT_NB_TO_SB HT_NB_TO_SB_CAD2HT_NB_TO_SB_CAD_P<2> HT_NB_TO_SB
HT_NB_TO_SB_CAD_N<1> HT_NB_TO_SB HT_NB_TO_SB_CAD1HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CAD5HT_NB_TO_SB_CAD_P<5> HT_NB_TO_SB
HT_SB_TO_NB HT_SB_TO_NB_CLKHT_SB_TO_NB_CLK_P HT_SB_TO_NB
HT_SB_TO_NB_CAD_P<2> HT_SB_TO_NB_CAD2HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_P<1> HT_SB_TO_NB_CAD1HT_SB_TO_NB HT_SB_TO_NB
HT_PWROK HT_2V5HT_PWROK
HT_SB_TO_NB_CAD_P<7> HT_SB_TO_NB_CAD7HT_SB_TO_NB HT_SB_TO_NBHT_SB_TO_NB_CAD_N<7> HT_SB_TO_NB_CAD7HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CTL_P HT_SB_TO_NB_CTLHT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB HT_NB_TO_SB_CAD6HT_NB_TO_SB_CAD_P<6> HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CAD3HT_NB_TO_SB_CAD_N<3> HT_NB_TO_SB
HT_NB_TO_SB HT_NB_TO_SB_CAD4HT_NB_TO_SB_CAD_N<4> HT_NB_TO_SB
HT_SB_TO_NBHT_SB_TO_NB_CAD_N<1> HT_SB_TO_NB_CAD1HT_SB_TO_NB
HT_SB_TO_NB_CAD_P<4> HT_SB_TO_NB_CAD4HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NBHT_SB_TO_NB_CAD_P<5> HT_SB_TO_NB_CAD5HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<4> HT_SB_TO_NB_CAD4HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<5> HT_SB_TO_NB_CAD5HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<6> HT_SB_TO_NB_CAD6HT_SB_TO_NB HT_SB_TO_NB
HT_CTL HT_2V5HT_LDTSTOP_L
PP1V2_HT
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<4>
PP1V2_HT
PP2V5_HT
HT_LDTREQ_L
HT_RESET_LHT_LDTSTOP_L
HT_PWROK
HT_SB_TO_NB_CAD_N<7>HT_SB_TO_NB_CAD_P<7>HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_N<4>HT_SB_TO_NB_CAD_P<5>HT_SB_TO_NB_CAD_N<5>HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_P<2>HT_SB_TO_NB_CAD_N<2>HT_SB_TO_NB_CAD_P<3>HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<0>HT_SB_TO_NB_CAD_N<0>HT_SB_TO_NB_CAD_P<1>
HT_CLK66M_NB
HT_NB_PVTREF1HT_NB_PVTREF0
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_N<7>HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_P<6>HT_NB_TO_SB_CAD_N<5>HT_NB_TO_SB_CAD_P<5>HT_NB_TO_SB_CAD_N<4>HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<1>HT_NB_TO_SB_CAD_P<2>HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_N<3>HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_P<1>HT_NB_TO_SB_CAD_N<0>HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CLK_PHT_NB_TO_SB_CLK_N
HT_SB_TO_NB_CLK_PHT_SB_TO_NB_CLK_N
HT_SB_TO_NB_CTL_PHT_SB_TO_NB_CTL_N
HT_NB_TO_SB_CTL_PHT_NB_TO_SB_CTL_N
PP2V5_HT
PP2V5_HT
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
PP1V5_PWRON_HT_NB_AVDDVOLTAGE=1.5V
PP1V5_PWRON_NB_AVDD
HT_SB_TO_NB_CAD_P<3> HT_SB_TO_NB_CAD3HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<2> HT_SB_TO_NB_CAD2HT_SB_TO_NB HT_SB_TO_NB
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Preliminary
www.vinafix.vn
SEL_HT00_H
HT_S100M66M
HT_CTLOUT_NHT_CTLOUT_P
HT_CTLIN_NHT_CTLIN_P
HT_LDTSTOP_LHT_RESET_L
HT_LDTREQ_L
HT_RXVDDHTHT_PLLVDDPDVDDAVDD
HT_CADIN_7_P
HT_CADIN_7_N
HT_PWROK_H
HT_CADIN_6_N
HT_CADIN_3_P
HT_CADIN_3_NHT_CADIN_4_P
HT_CADIN_4_NHT_CADIN_5_P
HT_CADIN_5_N
HT_CADIN_6_P
HT_CADIN_2_NHT_CADIN_2_P
HT_CADIN_1_N
HT_CADIN_1_P
HT_CLKIN_N
HT_CLKIN_P
HT_CADIN_0_P
HT_CADIN_0_N
AGND DGNDHT_PLL
HT_RXGND
HT_CADOUT_7_P
HT_CADOUT_7_N
HT_TXGND
HT_R100N
HT_R100P
HT_CADOUT_6_NHT_CADOUT_6_P
HT_CADOUT_5_N
HT_CADOUT_5_PHT_CADOUT_4_N
HT_CADOUT_4_PHT_CADOUT_3_N
HT_CADOUT_3_P
HT_CADOUT_2_NHT_CADOUT_2_P
HT_CADOUT_1_N
HT_CADOUT_1_PHT_CADOUT_0_N
HT_CADOUT_0_P
HT_CLKOUT_N
HT_CLKOUT_P(3 OF 8)
HT_TXVDD
HT_REFCLK
HYPERTRANSPORT
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
0 = 66MHz
HT RefClk
1 = 100MHz
HT I/F Speed
1 = 100MHz0 = 200MHz
1.0V pk-pk
Master: Fizzy
Shasta HyperTransport
- _PP1V2_PWRON_HT
Signal aliases required by this page:
AC coupled
(NONE)
- _PP2V5_PWRON_HT
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE
Page NotesPower aliases required by this page:
BOM options provided by this page:
DIFFERENTIAL_PAIR
- SB_HT_200M Stuffs resistor to select 200MHz HT I/F.
2
1 C62310.1uF
402CERM10V20%
2
1 C623020%10VCERM402
0.1uF
2
1 C622020%10VCERM402
0.1uF
2
1R62511K
402MF
1/16W5%
SB_HT_200M
B19
V6
G11
B9
B12
G10
A9
A12
D8
G13
B17
B15
G12
A17
A15
C18
C8 E10
F10
E16
B6
A6
C7
C6
E17 A19
C13
D13
F13
E13
B10
A10
D15
C15
A13B13
E12F12
C12
D12
A11
B11
D11C11
E11
F11
B8
A8
D10
C10
B14A14
E14F14
D14
C14
B16
A16
D16C16
F15
E15
B18
A18
D17
C17
U2300OMIT
SHASTABGAV1.0
21
C6255
20%10VCERM402
0.1uF
2
1R6255
402
1/16WMF
1%332
21
R6200
5%1/10WFF805
3.3
21
R6210
5%1/10WFF805
3.3
2
1R62545%
1/16WMF402
10K
2
1 C620010uF
CERM6.3V20%
12062
1 C6201
CERM402
10%1uF6.3V
2
1 C621110%
CERM402
1uF6.3V2
1 C621020%6.3VCERM1206
10uF
2
1C62505%50V
CERM402
47pF2
1 C62515%50VCERM402
47pF
21
R6250
1/16WMF402
1%
82.5
2
1R6252NO STUFF
4.7K
402MF
1/16W5%
2
1R62534.7K
402
5%1/16W
MF
2
1 C624020%10VCERM402
0.1uF2
1 C624110V
402
0.1uF20%
CERM 2
1 C6242
402CERM10V20%0.1uF
2
1 C623220%10VCERM402
0.1uF
TITLE=FIZZYABBREV=DRAWING
62 103
03051-6532
_PP1V2_PWRON_HT
MIN_NECK_WIDTH=15 mil
PP1V2_PWRON_HT_PLLAVDDVOLTAGE=1.2VMIN_LINE_WIDTH=20 mil
PP1V2_PWRON_HT_PLLDVDDVOLTAGE=1.2VMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=15 mil
HT_CLK66M_SB_C
HT_NB_TO_SB_CAD_P<0>HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CTL_N
HT_SB_TO_NB_CAD_P<3>
HT_RESET_L
15 MIL SPACING HT_CLK66M_SB_C
HT_SB_TO_NB_CTL_PHT_NB_TO_SB_CTL_P
HT_SB_TO_NB_CAD_P<6>HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<7>HT_SB_TO_NB_CAD_N<6>HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_N<7>
HT_NB_TO_SB_CAD_P<6>HT_NB_TO_SB_CAD_N<5>HT_NB_TO_SB_CAD_P<5>HT_NB_TO_SB_CAD_N<4>HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_P<3>HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_N<2>HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CLK_N
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CLK_P
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_P<4>HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_N<1>HT_SB_TO_NB_CAD_P<2>HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<1>HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CLK_N
HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CLK_P
HT_CLK66M_SBSB_HT_R100_NSB_HT_R100_P
_PP1V2_PWRON_HT
_PP2V5_PWRON_HT
HT_NB_TO_SB_CAD_P<7>
_PP1V2_PWRON_HT
HT_LDTREQ_L
HT_SB_TO_NB_CTL_N
HT_SB_TO_NB_CAD_N<7>
HT_LDTSTOP_L
HT_PWROK
SB_SELHT100
_PP1V2_PWRON_HT
SB_HT_S100M66M
LAST_MODIFIED=Mon Feb 23 19:06:27 2004
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5 Preliminary
www.vinafix.vn
PCI
(4 OF 8)
PCI1CLK_H
PCIBR_CLK_H
PCI1PAR_H
PCI1AD_31_HPCI1AD_30_H
PCI1AD_29_H
PCI1AD_28_HPCI1AD_27_H
PCI1AD_26_H
PCI1AD_19_H
PCI1AD_18_H
PCI1AD_16_HPCI1AD_17_H
PCI1AD_24_H
PCI1AD_25_H
PCI1AD_20_H
PCI1AD_21_H
PCI1AD_22_HPCI1AD_23_H
PCI1AD_15_H
PCI1AD_8_HPCI1AD_9_H
PCI1AD_10_H
PCI1AD_11_HPCI1AD_12_H
PCI1AD_13_H
PCI1AD_14_H
PCI1AD_7_H
PCI1AD_6_HPCI1AD_5_H
PCI1AD_4_H
PCI1AD_0_HPCI1AD_1_H
PCI1AD_2_H
PCI1AD_3_H
PCIVDDPVDDOPC
PCI1GNT_0_L
PCI1REQ_0_L
PCI1REQ_1_LPCI1GNT_1_L
PCI1REQ_2_L
PCI1GNT_2_L
ROMCS_L
ROMOE_LROMRW_L PCI1RST_L
PCI1STOP_L
PCI1TRDY_L
PCI1IRDY_LPCI1FRAME_L
PCI1DEVSEL_L
PCI1C_BE_3_LPCI1C_BE_2_L
PCI1C_BE_1_L
PCI1C_BE_0_L
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
"Slot G" - AD27
"Slot A" - AD17
"Slot D" - AD20
- _PP3V3_SB_PCI (can be _PP3V3_PCI)
Shasta PCI Interface
ELECTRICAL_CONSTRAINT_SET DIFFERENTIAL_PAIR
- _PP3V3_PCI
NET_SPACING_TYPE
Master: Link
Power aliases required by this page:
Page Notes
- _PP2V5_PWRON_SB
AD11 - PCI2 (0x106B/0x0055)AD11 - PCI1 (0x106B/0x0054)
BOM options provided by this page:(NONE)
(NONE)Signal aliases required by this page:
AD23 - KeyLargo (0x106B/0x004F, PCI1)
AD31 - Ethernet (0x106B/0x0051, PCI0)
AD11 - PCI0 (0x106B/0x0053)PCI Devices implemented on this page:
AD28 - SATA 150 (0x1166/0x0240, PCI0 or 2)AD29 - UATA 133 (0x106B/0x0050, PCI0 or 2)AD30 - FireWire (0x106B/0x0052, PCI0 or 2)
- _PP3V3_PWRON_SB
Shasta drives PCI RESET, but its output
it is ANDed with a reset from the SMU.may not be valid during power-up, so
2
1 C74090.1uF
402CERM10V20%
2
1 C740820%10VCERM402
0.1uF2
1 C74070.1uF
402CERM10V20%
2
1 C740620%10VCERM402
0.1uF2
1 C7405
CERM
20%0.1uF
402
10V
2
1 C7404
402
0.1uF20%10VCERM2
1 C740320%10VCERM402
0.1uF2
1 C74020.1uF
402CERM10V20%
2
1 C74010.1uF
402CERM10V20%
2
1 C740020%10VCERM402
0.1uF
2
1C74230.1uF
CERM10V20%
4022
1C74220.1uF
402CERM10V20%
2
1C74210.1uF
20%10V
CERM402
2
1C742020%
0.1uF
CERM10V
402
63
RP74024.7K
1/16W5%
SM154
RP7402
SM1
5%1/16W
4.7K
72
RP74024.7K
1/16W5%
SM181
RP74024.7K
5%1/16WSM1
72
RP74004.7K
5%1/16WSM1
81
RP74004.7K
1/16W5%
SM154
RP74004.7K
1/16W5%
SM163
RP74004.7K
1/16W5%
SM1
54
RP74014.7K
5%1/16WSM1
63
RP74014.7K
5%1/16WSM1
27
RP74014.7K
1/16W5%
SM1
V19
U21
R20
N21
M16
J21
H16
E21
B22
AA22
Y10
AA9AB8
U20
N20
J18
B20
AB9
P19
P17
U18
V17
AB20
AB18
N17
R21
V18
AB19
AA18
T21
T22
V20
V22P16
L19
U19
P22M20
N16
M21L20
M18
M22
T17AA21
L22
T16
W20Y21
T18
T19R18
Y22
W21R17
R16
K19
T20
P18
V21P20
R22
P21N19
M19
N18M17
L18
U2300 OMIT
SHASTAV1.0BGA
2
1 C7410
805
20%
CERM
10uF6.3V
NO STUFF
2
1 C7411
805
6.3V
10uF
CERM
20%
NO STUFF
5
4
1
2
3
U7450MC74VHC1G08SOT23-5
2
1 C7450
402
20%10VCERM
0.1uF
2
1R74504.7K
402MF1/16W5%
2
1R74554.7K
402MF1/16W5%
TITLE=LINKABBREV=DRAWING 74 103
03051-6532
PCI_CTL PCI_DEVSEL_LPCI_PARPCI
PCI PCI_CBE_L<3..0>
PCI_AD<16..0>PCI_AD
PCI_AD<20>PCI_AD20PCI_AD PCI_AD<19..18>
SYS_WARM_RESET_L
_PP3V3_SB_PCI
PCI_TRDY_LPCI_CTLPCI_CTL PCI_STOP_L
PCI_AD<17>PCI_AD17
PCI_AD PCI_AD<26..24>
PCI_FRAME_LPCI_CTL
PCI_AD<21>PCI_AD21
PCI_AD<27>PCI_AD27
PCI_AD<31..28>PCI_AD
PCI_AD<23>PCI_AD23
PCI_CTL PCI_IRDY_L
PCI_SLOTD_REQ_L
PCI_SLOTD_GNT_L
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
PCI_SLOTA_GNT_L
PCI_SLOTA_REQ_L
PCI_TRDY_L
PCI_FRAME_L
PCI_STOP_L
PCI_IRDY_L
PCI_DEVSEL_L
_PP3V3_PCI
_PP3V3_PCI
PCI_AD<22>PCI_AD22
PCI_CLK33M_SB_EXT
PCI_CLK66M_SB_INT
PCI_SLOTA_GNT_LPCI_SLOTA_REQ_L
PCI_SLOTG_REQ_LPCI_SLOTG_GNT_L
PCI_SLOTD_REQ_LPCI_SLOTD_GNT_L
ROM_CS_LROM_OE_LROM_WE_L
_PP2V5_PWRON_SB
PCI_SB_TRDY_LPCI_SB_STOP_L
PCI_SB_IRDY_L
PCI_SB_PAR
PCI_SB_FRAME_L
PCI_SB_CBE_L<3>
PCI_SB_AD<31>
PCI_SB_CBE_L<0>
PCI_SB_AD<28>
PCI_SB_CBE_L<2>
PCI_SB_AD<29>
PCI_SB_CBE_L<1>
PCI_SB_DEVSEL_L
PCI_SB_AD<30>
PCI_SB_AD<21>
PCI_SB_AD<19>PCI_SB_AD<18>
PCI_SB_AD<20>
PCI_SB_AD<22>PCI_SB_AD<23>PCI_SB_AD<24>PCI_SB_AD<25>PCI_SB_AD<26>PCI_SB_AD<27>
PCI_SB_AD<10>
PCI_SB_AD<7>
PCI_SB_AD<9>PCI_SB_AD<8>
PCI_SB_AD<11>PCI_SB_AD<12>
PCI_SB_AD<14>
PCI_SB_AD<17>
PCI_SB_AD<15>PCI_SB_AD<16>
PCI_SB_AD<13>
PCI_SB_AD<0>
PCI_SB_AD<6>
PCI_SB_AD<1>PCI_SB_AD<2>
PCI_SB_AD<4>PCI_SB_AD<3>
PCI_SB_AD<5>
_PP3V3_PWRON_SB
PCI_RESET_LSB_PCI_RESET_L
LAST_MODIFIED=Mon Feb 23 19:06:40 2004
49
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49
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49
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62
48
49
49
48
48
48
48
48
48
48
48
48
49
48
48
49
48
48
48
48
48
48
46
46
49
56
23
48
47
48
48
47
47
47
23
47
47
47
47
47
48
47
47
48
47
47
47
47
47
47
47
47
45
45
48
47
47
47
47
47
23
21
47
45
47
47
46
46
46
22
45
45
46
46
45
47
46
46
47
45
48
48
45
45
45
45
45
45
45
23
23
47
25
45
45
48
48
46
46
46
21
62
18
46
6
6
6
6
6
6
5
5
6
6
6
6
6
6
6
6
6
6
45
45
45
45
6
6
6
6
6
6
6
5
5
6
5
25
6
6
45
45
45
45
6
6
6
5
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
48
62
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5
5
Preliminary
www.vinafix.vn
A0A1
A6
A2A3A4A5
A9A8A7
A10A11A12A13A14A15A16
A20
A17A18A19
CEOEWEWPPWD
GND
DQ0DQ1
DQ6DQ5
DQ2DQ3DQ4
DQ7
VPP VCC
FEPR-1MX8
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Allows ROM override moduleto intercept ROM chip select
BootROM
- _PP3V3_PCIPower aliases required by this page:
Page Notes
(NONE)Signal aliases required by this page:
(NONE)
part number. Must use a TABLE_x_ITEM symbol to declare U7500 part number.
NOTE: This page does not specify a BootROM
BOM options provided by this page:
Master: Fizzy
12
9
11 3130
10
24
3923
35
34
33
32
28
27
26
25
22
7
8
14
15
16
17
18
38
19
37
13
40
1
2
3
4
5
6
36
20
21
U7500
TSOP
OMIT
90.0ns
21
R7502
1/16W
1K
5%
MF402
2
1R7501
402MF1/16W5%10K
2
1R75005%
10K1/16W
MF402
2
1C7500
805
20%10V
CERM
2.2uF2
1C7501
402CERM10V20%
0.1uF2
1C75020.1uF
20%10V
CERM402
ABBREV=DRAWINGTITLE=FIZZY
03051-6532
10375
_PP3V3_PCI
_PP3V3_PCI
ROM_CS_L
PCI_RESET_LROM_WP_LROM_WE_LROM_OE_L
PCI_AD<0>PCI_AD<1>
PCI_AD<10>PCI_AD<11>PCI_AD<12>PCI_AD<13>PCI_AD<14>PCI_AD<15>PCI_AD<16>PCI_AD<17>PCI_AD<18>PCI_AD<19>
PCI_AD<2>
PCI_AD<20>
PCI_AD<3>PCI_AD<4>PCI_AD<5>PCI_AD<6>PCI_AD<7>PCI_AD<8>PCI_AD<9>
PCI_AD<24>PCI_AD<25>PCI_AD<26>PCI_AD<27>PCI_AD<28>PCI_AD<29>PCI_AD<30>PCI_AD<31>
ROM_ONBOARD_CS_L
LAST_MODIFIED=Mon Feb 23 19:06:47 2004
49
49
48
48
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23
23
45
45
45
45
45
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45
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45
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45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
47
5
5
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DRAWING
- _PCI_CLK33M_AIRPORT (33MHz PCI clock)
- _PP3V3_PCI
(NONE)
NOTE: This AirPort implementation does
AD17 (Slot "A") - AirPort (0x????/0x????)
Page NotesPower aliases required by this page:
not support PME#.
PCI Devices implemented on this page:
Signal aliases required by this page:
BOM options provided by this page:
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
AirPort Extreme
NCNC
RESERVED FOR USB_DP AND USB_DN
NC
NCNC
NC
516S01792
1R7601
402MF
1/16W5%10K
21
R760022
1/16WMF
5%
402
9
82
81
80
8
79
7877
7675
7473
7271
70
7
69
6867
6665
6463
6261
60
6
59
5857
5655
5453
5251
50
5
49
4847
4645
4443
4241
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
J7600M-ST-SM
CPB-7280-1210
CRITICAL
051-6532 03
76 103TITLE=FIZZYABBREV=DRAWING
PCI_SLOTA_REQ_L
PCI_RESET_LTP_AIRPORT_RF_DISABLE
_PP3V3_PCI
PCI_AD<31>
PCI_AD<29>PCI_AD<27>PCI_AD<25>
PCI_CBE_L<3>
PCI_AD<21>PCI_AD<19>
PCI_AD<17>
PCI_CBE_L<2>PCI_IRDY_L
AIRPORT_CLKRUN_L_PD
PCI_CBE_L<1>PCI_AD<14>
PCI_AD<12>PCI_AD<10>ROM_WE_LPCI_AD<8>PCI_AD<7>
PCI_AD<5>ROM_ONBOARD_CS_LPCI_AD<3>
PCI_AD<1>ROM_CS_L
PCI_AD<23>
PCI_AD<11>
_PCI_CLK33M_AIRPORT
PCI_SLOTA_GNT_LTP_AIRPORT_PME_LPCI_SLOTA_INT_LPCI_AD<30>
PCI_AD<28>PCI_AD<26>PCI_AD<24>PCI_SLOTA_IDSEL
PCI_AD<22>PCI_AD<20>PCI_PARPCI_AD<18>PCI_AD<16>
PCI_FRAME_LPCI_TRDY_L
PCI_AD<15>PCI_AD<13>
PCI_AD<9>PCI_CBE_L<0>ROM_OE_LPCI_AD<6>
PCI_AD<4>PCI_AD<2>PCI_AD<0>
PCI_AD<17>
PCI_CLK_AIRPORT _PCI_CLK33M_AIRPORTCLOCKS
PCI_DEVSEL_LPCI_STOP_L
LAST_MODIFIED=Mon Feb 23 19:06:53 2004
62
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62
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62
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48
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46
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46
48
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48
46
46
48
48
46
46
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48
46
46
46
46
46
46
48
48
45
45
23
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
46
45
45
45
45
45
47
45
23
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
47
45
45
6
5
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
6
6
Preliminary
www.vinafix.vn
AD1
SRMOD
NANDTEST
NTEST1
SRDTASRCLK
TEST
TEBAMC
SMC
LEGC
PME
PCLKINTCINTBINTA
VBBRST
SMI
CRUN
SERR
REQ
STOPTRDYIRDYFRAME
IDSELDEVSEL
GNTPERR
PAR
CBE3CBE2CBE1CBE0
AD31AD30AD29AD28
AD24AD23AD22AD21AD20AD19AD18
AD25AD26AD27
AD14AD13AD12AD11AD10AD9AD8
AD15AD16AD17
AD7AD6
AD0
AD2
AD5AD4
VCCRST
AD3
VDD_PCI
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Master: Fizzy
facilitate NAND-tree testing
(PCI_AD<27>)
RP7702 & RP7703 required to
OD
OD
ODODODOD
IPD
IPD
IPDIPD
IPD
IPD
USB 2.0 PCI Interface
(PCI RESET)
(CHIP RESET)
DIFFERENTIAL_PAIRNET_SPACING_TYPE
Page Notes
BOM options provided by this page:
Power aliases required by this page:
Signal aliases required by this page:
PCI Devices implemented on this page:AD27 (Slot "G") - USB2 (0x1033/0x0035)
NOTE: This USB2 implementation supports
- _PCI_CLK33M_USB2 (33MHz PCI clock)
- _PPVIO_PCI (to 3.3V or 5V)
(NONE)
D3cold.
ELECTRICAL_CONSTRAINT_SET
2
1C77030.1uF
402CERM10V20%
2
1R77165%
402MF
1/16W
10K
72
RP7703
5%1/16WSM1
47
63
RP770247
SM11/16W5%
72
RP7702
5%1/16WSM1
47
54
RP770347
5%
SM11/16W
63
RP7703
1/16W5%
SM1
47
54
RP770247
SM11/16W5%
2
1R77141/16W
402MF
225%
C8
M4
H3
C9
B8
G1
L8
N7
G3
P9
N9
M9
L6
M7
H1
C6
D9
H2
A8
J4
M8
M10
L7
F4
A7
B7
C7
B3
D6
F3
G2
N6
C3
F1
J3
M2
P7
L1
L2
M1
N3
M3
N4
A6
B6
P4
C5
A5
C4
B5
A4
B4
C1
C2
D2
D1
N5
D3
E1
E3
F2
J1
J2
K3
K1
L3
K2
P5
M5
U7700FBGA
NEC_uPD720101_USB2
CRITICAL
2
1R77131/16W
MF402
5%10K
8
1
RP7703
1/16WSM1
5%47
2
1R77154.7K
402MF
1/16W5%
TITLE=FIZZYABBREV=DRAWING
77 103
03051-6532
CLOCKSPCI_CLK_USB2 _PCI_CLK33M_USB2
NEC_PME_L
TP_NEC_SMI_L
NEC_SERR_L_PU
TP_NEC_AMC
PCI_AD<0>
TP_NEC_SMC
TP_NEC_TEB
TP_NEC_SRDATA
PCI_AD<12>
NEC_INTC_L
NEC_INTA_L
NEC_VBBRST_L
NEC_VCCRST_L
_PP3V3_PCI
PCI_SLOTG_IDSEL
PCI_AD<4>PCI_AD<3>
PCI_AD<10>
PCI_AD<13>PCI_AD<14>
PCI_AD<17>PCI_AD<16>PCI_AD<15>
PCI_AD<18>PCI_AD<19>PCI_AD<20>
PCI_AD<22>PCI_AD<21>
PCI_AD<23>PCI_AD<24>PCI_AD<25>PCI_AD<26>
PCI_AD<29>PCI_AD<28>
PCI_AD<30>PCI_AD<31>
PCI_CBE_L<3>
PCI_CBE_L<1>PCI_CBE_L<2>
PCI_PARPCI_FRAME_LPCI_IRDY_LPCI_TRDY_LPCI_STOP_L
PCI_DEVSEL_LPCI_SLOTG_REQ_LPCI_SLOTG_GNT_L
_PCI_CLK33M_USB2
NEC_CRUN_L_PD
NEC_LEGC_PD
TP_NEC_NTEST1
TP_NEC_TEST
TP_NEC_SRCLKTP_NEC_NANDTEST
TP_NEC_SRMOD
NEC_INTB_L
SYS_WARM_RESET_L
PCI_RESET_L
SYS_PME_L
NEC_PERR_L_PU
PCI_AD<11>
PCI_SLOTG_INT_L
PCI_AD<1>PCI_AD<2>
PCI_AD<9>PCI_AD<8>
PCI_AD<6>PCI_AD<5>
PCI_AD<7>
_PPVIO_PCI_USB2
PCI_CBE_L<0>
PCI_AD<27>
PCI_SB_AD<27>
LAST_MODIFIED=Mon Feb 23 19:07:00 2004
62
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62
62
62
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49
49
49
49
49
49
49
49
49
62
62
62
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49
49
49
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49
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62
62
62
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62
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45
47
47
47
47
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49
47
46
46
45
46
46
46
46
46
46
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46
46
46
46
47
47
47
46
46
46
46
46
46
46
47
47
47
47
47
47
47
47
47
23
46
46
46
46
46
46
46
46
46
47
46
48
45
45
23
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
48
22
45
23
45
45
45
45
45
45
45
45
45
45
62
5
6
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
45
45
5
5
5
13
6
23
6
6
6
6
6
6
6
5
6
6
45
Preliminary
www.vinafix.vn
C/BE3*C/BE2*C/BE1*C/BE0*
VR_EN*VR_PORT
VCCCBVCCP
GND
VCC
GRST
MFUNC4MFUNC5MFUNC6
MFUNC3
MFUNC0
SUSPEND
MFUNC1MFUNC2
PCLK
SPKROUT
GNT
TRDYSTOPFRAME
PRSTREQ
DEVSEL
PERRIDSELSERRIRDY
AD31
PAR
AD30AD29AD28AD27
AD20AD21
AD18AD19
AD26AD25AD24AD23AD22
AD17
AD10AD11
AD9AD8
AD16AD15AD14AD13AD12
AD7
AD0
AD2AD3AD4AD5AD6
AD1
D14/RSVDD13/CAD6D12/CAD4D11/CAD2D10/CAD31
D15/CAD8
D9/CAD30D8/CAD28D7/CAD7D6/CAD5D5/CAD3D4/CAD1D3/CAD0D2/RSVD
D1/CAD29D0/CAD27
A22/CTRDY*
A20/CSTOP*
A23/CFRAME*
A21/CDEVSEL*
A19/CBLOCK*
A15/CIRDY*A14/CPERR*
A12/CC/BE2*
A8/CC/BE1*
A25/CAD19A24/CAD17
A18/RSVDA17/CAD16A16/CCLK
A13/CPAR
A11/CAD12A10/CAD9A9/CAD14
A7/CAD18A6/CAD20A5/CAD21
CE2/CAD10*INPACK/CREQ*WAIT/CSERR*
A4/CAD22A3/CAD23A2/CAD24A1/CAD25A0/CAD26
VPPD1VPPD0
VCCD0*VCCD1*
IORD*/CAD13IOWR*/CAD15OE*/CAD11
WE*/CGNT*
CD2*/CCD2*CD1*/CCD1*
CE1*/CC/BE0*
RDY/IREQ*/CINT*
VS1*/CVS1VS2*/CVS2
REG*/CC/BE3*RESET/CRST*
BVD1/CSTSCHG/STSCHG*/RI*BVD2/SPKR*/CAUDIO
WP/IOIS16*/CCLKRUN*
RI_OUT/PME
CLK_48_RSVD/NC
TPS2211
OC
AVPP
AVCC2AVCC1AVCC0
GND
SHTDWN
VCCD0VCCD1VPPD0VPPD1
V_5_2V_5_1
V_3_2V_3_1
V_12
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(or 3.3V)
(or 3.3V)
Allows thinner trace to BGAThis is an internal board short
0.1uF are used to increase ESD of up to 10kV
plane/traces to minimize inductance!
Master: Fizzy
CardBus Interface
TI reference schematic does not
NC
(PCI_AD<21>)
NCNC
NCNC
516S0089
Integrated PullupIntegrated Pullup
Integrated PullupIntegrated PullupIntegrated PullupIntegrated Pullup
Integrated Pullup
Integrated PullupIntegrated Pullup
Integrated PullupIntegrated Pullup
Integrated PullupIntegrated Pullup
Integrated Pullup /
have bulk on PPVCC_CBUS
Integrated Pullup
Clamp for PC Card
DIFFERENTIAL_PAIRNET_SPACING_TYPE
Power aliases required by this page:
Signal aliases required by this page:
NOTE: All 4 rails MUST implement the same power state (PWRON or RUN). For
alias to PCI_RESET_L instead.
- _PP3V3_CBUS- _PP3V3_PCI- _PP2V5_PCI
Page Notes- _PP5V_CBUS
to SYS_WARM_RESET_L. For RUN must PWRON must alias _PCI_CBUS_RESET_L
- _PPVIO_PCI (to _PP5V_PCI or _PP3V3_PCI)
PCI Devices implemented on this page:
(_PPVIO_PCI can be same as _PP3V3_PCI)
NOTE: This CardBus implementation does
AD21 (Slot "E") - CardBus (0x104C/0xAC56)
BOM options provided by this page:
2. _PPVIO_PCI3. _PP3V3_PCI
Power Down1. Assert RESET
(NONE)
3. _PPVIO_PCI
Power Up
2. _PP3V3_PCI1. Assert RESET
Power Sequencing:
not provide PME# or 12V Vpp support.
- _PCI_CLK33M_CBUS (33MHz PCI clock)- _PCI_CBUS_RESET_L (see note above)
ELECTRICAL_CONSTRAINT_SET
Clamp for PCI
Integrated PullupIntegrated Pullup
PC Card/CardBus Connector
(or 3.3V)
Make sure Vcc and Vpp are wide
NC
PC Card Power Switch
Disable card power during reset
Pulldown
NC
21
R7803
MF
5%1/16W
10K
40221
R7804
5%
402
10K
1/16WMF
21
R7805
5%
MF1/16W
10K
402
1
2
8
9
3
7
4
6
10
5
RP780010K5%
1/32W25V
SM
9
84
83 82
81
80
8
79
78 77
76 75
74 73
72 71
70
7
69
68 67
66 65
64 63
62 61
60
6
59
58 57
56 55
54 53
52 51
50
5
49
48 47
46 45
44 43
42 41
40
4
39
38 37
36 35
34 33
32 31
30
3
29
28 27
26 25
24 23
22 21
20
2
19
18 17
16 15
14 13
12 11
10
1
J7800QT500806-L111
M-ST-SM
CRITICAL
A5
D13
B6
A9
B2
L8
D4
M11
K9
L3
L12
N13
B11
N11N7M1E1D5C13A7
J3
N10
L1
M9
L2
M8
D8
C2
A8
A6
G3
K3
G1
N1
G10
L10
N12
M10
K10
L9
N9
K7
K1
C11
F12
B8
F2
L11
C1
N2M13K8H4F13D1A11A2
J1
K2
B4
C5
H12
J10
J13
K12
K11
A3
H11
J12
K13
J11
M12
B3
C4
A4
H10
G13
H13
B5
L13
A1
J2
M3
K6
D6
C6
M2
N4
N5
L6
M6
K4
E3
D3
N6
E4
D2
B1
F4
E2
F3
C3
F1
G4
G2
L7
H2
H3
H1
J4
M4
L5
K5
N3
L4
M5
M7
N8
F11
E11
A12
C9
C8
B12
D10
B9
B10
A10
C12
D11
E10
B7
A13
E13
F10
B13
C10
D12
E12
D9
G12
G11
D7
C7
U7800CRITICAL
PCI1510GGUBGA
2
1C78112.2uF
20%10V
CERM805
2
1C7810
805
20%10V
CERM
2.2uF
21
R7802
5%
402
10K
1/16WMF
2
1C780720%
6.3V
402
0.22uF
X5R
21
R7808
1/16W5%
MF402
47
2
1 C780010uF
CERM6.3V
805
20%2
1 C780120%6.3V
0.22uF
402X5R 2
1 C780220%6.3V
0.22uF
402X5R 2
1 C7803
402
6.3V20%0.22uF
X5R 2
1 C7804
402
20%0.22uF
X5R6.3V 2
1 C7805
402
0.22uF20%
X5R6.3V 2
1 C780620%6.3V
0.22uF
402X5R
2
1 C78090.1UF10V
402
20%
CERM
21
XW7800SM
6
5
4
3
9
14
15
2
1
16
87
10
13
12
11
U7801CRITICAL
SSOI
21
R780947
5%1/16WMF402
2
1C78080.1UF
CERM
20%10V
402
2
1R7806
MF
5%22
402
1/16W
TITLE=FIZZYABBREV=DRAWING 78
051-653210303
VOLTAGE=5VMIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=6 mil
PPVCC_CBUS_XW
CBUS_VPPD1
_PP5V_CBUS
CBUS_VCCD1_L
_PP3V3_CBUS
PCI_AD<9>
PPVCC_CBUSVOLTAGE=5VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
PPVPP_CBUSVOLTAGE=5V
CBUS_DATA<0>
_PPVIO_PCI_CBUS
CBUS_READY
CBUS_BVD1_L
CLOCKSPCI_CLK_CBUS _PCI_CLK33M_CBUS
_PCI_CBUS_RESET_L
PCI_TRDY_LPCI_STOP_L
CBUS_PERR_L_PU
PCI_AD<30>
CBUS_SERR_L_PU
CBUS_SUSPEND_L_PU
CBUS_VR_EN_L_PU
CBUS_PERR_L_PU
_PP3V3_PCI
_PP2V5_PCI
CBUS_WP_L
CBUS_MFUNC3_PDCBUS_MFUNC2_PDCBUS_MFUNC1_PD
CBUS_MFUNC4_PDCBUS_MFUNC5_PDCBUS_MFUNC6_PD
CBUS_ADDR16_R CBUS_ADDR<16>
CBUS_DET_1_LCBUS_DET_2_LCBUS_IORD_LCBUS_IOWR_LCBUS_OE_LCBUS_CE1_L
CBUS_WE_L
CBUS_RESET_LCBUS_REG_L
CBUS_BVD2_L
CBUS_CE2_LCBUS_INPACK_LCBUS_WAIT_L
CBUS_DATA<14>CBUS_DATA<13>CBUS_DATA<12>CBUS_DATA<11>CBUS_DATA<10>CBUS_DATA<9>CBUS_DATA<8>CBUS_DATA<7>CBUS_DATA<6>CBUS_DATA<5>CBUS_DATA<4>CBUS_DATA<3>
CBUS_DATA<1>CBUS_DATA<0>
CBUS_ADDR<25>CBUS_ADDR<24>CBUS_ADDR<23>CBUS_ADDR<22>CBUS_ADDR<21>CBUS_ADDR<20>CBUS_ADDR<19>CBUS_ADDR<18>CBUS_ADDR<17>
CBUS_ADDR<15>CBUS_ADDR<14>CBUS_ADDR<13>CBUS_ADDR<12>CBUS_ADDR<11>CBUS_ADDR<10>CBUS_ADDR<9>CBUS_ADDR<8>CBUS_ADDR<7>CBUS_ADDR<6>CBUS_ADDR<5>CBUS_ADDR<4>CBUS_ADDR<3>CBUS_ADDR<2>CBUS_ADDR<1>CBUS_ADDR<0>
CBUS_DATA<15>
PCI_SLOTE_INT_L
PCI_PAR
PCI_AD<8>PCI_AD<7>PCI_AD<6>PCI_AD<5>PCI_AD<4>PCI_AD<3>
PCI_AD<29>PCI_AD<28>PCI_AD<27>PCI_AD<26>PCI_AD<25>PCI_AD<24>PCI_AD<23>PCI_AD<22>
PCI_AD<20>
PCI_AD<2>
PCI_AD<18>PCI_AD<17>
PCI_AD<14>PCI_AD<13>PCI_AD<12>PCI_AD<11>PCI_AD<10>
PCI_AD<1>PCI_AD<0>
_PCI_CLK33M_CBUS
PCI_IRDY_LCBUS_SERR_L_PU
PCI_FRAME_L
PCI_DEVSEL_L
PCI_SLOTE_REQ_LPCI_SLOTE_GNT_L
CBUS_SUSPEND_L_PU
CBUS_VS1CBUS_VS2
CBUS_VR_EN_L_PU
PCI_CBE_L<0>
PCI_AD<21>
PPVCC_CBUS
CBUS_ADDR<0>
CBUS_DATA<1>CBUS_DATA<2>CBUS_WP_L
CBUS_ADDR<13>
CBUS_ADDR<14>CBUS_WE_LCBUS_READYPPVCC_CBUS
PPVPP_CBUSCBUS_ADDR<16>CBUS_ADDR<15>CBUS_ADDR<12>
CBUS_ADDR<7>CBUS_ADDR<6>CBUS_ADDR<5>CBUS_ADDR<4>
CBUS_ADDR<3>CBUS_ADDR<2>CBUS_ADDR<1>
CBUS_DATA<3>CBUS_DATA<4>CBUS_DATA<5>CBUS_DATA<6>
CBUS_DATA<7>CBUS_CE1_LCBUS_ADDR<10>CBUS_OE_L
CBUS_ADDR<11>CBUS_ADDR<9>CBUS_ADDR<8>
CBUS_ADDR<23>
CBUS_ADDR<25>
CBUS_DET_1_LCBUS_DATA<11>CBUS_DATA<12>CBUS_DATA<13>
CBUS_DATA<14>CBUS_DATA<15>CBUS_CE2_LCBUS_VS1
CBUS_IORD_LCBUS_IOWR_LCBUS_ADDR<17>CBUS_ADDR<18>
CBUS_ADDR<19>CBUS_ADDR<20>CBUS_ADDR<21>
PPVPP_CBUSCBUS_ADDR<22>
CBUS_ADDR<24>
CBUS_VS2CBUS_RESET_LCBUS_WAIT_L
CBUS_INPACK_LCBUS_REG_LCBUS_BVD2_LCBUS_BVD1_L
CBUS_DATA<10>CBUS_DET_2_L
PCI_AD<15>PCI_AD<16>
PCI_AD<19>
PCI_CBE_L<1>
PCI_CBE_L<3>PCI_CBE_L<2>
PCI_AD<31>
PCI_CBUS_RESET_L_R
PCI_SLOTE_IDSEL
CBUS_DATA<9>CBUS_DATA<8>
CBUS_DATA<2>
PCI_CBUS_RESET_L_R
CBUS_VCCD0_L
_PP3V3_PCI
CBUS_VPPD0
LAST_MODIFIED=Mon Feb 23 19:07:07 2004
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5
Preliminary
www.vinafix.vn
UATA
UD_IDECHRDY_H
UD_IDEDMARQ_H
UD_IDEINTRQ_H
UD_IDEDA2_H
UD_IDEDA1_H
UD_IDEDA0_H
UD_IDEDD_15_H
UD_IDEDD_14_H
UD_IDEDD_0_H
UD_IDEDD_1_HUD_IDEDD_2_H
UD_IDEDD_3_H
UD_IDEDD_4_HUD_IDEDD_5_H
UD_IDEDD_6_HUD_IDEDD_7_H
UD_IDEDD_8_H
UD_IDEDD_9_HUD_IDEDD_10_H
UD_IDEDD_11_H
UD_IDEDD_12_HUD_IDEDD_13_H
TXDN1
TXDP1
TXDN2TXDP2
RXDN2RXDP2
RXDN1
RXDP1
SATA_GND
SATA_VDD
SATA 0
SATA 1
(5 OF 8)
UD_IDECS1FX_LUD_IDECS3FX_L
UD_IDEDMACK_L
UD_IDERD_L
UD_IDEWR_LUD_IDERST_L
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Master: Link
UATA Termination
Shasta Disk
ELECTRICAL_CONSTRAINT_SET DIFFERENTIAL_PAIR
Page NotesPower aliases required by this page:
(NONE)
IORDY/HDMARDY*DSTROBE aka:
HSTROBE aka:DIOR*
STOP aka:DIOW*
SATA_VDD x 5Signal aliases required by this page:
NET_SPACING_TYPE
Recommend 0.1uF cap placed close to Shasta.AC coupling required for any SATA pair used.
(Caps provided by device page)
(NONE)BOM options provided by this page:
- _PP1V2_PWRON_DISK
NOTE: Target differential impedance for
Net Spacing Type: SATALine To Line: 15 milsLength Tolerance: 50 mils
SATA data pairs is 100 ohms.
Primary Max Sep: 9 mils innerPrimary Max Sep: 10 mils outer
Secondary Max Sep: 100 milsSecondary Length: 500 mils
2
1 C80020.1uF
402CERM
20%10V2
1 C80010.1uF20%10VCERM402
2
1 C800010V20%
CERM402
0.1uF2
1 C80040.1uF
402CERM10V20%
2
1 C800310V20%
CERM402
0.1uF
D3
E7
E4C5
D7 E8
D4
G5
G6E3
C2
C1E2
H6
H7
D5E5
F5
C3F6
G7
J6
D6
C4
E6
B4B3
F9
Y15
AA16
Y14
AB16
Y18
W15
T14
AB17
AB14
W16
T13
AA17
AA14
AB15
Y17
AA15
Y16
U2300 OMIT
BGAV1.0
SHASTA
54
RP8000
SM1
5%
33
1/16W
63
RP8000
SM1
33
1/16W5%
72
RP800033
5%1/16WSM1
54
RP8003
SM11/16W5%
33
81
RP8001
SM1
5%1/16W
33
72
RP8001
SM1
33
1/16W5%
63
RP8003
1/16W
33
5%
SM181
RP8002
SM1
5%1/16W
33
72
RP8002
1/16W
33
5%
SM1
81
RP8000
1/16W
33
5%
SM154
RP8002
SM1
5%1/16W
33
72
RP8003
SM1
33
1/16W5%
63
RP8001
5%
33
1/16WSM1
81
RP8004
SM1
5%1/16W
33
81
RP8003
SM1
5%1/16W
33
63
RP8002
SM11/16W
33
5%
72
RP8004
SM1
5%1/16W
33
54
RP8004
SM1
5%1/16W
33
54
RP8001
SM1
5%
33
1/16W
63
RP8004
SM1
33
1/16W5%
2
1R80055%
1/16WMF
10K
402
21
R800133
5%1/16WMF402
21
R800222
402MF
1/16W5%
21
R8003
5%1/16WMF402
22
21
R8004
5%1/16WMF402
22
21
R8000
402MF
1/16W5%
33
ABBREV=DRAWINGTITLE=FIZZY
1038003051-6532
SATASATA_RXD2 SATA_RXD_N2_CSATA_RXD2_C
UATA_HOST UATA_DA<2..0>
UATA_HOST UATA_CS0_L
UATA_DEV_R UATA_DMARQ
UATA_HOST UATA_CS1_L
UATA_DD UATA_DD<15..8>
SATASATA_TXD2 SATA_TXD_N2SATA_TXD2
SATA_RXD_N2_CSATA_RXD_P2_C
SATA_RXD_N1_CSATA_RXD_P1_C
SATA_TXD_P1SATA_TXD1SATASATA_TXD1
UATA_DEV_R_C UATA_DSTROBE
UATA_STOP_R UATA_STOP
UATA_CS1_L_R UATA_CS1_L
UATA_RESET_LUATA_RESET_L_R
UATA_DA<1>
UATA_DD<15>UATA_DD_R<15>
UATA_DD<13>UATA_DD_R<13>
UATA_DD<11>UATA_DD_R<11>
UATA_DD<9>UATA_DD_R<9>
UATA_DD<7>UATA_DD_R<7>
UATA_DD<5>UATA_DD_R<5>
UATA_DD<3>UATA_DD_R<3>
UATA_DD<1>UATA_DD_R<1>
UATA_DMACK_L_R UATA_DMACK_L
UATA_HSTROBE_R UATA_HSTROBE
UATA_CS0_L_R UATA_CS0_L
UATA_DA<2>UATA_DA_R<2>
UATA_DA<0>UATA_DA_R<0>
UATA_DD<14>UATA_DD_R<14>
UATA_DD<12>UATA_DD_R<12>
UATA_DD<10>UATA_DD_R<10>
UATA_DD<8>UATA_DD_R<8>
UATA_DD<6>UATA_DD_R<6>
UATA_DD<4>UATA_DD_R<4>
UATA_DD<2>UATA_DD_R<2>
UATA_DD<0>UATA_DD_R<0>
UATA_RESET_L_RUATA_STOP_RUATA_HSTROBE_RUATA_DMACK_L_R
UATA_CS1_L_RUATA_CS0_L_R
UATA_DA_R<0>
UATA_DD_R<15>
UATA_DD_R<13>UATA_DD_R<14>
UATA_DD_R<12>UATA_DD_R<11>UATA_DD_R<10>
UATA_DD_R<8>UATA_DD_R<7>
UATA_DD_R<9>
UATA_DD_R<6>UATA_DD_R<5>UATA_DD_R<4>UATA_DD_R<3>UATA_DD_R<2>UATA_DD_R<1>UATA_DD_R<0>
UATA_INTRQ
UATA_DMARQ
UATA_DSTROBE
SATA_TXD_N2SATA_TXD_P2
SATA_TXD_P1SATA_TXD_N1
UATA_DA_R<2>UATA_DA_R<1>
UATA_DEV_R UATA_INTRQ
UATA_HOST_R UATA_RESET_LUATA_HOST_R UATA_DMACK_LUATA_HOST UATA_STOP
UATA_DD7 UATA_DD<7>
UATA_DA_R<1>
_PP1V2_PWRON_DISK_SB
SATA_RXD_N1_CSATA_RXD1_CSATA_RXD1 SATASATA_RXD1 SATA_RXD1_CSATA SATA_RXD_P1_C
SATA_TXD1 SATA_TXD1SATA SATA_TXD_N1
SATA SATA_TXD_P2SATA_TXD2 SATA_TXD2
UATA_DD<6..0>UATA_DD
UATA_HOST UATA_HSTROBE
SATASATA_RXD2 SATA_RXD_P2_CSATA_RXD2_C
LAST_MODIFIED=Mon Feb 23 19:07:21 2004
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6 50
50 6
50 6
50 6
6 50
6 50
6 50
6 50
6 50
6 50
6 50
6 50
6 50
6 50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
5
5
50
50
50
50
50
6
6
6
6
50
5
50
50
50
5
6
6
5
Preliminary
www.vinafix.vn
1414
UAIUAO
H_STROBE
RX_PRX_M
TX_PTX_M
RST*
XTLIN/OSC
XTLOUT
T0T1
CNFG1CNFG0
T7T6T5T4T3T2
CNFG2
H_INTRQ
H_DMARQ
H_IORDY/
H_DDMARDY*H_DSTROBE/
H_PDIAG*
H_IOCS16*
ATAIOSEL
H_DD[3]H_DD[2]H_DD[1]H_DD[0]
H_DD[4]
H_DD[9]H_DD[8]H_DD[7]H_DD[6]H_DD[5]
H_DD[13]H_DD[12]H_DD[11]H_DD[10]
H_DD[14]
H_DA[2]H_DA[1]H_DA[0]
H_RESET*
H_DMACK*
H_DMARDY*/H_DIOR*/
H_CS[1]*H_CS[0]*
H_DD[15]
H_DIOW*/H_STOP
ISET
GND VSS1 VSS2
VDDIO VDD VAA1VAA2
SATA
CONFIG/DEBUG
PARALLEL ATA
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DRAWING
CONTROLLER
ELECTRICAL_CONSTRAINT_SET
Master: Link
88SA8040 requires Schmitt-Trigger on RST* input
T<4..3> - Reference Clock Configuration1 - Enable translation of ATA power management
T2 - SSC Enable1 - Enable SATA Spread Spectrum Clocking
NET_SPACING_TYPE
Place C8162 & C8163near SATA host device
Signal aliases required by this page:
(Internal Pull-down)
CNFG<2..0> - Mode Configuration
000 Device Mode - 100MB/s001 Device Mode - 133MB/s010 Device Mode - 150MB/s (default)100 Host Mode - 100MB/s101 Host Mode - 133MB/s
H_IOCS16_N - DMA_EN
1 - Reverse Order mode for Parallel ATA pins
PATA Termination
88SA8040 Config Straps (Device Mode):
00 20 MHz
11 40 MHz
0 - UDMA mode adjustable with Set Features
- _PP1V8_SATABR
BOM options provided by this page:
(NONE)
- _PP3V3_SATABR
SATA port 1.
- SATA_1_BRIDGE (/ SATA_1_CONN)
SATA connector is connected to Shasta Selects whether 88SA8040 SATA Bridge or
VSS does NOT connect to GND
10mA 50mA 10mA 60mA
0 - Disable SATA Spread Spectrum Clocking
10 1 1 (default)
(Internal Pull-down)
T<1..0> VU Type R/W Long Type00 1 101 1 2
11 2 2
T<1..0> - Vendor Unique (VU) and Read/Write Long
(Internal Pull-up)
T5 - Fixed UDMA
(Internal Pull-downs)
10 30 MHz01 25 MHz
T<4..3> Clock Frequency
1 - UDMA mode fixed by CNFG<2..0> pins
1 - SATA cable plugged in0 - SATA cable unplugged
T7 - Plug-in (output)
T6 - Power Mode Enable
0 - Disable translation(Internal Pull-down)
commands into SATA Partial or Slumber modeCNFG<2..0> Mode
011 Reserved111 Reserved
110 Host Mode - 150MB/s
(Internal Pull-up)
H_PDIAG_N - PATA_ORDER
0 - Normal Order mode
ATAIOSEL - ATA I/O Enable
(Internal Pull-up)
0 - Error status on Set Features to set DMA1 - Good status on Set Features to set DMA
0 - Disable output to ATA bus1 - Enable output to ATA bus
Power aliases required by this page:
Page Notes
Serial ATA Bridge
Sourced by host or bi-directionalTerminate near bridge
DIFFERENTIAL_PAIR
PROVIDED
SATABY
2
1 C8154
CERM
0.1uF
402
10V20%
2
1 C8153
CERM402
10V20%0.1uF
2
1C8152
CERM402
20%10V
0.1uF
2
1C81570.01uF
16V20%
402CERM2
1C81580.1uF
10V20%
CERM402
542
3
U8199SC7074AHC1G14
CRITICAL
542
3
U8198CRITICAL
SC7074AHC1G14
2
1C819910V20%
0.1uF
402CERM
2
1R81985%
1/16WMF402
330K
2
1C819810V
NO STUFF
402CERM
20%0.1uF
54
RP8170
SM1
5%1/16W
33
72
RP8170
SM1
5%1/16W
33
54
RP8171
SM1
33
1/16W5%
72
RP8171
SM1
33
1/16W5%
54
RP8172
SM1
33
1/16W5%
72
RP8172
SM1
5%
33
1/16W
54
RP8173
SM1
33
1/16W5%
72
RP8173
SM1
33
1/16W5%
54
RP8174
SM1
33
1/16W5%
81
RP817433
SM11/16W5%
21
R817033
5%1/16WMF402
21
R817222
402MF
1/16W5%
21
R817422
402MF
1/16W5%
63
RP8170
SM1
5%1/16W
33
81
RP8170
SM1
33
1/16W5%
63
RP8171
SM1
5%1/16W
33
21
L8155FERR-EMI-600-OHM
SM
81
RP8171
SM1
33
1/16W5%
63
RP8172
SM1
5%1/16W
33
81
RP8172
SM1
33
1/16W5%
2
1R8175
402
10K
MF1/16W
5%
63
RP8173
SM1
5%
33
1/16W
81
RP8173
SM1
33
1/16W5%
72
RP8174
SM1
33
1/16W5%
21
R817133
5%1/16WMF402
2
1C8155
805
6.3V
10uF20%
CERM
21
R8173
5%1/16WMF402
22
21
R817922
402MF
1/16W5%
23
22
30
25
44
4 5641
9 29
24
45
43
32
31
4039
38
3736
3534
33
2728
17
26
16
46
55
52
53
6054
59
58
12
14
1513
117
5
2
61
63
13
6
10
64
62
49
5150
47
48
57
428
20
1918
21
U8150QFP-64
88SA8040
2
1C815610V
402
20%
CERM
0.1uF
21
C8162
402
20%
CERM
0.01uF
16V
21
C8163
20%
CERM402
0.01uF
16V
2
1R816012.1K
402MF
1/16W1%
21
C8160
CERM
20%
402
0.01uF
16V
21
C8161
20%
402CERM
0.01uF
16V
2
1C81500.1uF
CERM
20%10V
4022
1C815110V
0.1uF
402
20%
CERM 2
1C8159
805
6.3VCERM
20%10uF
051-6532 03
10381ABBREV=DRAWINGTITLE=FIZZY
PATA_DEV_R_C PATA_DSTROBE
SATA_BR_RXD_NSATA SATA_BR_RXD
PATA_HOST PATA_CS1_LPATA_HSTROBEPATA_HOST
TP_SATABR_CLK25M_XTLOUT
SATA_BR_RXD_P
PATA_DSTROBE
SYS_COLD_RESET_L
PATA_DEV_R PATA_DMARQ
PATA_RESET_LPATA_RESET_L_R
PATA_DMACK_L_R PATA_DMACK_L
PATA_STOP_R PATA_STOP
PATA_HSTROBE_R PATA_HSTROBE
PATA_CS1_L_R PATA_CS1_L
PATA_CS0_L_R PATA_CS0_L
PATA_DD_R<15>
PATA_DD_R<13>
PATA_DD_R<11>
PATA_DD_R<9>
PATA_DD_R<3>
PATA_DD_R<1>
PATA_DD_R<12>
PATA_DD_R<10>
PATA_DD_R<8>
PATA_DD_R<6>
PATA_DD_R<4>
PATA_DD_R<2>
PATA_DD_R<0>
PATA_DA<1>
PATA_DA<2>
PATA_DA<0>
PATA_DD<13>
PATA_DD<11>
PATA_DD<9>
PATA_DD<12>
PATA_DD<10>
PATA_DD<7>
PATA_DD<8>
PATA_DD<6>
PATA_DD<5>
PATA_DD<3>
PATA_DD<4>
PATA_DD<2>
PATA_DD<1>
PATA_DD<0>
PATA_HOST PATA_DD<15..8>
PATA_DA<3..0>PATA_HOST
PATA_RESET_LPATA_HOST_R
PATA_HOST PATA_CS0_L_PP3V3_SATABR
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=20 milVOLTAGE=0V
SATABR_VSS
PATA_CS1_L_R
PATA_HSTROBE_R
PATA_STOP_R
SATABR_ISET_PD
PATA_DMACK_L_R
PATA_RESET_L_R
PATA_CS0_L_R
PATA_DA_R<2>PATA_DA_R<1>
PATA_DD_R<14>PATA_DD_R<15>
PATA_DA_R<0>
PATA_DD_R<12>PATA_DD_R<13>
PATA_DD_R<9>PATA_DD_R<10>PATA_DD_R<11>
PATA_DD_R<8>PATA_DD_R<7>
PATA_DD_R<4>PATA_DD_R<5>PATA_DD_R<6>
PATA_DD_R<1>PATA_DD_R<2>PATA_DD_R<3>
PATA_DD_R<0>
TP_SATABR_T7
TP_SATABR_UAOSATA_TXD_N1
PATA_DD<6..0>PATA_HOST
TP_SATABR_UAI
PATA_DA_R<2>
PATA_DA_R<1>
PATA_DD_R<5>
PATA_DD<14>
PATA_DD<15>
PATA_DA_R<0>
PATA_DD_R<14>
PATA_HOST_R PATA_DMACK_L
SATA_BR_RXD_N
PATA_INTRQPATA_DEV_R
_PP1V8_SATABR
SATABR_VSS
_PP3V3_SATABR
SATA_BR_TXD_PSATA_BR_TXD_N
SATA_TXD_P1 SATA_RXD_P1_C
SATA_RXD_N1_C
PATA_DD_R<7>
VOLTAGE=3.3VPP3V3_SATABR_VAA
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
SATA SATA_BR_RXD_PSATA_BR_RXD
SATABR_RESET_STSB_SATABR_RESET_L
_PP3V3_SATABR
PATA_INTRQ
PATA_DD7 PATA_DD<7>
PATA_HOST PATA_STOP
SATA SATA_BR_TXD_PSATA_BR_TXDSATA_BR_TXD SATA_BR_TXD_NSATA
CLOCKS _SATA_CLK25M
SATABR_RESET_L
PATA_DMARQ
_SATA_CLK25M
LAST_MODIFIED=Mon Feb 23 19:07:28 2004
52
52
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52
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52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
51
51
52
22
52
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
52
51
51
52
51
51
51
52
51
51
51
6
6
51
51
13
51
6 51
51 6
51 6
51 6
51 6
51 6
51
51
51
51
51
51
51
51
51
51
51
51
51
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51 50
6
51
51
51
6
6
51
51
6
51
51
5
51
5
51
51
50 50
50
51
51
23
5
51
6
6
51
51
5
51
5
Preliminary
www.vinafix.vn
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
IDE Connectors
(NONE)
(NONE)
NOTE: ATA constraints are expected to be
BOM options provided by this page:
- _PP3V3_UATA- _PP3V3_PATA- _PP5V_UATA- _PP5V_PATAPower aliases required by this page:
NC
516S0140
NC
NC
516S0140
PATA (SATA Bridge) Connector
defined on another page (ATA host) and apply to this page via XNets.
Signal aliases required by this page:
Page Notes
UATA (SouthBridge) Connector
21
R8307
5%1/16WMF402
82
2
1R83515%1/16WMF402
4.7K
9
8
7
6
50
5
49
48
47
46
45
44
43
42
41
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
2625
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J8300CRITICAL
M-ST-SM1
2
1R830420K
402MF
1/16W5%
2
1R830510K
402MF
5%1/16W
2
1R8300NO STUFF
5%1/16WMF402
10K
2
1R830110K
5%1/16W
MF4022
1R8302NO STUFF
10K
402MF
1/16W5%
21
R830882
402MF
1/16W5%
21
R8309
1/16W5%
MF402
82
2
1 C830850V
10pF
402CERM
5%
9
8
7
6
50
5
49
48
47
46
45
44
43
42
41
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
2625
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J8350CRITICAL
M-ST-SM1
2
1R8352NO STUFF
5%1/16WMF402
10K
2
1R8350NO STUFF
10K
402MF
1/16W5%
2
1R83545%
1/16WMF402
20K
21
R8357
5%1/16WMF402
82
2
1R835510K
402MF1/16W5%
21
R8358
5%1/16WMF402
82
21
R835982
402MF
1/16W5%
2
1 C83585%50VCERM402
10pF
2
1R8363PATA_3V3_LOGIC
5%1/16WMF603
0
2
1R8365
MF1/16W
5%
603
0
PATA_5V_LOGIC
TITLE=FIZZYABBREV=DRAWING
03051-653210383
UATA_INTRQ_R
UATA_DD<9>
PATA_DMARQ
PATA_DD<7>PATA_DD<6>
PATA_DD<3>PATA_DD<2>
PATA_DD<1>PATA_DD<0>
PATA_DMARQ_RPATA_HSTROBE
PATA_DA<1>
PATA_DA<0>PATA_CS0_L
PATA_DD<8>PATA_DD<9>
PATA_DD<10>PATA_DD<11>
PATA_DD<12>PATA_DD<13>
PATA_DD<14>PATA_DD<15>
PATA_STOP
PATA_DA<2>
PATA_CS1_L
PATA_DD<5>PATA_DD<4>
PATA_INTRQ
MIN_LINE_WIDTH=15 milVOLTAGE=5V
PPLOGIC_PATA
MIN_NECK_WIDTH=10 mil
PATA_DMACK_L
PATA_DSTROBE_R
PATA_INTRQ_R
PATA_RESET_L
PATA_DSTROBEUATA_DMARQ
UATA_DA<0>
UATA_DD<8>
UATA_DD<10>
UATA_DD<13>UATA_DD<14>
UATA_HSTROBE
UATA_DA<2>UATA_CS1_L
UATA_DD<4>
UATA_DD<0>
UATA_STOP
UATA_DA<1>
UATA_CS0_L
UATA_DD<11>
UATA_DD<12>
UATA_DD<15>
UATA_INTRQ
UATA_DMACK_L
UATA_DSTROBE
_PP5V_UATA
UATA_RESET_L
UATA_DD<7>UATA_DD<6>UATA_DD<5>
UATA_DD<2>UATA_DD<3>
UATA_DSTROBE_R
UATA_DD<1>
UATA_DMARQ_R
_PP3V3_PATA
_PP5V_PATA
LAST_MODIFIED=Mon Feb 23 19:07:36 2004
50
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
6
6
51
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
51
6
6
6
6
6
51
50
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
50
6
50
5
6
6
6
6
6
6
6
6
6
5
5
Preliminary
www.vinafix.vn
ETHERNET
(6 OF 8)
ETH_GTX_CLK_H
ETH_TX_ER_HETH_TX_EN_H
ETH_TXD_7_H
ETH_TXD_6_H
ETH_TXD_5_HETH_TXD_4_H
ETH_TXD_3_HETH_TXD_2_H
ETH_TXD_1_H
ETH_TXD_0_H
ETH_MDC_H
ETH_MDIO_H
ETH_TX_CLK_HETH_RX_CLK_H
ETH_RXD_0_H
ETH_RXD_1_H
ETH_RXD_2_H
ETH_REFCLK_H
ETH_RXD_3_H
ETH_RXD_4_HETH_RXD_5_H
ETH_RXD_6_H
ETH_RXD_7_H
ETH_RX_DV_HETH_RX_ER_H
ETH_CRS_H
ETH_COL_H
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DIFFERENTIAL_PAIRNET_SPACING_TYPENET_PHYSICAL_TYPE
Page Notes
Signal aliases required by this page:
BOM options provided by this page:(NONE)
(NONE)
Power aliases required by this page:(NONE)
Shasta Ethernet
ELECTRICAL_CONSTRAINT_SET
Master: Link
F1H3
H5
K6
J4
F2G3
J5
H4E1
G4
G2K4
J3
G1
J2
K3L4
J1
K2L3
K1
M5
M6
M4
K5
L6
L5
U2300OMIT
BGAV1.0
SHASTA
72
RP8400
1/16W
0K
5%
SM154
RP84000K
1/16W5%
SM181
RP84000K
5%1/16WSM1
63
RP84000K
5%1/16WSM1
72
RP84010K
5%1/16WSM1
54
RP84010K
SM11/16W5%
81
RP84010K
5%1/16WSM1
63
RP8401
5%1/16WSM1
0K
21
R84000
402MF
1/16W5%
21
R8401
5%1/16W
0
MF402
21
R84020
5%1/16WMF402
TITLE=FIZZYABBREV=DRAWINGLAST_MODIFIED=Mon Feb 23 18:36:38 2004 10384
03051-6532
ENET_TXD_R<6>
ENET_TXD_R<3>
ENET_TXD_R<7>
ENET_TXD_R<4>
ENET_TX_EN_R
ENET_CLK125M_GBE_REF
ENET_CLK125M_RXENET_CLK25M_TX
ENET_TXD_R<5>
ENET_TX_ER_R
ENET_CLK125M_GTX_R
ENET_TXD_R<1>ENET_TXD_R<0>
ENET_TXD_R<2>
ENET_COL
ENET_CRS
ENET_RX_ERENET_RX_DV
ENET_RXD<7>ENET_RXD<6>ENET_RXD<5>ENET_RXD<4>ENET_RXD<3>ENET_RXD<2>ENET_RXD<1>ENET_RXD<0>
ENET_MDC
ENET_MDIO
ENET_TXD<7>
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<4>
ENET_TXD<3>
ENET_TXD<6>
ENET_TX_EN
ENET_TXD<5>
ENET_CLK125M_GTX
ENET_TX_ER
ENET_TX ENET_TXD<7..0>ENET
ENET_RX_DVENET_RX_CTL ENET
ENET_CLK125M_GTX_R15 MIL SPACINGENET
ENET_RX_CLK ENET_CLK125M_RX15 MIL SPACINGENET
ENET_RX ENET_RXD<7..0>ENET
ENET_RX_CTL ENET_RX_ERENET
ENET_TX_ENENET_TX_CTL ENET
ENET_COLENET_RX_CTL ENETENET_MDCENET_MDC ENETENET_MDIOENET_MDIO ENET
ENET_TX_CLK ENET_CLK125M_GTX15 MIL SPACINGENETENET_GBE_REF ENET_CLK125M_GBE_REF15 MIL SPACINGENET
ENET_TX_CTL ENET_TX_ERENET
ENET_CRSENET_RX_CTL ENET
ENET_RX_CLK ENET_CLK25M_TX15 MIL SPACINGENET
54
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Preliminary
www.vinafix.vn
INTR*/ENERGYDET
GTXCLK
XTALGND BIASGND PLLGND1
CLK125
TXD[4]TXD[3]TXD[2]TXD[1]TXD[0]
MDIOMDC
TX_ERTX_EN
TXD[7]TXD[6]TXD[5]
LOWPWR
TXC
RXC
RXD[7]
RX_DVRX_ER
XTALOXTALI
ERHUBMANMSSPD0F1000FDXRGMIIENEN_10B
PHYA[4]PHYA[3]PHYA[2]PHYA[1]PHYA[0]
TVCO
TEST[0]TEST[1]
COLCRS
RBC0
TRD+[0]TRD-[0]
TRD+[1]TRD-[1]
TRD+[2]TRD-[2]
TRD-[3]TRD+[3]
RBC1
RXD[2]RXD[3]RXD[4]RXD[5]RXD[6]
RXD[1]RXD[0]
SLAVE*/AN_EN
ACTLED*XMTLED*FDXLED*LINK2*LINK1*
QUALITY*/TXC_RXC_DELAY
RDAC1
PLLVDD1BIASVDD1XTALVDD1
VESTA ENET
2 OF 3
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(NONE)
(NONE)
Secondary Max Sep: 100 milsSecondary Length: 500 mils
Primary Max Sep: 5 milsLength Tolerance: 50 milsLine To Line: 15 mils
BOM options provided by this page:
Signal aliases required by this page:
NOTE: Target differential impedance for ENET data pairs is 100 ohms.
Net Spacing Type: ENET
Page Notes- _PP2V5_ENETFW- _PP3V3_ENETPower aliases required by this page:
DIFFERENTIAL_PAIRNET_SPACING_TYPE
Vesta Ethernet PHY
ELECTRICAL_CONSTRAINT_SET
PLACE RESISTORS CLOSE TO PHY
ESR < 0.5 ohms
Sets Hub/DTE bit and master/slave configuration value bit
(Internal Pull-up)0 - Auto-negotiation disabled1 - Auto-negotiation enabledAN_EN - Auto-Negotiation Select
0 - Rise time approx. 4 ns1 - Rise time approx. 5 nsER - Edge Rate Select
(Internal Pull-down)
FDX - Full-Duplex SelectSets manual duplex mode bit(Internal Pull-up)
0 - GMII/TBI Mode1 - RGMII/RTBI ModeRGMIIEN - RGMII Enable
(Internal Pull-down)0 - GMII/RGMII Mode
(Internal Pull-down)
F1000 - Speed SelectTXC_RXC_DELAY
GTXCLK are delayed by 1.9 ns
(Internal Pull-down)0 - No clock delay
0 1 X Force 1000BASE-T (test use only)
1 1 0 Auto-negotiate advertise 10/100/1000BASE-T1 0 1 Auto-negotiate advertise 10/100BASE-TX1 0 0 Auto-negotiate advertise 10BASE-T
0 0 1 Force 100BASE-TX
SPD0 - Speed Select
(Internal Pull-down)See table below
(Internal Pull-up)
AN_EN F1000 SPD0 Description0 0 0 Force 10BASE-T
See table below
- _PP1V2_ENETFW
1 1 1 Auto-negotiate advertise 1000BASE-T
(Internal Pull-down)
Vesta Config Straps:
1 - TBI/RTBI ModeEN_10B - TBI Interface Select
PHYA<4..0> - PHY Address Select(Internal Pull-downs)
(Internal Pull-down)
HUB - Repeater Select
Sets manual master/slave configuration enable bitMANMS - Manual Master/Slave Configuration Select
1 - If RGMII Mode enabled, RXC clock and
CRYSTAL LOAD CAPACITANCE IS 20PF
Put crystal circuit close to PHY
Master: Link
2
1R861649.9
1%1/16W
MF402
2
1R86171/16W
402MF
1%49.9
2
1R8614
402MF
1/16W1%
49.9
2
1R8615
402MF1/16W1%49.9
21
R86020
402
5%1/16WMF
21
Y8600CRITICAL
25.0000M
8X4.5MM-SM
2
1R862049.9
1%
MF402
1/16W
2
1R8618
MF1/16W
1%49.9
402
2
1R8621
402MF1/16W
49.91%
2
1R86191%49.91/16WMF402
2
1 C862020%0.01UF16VCERM402
2
1 C8622
402
0.01UF
CERM16V20%
2
1 C86230.01UF
402CERM16V20%
21
R86010
402
5%1/16WMF
21
R86000
MF1/16W
402
5%
2
1R8613
402MF
1/16W1%
1.24K
2
1R8609
MF1/16W5%0
402
2
1 C86210.01UF20%16VCERM402
2
1R86501/16W
402MF
5%1.5K
2
1C86040.001uF
50V20%
CERM402
21
L8602
SM
FERR-EMI-600-OHM
2
1C8605
1206
6.3V20%
CERM
10uF
2
1 C8601
402CERM
20%0.1uF10V
21
L8600
SM
FERR-EMI-600-OHM
21
L8601
SM
FERR-EMI-600-OHM
2
1 C8603
402
50VCERM
0.001uF20%
2
1 C8602
805
20%10uF6.3VCERM
N1
P2
N2
P3
B12
C4
B4
A5
B5C5
E6
D6C7
C6B6
A6
N3
R10R11
R9
R8
R6R7
R5
R4
M5
M4
K5
C10
C2
D2
D3
D4D5
E3
E4E5
F5F4
C1
B8
R1
B3
A3
A8
M1
M2
L1
L2
L3L4
L5
G2
G1
D9
H5
B11
A10
D10
A9
A4
B10
C8
K4
H3
K3
G3
F3
D1
P1
R2
A11
U8600
OMIT
BCM5462FBGA-200
2
1C86185%50V
CERM402
33pF2
1C86195%50V
CERM402
33pF
TITLE=FIZZYABBREV=DRAWING
03051-653210386
VOLTAGE=2.5VPP2V5_VESTA_BIASVDD1
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=15 mil
TP_VESTA_SPD0TP_VESTA_MANMSTP_VESTA_HUB
TP_VESTA_TVCO
TP_VESTA_ER
VOLTAGE=1.2VMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=15 mil
PP1V2_VESTA_PLLVDD1
ENET_MDI ENET_MDI3 ENET_MDI_N<3>ENET
ENET_CLK125M_RX_R15 MIL SPACING
ENET_MDI ENET_MDI_P<3>ENET_MDI3ENET
VESTA_CLK25M_XTAL 15 MIL SPACING VESTA_CLK25M_XTALI
_PP2V5_ENETFW
ENET_MDC
TP_VESTA_PHYA<4>
_PP1V2_ENETFW
ENET_CLK25M_TX_R
TP_VESTA_TXC_RXC_DELAYTP_VESTA_AN_EN
ENET_ENERGYDET
ENET_CLK125M_GTX
ENET_TXD<1>ENET_TXD<0>
ENET_TXD<4>
ENET_TXD<2>ENET_TXD<3>
ENET_TXD<5>ENET_TXD<6>ENET_TXD<7>
ENET_TX_ENENET_TX_ER
ENET_CLK125M_RX_R
ENET_RXD<7>
ENET_RX_DVENET_RX_ER
VESTA_CLK25M_XTALO_R
TP_VESTA_PHYA<0>TP_VESTA_PHYA<1>TP_VESTA_PHYA<2>TP_VESTA_PHYA<3>
TP_VESTA_EN_10B
TP_VESTA_FDXTP_VESTA_RGMIIEN
TP_VESTA_F1000
TP_VESTA_TEST<1>TP_VESTA_TEST<0>
ENET_COLENET_CRS
TP_VESTA_RBC0
ENET_RXD<0>
ENET_RXD<3>
ENET_RXD<1>
ENET_RXD<4>ENET_RXD<5>ENET_RXD<6>
TP_VESTA_LINK1_L
TP_VESTA_FDXLED_LTP_VESTA_XMTLED_LTP_VESTA_ACTLED_L
VESTA_RDAC1_PD
VESTA_ENET_LOWPWR
ENET_CLK125M_RX
ENET_CLK125M_GBE_REF
ENET_CLK25M_TX
VESTA_CLK25M_XTALI
VESTA_CLK25M_XTALO
ENET_MDIO
ENET_MDI0 ENET_MDI1
ENET_MDI_P<0>ENET_MDI_N<0>
ENET_MDI_N<1>ENET_MDI_P<1>
ENET_MDI2 ENET_MDI3
ENET_MDI_N<2>ENET_MDI_P<2>
ENET_MDI_P<3>
_PP3V3_ENET
ENET_CLK125M_GBE_REF_R
VOLTAGE=2.5VMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=15 mil
PP2V5_VESTA_XTALVDD1
ENET_CLK125M_GBE_REF_R15 MIL SPACING
15 MIL SPACING VESTA_CLK25M_XTALO
15 MIL SPACING VESTA_CLK25M_XTALO_R
ENET_MDI ENET_MDI0 ENET_MDI_P<0>ENET
ENETENET_MDI ENET_MDI1 ENET_MDI_N<1>
ENET_MDI ENET_MDI2 ENET_MDI_P<2>ENET
ENET_CLK25M_TX_R15 MIL SPACING
ENET_MDI ENET_MDI1 ENET_MDI_P<1>ENET
TP_VESTA_LINK2_L
ENET_MDI_N<3>
TP_VESTA_RBC1
ENET_RXD<2>
ENET_MDI2 ENET_MDI_N<2>ENET_MDI ENET
ENET_MDI0ENET_MDI ENET_MDI_N<0>ENET
LAST_MODIFIED=Mon Feb 23 19:07:51 2004
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12
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23
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12
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12
54
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54
Preliminary
www.vinafix.vn
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Place one cap at each pin of transformer
.
Ethernet Connector
DIFFERENTIAL_PAIRNET_SPACING_TYPEELECTRICAL_CONSTRAINT_SET
Page Notes
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
- _GND_CHASSIS_ENET- _PP2V5_ENET
BOM options provided by this page:
PHYETHERNET
BYPROVIDED
Place close to connector
Short shielded RJ-45
514-005924
21
18
15
22
19
16
13
23
20
17
14
3
6
9
12
2
5
8
11
1
4
7
10
T8700XFR-ENET-1000BT
SM
CRITICAL
2
1 C870020%10V
402CERM
0.1uF2
1 C870110V
0.1uF
CERM402
20%2
1 C870220%10V
402CERM
0.1uF2
1 C87030.1uF
CERM402
10V20%
8
7
6
5
4
3
2
1
12
11
10
9
J8710CRITICAL
RT-THRJ45
2
1R870575
402MF
1/16W5%
2
1R87065%
1/16WMF402
75
2
1R8708
402MF
1/16W5%75
2
1R87075%
1/16WMF402
75
2
1C8705
1808
3KV10%
100pF
CERM
21
R8710NO STUFF
5%1/10WFF805
0
ABBREV=DRAWINGTITLE=FIZZY
051-6532 03
87 103
ENET_RJ45_P<1>ENET_RJ45_N<0>
ENET_CTAP_COMMON
_GND_CHASSIS_ENET
ENET_CTAP<3>
ENET_CTAP<2>
ENET_CTAP<1>
ENET_CTAP<0>
ENET_RJ45_N<3>
ENET_RJ45_N<1>ENET_RJ45_P<2>
ENET_RJ45_P<0>
ENET_RJ45_P<3>ENET_RJ45_N<2>
_PP2V5_ENET
ENET_MDI_N<3>
ENET_MDI_N<2>ENET_MDI_P<3>
ENET_MDI_P<2>ENET_MDI_N<1>
ENET_MDI_N<0>ENET_MDI_P<1>
ENET_MDI_P<0>
ENET_RJ45_3 ENET_RJ45_N<3>ENETENET_RJ45_3 ENET_RJ45_P<3>ENET
ENET_RJ45_2 ENET_RJ45_P<2>ENETENET_RJ45_2 ENET_RJ45_N<2>ENET
ENET_RJ45_1 ENET_RJ45_N<1>ENET
ENET_RJ45_0 ENET_RJ45_N<0>ENETENET_RJ45_1 ENET_RJ45_P<1>ENET
ENET_RJ45_0 ENET_RJ45_P<0>ENET
LAST_MODIFIED=Mon Feb 23 19:07:58 2004
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55
Preliminary
www.vinafix.vn
PHY_LINKON_LPHY_PINT_L
FWVDDP
PHY_LREQ_H
PHY_LPS_H
PHY_CTL_1_H
PHY_CTL_0_H
PHY_DATA_7_HPHY_DATA_6_H
PHY_DATA_0_H
PHY_DATA_1_HPHY_DATA_2_H
PHY_DATA_3_H
PHY_DATA_4_HPHY_DATA_5_H
(7 OF 8)
PHY_LCLK_HPHY_SCLK_H
FIREWIRE
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
Page Notes
Shasta FireWire
ELECTRICAL_CONSTRAINT_SET
BOM options provided by this page:
- _PP2V5_PWRON_SB
(NONE)
(NONE)
Signal aliases required by this page:
Power aliases required by this page:
Master: Link
21
R8800
5%1/16W
22
MF402
2
1 C88020.1uF10VCERM402
20%2
1 C880120%10VCERM402
0.1uF2
1 C88000.1uF
402CERM10V20%
P2
P3
P1P6
N7
R1
L2M3
L1
N6M7
N1
P5N4
N3
N2
A4
J7
N5
U2300 OMIT
BGAV1.0
SHASTA
TITLE=FIZZYABBREV=DRAWING
051-6532 03
88 103
FW_LINKONFW_PINT
_PP2V5_PWRON_SB
FW_DATA<0>FW_DATA<1>FW_DATA<2>FW_DATA<3>FW_DATA<4>FW_DATA<5>
FW_DATA<7>FW_DATA<6>
FW_CTL<1>FW_CTL<0>
FW_LPSFW_LREQ
FW_CLK98M_LCLK_RFW_CLK98M_PCLK FW_CLK98M_LCLK
FW_PINT FW_PINTFW
FW_PCLK FW_CLK98M_PCLK15 MIL SPACINGFW
FW_LREQ FW_LREQFW
FW_LPSFW_LPS FW
FW_CTL<1..0>FW FW
FW_CLK98M_LCLK_R15 MIL SPACING
FW_LCLK FW_CLK98M_LCLK15 MIL SPACINGFW
FW FW_DATA<7..0>FW
LAST_MODIFIED=Mon Feb 23 19:08:06 2004
45 23
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21
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5
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Preliminary
www.vinafix.vn
VCC
VSS
E2E1E0 SDA
SCL
WC*
FAVDDLFAVDDMFAVDDH
TDBL[1]TDBL[2]
PLI_PCLK
TDBL[0]
TPBIAS[0]TPAP[0]TPAN[0]TPBP[0]TPBN[0]
TPBIAS[1]TPAP[1]TPAN[1]TPBP[1]TPBN[1]
TPAP[2]TPAN[2]TPBP[2]TPBN[2]
TPBIAS[2]
PLI_INTPLI_LINK
SDCSDA
RDAC2
XTALVDD2
BIASVDD2
PLLVDD2
BIASGND PLLGND2
TEST_1394[0]TEST_1394[1]TVCO_24
XTALI_24XTALO_24
CPS
ESDET1ESDET0
ESDET2
PLI_LCLK
PLI_DATA[7]
PLI_DATA[0]PLI_DATA[1]PLI_DATA[2]PLI_DATA[3]PLI_DATA[4]PLI_DATA[5]PLI_DATA[6]
PLI_CTL[0]
PWR_CLASS
PLI_CTL[1]
PLI_LPSPLI_LREQ
LPWR_1394DS_ONLY_EN0
3 OF 3
VESTA FW
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CRYSTAL LOAD CAPACITANCE IS 12PF
Put crystal circuit close to PHY
Vesta Config Straps:PWR_CLASS - FireWire Power Class1 - Sets Power Class to 0x40 - Sets Power Class to 0x0(Internal Pull-up)
DS_ONLY_EN0 - Port 0 Data/Strobe1 - Port 0 Data/Strobe mode only
(Internal Pull-down)0 - Port 0 Bilingual mode
Page Notes
- _PP1V2_ENETFW- _PP2V5_ENETFW- _PP3V3_ENETFW
DIFFERENTIAL_PAIRNET_SPACING_TYPE
Power aliases required by this page:- _PPFW_PHY- _PP3V3_FW
ESR < 0.5 ohms
Internal Pull-DownInternal Pull-Up
Vesta FireWire PHY(I2C_VESTA_SDA)
I2C Addr A0
(I2C_VESTA_SCL)
ELECTRICAL_CONSTRAINT_SET
(PROVIDED BY LINK PAGE)
counter internal pull-down in Vesta. If stuffed, adds external pull-up to
Signal aliases required by this page:
BOM options provided by this page:
(NONE)
- VESTA_DS_ONLY_EN0
See straps table for more information.
Net Spacing Type: FWLine To Line: 15 mils
Secondary Length: 500 milsSecondary Max Sep: 100 mils
NOTE: Target differential impedance for
Primary Max Sep: 7.5 mils
FW data pairs is 110 ohms.
Length Tolerance: 100 mils
See straps table for more information.
- VESTA_PWR_CLASS_0 If stuffed, adds external pull-down to counter internal pull-up in Vesta.
Master: Link
54
RP8900
1/16W
22
SM1
5%
63
RP8900
1/16W5%
SM1
22
72
RP890022
SM11/16W5%
81
RP8900
5%1/16WSM1
22
63
RP890122
SM11/16W5%
81
RP890122
SM11/16W5%
54
RP890122
5%1/16WSM1
72
RP8901
5%1/16WSM1
22
21
R8900
5%1/16WMF402
22
21
R8901
5%1/16WMF402
22
21
R8902
1/16W5%
MF402
22
2
1R89092K
402MF
1/16W1%
2
1R8911
402MF
VESTA_DS_ONLY_EN0
1/16W
10K5%
2
1R89125%
1/16WMF402
10K
VESTA_PWR_CLASS_0
2
1 C89130.1uF10V20%
CERM402
2
1 C891420%10VCERM402
0.1uF2
1 C891520%10VCERM
0.1uF
402
2
1 C89110.1uF
402CERM10V20%
2
1 C890920%10VCERM402
0.1uF
2
1 C890820%10VCERM402
0.1uF2
1 C8907
CERM
20%10V
402
0.1uF2
1 C89060.1uF
402CERM10V20%
2
1 C8903
402CERM
20%0.1uF10V
21
L8901FERR-EMI-600-OHM
SM
2
1 C89010.001uF
402CERM
20%50V2
1 C8900
CERM
20%10uF6.3V
1206
21
L8900
SM
FERR-EMI-600-OHM
2
1 C890520%50VCERM402
0.001uF2
1 C8904
805
6.3V
10uF20%
CERM
21
L8902
SM
FERR-EMI-600-OHM
2
1R89211/16W
402MF
5%0
21
Y8920CRITICAL
24.576M
8X4.5MM-SM
2
1R89031K
402MF
1/16W1%
7
4
8
5
6
3
2
1
U8950
OMIT
16KX8_M24128BSOI
2
1 C89500.1uF
402CERM10V20%
2
1R895610K
5%1/16W
MF402
2
1R89141/16W
5%390K
MF402
N15
P13
P14
N13
H15
K15
M15
H14
K14
M14
H13
J13
L13
G15
J15
L15
G14
J14
L14
J4
J5
B14B13
A14
H1
H2
R15
A12
P15
N14
E15
D12
D11
D14
D15D13
G11G12
G13
F13F12
F11
E11E12
E13E14
J3
M12
M11
L12
L11
N12
N11
M10
L10
K13
K12
K11
C13C12
C11
A13
R13
R14
P12
U8600BCM5462FBGA-200
OMIT
2
1R89151/16W
5%
MF402
10K
2
1R891610K1/16W5%
MF402
21
L8906FERR-EMI-600-OHM
SM
21
L8909
SM
FERR-EMI-600-OHM
21
L8913
SM
FERR-EMI-600-OHM
2
1 C8917
805CERM
10uF6.3V20%
2
1 C8918
CERM805
20%10uF6.3V
2
1 C8919
CERM
20%10uF
805
6.3V
2
1C89205%50V
CERM402
22pF2
1C8921
402CERM50V5%
22pF
2
1R89041%1/16WMF402
10K
ABBREV=DRAWINGTITLE=FIZZY
1038903051-6532
FW_TPBIAS<2>MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
FW_TPBIAS<1>MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
FW_TPBIAS<0>MIN_LINE_WIDTH=10 milMIN_NECK_WIDTH=10 mil
FW_TPB2 FW FW_TPB1 FW_TPB_P<1>
15 MIL SPACING VESTA_CLK24M_XTALO
FW_TPA_P<1>
_PP3V3_FW
FW_DATA<3>
_PPFW_PHY
FW_CTL<0>
FW_DATA<6>
FW_DATA<4>
FW_DATA<2>
FW_DATA<0>
FW_CTL<1>
FW_DATA<7>
FW_DATA<5>
FW_DATA<1>FW_CLK98M_PCLK
FW_PINT
FW_TPA_P<2>
FW_TPA_P<0>
FW_TPB_N<0>
TP_VESTA_TDBL<0>
TP_VESTA_TDBL<2>
_PP3V3_ENETFW
_PP2V5_ENETFW
FW_TPB_N<2>
FW_TPA_N<1>
_PP2V5_ENETFW
FW_DATA_R<1>FW_DATA_R<0>
FW_CLK98M_LCLK
FW_LOWPWR
TP_VESTA_ESDET<1>
TP_VESTA_TEST_1394<1>
VESTA_CLK24M_XTALO_R
FW_LREQ
VESTA_CLK24M_XTALI
_PP3V3_FW
VESTA_RDAC2_PD
_PP1V2_ENETFW
_PP1V2_ENETFW
MIN_NECK_WIDTH=15 milMIN_LINE_WIDTH=20 milVOLTAGE=2.5V
PP2V5_VESTA_BIASVDD2
MIN_NECK_WIDTH=15 milMIN_LINE_WIDTH=20 mil
PP2V5_VESTA_XTALVDD2VOLTAGE=2.5V
TP_VESTA_TDBL<1>
FW_TPB_P<2>
15 MIL SPACINGVESTA_CLK24M_XTAL VESTA_CLK24M_XTALI
15 MIL SPACING VESTA_CLK24M_XTALO_R
FW_TPB1 FW FW_TPB0 FW_TPB_P<0>
FW_TPB1 FW FW_TPB0 FW_TPB_N<0>
FW_TPA2 FW FW_TPA_P<1>FW_TPA1FW_TPA2 FW FW_TPA1 FW_TPA_N<1>
FW_TPB2 FW FW_TPB_N<1>FW_TPB1
FW_TPA3 FW FW_TPA_P<2>FW_TPA2
FW_TPB3 FW FW_TPB_P<2>FW_TPB2FW_TPB3 FW FW_TPB_N<2>FW_TPB2
15 MIL SPACING FW_CLK98M_PCLK_R
FW_TPA0FW_TPA1 FW FW_TPA_N<0> PP1V2_VESTA_PLLVDD2
MIN_NECK_WIDTH=15 milMIN_LINE_WIDTH=20 milVOLTAGE=1.2V
FW_TPA3 FW FW_TPA_N<2>FW_TPA2
FW_TPA1 FW FW_TPA_P<0>FW_TPA0
MIN_LINE_WIDTH=20 milVOLTAGE=1.2VMIN_NECK_WIDTH=15 mil
PP1V2_VESTA_FAVDDL
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=15 milVOLTAGE=2.5V
PP2V5_VESTA_FAVDDM
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=15 milVOLTAGE=3.3V
PP3V3_VESTA_FAVDDH
I2C_VESTA_SCL
FW_TPA_N<2>
FW_TPB_P<1>
VESTA_CLK24M_XTALO
VESTA_DS_ONLY_EN0
FW_DATA_R<4>FW_DATA_R<5>FW_DATA_R<6>
TP_VESTA_TEST_1394<0>
FW_LPS
FW_CLK98M_PCLK_R
FW_LINKON
FW_TPA_N<0>
FW_TPB_N<1>
FW_TPB_P<0>
FW_CTL_R<1>
FW_DATA_R<7>
FW_DATA_R<3>FW_DATA_R<2>
FW_CTL_R<0>
TP_VESTA_TVCO_24
VESTA_PWR_CLASS
FWEEPROM_WP_PD
I2C_VESTA_SDA
TP_VESTA_ESDET<0>
TP_VESTA_ESDET<2>
FW_CPS
LAST_MODIFIED=Mon Feb 23 19:08:14 2004
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12
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12
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Preliminary
www.vinafix.vn
SYM_VER-1
SYM_VER-1
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
VP
VGND
TPI#
TPO
TPI
TPO#
ALIAS
ALIAS
ALIAS
SYM_VER-2
SYM_VER-2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DRAWING
to apply to entire TPA/TPB XNets.
Place close to FireWire PHY
properly terminate unused signals.
connected to a beta-only device,
"Snapback" & "Late VG" Protection
appropriate connectors and/or to
assumed that FireWire PHY page will
AREF needs to be isolated from
PAGEPHY
BYPROVIDED
ELECTRICAL_CONSTRAINT_SET
ESD Rail
1394b implementation based on AppleFireWire Design Guide (FWDG 0.6, 5/14/03)
provide the appropriate constraints
- _PPFW_PORT2- _PPFW_PORT1
- _PPFW_PORT3- _PP3V3_FW
- _GND_CHASSIS_FW_PORT2
(NONE)
(NONE)
- _GND_CHASSIS_FW_PORT3
- _GND_CHASSIS_FW_PORT1
Power aliases required by this page:
Page Notes
BOM options provided by this page:
NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is
Signal aliases required by this page:
necessary aliases to map the FireWire TPA/TPB pairs to their
NOTE: This page is expected to contain the
NET_SPACING_TYPE DIFFERENTIAL_PAIR
Cable Power
514-0057
PORT 2
(TPA+)
(TPB+)
(TPA-)
(TPB-)
logic ground for speed signaling
per 1394b V1.33
there is no DC path between them
When a bilingual device is
(to avoid ground offset issue)
all local grounds per 1394b spec
BREF should be hard-connected to
and connection detection currents
(GND_FW_PORT1_VG)
FireWire Ports
NC
OUTPUT
INPUT
TPB-TPB<R>TPB+
TPA+TPA<R>TPA-
NCVG
(FW_PORT1_BREF)
(PPFW_PORT1_VP)
(Is this correct for Vesta?)
Termination
(PPFW_PORT2_VP)
1394A
PORT 1BILINGUAL
Cable Power
VP
514S0058
"Snapback" & "Late VG" Protection
3rd TPA/TPB pair unused
21
L9090400-OHM-EMI
SM-1
2
1 C90920.001uF20%50VCERM402
2
1 C909120%10VCERM402
0.1uF
21
R9090
5%1/16WMF402
0
2
1C90900.1uF
20%10V
CERM402
3
1
D90901N5227BSOT23
21
L9020
SM
FERR-250-OHM
2
1 C902450V
0.001uF
CERM
20%
402
21
F9020
SM
1.5AMP-33V
3
5
4
DP9020BAV99DWSOT-363
2
1C90210.001uF
402CERM50V20%
2
1 C9025
402CERM16V20%0.01uF
2
1C902620%16V
CERM402
0.01uF
3
5
4
DP9021SOT-363BAV99DW
2
1C902320%
0.001uF
402CERM50V
6
2
1
DP9020SOT-363BAV99DW
2
1C902020%50V
CERM402
0.001uF
6
2
1
DP9021SOT-363BAV99DW
2
1C9022
402
50V20%
CERM
0.001uF
2
1C90190.01uF
20%16V
402CERM
NO STUFF
21
L9010FERR-250-OHM
SM
2
1 C90140.001uF
402CERM50V20%3
5
4
DP9010BAV99DWSOT-363
2
1C9011
CERM402
0.001uF50V20%
2
1 C90180.01uF
402CERM
20%
NO STUFF
16V
2
1C90170.01uF
NO STUFF
402CERM16V20%
2
1C9015
603-1X7R50V
0.1uF10%
2
1 C90160.01uF
NO STUFF
16V20%
CERM4022
1R90111M1/16WMF402
5%
2
1R9010
805
0
FF
5%1/10W
3
5
4
DP9011SOT-363BAV99DW
2
1C90130.001uF
402CERM50V20%
6
2
1
DP9010SOT-363BAV99DW
2
1C9010
CERM402
0.001uF50V20%
6
2
1
DP9011SOT-363BAV99DW
2
1C90120.001uF
402CERM50V20%
4
32
1
FL90102012H
90-OHM-300mA
4
32
1
FL90112012H
90-OHM-300mA
2
1 C9060
CERM402
6.3V10%1uF
2
1 C9050
CERM
1uF6.3V10%
402
2
1R90611%1/16WMF402
56.2
2
1R906056.2
402MF
1%1/16W
2
1R906356.2
402MF1/16W1%
2
1R90621/16W
402MF
1%56.2
2
1R90511%1/16WMF402
56.2
2
1R905056.2
1%1/16W
MF402
2
1R905356.21%1/16WMF4022
1R905256.2
1%1/16W
MF402
2
1R9064
MF
4.99K
402
1/16W1%
2
1C9064270pF
402CERM25V5%
2
1R9054
402
4.99K1%1/16WMF
2
1C905425V5%
CERM402
270pF
2
1R90701K5%
402MF1/16W
9
8
7
6
5
4
3
2
15
14
13
12
11
10
1
J90101394B-Q41
F-RT-SM
CRITICAL
1
2
5
6
3
4
10987
J90201394AF-RT-TH
CRITICAL
21
R90201/10W5%
FF805
0
3
21
4
FL9020260-OHM-330MA
SM1
3
21
4
FL9021260-OHM-330MA
SM1
1039003051-6532
ABBREV=DRAWINGTITLE=FIZZY
FW_TPB_N<1>
FW FW_PORT1_TPA_P_FLFW_PORT1_TPA_FL
_GND_CHASSIS_FW_PORT2
MIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 milVOLTAGE=0V
GND_FW_PORT1_VG
MIN_NECK_WIDTH=10 mil
PPFW_PORT1_VPVOLTAGE=33VMIN_LINE_WIDTH=25 mil
PP3V3_FW_ESD
_PPFW_PORT1
MIN_NECK_WIDTH=10 mil
PP3V3_FW_ESDVOLTAGE=3.3VMIN_LINE_WIDTH=15 mil
FW_TPA_P<0>
FW_TPB2_PDMAKE_BASE=TRUE
FW_TPB_N<2>FW_TPB_P<2>
FW_TPBIAS<2>
FW_PORT1_TPB_N_FL
MAKE_BASE=TRUEFW_PORT1_TPB_NMAKE_BASE=TRUEFW_PORT1_TPB_P
FW_PORT1_TPB_P_FL
FW FW_PORT1_TPA_N_FLFW_PORT1_TPA_FLFW FW_PORT1_TPB_P_FLFW_PORT1_TPB_FL
FW_PORT1_TPB_N_FLFW FW_PORT1_TPB_FL
FW_TPBIAS<0>
FW_TPA_C<0>
MAKE_BASE=TRUEFW_PORT2_TPA_N
MAKE_BASE=TRUEFW_PORT2_TPB_P
MAKE_BASE=TRUEFW_PORT2_TPB_N
MAKE_BASE=TRUEFW_PORT1_TPA_P
MAKE_BASE=TRUEFW_PORT1_TPA_N
MIN_NECK_WIDTH=10 milVOLTAGE=3.3V
PP3V3_FW_ESD_F
MIN_LINE_WIDTH=15 mil
_PP3V3_FW
FW_PORT2_TPB_N_FLFW FW_PORT2_TPB_FLFW FW_PORT2_TPB_P_FLFW_PORT2_TPB_FL
FW FW_PORT2_TPA_FL FW_PORT2_TPA_P_FL
FW FW_PORT2_TPA_N_FLFW_PORT2_TPA_FL
MIN_NECK_WIDTH=10 mil
PPFW_PORT2_VP_FVOLTAGE=33VMIN_LINE_WIDTH=25 mil
MAKE_BASE=TRUEFW_PORT2_TPA_P
FW_TPB_P<0>
FW_TPA_N<2>
FW_TPA_P<2>
FW_TPBIAS<1>
FW_PORT1_TPA_P
FW_PORT1_TPB_N
_PPFW_PORT2
FW_TPA_N<0>
FW_TPA_C<1>
MAKE_BASE=TRUENC_FW_TPA_N2
NO_TEST=TRUE
NC_FW_TPBIAS2MAKE_BASE=TRUENO_TEST=TRUE
MAKE_BASE=TRUENO_TEST=TRUE
NC_FW_TPA_P2
FW_PORT1_TPA_P_FLFW_PORT1_AREFFW_PORT1_TPA_N_FL
FW_PORT1_TPB_P
_GND_CHASSIS_FW_PORT1
FW_PORT1_TPA_N
PP3V3_FW_ESD
FW_TPB_N<0>
FW_TPB_P<1>
FW_TPA_P<1>FW_TPA_N<1>
FW_PORT2_TPA_N_FL
FW_PORT2_TPA_N
MIN_NECK_WIDTH=10 mil
PPFW_PORT2_VPVOLTAGE=33VMIN_LINE_WIDTH=25 mil
GND_FW_PORT2_VGVOLTAGE=0VMIN_LINE_WIDTH=25 milMIN_NECK_WIDTH=10 mil
FW_PORT2_TPB_N_FLFW_PORT2_TPB_N
FW_PORT2_TPA_P
FW_PORT2_TPA_P_FL
FW_PORT2_TPB_P_FLFW_PORT2_TPB_P
LAST_MODIFIED=Mon Feb 23 19:08:30 2004
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58 Preliminary
www.vinafix.vn
DM1DP1
DM2DP2
RSDM2
RSDP1
RSDM1
RSDP2
AVDD
DM3DP3
RSDM3
RSDP3
PPON1
OCI2OCI1
OCI3OCI4OCI5
PPON2
PPON5PPON4PPON3
RSDM4DM4DP4
DM5DP5
RSDP4
RSDM5
RSDP5
RREF
AVSS(R)
AVSS
NC1NC2
XT1/SCLKXT2
VDD
VSS
(8 OF 8)NC0
NC1
NC3
NC2
NC4
NC5
NC6NC7
NC8
NC9NC10
NC12
NC11
NC14
NC13
NC15
NC19
NC18NC17
NC16
NC20
NC22
NC23NC24
NC21
NC25
NC29NC28
NC27
NC26
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
(USB2_OC<3>)(USB2_OC<4>)
(USB2_OC<0>)(USB2_OC<1>)
Tie to GND at ball N11
(USB2_N<4>)(USB2_P<4>)
(USB2_N<3>)(USB2_P<3>)
(USB2_P<2>)(USB2_N<2>)
(USB2_P<1>)(USB2_N<1>)
(USB2_N<0>)(USB2_P<0>)
USB Host Interfaces
ELECTRICAL_CONSTRAINT_SET
(USB2_OC<2>)
Y9145 LOAD CAPACITANCE IS 16pF
Master: Fizzy
Secondary Max Sep: 100 milsSecondary Length: 500 mils
Length Tolerance: 50 milsLine To Line: 19.5 mils
Primary Max Sep: 7.5 mils
USB2 data pairs is 90 ohms.
(NONE)
Net Spacing Type: USB2
NOTE: Target differential impedance for
BOM options provided by this page:
- _PP3V3_PWRON_USBPower aliases required by this page:
Signal aliases required by this page:(NONE)
Page Notes
21
R910236
402MF
1/16W1%
21
R9103
MF402
36
1/16W1%
21
R910436
1%1/16WMF402
21
R910536
402MF
1/16W1%
21
R9106
1%1/16WMF402
36
21
R910736
402
1/16W1%
MF
21
R910836
402MF
1/16W1%
21
R9109
1%1/16WMF402
36
2
1R91381/16W
MF
1%9.09K
402
2
1C912520%
0.1uF
CERM10V
4022
1C91240.1uF
20%10V
CERM402
2
1C9130
402
0.1uF
CERM10V20%
2
1C912920%10V
CERM
0.1uF
402
12
R9139
603MF
5%
0
1/16W
2
1R91415%1/16WMF402
1.5K
P8
L9
N2
B2
A2
B14
H14
N14
P10
N1
D8
F11
J11
G4
D12
H12
L12
M11
B13
N13
B1
L13
N8
E2
A3
A12
A13
P12
P3
D7
H4
G12
D13
F13
H13
J13
P2
C14
E14
G14
J12
K13
E13
F12
H11
K14
M14
P11
A9
C10
C11
A11
C12
B9
A10
B10
B11
B12
M6
P6
C13
E12
G13
J14
L14
D14
F14
G11
K12
M13
N11
M12
P13
N12
N10
U7700NEC_uPD720101_USB2
FBGA
CRITICAL
1
2R9145
402
1005%1/16WMF
2
1 C9146
402CERM50V5%22pF
2
1C9123
402
0.1uF
CERM10V20%
2
1C912220%10V
CERM
0.1uF
402
2
1C9128
CERM10V20%
402
0.1uF2
1C912720%10V
CERM
0.1uF
402
2
1C9121
402
0.1uF
CERM10V20%
2
1C912620%10V
CERM
0.1uF
402
5678
4321
RP9110
SM11/16W5%10K
1
2R9110
402MF
1/16W5%
10K
2
1C912020%
CERM805
6.3V
10uF
2
1R91405%
1/16W
1.5K
402MF
21
Y9145CRITICAL
30.0000M
8X4.5MM-SM
2
1C9145
402CERM50V5%
22pF
T2T1
R8R7
R6
R5R4
Y3Y1
W3
W1V4
V3
V2V1
U6
U5
R3
U4
U3U2
U1
T8T7
T6
T5T4
T3
P8P7
U2300
OMIT
SHASTA
BGAV1.0
2
1C9137
CERM10V
402
0.1uF20%
2
1C9136
402CERM10V20%
0.1uFC9135
20%10uF6.3VCERM805
21
L9135FERR-EMI-100-OHM
SM
21
R9135
603
4.7
MF1/16W5%
21
R9100
1/16W1%
36
MF402
21
R910136
1/16W1%
MF402
TITLE=FIZZYABBREV=DRAWING
03051-653291 103
NEC_NC2_PU
USB2_PWREN<0>
USB2_PWREN<2>
TP_SB_NC_R4
USB2_P<3>USB2_N<3>
_PP3V3_PWRON_USBPP3V3_PWRON_NEC_AVDDVOLTAGE=3.3VMIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
VOLTAGE=0VGND_NEC_AVSS_R
MIN_LINE_WIDTH=20 milMIN_NECK_WIDTH=10 mil
USB2_N<1>
USB_NEC_N<0>
USB_NEC_P<0>
USB_NEC_N<1>
USB_NEC_P<1>
USB_NEC_N<2>
USB_NEC_P<2>
USB_NEC_N<3>
USB_NEC_P<3>
USB_NEC_N<4>
USB_NEC_P<4>
USB2_N<0>USB2_P<0>
USB2_P<1>
USB2_P<2>USB2_N<2>
USB2_P<4>
USB2_OC<0>
NEC_CLK30M_XT2
_PP3V3_PWRON_USB
USB2_OC<1>
USB2_OC<3>USB2_OC<2>
USB2_OC<4>
_PP3V3_PWRON_USB
NEC_CLK30M_XT1
NEC_RREF_PD
NEC_NC1_PU
NEC_CLK30M_XT2_R
USB2_PWREN<4>USB2_PWREN<3>
USB2_PWREN<1>
TP_SB_NC_Y1TP_SB_NC_Y3
TP_SB_NC_W3TP_SB_NC_W1
TP_SB_NC_V2TP_SB_NC_V3TP_SB_NC_V4
TP_SB_NC_V1TP_SB_NC_U6TP_SB_NC_U5
TP_SB_NC_U3TP_SB_NC_U4
TP_SB_NC_U2
TP_SB_NC_T8TP_SB_NC_U1
TP_SB_NC_T7TP_SB_NC_T6TP_SB_NC_T5
TP_SB_NC_T3TP_SB_NC_T4
TP_SB_NC_T2TP_SB_NC_T1TP_SB_NC_R8
TP_SB_NC_R6TP_SB_NC_R7
TP_SB_NC_R5
TP_SB_NC_R3
TP_SB_NC_P7TP_SB_NC_P8
USB2_N<4>
USB2_1USB2_1 USB2_N<1>USB2USB2
USB2_0USB2_0 USB2_P<0>USB2USB2
USB2_2 USB2_2 USB2_P<2>USB2USB2
USB2_1 USB2_P<1>USB2_1USB2USB2
USB2_0USB2_0 USB2_N<0>USB2USB2
USB2_4 USB2_4 USB2_N<4>USB2USB2
USB2_2 USB2_N<2>USB2_2 USB2USB2
USB2_3 USB2_N<3>USB2_3 USB2USB2
USB2_4 USB2_P<4>USB2_4 USB2USB2
USB2_NEC_XTAL NEC_CLK30M_XT115 MIL SPACINGNEC_CLK30M_XT215 MIL SPACINGNEC_CLK30M_XT2_R15 MIL SPACING
USB2_3 USB2_3 USB2_P<3>USB2USB2
LAST_MODIFIED=Mon Feb 23 19:08:38 2004
59
59
59
59
59
59
59
59
59
59
59
59
59
59
59
59
59
59
59
59
6
6
6
59
6
6
6
6
6
6
6
6
59
6
59
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
59
5
5
5
5
5
5
59
59
5
5
5
5
5
5
5
5
5
5
5
5
5
59
59
59
5
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DRAWING
516S0143
(DTR#)
(SCCA)
- _PP3V3_PWRON_MODEM
to 5V power supply output caps
(RTS#)(TXD#)
(RXD)
Modem Interface
(NONE)
(GPIO#)
(TRXC)
MOVE TO GPIO PAGE!
Page Notes
BOM options provided by this page:
(NONE)Signal aliases required by this page:
Spec Load: 0.5 A active, 3 mA auxiliary
Supports both The Last Dash and Q52 Modems
Removed 10uF bulk cap because modem connector is close
Modem Connector
Power aliases required by this page:
9
8 7
6 5
4 3
2
16 15
14 13
12 11
10
1
J9400QT510166-L010
F-ST-SM1
CRITICAL
2
1 C940310uF20%6.3VCERM805
2
1R9400
402
10K
MF1/16W5%
2
1R941115K5%1/16WMF4022
1R941015K
5%1/16W
MF402
03
10394051-6532
ABBREV=DRAWINGTITLE=FIZZY
USB_MODEM_P
I2S1_RESET_LUDASH_SDOWN
I2C_MODEM_SDA
_PP5V_PWRON_MODEM
I2S1_SB_TO_DEV_DTO
I2C_MODEM_SCL
I2S1_SYNCI2S1_DEV_TO_SB_DTI
_PP3V3_PWRON_MODEM
I2S1_BITCLK
USB_MODEM_N
MODEM_RING2SYS_L
I2S1_MCLK
LAST_MODIFIED=Mon Feb 23 19:08:46 2004
23
23 23
23
23
23
16
23
16 16
16
16
23
16
5
6
6
18
5
6
18
6
6
5
6
5
6
6
Preliminary
www.vinafix.vn
DRAWINGD
SIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
AUDIO_LI_OPTICAL_PLUG_L - 100k PU on Kazoo (pg 8)
AUDIO_LO_OPTICAL_PLUG_L - 100k PU on Kazoo (pg 6)
(SLEEP_LED_GND)
516S0154
EMI Filtering
for ALL audio GPIOs.
BOM options provided by this page:(NONE)
(NONE)
appropriate pull-ups and pull-downs
NOTE: It is considered the responsibility of the audio section to provide the
- _PP5V_PWRON_AUDIOPower aliases required by this page:
Signal aliases required by this page:
- _PP3V3_PWRON_AUDIO
Page Notes
Audio GPIO Pull-ups & Pull-downs
AUDIO_LO_DET_L - 100k PU on Kazoo (pg 6)
AUDIO_LO_MUTE_L - 100k PD on Kazoo (pg 6)
AUDIO_SPKR_MUTE_L - 100k PD on Kazoo (pg 5)
AUDIO_EXT_MCLK_SEL - 100k PD on Kazoo (pg 8)
AUDIO_GPIO_11 - 100k PD on Kazoo (pg 8)
I2S0_RESET_L - 100k PD on Kazoo (pg 4)
I2S2_RESET_L - 100k PD on Kazoo (pg 8)
Audio Interface
AUDIO_LI_DET_L - 100k PU on Kazoo (pg 7)
Sound Board Connector
Place shorts at 3.3V and 5V regulators
Place shorts at 3.3V and 5V regulators
This is an internal board short
This is an internal board short
This is an internal board short
Place ground short near 3.3V and 5V regulators
21
L9530FERR-220-OHM
0402
21
L9531
0402
FERR-220-OHM
21
L9532
0402
FERR-220-OHM
21
L9533FERR-220-OHM
0402
21
L9534FERR-220-OHM
0402
21
L9535FERR-220-OHM
0402
21
L9536FERR-220-OHM
0402
9
87
65
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
4443
4241
J9500CRITICAL
M-ST-SM1QT500406-L111
2 1
XW9505SM
2 1
XW9500SM
21
L9538
0402
FERR-220-OHM
21
L9537FERR-220-OHM
0402
21
L9539
0402
FERR-220-OHM
21
L9540FERR-220-OHM
0402
2 1
XW9503SM
21
R9515NO STUFF
10K
MF
5%1/16W
402
21
R950410K
MF1/16W5%
402
21
R9505
402
1/16W5%
MF
10K
21
R950710K
MF1/16W5%
402
21
R951110K
MF1/16W5%
402
ABBREV=DRAWINGTITLE=LINK
03051-653295 103
_PP5V_RUN_AUDIO
PP5V_PWRON_AUDIO
MIN_LINE_WIDTH=20 milVOLTAGE=5VMIN_NECK_WIDTH=10 mil
_PP5V_PWRON_AUDIO
AUDIO_GPIO_11
I2S0_SB_TO_DEV_DTO_F
MIN_LINE_WIDTH=20 milVOLTAGE=0VMIN_NECK_WIDTH=10 mil
GND_AUDIO
_PP3V3_PWRON_AUDIO
I2S0_BITCLK_FI2S0_SYNC_F
AUDIO_EXT_MCLK_SEL
AUDIO_GPIO_12
AUDIO_HP_MUTE_L
AUDIO_SPKR_DET_L
_PP3V3_PWRON_AUDIO
AUDIO_HP_DET_L
I2S0_SB_TO_DEV_DTO I2S0_SB_TO_DEV_DTO_F
I2S0_BITCLK
I2S0_DEV_TO_SB_DTI
I2S0_MCLK
I2S0_SYNC I2S0_SYNC_F
I2S2_DEV_TO_SB_DTI I2S2_DEV_TO_SB_DTI_F
I2S2_BITCLK I2S2_BITCLK_F
I2S2_SYNC_F
I2S0_BITCLK_F
I2S0_RESET_L
I2S2_RESET_L_FI2S2_RESET_L
I2S0_DEV_TO_SB_DTI_F
I2S2_DEV_TO_SB_DTI_FI2S2_SYNC_F
I2S0_DEV_TO_SB_DTI_F
I2S0_MCLK_F
AUDIO_SPKR_MUTE_L_F
I2S2_SYNC
I2S2_BITCLK_F
MIN_LINE_WIDTH=20 mil
PP3V3_PWRON_AUDIOVOLTAGE=3.3VMIN_NECK_WIDTH=10 mil
I2S0_RESET_L_F
AUDIO_SPKR_MUTE_L
I2S0_MCLK_F
AUDIO_LO_MUTE_LAUDIO_LI_DET_L
AUDIO_SPKR_MUTE_L_F
AUDIO_LO_OPTICAL_PLUG_LAUDIO_LO_DET_L
AUDIO_LI_OPTICAL_PLUG_L
I2C_AUDIO_SDA
I2S0_RESET_L_FI2S2_RESET_L_F
I2C_AUDIO_SCL
SLEEPLED_ANODE
LAST_MODIFIED=Mon Feb 23 19:08:54 2004
23
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23
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
23
61
23
23
23
23
23
61
61
19
5
6 5
6
6
6
5
6
6
6
23
23
23
5
23
23 6
23
23
23
23 6
23 6
23 6
6
6
23
6 23
6
6
6
6
6
61
23
6
6
6
6
6
6
6
61
6
6
6
18
6
6
18
6
Preliminary
www.vinafix.vn
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DRAWING
DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE
NET_SPACING_TYPEELECTRICAL_CONSTRAINT_SET
Electrical Constraints
DIFFERENTIAL_PAIR
No series termination on PCI signalsElectrical ConstraintsNET_SPACING_TYPEELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
051-6532 03
99 103TITLE=LINKABBREV=DRAWINGLAST_MODIFIED=Mon Feb 23 18:36:43 2004
RAM_CAD RAM_DQS<1>RAM_DQS1
SI_TMDS_DP<2>TMDS SI_TMDS_D2
TMDS SI_TMDS_DN<3>SI_TMDS_D3
SI_TMDS_DP<3>TMDS SI_TMDS_D3
TMDS TMDS_DN<5>TMDS_D5
PCI_SB_IRDY_L
PCI_TRDY_LMAKE_BASE=TRUE
PCI_SB_AD<26>
TMDS_CONN_DP<1>TMDS CONN_TMDS_D1
TMDS_CONN_DP<0>TMDS CONN_TMDS_D0
TMDS TMDS_DP<4>TMDS_D4TMDS TMDS_DN<3>TMDS_D3
TMDS_DP<3>TMDS TMDS_D3
TMDS_CLKNTMDS TMDS_CLK
EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK_P
EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK_N
RAM_CLKRAM_CLK0 RAM_CLK_A_PRAM_CLK_ATMDS GPU_TMDS_DN_R<2>GPU_TMDS_D2_RTMDS GPU_TMDS_CLKP_RGPU_TMDS_CLK_R
TMDS GPU_TMDS_DP_R<2>GPU_TMDS_D2_R
RAM_CADRAM_DQS15 RAM_DQ<127..120>
RAM_CADRAM_DQS13 RAM_DQ<111..104>RAM_CADRAM_DQS13 RAM_DQS<13>
SI_TMDS_DN<5>TMDS SI_TMDS_D5GPU_TMDS_DP<0>TMDS GPU_TMDS_D0GPU_TMDS_DN<0>GPU_TMDS_D0TMDS
TMDS_DN<4>TMDS TMDS_D4
TMDS_DN<1>TMDS TMDS_D1
TMDS_DP<1>TMDS TMDS_D1
TMDS_DN<0>TMDS TMDS_D0
TMDS TMDS_DP<2>TMDS_D2
TMDS_CLKPTMDS_CLKTMDS
TMDS_DN<2>TMDS TMDS_D2
TMDS TMDS_DP<0>TMDS_D0
PCI_DEVSEL_LMAKE_BASE=TRUE
PCI_FRAME_LMAKE_BASE=TRUE
PCI_IRDY_LMAKE_BASE=TRUE
PCI_STOP_LMAKE_BASE=TRUE
MAKE_BASE=TRUEPCI_PARPCI_SB_PAR
PCI_SB_STOP_L
PCI_SB_TRDY_L
PCI_SB_FRAME_L
PCI_SB_DEVSEL_L
GPU_TMDS_CLKPTMDS GPU_TMDS_CLK
PCI_SB_AD<31>
PCI_SB_AD<15>
PCI_SB_CBE_L<3>
PCI_SB_CBE_L<2>
PCI_SB_CBE_L<1>
PCI_SB_CBE_L<0>
PCI_CBE_L<3>MAKE_BASE=TRUE
PCI_CBE_L<2>MAKE_BASE=TRUE
PCI_CBE_L<1>MAKE_BASE=TRUE
PCI_CBE_L<0>MAKE_BASE=TRUE
MAKE_BASE=TRUEPCI_AD<0>
PCI_AD<1>MAKE_BASE=TRUE
PCI_AD<2>MAKE_BASE=TRUE
PCI_AD<3>MAKE_BASE=TRUE
PCI_SB_AD<0>
PCI_SB_AD<1>
PCI_SB_AD<2>
PCI_SB_AD<3>
PCI_SB_AD<24>
PCI_SB_AD<25>
PCI_SB_AD<27>
PCI_AD<18>MAKE_BASE=TRUE
TMDS SI_TMDS_DP<5>SI_TMDS_D5
RAM_CAD RAM_DQS<0>RAM_DQS0
RAM_CLK_A_N_RRAM_CLK_A_RRAM_CLKRAM_CLK_B_R RAM_CLK_B_P_RRAM_CLKRAM_CLK_B_R RAM_CLK_B_N_RRAM_CLK
RAM_CLK_D_P_RRAM_CLK_D_RRAM_CLK
RAM_CLK_E_P_RRAM_CLK_E_RRAM_CLKRAM_CLK_E_N_RRAM_CLK_E_RRAM_CLK
RAM_CLK_A_NRAM_CLK_ARAM_CLK0 RAM_CLKRAM_CLK_B_PRAM_CLK_BRAM_CLK0 RAM_CLKRAM_CLK_B_NRAM_CLK_BRAM_CLK0 RAM_CLK
RAM_CLK_D_NRAM_CLK_DRAM_CLK1 RAM_CLKRAM_CLK_E_PRAM_CLK_ERAM_CLK1 RAM_CLKRAM_CLK_E_NRAM_CLK_ERAM_CLK1 RAM_CLK
RAM_CKE_R<5..4>RAM_CADRAM_CKE0 RAM_CKE<0>RAM_CADRAM_CKE0 RAM_CKE<1>RAM_CADRAM_CKE1 RAM_CKE<4>RAM_CADRAM_CKE1 RAM_CKE<5>RAM_CAD
RAM_CAD RAM_CS_L_R<9..8>
RAM_CS0 RAM_CAD RAM_CS_L<0>
RAM_CAD RAM_BA_R<1..0>
RAM_CAD RAM_RAS_L_R
RAM_CAD RAM_CAS_L_R
RAM_BA_R<1..0>RAM_CADRAM_A_CTLRAM_RAS_L_RRAM_CADRAM_A_CTLRAM_CAS_L_RRAM_CADRAM_A_CTLRAM_WE_L_RRAM_CADRAM_A_CTL
RAM_CLK_D_PRAM_CLK_DRAM_CLK1 RAM_CLK
RAM_CLK_A_RRAM_CLK RAM_CLK_A_P_R
RAM_A<13..0>RAM_A_CTL RAM_CAD
RAM_WE_L_RRAM_CAD
RAM_A_R<13..0>RAM_CAD
RAM_CS1 RAM_CAD RAM_CS_L<9>RAM_CS1 RAM_CAD RAM_CS_L<8>RAM_CS0 RAM_CAD RAM_CS_L<1>
RAM_CS_L_R<1..0>RAM_CAD
RAM_CAD RAM_CKE_R<1..0>
RAM_CAD RAM_DQ_R<127..0>RAM_CAD RAM_DQS_R<15..0>
RAM_CAD RAM_DQ<23..16>RAM_DQS2RAM_CAD RAM_DQS<2>RAM_DQS2
RAM_DQ<31..24>RAM_CADRAM_DQS3RAM_DQS<4>RAM_CADRAM_DQS4RAM_DQ<39..32>RAM_CADRAM_DQS4
RAM_CADRAM_DQS5 RAM_DQ<47..40>
RAM_DQ<63..56>RAM_CADRAM_DQS7
RAM_DQS<7>RAM_CADRAM_DQS7
RAM_DQS<8>RAM_CADRAM_DQS8
RAM_DQS<9>RAM_CADRAM_DQS9
RAM_DQ<71..64>RAM_CADRAM_DQS8
RAM_CAD RAM_DQS<10>RAM_DQS10RAM_CADRAM_DQS10 RAM_DQ<87..80>
RAM_CADRAM_DQS11 RAM_DQS<11>
RAM_CADRAM_DQS11 RAM_DQ<95..88>
RAM_CADRAM_DQS12 RAM_DQ<103..96>
RAM_CADRAM_DQS14 RAM_DQS<14>
RAM_CADRAM_DQS14 RAM_DQ<119..112>
RAM_CADRAM_DQS15 RAM_DQS<15>
EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK_P
EI_CPU_TO_NB_AD<43..0>EI_CPU_NB_DATAEI_NB_TO_CPU_AD<43..0>EI_NB_CPU_DATA
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_SR_N<1>EI_CPU_TO_NB_CAD EI_CPU_TO_NB_SR_P<1>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_SR_N<1>EI_NB_TO_CPU_CAD EI_NB_TO_CPU_SR_P<1>EI_NB_TO_CPU_CAD EI_NB_TO_CPU_SR_N<0>
RAM_DQ<55..48>RAM_CADRAM_DQS6
RAM_CAD RAM_DQS<5>RAM_DQS5
RAM_DQS<3>RAM_CADRAM_DQS3TMDS_CONN_DN<0>TMDS CONN_TMDS_D0
TMDS_CONN_DN<1>TMDS CONN_TMDS_D1
TMDS_CONN_DN<2>TMDS CONN_TMDS_D2
TMDS TMDS_CONN_CLKNCONN_TMDS_CLK
TMDS_CONN_DP<4>TMDS CONN_TMDS_D4TMDS_CONN_DN<4>TMDS CONN_TMDS_D4
TMDS SI_TMDS_DP<0>SI_TMDS_D0
SI_TMDS_DN<2>TMDS SI_TMDS_D2SI_TMDS_CLKPTMDS SI_TMDS_CLK
GPU_TMDS_DN<2>TMDS GPU_TMDS_D2
TMDS GPU_TMDS_DP_R<0>GPU_TMDS_D0_RTMDS GPU_TMDS_DN_R<0>GPU_TMDS_D0_R
TMDS GPU_TMDS_DN_R<1>GPU_TMDS_D1_R
TMDS GPU_TMDS_CLKNGPU_TMDS_CLK
TMDS CONN_TMDS_D3 TMDS_CONN_DN<3>TMDS_CONN_DP<3>TMDS CONN_TMDS_D3
TMDS SI_TMDS_CLKNSI_TMDS_CLK
SI_TMDS_DP<4>TMDS SI_TMDS_D4TMDS SI_TMDS_DN<4>SI_TMDS_D4
TMDS GPU_TMDS_DP_R<1>GPU_TMDS_D1_R
GPU_TMDS_DP<2>TMDS GPU_TMDS_D2
TMDS_CONN_DP<5>TMDS CONN_TMDS_D5
TMDS TMDS_CONN_CLKPCONN_TMDS_CLK
TMDS GPU_TMDS_CLKN_RGPU_TMDS_CLK_R
RAM_CLK_D_N_RRAM_CLK_D_RRAM_CLK
RAM_CADRAM_DQS12 RAM_DQS<12>
RAM_DQ<79..72>RAM_CADRAM_DQS9
RAM_DQS<6>RAM_CADRAM_DQS6
RAM_CAD RAM_DQ<15..8>RAM_DQS1
RAM_CAD RAM_DQ<7..0>RAM_DQS0
GPU_TMDS_DN<1>GPU_TMDS_D1TMDS
GPU_TMDS_DP<1>TMDS GPU_TMDS_D1
TMDS SI_TMDS_DN<1>SI_TMDS_D1
SI_TMDS_DP<1>TMDS SI_TMDS_D1
SI_TMDS_DN<0>TMDS SI_TMDS_D0
TMDS_CONN_DN<5>TMDS CONN_TMDS_D5
TMDS_DP<5>TMDS TMDS_D5
TMDS_CONN_DP<2>TMDS CONN_TMDS_D2
PCI_SB_AD<12>
PCI_SB_AD<13>
PCI_SB_AD<14>
PCI_SB_AD<4>
PCI_SB_AD<5>
PCI_SB_AD<6>
PCI_SB_AD<7>
PCI_SB_AD<8>
PCI_SB_AD<9>
PCI_SB_AD<10>
PCI_SB_AD<11>
PCI_AD<4>MAKE_BASE=TRUE
PCI_AD<5>MAKE_BASE=TRUE
PCI_AD<6>MAKE_BASE=TRUE
PCI_AD<7>MAKE_BASE=TRUE
PCI_AD<8>MAKE_BASE=TRUE
PCI_AD<9>MAKE_BASE=TRUE
PCI_AD<10>MAKE_BASE=TRUE
PCI_AD<11>MAKE_BASE=TRUE
PCI_AD<12>MAKE_BASE=TRUE
PCI_AD<13>MAKE_BASE=TRUE
PCI_AD<14>MAKE_BASE=TRUE
PCI_AD<15>MAKE_BASE=TRUE
PCI_AD<31>MAKE_BASE=TRUE
PCI_AD<30>MAKE_BASE=TRUE
PCI_AD<29>MAKE_BASE=TRUE
PCI_AD<28>MAKE_BASE=TRUE
PCI_AD<27>MAKE_BASE=TRUE
PCI_AD<25>MAKE_BASE=TRUE
PCI_AD<23>MAKE_BASE=TRUE
PCI_AD<22>MAKE_BASE=TRUE
PCI_AD<21>MAKE_BASE=TRUE
PCI_AD<20>MAKE_BASE=TRUE
PCI_AD<19>MAKE_BASE=TRUE
PCI_AD<17>MAKE_BASE=TRUE
PCI_AD<16>MAKE_BASE=TRUE
PCI_SB_AD<23>
PCI_SB_AD<22>
PCI_SB_AD<21>
PCI_SB_AD<20>
PCI_SB_AD<19>
PCI_SB_AD<18>
PCI_SB_AD<17>
PCI_SB_AD<16>
PCI_SB_AD<30>
PCI_SB_AD<29>
PCI_SB_AD<28>
PCI_AD<26>MAKE_BASE=TRUE
PCI_AD<24>MAKE_BASE=TRUE
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35
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Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE 100
*** Signal Cross-Reference for the entire design ***
1V2PWRON_ITH 9B6<> 1V2PWRON_ITH_RC 9A7< 1V2PWRON_MODE 9A6<> 1V2PWRON_PGOOD 9B4<> 1V2PWRON_RT 9B6<
1V2PWRON_RUNSS 9B6<> 1V2PWRON_SGND 9A6<> 1V2PWRON_SW 9B4<> 1V2PWRON_VFB 9A5<> 1V2PWRON_VFB_DIV 9A5< 1V2RUN_EN 9A2<> 14C6<
1V5PWRON_SW 9C5<> 1V5PWRON_VFB_DIV 9B5< 1V5RUN_EN 9C2<> 14C6< 1V8RUN_CC 9D5<> 1V8RUN_PGOOD 9D5<> 14B8<
1V8RUN_SHDN_L 9D6<> 14B6< 2V5NBVCORE_STBY_L 11C3< 14D6< 2V5PWRON_SW 11C3<> 2V5RUN_EN_L 11D2<> 14C6< 2V5_BOOST_ESR 11C3<> 2V5_BST_HI 11C4<>
2V5_BST_LO 11C4<> 2V5_FB 11C4<> 2V5_FB_RC 11B2< 2V5_HI_GATE 11C4<> 2V5_INV 11C4<
2V5_INV_RC 11C1< 2V5_ITRIP 11C4< 2V5_LO_GATE 11C4<> 2V5_NBVCORE_CT 11C4<> 2V5_NBVCORE_FLT 11C4<> 2V5_NBVCORE_PGOOD 11B4<> 14B8<
2V5_NBVCORE_PWM 11B5< 2V5_NBVCORE_REF 11C4<> 2V5_NBVCORE_VCC 11D3< 2V5_NBVCORE_VREF5 11D5<> 2V5_SS 11C4<>
3V3ALL_ESR 11A3< 3V3ALL_FB 11A4< 3V3PWRON_BOOST_ESR 10D3<> 3V3PWRON_FB 10C4<> 3V3PWRON_FB_RC 10C2< 3V3PWRON_INV 10C4<
3V3PWRON_INV_RC 10C2< 3V3PWRON_LH 10C4<> 3V3PWRON_LL 10C4<> 3V3PWRON_OUT_D 10C4<> 3V3PWRON_OUT_U 10C4<>
3V3PWRON_SS 10C4<> 3V3PWRON_SW 10C2<> 3V3PWRON_TRIP 10C4< 3V3RUN_EN_L 10A4<> 14C5< 3V3_STBY_L 10D4< 14D6< 4V85ALL_ESR 11A5<
4V85ALL_FB 11A6< 5V3VPWRON_CT 10C4<> 5V3VPWRON_FLT 10C4<> 5V3VPWRON_PGOOD 10C5<> 14B8< 5V3VPWRON_REF 10C4<>
5V3VPWRON_SKIP 10C5< 5VPWRON_BOOST_ESR 10D6<> 5VPWRON_FB 10C5<> 5VPWRON_FB_RC 10C7< 5VPWRON_INV 10C5< 5VPWRON_INV_RC 10C7<
5VPWRON_LH 10C5<> 5VPWRON_LL 10C5<> 5VPWRON_OUT_D 10C5<> 5VPWRON_OUT_U 10C5<> 5VPWRON_SS 10C5<>
5VPWRON_SW 10C7<> 5VPWRON_TRIP 10C5< 5VRUNHD_EN_L 10B6<> 14D5< 5VRUN_EN_L 10A6<> 14D5< 5V_STBY_L 10D5< 14D4< ACIN_1V20_REF 7C6<
ACIN_DIV 7C6< ACIN_ENABLE_L 7C3<> ACIN_ENABLE_L_DIV 7D3<> ADAPTER_ID 6A3> 17D7<> ADAPTER_PD 7C6<
ADC_REF 32A6<> 32B2< 32B3< 32C4< AGP_AD<0> 36D4<> 37C7<> AGP_AD<15..0> 36D3< AGP_AD<1> 36D4<> 37C7<> AGP_AD<2> 36D4<> 37C7<> AGP_AD<3> 36D4<> 37C7<>
AGP_AD<4> 36D4<> 37C7<> AGP_AD<5> 36D4<> 37C7<> AGP_AD<6> 36D4<> 37C7<> AGP_AD<7> 36D4<> 37C7<> AGP_AD<8> 36D4<> 37C7<>
AGP_AD<9> 36D4<> 37C7<> AGP_AD<10> 36D4<> 37C7<> AGP_AD<11> 36C4<> 37C7<> AGP_AD<12> 36C4<> 37C7<> AGP_AD<13> 36C4<> 37C7<> AGP_AD<14> 36C4<> 37C7<>
AGP_AD<15> 36C4<> 37C7<> AGP_AD<16> 36C4<> 37C7<> AGP_AD<31..16> 36D3< AGP_AD<17> 36C4<> 37C7<> AGP_AD<18> 36C4<> 37C7<>
AGP_AD<19> 36C4<> 37C7<> AGP_AD<20> 36C4<> 37C7<> AGP_AD<21> 36C4<> 37C7<> AGP_AD<22> 36C4<> 37C7<> AGP_AD<23> 36C4<> 37C7<> AGP_AD<24> 36C4<> 37C7<>
AGP_AD<25> 36C4<> 37D7<> AGP_AD<26> 36C4<> 37D7<> AGP_AD<27> 36C4<> 37D7<> AGP_AD<28> 36C4<> 37D7<> AGP_AD<29> 36C4<> 37D7<>
AGP_AD<30> 36C4<> 37D7<> AGP_AD<31> 36C4<> 37D7<> AGP_AD_STBF<0> 36D3< 36D7<> 37D6<> AGP_AD_STBF<1> 36C7<> 36D3< 37D6<> AGP_AD_STBS<0> 36D3< 36D7<> 37D6<> AGP_AD_STBS<1> 36C7<> 36D3< 37D6<>
AGP_ATI_MVREF 37B7< AGP_ATI_VREFG 37B7< AGP_BUSY_L 36C3<> 37D6> AGP_BUSY_L_F 36C2<> AGP_CBE<0> 36D7<> 37B7<>
AGP_CBE<1..0> 36D3< AGP_CBE<1> 36D7<> 37B7<> AGP_CBE<2> 36C7<> 37B7<> AGP_CBE<3..2> 36D3< AGP_CBE<3> 36C7<> 37C7<> AGP_CLK66M_GPU 25B1< 25D8< 37B7<
AGP_CLK66M_GPU_R 25B4<> AGP_CLK66M_NB 25B1< 25D8< 36B4<> AGP_CLK66M_NB_R 25B4<> AGP_DBI_HI 36C7<> 36D3< 37C6<> AGP_DBI_LO 36D3< 36D7<> 37C6<>
AGP_DEVSEL 36B7<> 37B7<> AGP_FRAME 36B7<> 37B7<> AGP_GNT 36B7> 37B7< AGP_INT_L 23B3<> 37B7<> AGP_IRDY 36B7<> 37B7<> AGP_PAR 36B7<> 37B7>
AGP_PVTREF1 36B5<> AGP_PVTREF2 36B5<> AGP_RBF 36B7< 37C6> AGP_REQ 36B7< 37B7<> AGP_SBA_L<0> 36C4< 37C6>
AGP_SBA_L<7..0> 36D3< AGP_SBA_L<1> 36C4< 37C6> AGP_SBA_L<2> 36C4< 37C6> AGP_SBA_L<3> 36C4< 37C6> AGP_SBA_L<4> 36B4< 37C6> AGP_SBA_L<5> 36B4< 37C6>
AGP_SBA_L<6> 36B4< 37C6> AGP_SBA_L<7> 36B4< 37C6<> AGP_SB_STBF 36C7< 36D3< 37C6<> AGP_SB_STBS 36C7< 36D3< 37C6<> AGP_ST<0> 36B7> 37C6<
AGP_ST<1> 36B7> 37C6< AGP_ST<2> 36B7> 37C6< AGP_STOP 36B7<> 37B7<> AGP_SUS_STAT_L_PU 37C6< AGP_TRDY 36B7<> 37B7<> AGP_TYPEDET_L 36B7< 37D5<
AGP_VREF_GC 36B4<> 37D5< 37D7<
AGP_WBF 36B7< 37B7> AIRPORT_CLKRUN_L_PD 6A8> 47B5<>
ALS0_OUT 6B3> 13A7> 17C5< ALS0_OUT_R 17D7<> ALS1_GAIN_BOOST_L 19C7<> ALS1_OP_IN 19D8< ALS1_OUT 13A7> 19D5<
ALS1_OUT_DIV 19C7< ALS1_OUT_R 19D7<> ALS1_PHOTODIODE 19C8<> ALS_GAIN_BOOST 6A3> 13A7> 17D6<> 19C7<> ATI_DVOVMODE 40A3< ATI_RSTB_MSK 37C6<>
AUDIO_EXT_MCLK_SEL 6C2> 23A3<> 61C5<> AUDIO_GPIO_11 6C2> 23A3<> 61C5<> AUDIO_GPIO_12 23A3<> 61B2< AUDIO_HP_DET_L 23B3<> 61C2< AUDIO_HP_MUTE_L 23A3<> 61B2<
AUDIO_LI_DET_L 6C2> 23B3<> 61C4<> AUDIO_LI_OPTICAL_PLUG_L 6C2> 23B3<> 61C4<> AUDIO_LO_DET_L 6C2> 23B3<> 61C4<> AUDIO_LO_MUTE_L 6C2> 23A3<> 61C5<> AUDIO_LO_OPTICAL_PLUG_L 6C2> 23B3<> 61C4<> AUDIO_SPKR_DET_L 23A3<> 61C2<
AUDIO_SPKR_MUTE_L 6C2> 23A3<> 61C8< AUDIO_SPKR_MUTE_L_F 61C4<> 61C7< AVPRESET_L 27B8<> 28B3< BATT_ACIN_L_RC 8B2<> BATT_DET_L 6A5> 7A7<>
BATT_PBUSA_EN_L 8B2<> BATT_PBUSB_EN_L 8C2<> BATT_PBUS_EN_L 8B2<> BIMODE_L 27B8<> 28C7< BKFD_PROT_EN_L 8D8<> BKFD_PROT_EN_L_DIV 8D8<>
BRIGHT_PWM 6A7> 42A2<> BRIGHT_PWM_UF 42A2<> BUSCFG0 27B6<> 28B3< BUSCFG1 27B6<> 28B3< BUSCFG2 27B6<> 28B3<
C1UNDGLOBAL 27B8<> 28C8< C2UNDGLOBAL 27B8<> 28C8< CBUS_ADDR16_R 49B4<> CBUS_ADDR<0> 49B1<> 49B3> CBUS_ADDR<1> 49B1<> 49B3> CBUS_ADDR<2> 49B1<> 49B3>
CBUS_ADDR<3> 49B1<> 49B3> CBUS_ADDR<4> 49B1<> 49B3> CBUS_ADDR<5> 49B1<> 49B3> CBUS_ADDR<6> 49B1<> 49B3> CBUS_ADDR<7> 49B1<> 49B3>
CBUS_ADDR<8> 49B1<> 49B3> CBUS_ADDR<9> 49B1<> 49B3> CBUS_ADDR<10> 49B3> 49C1<> CBUS_ADDR<11> 49B1<> 49B3> CBUS_ADDR<12> 49B1<> 49B3> CBUS_ADDR<13> 49B1<> 49B3>
CBUS_ADDR<14> 49B1<> 49B3> CBUS_ADDR<15> 49B1<> 49B3> CBUS_ADDR<16> 49B1<> 49B3< CBUS_ADDR<17> 49B2<> 49B3> CBUS_ADDR<18> 49B2<> 49B3>
CBUS_ADDR<19> 49B2<> 49B3> CBUS_ADDR<20> 49B2<> 49B3> CBUS_ADDR<21> 49A3> 49B2<> CBUS_ADDR<22> 49A3> 49B2<> CBUS_ADDR<23> 49A3> 49B2<> CBUS_ADDR<24> 49A3> 49B2<>
CBUS_ADDR<25> 49A3> 49B2<> CBUS_BVD1_L 49A2<> 49C3< CBUS_BVD2_L 49B2<> 49C3< CBUS_CE1_L 49C1<> 49C3> CBUS_CE2_L 49B2<> 49B3>
CBUS_DATA<0> 49A1<> 49A3<> CBUS_DATA<1> 49A1<> 49A3<> CBUS_DATA<2> 49A1<> 49A3<> CBUS_DATA<3> 49A3<> 49C1<> CBUS_DATA<4> 49A3<> 49C1<> CBUS_DATA<5> 49A3<> 49C1<>
CBUS_DATA<6> 49A3<> 49C1<> CBUS_DATA<7> 49A3<> 49C1<> CBUS_DATA<8> 49A2<> 49A3<> CBUS_DATA<9> 49A2<> 49A3<> CBUS_DATA<10> 49A2<> 49A3<>
CBUS_DATA<11> 49A3<> 49C2<> CBUS_DATA<12> 49A3<> 49C2<> CBUS_DATA<13> 49A3<> 49C2<> CBUS_DATA<14> 49A3<> 49C2<> CBUS_DATA<15> 49A3<> 49C2<> CBUS_DET_1_L 49C2<> 49C3<
CBUS_DET_2_L 49A2<> 49C3< CBUS_INPACK_L 49B2<> 49B3< CBUS_IORD_L 49B2<> 49C3> CBUS_IOWR_L 49B2<> 49C3> CBUS_MFUNC1_PD 49A6<>
CBUS_MFUNC2_PD 49A6<> CBUS_MFUNC3_PD 49A6<> CBUS_MFUNC4_PD 49A6<> CBUS_MFUNC5_PD 49A6<> CBUS_MFUNC6_PD 49A6<> CBUS_OE_L 49B1<> 49C3>
CBUS_PERR_L_PU 49B6<> 49C7< CBUS_READY 49B1<> 49C3< CBUS_REG_L 49B2<> 49C3> CBUS_RESET_L 49B2<> 49C3> CBUS_SERR_L_PU 49B6> 49B7<
CBUS_SUSPEND_L_PU 49A6< 49B7< CBUS_VCCD0_L 49C4<> CBUS_VCCD1_L 49C4<> CBUS_VPPD0 49C4<> CBUS_VPPD1 49C4<> CBUS_VR_EN_L_PU 49C6< 49C7<
CBUS_VS1 49B2<> 49C3<> CBUS_VS2 49B2<> 49C3<> CBUS_WAIT_L 49B2<> 49B3< CBUS_WE_L 49B1<> 49C3> CBUS_WP_L 49A1<> 49B3<
CHGR_ACIN 8B6< CHGR_ACIN_RC 8C4<> CHGR_CCI 8A6< CHGR_CCI_RC 8A8< CHGR_CCS 8A6< CHGR_CCS_RC 8A8<
CHGR_CCV 8A6< CHGR_CCV_RC 8A7< CHGR_CHARGE_EN_L 8B2<> CHGR_CHARGE_EN_L_DIV 8C2<> CHGR_CSIN 8A6<
CHGR_CSIP 8A6< CHGR_CSSN 8B6< CHGR_CSSP 8B6< CHGR_DAC 8A5<> CHGR_DCIN 8B6<> CHGR_DHI 8B5<>
CHGR_DHIV 8B5<> CHGR_DLO 8A5<> CHGR_DLOV 8B6<> CHGR_DLOV_RC 8B5< CHGR_IMAX 8B6<
CHGR_PBUS_EN_L 8D3<> CHGR_PBUS_EN_L_DIV 8D4<> CHGR_REF 8B5<> 8B7< CHGR_THM 8A5< CHGR_VMAX 8B6< CHKSTOP_L 16A5< 27A5< 27B8<>
CKTERMDIS_L 27B6<> 28A8< CLKLVDS_LN 6B7> 39A5> 39D6> 42A4<> CLKLVDS_LP 6B7> 39A5> 39D6> 42A4<> CLKLVDS_UN 6A7> 39A5> 39D6> 42A4<> CLKLVDS_UP 6A7> 39A5> 39D6> 42A4<>
CLOCK_ERROR_L 25B4> CLOCK_RESET_L 13B3<> 25C6< COMP_DISABLE 42C2<> COMP_ENABLE 42C1<> CORE_ISNS_N 32C6< CORE_ISNS_P 32B6<
CPU1_HTBEN_R 5A7< 25B4> CPUIMON_PHASE1_N 32C7<> CPUIMON_PHASE1_P 32C7<> CPUIMON_PHASE2_N 32C7<> CPUIMON_PHASE2_P 32C7<>
CPUVCORE_BSTM 31C5<> CPUVCORE_BSTM_R 31D5<> CPUVCORE_BSTS 31C6<> CPUVCORE_BSTS_R 31C5<> CPUVCORE_CCI 31C6<> CPUVCORE_CCI_C 31B5<
CPUVCORE_CCV 31C6<>
CPUVCORE_CM_N 31A3> 31A6<> CPUVCORE_CM_N_R 31C7<
CPUVCORE_CM_P 31A3> 31A6< 32C8<> CPUVCORE_CM_P_R 31C7< CPUVCORE_CS_N 31A6<> 31B3> CPUVCORE_CS_N_R 31C7< CPUVCORE_CS_P 31B3< 31B3> 32C8<>
CPUVCORE_CS_P_R 31C7< CPUVCORE_DHM 31C6<> CPUVCORE_DHS 31C6<> CPUVCORE_DLM 31C6<> CPUVCORE_DLS 31C6<> CPUVCORE_FB 31B7<
CPUVCORE_GNDS 31A6< 31B3> CPUVCORE_GNDSENSE 31A1<> CPUVCORE_GNDS_RC 31B7< CPUVCORE_ILIM 31C6<> CPUVCORE_LXM 31C5<>
CPUVCORE_LXS 31C5<> CPUVCORE_OAIN_N 31B7< CPUVCORE_OAIN_P 31B7< CPUVCORE_OFS 31C7< CPUVCORE_OVP 31C7< CPUVCORE_SENSE 31A1<>
CPUVCORE_SHDN_L 14B6< 31C7< CPUVCORE_SKIP_L 31C7< CPUVCORE_SNS 31A6< 31B3> CPUVCORE_SW_TIME 31B5< CPUVCORE_TIME 31C6<>
CPUVCORE_TON 31C7< CPUVCORE_VID<3> 31C7< 31D6< 31D8< CPUVCORE_VID<4> 31C7< 31D6< 31D8< CPUVCORE_VREF 31D7<> CPU_APSYNC 27B6<> CPU_AVDD_EN 14B6< 29D8<>
CPU_AVDD_NOISE 29D7<> CPU_BYPASS_L 13C6<> 27B6<> 28B8< CPU_CHKSTOP_L 26B5<> 27A7< CPU_HRESET_L 13B3<> 27B8<> 28B7< CPU_HTBEN 25B1< 27A8< 27B8<> 28A7<
CPU_HTBEN_R 25B4<> CPU_INT_L 23B8< 27B6<> 28B7< CPU_SENSE_I 13C6<> 32C5< CPU_SENSE_I_R 32C6<> CPU_SENSE_V 13C6<> 32B5< CPU_SENSE_V_R 32B7<>
CPU_SPARE 27B6<> 28B6< CPU_SRESET_L 23B3<> 23D2< 27B8<> 28B7< CPU_TDIODE_NEG 32B4<> CPU_TDIODE_POS 32B4<> CPU_TEMP 13C6<> 32B1<
CPU_TEMP_R 32B2<> CPU_VID<0> 13A5< 13C3<> 31C7< 31D8< CPU_VID<1> 13A5< 13C3<> 31C7< 31D8< CPU_VID<2> 13A5< 13C3<> 31C7< 31D8< CPU_VID<3> 13C3<> 31D7< CPU_VID<4> 6A1> 13C3<> 31D7<
CPU_VID<5> 6A1> 13C3<> D3001_1 16A5< D3002_1 16A4< DAGND 32A6<> 32B2< 32B3< 32C2< 32C3<
32C4< 32C4< 32C6<> 32C6< 32D3<>
DAVDD 32B2< 32C3< 32C3< 32C6< 32D3< DDC_CLK_ISO 42D4<> DI2_L 27B8<> 28C7< DVI_DDC_CLK 42D4<> DVI_DDC_CLK_UF 6C7> 42C5<> 42D3<> DVI_DDC_DATA 42C4<>
DVI_DDC_DATA_UF 6C7> 42C5<> DVI_HPD 42C4<> DVI_HPD_DIV 42C3< DVI_HPD_UF 6C7> 42C3< 42C5<> DVI_TRUN_ON_ILIM 42D2<
DVI_TURN_ON 42D2<> DVI_TURN_ON_BASE 42D2< EI_APCLK_VREF 26B4< EI_CPU1_CLK_N 25D8< EI_CPU1_CLK_N_R 5A7< 25C4> EI_CPU1_CLK_P 25D8<
EI_CPU1_CLK_P_R 5A7< 25C4> EI_CPU1_SYNC 25D8< EI_CPU1_SYNC_R 5A7< 25B4> EI_CPU_CLK_N 25C1< 25D8< 27D8<> EI_CPU_CLK_N_C 25C4<>
EI_CPU_CLK_P 25C1< 25D8< 27D8<> EI_CPU_CLK_P_C 25C4<> EI_CPU_SYNC 25B1< 25D8< 27B5< EI_CPU_SYNC_R 25B4<> EI_CPU_TO_NB_AD<0> 26D5< 27C6<> EI_CPU_TO_NB_AD<0..43> 26D4< 62A4>
EI_CPU_TO_NB_AD<1> 26D5< 27C6<> EI_CPU_TO_NB_AD<2> 26C5< 27C6<> EI_CPU_TO_NB_AD<3> 26C5< 27C6<> EI_CPU_TO_NB_AD<4> 26C5< 27C6<> EI_CPU_TO_NB_AD<5> 26C5< 27C6<>
EI_CPU_TO_NB_AD<6> 26C5< 27C6<> EI_CPU_TO_NB_AD<7> 26C5< 27C6<> EI_CPU_TO_NB_AD<8> 26C5< 27C6<> EI_CPU_TO_NB_AD<9> 26C5< 27C6<> EI_CPU_TO_NB_AD<10> 26C5< 27C6<> EI_CPU_TO_NB_AD<11> 26C5< 27C6<>
EI_CPU_TO_NB_AD<12> 26C5< 27C6<> EI_CPU_TO_NB_AD<13> 26C5< 27C6<> EI_CPU_TO_NB_AD<14> 26C5< 27C6<> EI_CPU_TO_NB_AD<15> 26C5< 27C6<> EI_CPU_TO_NB_AD<16> 26C5< 27C6<>
EI_CPU_TO_NB_AD<17> 26C5< 27C6<> EI_CPU_TO_NB_AD<18> 26C5< 27C6<> EI_CPU_TO_NB_AD<19> 26C5< 27C6<> EI_CPU_TO_NB_AD<20> 26C5< 27C6<> EI_CPU_TO_NB_AD<21> 26C5< 27C6<> EI_CPU_TO_NB_AD<22> 26C5< 27C6<>
EI_CPU_TO_NB_AD<23> 26C5< 27C6<> EI_CPU_TO_NB_AD<24> 26C5< 27C6<> EI_CPU_TO_NB_AD<25> 26C5< 27C6<> EI_CPU_TO_NB_AD<26> 26C5< 27C6<> EI_CPU_TO_NB_AD<27> 26C5< 27C6<>
EI_CPU_TO_NB_AD<28> 26B5< 27C6<> EI_CPU_TO_NB_AD<29> 26B5< 27C6<> EI_CPU_TO_NB_AD<30> 26B5< 27C6<> EI_CPU_TO_NB_AD<31> 26B5< 27C6<> EI_CPU_TO_NB_AD<32> 26B5< 27C6<> EI_CPU_TO_NB_AD<33> 26B5< 27C6<>
EI_CPU_TO_NB_AD<34> 26B5< 27C6<> EI_CPU_TO_NB_AD<35> 26B5< 27C6<> EI_CPU_TO_NB_AD<36> 26B5< 27C6<> EI_CPU_TO_NB_AD<37> 26B5< 27C6<> EI_CPU_TO_NB_AD<38> 26B5< 27C6<>
EI_CPU_TO_NB_AD<39> 26B5< 27C6<> EI_CPU_TO_NB_AD<40> 26B5< 27C6<> EI_CPU_TO_NB_AD<41> 26B5< 27C6<> EI_CPU_TO_NB_AD<42> 26B5< 27C6<> EI_CPU_TO_NB_AD<43> 26B5< 27C6<> EI_CPU_TO_NB_CLK_N 26D4< 26D5< 27C6<> 62A4>
EI_CPU_TO_NB_CLK_P 26D4< 26D5< 27C6<> 62A4> EI_CPU_TO_NB_SR_N<0> 26B5< 26D4< 27B6<> 62A4> EI_CPU_TO_NB_SR_N<1> 26B5< 26D4< 27B6<> 62A4> EI_CPU_TO_NB_SR_P<0> 26B5< 26D4< 27B6<> 62A4> EI_CPU_TO_NB_SR_P<1> 26B5< 26D4< 27B6<> 62A4>
EI_DISABLE 27B6<> 28B3< EI_NB_CLK_N 25C1< 25D8< 26B3< EI_NB_CLK_N_C 25C4<> EI_NB_CLK_P 25C1< 25D8< 26B3< EI_NB_CLK_P_C 25C4<> EI_NB_SYNC 25B1< 25D8< 26B8<
EI_NB_SYNC_R 25B4<> EI_NB_TO_CPU_AD<0> 26D7> 27C8<> EI_NB_TO_CPU_AD<0..43> 26D4< 62A4> EI_NB_TO_CPU_AD<1> 26D7> 27C8<> EI_NB_TO_CPU_AD<2> 26C7> 27C8<>
EI_NB_TO_CPU_AD<3> 26C7> 27C8<> EI_NB_TO_CPU_AD<4> 26C7> 27C8<> EI_NB_TO_CPU_AD<5> 26C7> 27C8<> EI_NB_TO_CPU_AD<6> 26C7> 27C8<> EI_NB_TO_CPU_AD<7> 26C7> 27C8<> EI_NB_TO_CPU_AD<8> 26C7> 27C8<>
EI_NB_TO_CPU_AD<9> 26C7> 27C8<> EI_NB_TO_CPU_AD<10> 26C7> 27C8<> EI_NB_TO_CPU_AD<11> 26C7> 27C8<> EI_NB_TO_CPU_AD<12> 26C7> 27C8<> EI_NB_TO_CPU_AD<13> 26C7> 27C8<>
EI_NB_TO_CPU_AD<14> 26C7> 27C8<> EI_NB_TO_CPU_AD<15> 26C7> 27C8<> EI_NB_TO_CPU_AD<16> 26C7> 27C8<> EI_NB_TO_CPU_AD<17> 26C7> 27C8<> EI_NB_TO_CPU_AD<18> 26C7> 27C8<> EI_NB_TO_CPU_AD<19> 26C7> 27C8<>
EI_NB_TO_CPU_AD<20> 26C7> 27C8<>
EI_NB_TO_CPU_AD<21> 26C7> 27C8<> EI_NB_TO_CPU_AD<22> 26C7> 27C8<>
EI_NB_TO_CPU_AD<23> 26C7> 27C8<> EI_NB_TO_CPU_AD<24> 26C7> 27C8<> EI_NB_TO_CPU_AD<25> 26C7> 27C8<> EI_NB_TO_CPU_AD<26> 26C7> 27C8<> EI_NB_TO_CPU_AD<27> 26C7> 27C8<>
EI_NB_TO_CPU_AD<28> 26B7> 27C8<> EI_NB_TO_CPU_AD<29> 26B7> 27C8<> EI_NB_TO_CPU_AD<30> 26B7> 27C8<> EI_NB_TO_CPU_AD<31> 26B7> 27C8<> EI_NB_TO_CPU_AD<32> 26B7> 27C8<> EI_NB_TO_CPU_AD<33> 26B7> 27C8<>
EI_NB_TO_CPU_AD<34> 26B7> 27C8<> EI_NB_TO_CPU_AD<35> 26B7> 27C8<> EI_NB_TO_CPU_AD<36> 26B7> 27C8<> EI_NB_TO_CPU_AD<37> 26B7> 27C8<> EI_NB_TO_CPU_AD<38> 26B7> 27C8<>
EI_NB_TO_CPU_AD<39> 26B7> 27C8<> EI_NB_TO_CPU_AD<40> 26B7> 27C8<> EI_NB_TO_CPU_AD<41> 26B7> 27C8<> EI_NB_TO_CPU_AD<42> 26B7> 27C8<> EI_NB_TO_CPU_AD<43> 26B7> 27C8<> EI_NB_TO_CPU_CLK_N 26D4< 26D7> 27C8<> 62A4>
EI_NB_TO_CPU_CLK_P 26D4< 26D7> 27C8<> 62A4> EI_NB_TO_CPU_SR_N<0> 26B7> 26D4< 27B8<> 62A4> EI_NB_TO_CPU_SR_N<1> 26B7> 26D4< 27B8<> 62A4> EI_NB_TO_CPU_SR_P<0> 26B7> 26D4< 27B8<> 62A4> EI_NB_TO_CPU_SR_P<1> 26B7> 26D4< 27B8<> 62A4>
EI_QACK_L 26B7> 27B8<> EI_QREQ_L 26B5< 27B6<> 28C6< EI_SE 26A7> 27B8<> 28B6< EI_SYNC_FROM_NB 26A8< 27B5< ENETFW_RESET 12A7< 23B3<> 23C2< ENET_CLK25M_TX 53C6< 53D6> 54C2<
ENET_CLK25M_TX_R 54C3<> 54D6> ENET_CLK125M_GBE_REF 53B6< 53D6> 54C2< ENET_CLK125M_GBE_REF_R 54C3<> 54D6> ENET_CLK125M_GTX 53B3< 53D6> 54C5< ENET_CLK125M_GTX_R 53B4<> 53D6>
ENET_CLK125M_RX 53C6< 53D6> 54C2< ENET_CLK125M_RX_R 54C3<> 54D6> ENET_COL 53B6< 53D6> 54C3<> ENET_CRS 53B6< 53D6> 54C3<> ENET_CTAP<0> 55C5<> ENET_CTAP<1> 55C5<>
ENET_CTAP<2> 55B5<> ENET_CTAP<3> 55B5<> ENET_CTAP_COMMON 55B5< ENET_ENERGYDET 23B3<> 23C2< 54B3> ENET_MDC 53B4> 53D6> 54C6<
ENET_MDI0 54B2< ENET_MDI1 54B2< ENET_MDI2 54B1< ENET_MDI3 54B1< ENET_MDIO 53B4<> 53D6> 54C6<> ENET_MDI_N<0> 54B1<> 54D6> 55C6<>
ENET_MDI_N<1> 54B1<> 54D6> 55C6<> ENET_MDI_N<2> 54B1<> 54D6> 55B6<> ENET_MDI_N<3> 54B1<> 54D6> 55B6<> ENET_MDI_P<0> 54B1<> 54D6> 55C6<> ENET_MDI_P<1> 54B1<> 54D6> 55C6<>
ENET_MDI_P<2> 54B1<> 54D6> 55B6<> ENET_MDI_P<3> 54B1<> 54D6> 55B6<> ENET_RJ45_N<0> 55C5<> 55D6> ENET_RJ45_N<1> 55C5<> 55D6> ENET_RJ45_N<2> 55B5<> 55D6> ENET_RJ45_N<3> 55B5<> 55D6>
ENET_RJ45_P<0> 55C5<> 55D6> ENET_RJ45_P<1> 55C5<> 55D6> ENET_RJ45_P<2> 55B5<> 55D6> ENET_RJ45_P<3> 55B5<> 55D6> ENET_RXD<0> 53C6< 54C3<>
ENET_RXD<7..0> 53D6> ENET_RXD<1> 53C6< 54C3<> ENET_RXD<2> 53B6< 54C3<> ENET_RXD<3> 53B6< 54C3<> ENET_RXD<4> 53B6< 54C3<> ENET_RXD<5> 53B6< 54C3<>
ENET_RXD<6> 53B6< 54C3<> ENET_RXD<7> 53B6< 54C3<> ENET_RX_DV 53B6< 53D6> 54C3<> ENET_RX_ER 53B6< 53D6> 54C3<> ENET_TXD<0> 53C3< 54C5<
ENET_TXD<7..0> 53D6> ENET_TXD<1> 53C3< 54C5< ENET_TXD<2> 53C3< 54C5< ENET_TXD<3> 53C3< 54C5< ENET_TXD<4> 53B3< 54C5< ENET_TXD<5> 53B3< 54C5<
ENET_TXD<6> 53B3< 54C5< ENET_TXD<7> 53B3< 54C5< ENET_TXD_R<0> 53C4<> ENET_TXD_R<1> 53C4<> ENET_TXD_R<2> 53B4<>
ENET_TXD_R<3> 53B4<> ENET_TXD_R<4> 53B4<> ENET_TXD_R<5> 53B4<> ENET_TXD_R<6> 53B4<> ENET_TXD_R<7> 53B4<> ENET_TX_EN 53B3< 53D6> 54C5<
ENET_TX_EN_R 53B4<> ENET_TX_ER 53B3< 53D6> 54C5< ENET_TX_ER_R 53B4<> EXT_LED_L 5A8< EXT_TMDS_CLK_CMF 41B2<
EXT_TMDS_D0_CMF 41B2< EXT_TMDS_D1_CMF 41B2< EXT_TMDS_D2_CMF 41A2< FAN_PWM6 13A4> FAN_PWM7 13A4> FAN_PWM8 13A8< 13C3<>
FAN_RPM0 6C3> 13C3<> 15C2<> FAN_RPM1 6B3> 13C3<> 15B2<> FAN_RPM2 5A8< 13C3<> FAN_RPM3 13A8< 13C6<> FAN_RPM4 13A8< 13C6<>
FAN_RPM5 13A8< 13C6<> FAN_TACH0 6C3> 13C6<> 15C2<> FAN_TACH1 6B3> 13C6<> 15B2<> FAN_TACH2 5A8< 13C6<> FAN_TACH3 5A8< 13A7< 13C6<> FAN_TACH4 5A8< 13A7< 13C6<>
FAN_TACH5 5A8< 13A7< 13B6<> FAN_TACH6 13A4> FAN_TACH7 13A4> FAN_TACH8 13A4> FP_PWR_EN 39B6<> 42A6< 42B3<>
FP_PWR_EN_L 42B3<> FWEEPROM_WP_PD 57A3<> FWLM2594_VOUT 12D3<> FWPWR_ACIN 12C7<> FWPWR_EN 12C7<> FWPWR_EN_L 12C6<>
FWPWR_EN_L_DIV 12C7<> FWPWR_PWRON 12C8<> 14D4< FWPWR_RUN 12C7<> FW_CLK98M_LCLK 56B3< 56D6> 57C5< FW_CLK98M_LCLK_R 56B4<> 56D6>
FW_CLK98M_PCLK 56B5<> 56D6> 57C2< FW_CLK98M_PCLK_R 57C3<> 57D6> FW_CPS 57C5<> FW_CTL<0> 56B4<> 57B7< FW_CTL<1..0> 56D6> FW_CTL<1> 56B4<> 57B7<
FW_CTL_R<0> 57B5<> FW_CTL_R<1> 57B5<> FW_DATA<0> 56C4<> 57C7< FW_DATA<7..0> 56D6> FW_DATA<1> 56C4<> 57C7<
FW_DATA<2> 56C4<> 57C7< FW_DATA<3> 56C4<> 57B7< FW_DATA<4> 56B4<> 57B7< FW_DATA<5> 56B4<> 57B7< FW_DATA<6> 56B4<> 57B7< FW_DATA<7> 56B4<> 57B7<
FW_DATA_R<0> 57B5<> FW_DATA_R<1> 57B5<> FW_DATA_R<2> 57B5<> FW_DATA_R<3> 57B5<> FW_DATA_R<4> 57B5<>
FW_DATA_R<5> 57B5<> FW_DATA_R<6> 57B5<> FW_DATA_R<7> 57B5<> FW_LINKON 56B4< 57C3> FW_LOWPWR 23B3<> 23C2< 57B5< FW_LPS 56B4> 56D6> 57B5<
FW_LREQ 56B4> 56D6> 57B5<
FW_PINT 56B5< 56D6> 57C3> FW_PORT1_AREF 6D3> 58C2<>
FW_PORT1_TPA_N 58C5> 58C5<> FW_PORT1_TPA_N_FL 6D3> 58C2<> 58D6> FW_PORT1_TPA_P 58C5> 58C5<> FW_PORT1_TPA_P_FL 6D3> 58C2<> 58D6> FW_PORT1_TPB_N 58C5> 58D5<>
FW_PORT1_TPB_N_FL 6D3> 58D2<> 58D6> FW_PORT1_TPB_P 58C5> 58D5<> FW_PORT1_TPB_P_FL 6D3> 58D2<> 58D6> FW_PORT2_TPA_N 58A5<> 58C5> FW_PORT2_TPA_N_FL 6C3> 58A3<> 58D6> FW_PORT2_TPA_P 58B5<> 58C5>
FW_PORT2_TPA_P_FL 6C3> 58A3<> 58D6> FW_PORT2_TPB_N 58A5<> 58C5> FW_PORT2_TPB_N_FL 6C3> 58A3<> 58D6> FW_PORT2_TPB_P 58A5<> 58C5> FW_PORT2_TPB_P_FL 6C3> 58A3<> 58D6>
FW_TPA_C<0> 58C7< FW_TPA_C<1> 58C6< FW_TPA_N<0> 57B3<> 57D6> 58C7< FW_TPA_N<1> 57B3<> 57D6> 58C7< FW_TPA_N<2> 57B3<> 57D6> 58B7< FW_TPA_P<0> 57B3<> 57D6> 58C7<
FW_TPA_P<1> 57B3<> 57D6> 58C7< FW_TPA_P<2> 57B3<> 57D6> 58B7< FW_TPB2_PD 58B6< FW_TPBIAS<0> 57B3<> 58D7< FW_TPBIAS<1> 57B3<> 58D7<
FW_TPBIAS<2> 57B3<> 58B7< FW_TPB_N<0> 57B3<> 57D6> 58C7< FW_TPB_N<1> 57B3<> 57D6> 58C7< FW_TPB_N<2> 57B3<> 57D6> 58B7< FW_TPB_P<0> 57B3<> 57D6> 58C7< FW_TPB_P<1> 57B3<> 57D6> 58C7<
FW_TPB_P<2> 57B3<> 57D6> 58B7< GND_2V5_NBVCORE 11B5<> GND_5V3V 10B3<> GND_AUDIO 6C2> 61B5<> GND_BATT 6A5> 7B6<>
GND_CHASSIS_DVI 5A4< 17C2<> GND_CHASSIS_INVERTER 5A4< 17B4<> GND_CHASSIS_IO 5A4< 6C7> 17B2<> GND_CHASSIS_LVDS 5A4< 6A7> GND_CHGR 8A8<> GND_CPUVCORE 31B5<>
GND_CPU_AVDD 29B5<> GND_FW_PORT1_VG 6D3> 58C2<> GND_FW_PORT2_VG 6C3> 58A3<> GND_GPUVCORE 38B7<> 38C6< 38D5< GND_NEC_AVSS_R 59A3<
GND_SMU_AVSS 13A4<> 13D4< 17C5< 17D5< 19C5<32B1< 32B6< 32C5<
GND_SPARE_GND 29A3< 29B3<> GND_Z_OUT 29B3< 29D2<> GND_Z_SENSE 29B3< 29D2<> GPOVCORE_LX_RC 38C3<
GPUL_DBG 27B6<> 28A8< GPUPVDD_EN 14A6< 40B8<> 40D8<> GPUPVDD_NOISE 40D7<> GPUSS_CLK27M 37B2< 37D1< GPUSS_S0 37B2<
GPUSS_S1 37B2< GPUTPVDD_NOISE 40B7<> GPUVCORE_BST 38C5<> GPUVCORE_BST_RC 38D5<> GPUVCORE_CNTL_L 38C7<> 39A7<> GPUVCORE_CSN 38C7<
GPUVCORE_CSP 38C7< GPUVCORE_DH 38C5<> GPUVCORE_DL 38C5<> GPUVCORE_FB 38C5<> GPUVCORE_FBLANK 38C7<>
GPUVCORE_ILIM 38C5<> GPUVCORE_LSAT 38C5<> GPUVCORE_LX 38C5<> GPUVCORE_OD 38C7<> GPUVCORE_OVP_UVP 38C7<> GPUVCORE_PGOOD 14A8< 38C7<>
GPUVCORE_REF 38C5<> GPUVCORE_REFIN 38C5< GPUVCORE_SHDN_L 14B6< 38B6<> GPUVCORE_SKIP_L 38C7< GPUVCORE_TON 38C7<>
GPUVDD15_EN 14A6< 39D4<> GPU_AGP_FBSKEW<0> 39B2< 39B7<> GPU_AGP_FBSKEW<1> 39B2< 39B7<> GPU_AGP_TEST 37D6< GPU_AUXWIN 39B6<> GPU_B 39C6<> 42D8<
GPU_BUS_CFG<0> 39B2< 39B7<> GPU_BUS_CFG<1> 39B2< 39B7<> GPU_BUS_CFG<2> 39B2< 39B7<> GPU_C 39B6<> 42A8< GPU_CLK27M_DIV 37C1< 39A7<
GPU_CLK27M_OSC 37D2< GPU_COMP 39B6<> 42A8< GPU_DVI_DDC_CLK 39B5<> 42D3<> GPU_DVI_DDC_DATA 39B5<> 42C3<> GPU_DVOD<0> 39C7<> 41B8<> GPU_DVOD<0..19> 39D6>
GPU_DVOD<1> 39C7<> 41B8<> GPU_DVOD<2> 39C7<> 41B8<> GPU_DVOD<3> 39C7<> 41B8<> GPU_DVOD<4> 39C7<> 41B8<> GPU_DVOD<5> 39C7<> 41B8<>
GPU_DVOD<6> 39C7<> 41B8<> GPU_DVOD<7> 39C7<> 41B8<> GPU_DVOD<8> 39C7<> 41B8<> GPU_DVOD<9> 39C7<> 41B8<> GPU_DVOD<10> 39C7<> 41B8<> GPU_DVOD<11> 39C7<> 41B8<>
GPU_DVOD<12> 39C7<> 41B8<> GPU_DVOD<13> 39C7<> 41B8<> GPU_DVOD<14> 39C7<> 41B8<> GPU_DVOD<15> 39C7<> 41B8<> GPU_DVOD<16> 39B7<> 41B8<>
GPU_DVOD<17> 39B7<> 41A8<> GPU_DVOD<18> 39B7<> 41A8<> GPU_DVOD<19> 39B7<> 41A8<> GPU_DVOD<20> 39B7<> 39D6> 41A8<> GPU_DVOD<21> 39B7<> 41A8<> GPU_DVOD<21..23> 39D6>
GPU_DVOD<22> 39B7<> 41A8<> GPU_DVOD<23> 39B7<> 41A8<> GPU_DVO_CLKP 39B7<> 39C6> 41A8<> GPU_DVO_DE 39B7<> 39C6> 41A8<> GPU_DVO_HSYNC 39B7<> 39D6> 41A8<>
GPU_DVO_VSYNC 39B7<> 39C6> 41A8<> GPU_G 39C6<> 42D8< GPU_GPIO8_PD 39B7<> GPU_HPD 39B6< 42C3<> GPU_HSYNC 39C6<> 42C8< GPU_MEMTEST 37A6<>
GPU_MEMVMODE0 37A7< GPU_MEMVMODE1 37A7< GPU_OSC_OE 37D2< GPU_R 39C6<> 42D8< GPU_R2SET 39C6<>
GPU_RESET_L_R 37B7< GPU_RSET 39C6<> GPU_SSCLK_IN 37B1< 39A7<> GPU_SSCLK_UF 37B1<> GPU_TESTEN 39A7< GPU_THMDIODE_N 15A8< 37A6<>
GPU_THMDIODE_P 15A8< 37A6<> GPU_TMDS_CLKN 39A7> 41D5< 62B4> GPU_TMDS_CLKN_R 41D2< 41D2< 41D4< 62B4> GPU_TMDS_CLKP 39A7> 41D5< 62B4> GPU_TMDS_CLKP_R 41D2< 41D3< 41D4< 62B4>
GPU_TMDS_DN<0> 39A7> 41D5< 62B4> GPU_TMDS_DN<1> 39A7> 41C5< 62B4> GPU_TMDS_DN<2> 39A7> 41C5< 62B4> GPU_TMDS_DN_R<0> 41D2< 41D2< 41D4< 62B4> GPU_TMDS_DN_R<1> 41C2< 41C2< 41C4< 62B4> GPU_TMDS_DN_R<2> 41C2< 41C2< 41C4< 62B4>
GPU_TMDS_DP<0> 39A7> 41C5< 62B4> GPU_TMDS_DP<1> 39A7> 41C5< 62B4> GPU_TMDS_DP<2> 39A7> 41C5< 62B4> GPU_TMDS_DP_R<0> 41C4< 41D2< 41D4< 62B4> GPU_TMDS_DP_R<1> 41C2< 41C4< 41C4< 62B4>
GPU_TMDS_DP_R<2> 41C2< 41C4< 41C4< 62B4> GPU_TV_GND1 42B8<> GPU_TV_GND2 42A8<> GPU_VSYNC 39C6<> 42C8< GPU_X1CLK_SKEW<0> 39B2< 39B7<> GPU_X1CLK_SKEW<1> 39B2< 39B7<>
GPU_Y 39C6<> 42A8<
HPD_4V_REF 42C3< HPD_BASE 42C1<
HPD_ON 42C2<> HPD_ON_RC 42C2< HPD_PWR_SNS_EN 39A7<> 42C3<> HPD_PWR_SW 42C2<> HT_CLK66M_NB 25C1< 25D8< 43D6<
HT_CLK66M_NB_R 25C4<> HT_CLK66M_SB 25B1< 25D8< 44B6< HT_CLK66M_SB_C 44B5< 44D6> HT_CLK66M_SB_R 25B4<> HT_LDTREQ_L 43B3< 43C8<> 44B4<> HT_LDTSTOP_L 43C3< 43C8<> 44B5<>
HT_NB_PVTREF0 43C5<> HT_NB_PVTREF1 43C5<> HT_NB_TO_SB_CAD_N<0> 43D3< 43D4> 44C5< HT_NB_TO_SB_CAD_N<1> 43D3< 43D4> 44C5< HT_NB_TO_SB_CAD_N<2> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_N<3> 43C4> 43D3< 44B5< HT_NB_TO_SB_CAD_N<4> 43C4> 43D3< 44B5< HT_NB_TO_SB_CAD_N<5> 43C4> 43D3< 44B5< HT_NB_TO_SB_CAD_N<6> 43C4> 43D3< 44B5< HT_NB_TO_SB_CAD_N<7> 43C3< 43C4> 44B5< HT_NB_TO_SB_CAD_P<0> 43D3< 43D4> 44C5<
HT_NB_TO_SB_CAD_P<1> 43D3< 43D4> 44C5< HT_NB_TO_SB_CAD_P<2> 43C4> 43D3< 44C5< HT_NB_TO_SB_CAD_P<3> 43C4> 43D3< 44B5< HT_NB_TO_SB_CAD_P<4> 43C4> 43D3< 44B5< HT_NB_TO_SB_CAD_P<5> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_P<6> 43C4> 43D3< 44B5< HT_NB_TO_SB_CAD_P<7> 43C4> 43D3< 44B5< HT_NB_TO_SB_CLK_N 43D3< 43D4> 44C5< HT_NB_TO_SB_CLK_P 43D3< 43D4> 44C5< HT_NB_TO_SB_CTL_N 43C4> 43D3< 44B5< HT_NB_TO_SB_CTL_P 43C4> 43D3< 44B5<
HT_PWROK 43C3< 43C8<> 44B5< HT_RESET_L 43C3< 43C8<> 44B5<> HT_SB_TO_NB_CAD_N<0> 43C3< 43D6< 44C4> HT_SB_TO_NB_CAD_N<1> 43C3< 43D6< 44C4> HT_SB_TO_NB_CAD_N<2> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_N<3> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_N<4> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_N<5> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_N<6> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_N<7> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_P<0> 43C3< 43D6< 44C4>
HT_SB_TO_NB_CAD_P<1> 43C3< 43D6< 44C4> HT_SB_TO_NB_CAD_P<2> 43C3< 43C6< 44C4> HT_SB_TO_NB_CAD_P<3> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_P<4> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_P<5> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_P<6> 43C3< 43C6< 44B4> HT_SB_TO_NB_CAD_P<7> 43C3< 43C6< 44B4> HT_SB_TO_NB_CLK_N 43C3< 43D6< 44C4> HT_SB_TO_NB_CLK_P 43C3< 43D6< 44C4> HT_SB_TO_NB_CTL_N 43C3< 43C6< 44B4> HT_SB_TO_NB_CTL_P 43C3< 43C6< 44B4>
I2CGO 27B6<> 28A7< I2C_0V546_REF 18C4< I2C_AUDIO_SCL 18A1> 61B4<> I2C_AUDIO_SDA 18A1> 61C4<> I2C_BATT_SCL 7B5< 18A3>
I2C_BATT_SCL_F 7A7<> I2C_BATT_SDA 7A5< 18A3> I2C_BATT_SDA_F 7A7<> I2C_CHGR_SCL 8B6< 18A3> I2C_CHGR_SDA 8B6<> 18A3> I2C_CLOCK_SCL 18B5> 25C6<>
I2C_CLOCK_SDA 18B5> 25C6<> I2C_CPU_A_SCL 18C3< 18D6> 27B6<> I2C_CPU_A_SDA 18C3< 18D6> 27B6<> I2C_CPU_A_SDA_TO_SMU 18C6< 18D6> I2C_DIMM_SCL 18C1> 35A3<> 35A7<>
I2C_DIMM_SDA 18C1> 35A3<> 35A7<> I2C_DS1775_SCL 17A8<> 18A5> I2C_DS1775_SDA 17A8<> 18A5> I2C_MAX1989_SCL 15D3< 18A5> I2C_MAX1989_SDA 15D3<> 18A5> I2C_MODEM_SCL 18B1> 60B3<>
I2C_MODEM_SDA 18B1> 60B3<> I2C_NB_A_SCL 18D3> 22D4<> I2C_NB_A_SDA 18D3> 22C4<> I2C_NB_B_SCL 18D2< 18D6> 22C4<> I2C_NB_B_SDA 18D2< 18D6> 22C4<>
I2C_NB_C_SCL 18C2< 18D6> 22C4<> I2C_NB_C_SDA 18C2< 18D6> 22C4<> I2C_RTC_SCL 13D2<> 18B3> I2C_RTC_SDA 13D2<> 18B3> I2C_SB_SCL 6A2> 18B2< 18C6> 23B5<> I2C_SB_SDA 6A2> 18B2< 18C6> 23B5<>
I2C_SMU_A_SCL_IN 13B6<> 18D6< 18D6> I2C_SMU_A_SCL_OUT 13B6<> 18B8<> 18D6> I2C_SMU_A_SCL_OUT_L 18C7<> 18D6< I2C_SMU_A_SDA_IN 13B6<> 18D6> 18D6< I2C_SMU_A_SDA_OUT 13B6<> 18B8<> 18D6>
I2C_SMU_A_SDA_OUT_L 18B7<> 18D6< I2C_SMU_B_SCL 6A4> 13C3<> 18B7< 18D6> I2C_SMU_B_SDA 6A4> 13C3<> 18B7< 18D6> I2C_SMU_CPU_SCL_IN 13A5< 13C3<> 18C7< 18D6> I2C_SMU_CPU_SCL_OUT 13B3<> 18C7< 18D6> I2C_SMU_CPU_SDA_IN 13A5< 13C3<> 18C7< 18D6>
I2C_SMU_CPU_SDA_OUT 13C3<> 18C7< 18D6> I2C_SMU_D_SCL 5A8< 13B6<> I2C_SMU_D_SDA 13B6<> I2C_SMU_E_SCL 6A5> 13C6<> 18B5< I2C_SMU_E_SDA 6A5> 13C6<> 18B5<
I2C_VESTA_SCL 57B3<> I2C_VESTA_SDA 57B3<> I2S0_BITCLK 23C6< 23D6> 61B8< I2S0_BITCLK_F 6D2> 61B7< 61C5<> I2S0_BITCLK_R 23C5<> I2S0_DEV_TO_SB_DTI 23C6< 23D6> 61C8<
I2S0_DEV_TO_SB_DTI_F 6D2> 61C5<> 61C7< I2S0_MCLK 23C6< 23D6> 61C8< I2S0_MCLK_F 6D2> 61C5<> 61C7< I2S0_MCLK_R 23C5<> I2S0_RESET_L 23A3<> 61B8<
I2S0_RESET_L_F 6C2> 61B7< 61C4<> I2S0_SB_TO_DEV_DTO 23C6< 23D6> 61C8< I2S0_SB_TO_DEV_DTO_F 6D2> 61C5<> 61C7< I2S0_SB_TO_DEV_DTO_R 23C5<> I2S0_SYNC 23C6< 23D6> 61C8< I2S0_SYNC_F 6D2> 61C5<> 61C7<
I2S0_SYNC_R 23C5<> I2S1_BITCLK 6B2> 16C4<> 23B6< 23D6> 60B5<> I2S1_BITCLK_R 23B5<> I2S1_DEV_TO_SB_DTI 6B2> 16C4<> 23C6< 23D6> 60B5<> I2S1_MCLK 6B2> 16C3<> 23B6< 23D6> 60B3<>
I2S1_MCLK_R 23B5<> I2S1_RESET_L 6B2> 16C3<> 23B6<> 23C2< 60B3<> I2S1_SB_TO_DEV_DTO 6B2> 16C3<> 23B6< 23D6> 60C3<> I2S1_SB_TO_DEV_DTO_R 23B5<> I2S1_SYNC 6B2> 16C4<> 23B6< 23D6> 60C5<> I2S1_SYNC_R 23B5<>
I2S2_BITCLK 23B6< 23D6> 61B8< I2S2_BITCLK_F 6C2> 61B5<> 61B7< I2S2_BITCLK_R 23B5<> I2S2_DEV_TO_SB_DTI 23B6< 23D6> 61B8< I2S2_DEV_TO_SB_DTI_F 6D2> 61B5<> 61B7<
I2S2_MCLK 23B6< 23D6> I2S2_MCLK_R 23B5<> I2S2_RESET_L 23B6<> 61A8< I2S2_RESET_L_F 6C2> 61A7< 61C4<> I2S2_SB_TO_DEV_DTO 23B6< 23D6> I2S2_SB_TO_DEV_DTO_R 23B5<>
I2S2_SYNC 23B6< 23D6> 61B8< I2S2_SYNC_F 6C2> 61B5<> 61B7< I2S2_SYNC_R 23B5<> INT_TMDS_CLK_CMF 41D2< INT_TMDS_D0_CMF 41D2<
INT_TMDS_D1_CMF 41C2< INT_TMDS_D2_CMF 41C2< INV_ON_PWM 39B6<> 42A3< ISNS0 32C6< ISNS1 32C6< JTAGMODE_SPARE2 27B6<> 28D6<
JTAG_CPU_TCK 6B1> 18C5< 27B6<> 28D4< JTAG_CPU_TDI 6B1> 18C5< 27B6<> 28D4< JTAG_CPU_TDO 6B1> 18C5< 27B6<> 28C7< JTAG_CPU_TMS 6C1> 18C5< 27B6<> 28C4< JTAG_CPU_TRST_L 6B1> 27B6<> 28C7<
JTAG_NB_TCK 6C1> 22D8<> JTAG_NB_TDI 6D1> 22D8<> JTAG_NB_TDO 6D1> 22D8<> JTAG_NB_TMS 6D1> 22C8<> JTAG_NB_TRST_L 6C1> 22C8<> JTAG_SB_TCK 6C1> 18A7< 23A5<
JTAG_SB_TDI 6C1> 18A7< 23B5<
JTAG_SB_TDO 6C1> 23A5> JTAG_SB_TMS 6C1> 18A7< 23A5<
JTAG_SB_TRST_L 6C1> 18A7< 23A5< JTAG_SEL 28D4< JTAG_VESTA_TCK 6C1> 12A6< JTAG_VESTA_TDI 6C1> 12A6< JTAG_VESTA_TDO 6C1> 12A6>
JTAG_VESTA_TMS 6C1> 12A6< JTAG_VESTA_TRST_L 6C1> 12A6< KBDLED_ANODE 6A4> 17A8<> 19A5<> KBDLED_COMP 19A7< KBDLED_LX 19B6<> KBDLED_RETURN 6A4> 17A8<> 19A5<
KPGND2 29A3<> KPVDD2 29A3<> LCD_DIGON_L 42A6< LCD_PWREN_L 42A5<> LSSDMODE 27B8<> 28D6<
LSSDSCANENABLE 27B8<> 28D6< LSSDSTOPC2ENABLE 27B8<> 28C6< LSSDSTOPC2STARENABLE 27B8<> 28C6< LSSDSTOPENABLE 27B8<> 28C6< LTUSB_OVERCURRENT 5C7> 17D6<> LTUSB_PWREN 5C7> 17D6<>
LVDS_DDC_CLK 6A7> 39B5<> 42B5<> LVDS_DDC_DATA 6A7> 39B5<> 42B5<> LVDS_L0N 6B7> 39A5> 39D6> 42B4<> LVDS_L0P 6B7> 39A5> 39D6> 42B4<> LVDS_L1N 6B7> 39A5> 39D6> 42B4<>
LVDS_L1P 6B7> 39A5> 39D6> 42B4<> LVDS_L2N 6B7> 39A5> 39D6> 42B4<> LVDS_L2P 6B7> 39A5> 39D6> 42B4<> LVDS_U0N 6B7> 39B5> 39D6> 42A4<> LVDS_U0P 6B7> 39B5> 39D6> 42A4<> LVDS_U1N 6B7> 39A5> 39D6> 42A4<>
LVDS_U1P 6B7> 39A5> 39D6> 42A4<> LVDS_U2N 6A7> 39A5> 39D6> 42A4<> LVDS_U2P 6A7> 39A5> 39D6> 42A4<> MAX1989_D1_N 15B5< 15D5< 15D6> MAX1989_D1_P 15B5< 15D5< 15D6>
MAX1989_D2_N 15B5< 15D5< 15D6> MAX1989_D2_P 15B5< 15D5< 15D6> MAX1989_D3_N 15A5< 15C5< 15D6> MAX1989_D3_P 15A5< 15D5< 15D6> MAX1989_D4_N 15A7< 15C5< 15D6> MAX1989_D4_P 15A7< 15C5< 15D6>
MCP_L 27A5< 27B8<> MODEM_RING2SYS_L 6A2> 23B5<> 23D2< 60B5<> NBVCORE_BOOST_ESR 11C6<> NBVCORE_BST_HI 11C5<> NBVCORE_BST_LO 11C5<>
NBVCORE_FB 11C5<> NBVCORE_FB_RC 11B6< NBVCORE_HI_GATE 11C5<> NBVCORE_INV2 11C5< NBVCORE_INV_RC 11C7< NBVCORE_ITRIP 11C5<
NBVCORE_LO_GATE 11C5<> NBVCORE_SS 11C5<> NBVCORE_SW 11C6<> NB_AGP_BUSY_L 36B4< 36C1<> NB_AGP_GCDET_L 36B7< 37C6<>
NB_APSYNC 26B7<> NB_INT_L 22C4<> 23B8< NB_INT_L_R 23B7< NB_MC_PD 22C6<> NB_PMR_OBSV 5A8< 22C4<> NB_PU_RESET 22B7<>
NB_PU_RST_L 22B6<> 22D4<> NB_RESET 22B5<> NB_RE_PD 22C6<> NB_RI_PU 22C6<> NB_RST_L 22B3<> 22D4<>
NB_STOP_AGP_L 36B3< 36B4> NB_SUSPENDACK_L 13B3<> 22B1< NB_SUSPEND_ACK 22B2<> NB_SUSPEND_ACK_L 22B3<> 22D4<> NB_SUSPEND_REQ_L 22D1<> 22D4<> NB_TEST_PD 22C6<>
NB_THMI 5A8< 22C4<> NB_THMO 5A8< 22C4<> NB_TO_SB_INT 23A3<> 23B7< NB_VSP_CLK_VREF 22D6< NC_FW_TPA_N2 58B6>
NC_FW_TPA_P2 58B6> NC_FW_TPBIAS2 58B6> NEC_CLK30M_XT1 59A5< 59D6> NEC_CLK30M_XT2 59A5< 59D6> NEC_CLK30M_XT2_R 59A5<> 59D6> NEC_CRUN_L_PD 48A5<>
NEC_INTA_L 48B5<> NEC_INTB_L 48B5<> NEC_INTC_L 48B5<> NEC_LEGC_PD 48A5< NEC_NC1_PU 59A5<>
NEC_NC2_PU 59A5<> NEC_PERR_L_PU 48B5<> NEC_PME_L 48A5<> NEC_RREF_PD 59A3<> NEC_SERR_L_PU 48B5<> NEC_VBBRST_L 48A5<
NEC_VCCRST_L 48A5< PATA_CS0_L 6B5> 51B1< 51D6> 52B3<> PATA_CS0_L_R 51B2< 51B4<> PATA_CS1_L 6B5> 51B1< 51D6> 52B2<> PATA_CS1_L_R 51B2< 51B4<>
PATA_DA<0> 6B5> 51B1< 52B3<> PATA_DA<3..0> 51D6> PATA_DA<1> 6B5> 51B1< 52B3<> PATA_DA<2> 6B5> 51B1< 52B2<> PATA_DA_R<0> 51B2< 51C4<> PATA_DA_R<1> 51B2< 51C4<>
PATA_DA_R<2> 51B2< 51B4<> PATA_DD<0> 6C5> 51D1< 52B3<> PATA_DD<6..0> 51D6> PATA_DD<1> 6C5> 51D1< 52B3<> PATA_DD<2> 6C5> 51D1< 52B3<>
PATA_DD<3> 6C5> 51D1< 52B3<> PATA_DD<4> 6C5> 51D1< 52C3<> PATA_DD<5> 6C5> 51D1< 52C3<> PATA_DD<6> 6C5> 51C1< 52C3<> PATA_DD<7> 6C5> 51C1< 51D6> 52C3<> PATA_DD<8> 6C5> 51C1< 52C2<>
PATA_DD<15..8> 51D6> PATA_DD<9> 6C5> 51C1< 52C2<> PATA_DD<10> 6C5> 51C1< 52C2<> PATA_DD<11> 6C5> 51C1< 52C2<> PATA_DD<12> 6C5> 51C1< 52B2<>
PATA_DD<13> 6B5> 51C1< 52B2<> PATA_DD<14> 6B5> 51B1< 52B2<> PATA_DD<15> 6B5> 51B1< 52B2<> PATA_DD_R<0> 51C4<> 51D2< PATA_DD_R<1> 51C4<> 51D2< PATA_DD_R<2> 51C4<> 51D2<
PATA_DD_R<3> 51C4<> 51D2< PATA_DD_R<4> 51C4<> 51D2< PATA_DD_R<5> 51C4<> 51D2< PATA_DD_R<6> 51C2< 51C4<> PATA_DD_R<7> 51C2< 51C4<>
PATA_DD_R<8> 51C2< 51C4<> PATA_DD_R<9> 51C2< 51C4<> PATA_DD_R<10> 51C2< 51C4<> PATA_DD_R<11> 51C2< 51C4<> PATA_DD_R<12> 51C2< 51C4<> PATA_DD_R<13> 51C2< 51C4<>
PATA_DD_R<14> 51B2< 51C4<> PATA_DD_R<15> 51B2< 51C4<> PATA_DMACK_L 6B5> 51A1< 51D6> 52B3<> PATA_DMACK_L_R 51A2< 51B4<> PATA_DMARQ 51B5<> 51D6> 52B4<
PATA_DMARQ_R 6B5> 52B3<> PATA_DSTROBE 51B5<> 51D6> 52B1< PATA_DSTROBE_R 6B5> 52B2<> PATA_HSTROBE 6B5> 51B1< 51D6> 52B3<> PATA_HSTROBE_R 51B2< 51B4<> PATA_INTRQ 51B5<> 51D6> 52B1<
PATA_INTRQ_R 6A5> 52B2<> PATA_RESET_L 6B5> 51A1< 51D6> 52C3<> PATA_RESET_L_R 51A2< 51B4<> PATA_STOP 6A5> 51B1< 51D6> 52B2<> PATA_STOP_R 51B2< 51B4<>
PCI_AD<0> 6D8> 46C5< 47B4<> 48D5<> 49C6<>62D1>
PCI_AD<16..0> 45D6> PCI_AD<1> 6D8> 46C5< 47B5<> 48C5<> 49C6<>
62D1> PCI_AD<2> 6D8> 46C5< 47B4<> 48C5<> 49C6<>
62D1>
PCI_AD<3> 6D8> 46C5< 47B5<> 48C5<> 49C6<>62D1>
PCI_AD<4> 6D8> 46C5< 47B4<> 48C5<> 49C6<>62D1>
PCI_AD<5> 6D8> 46C5< 47B5<> 48C5<> 49C6<>62D1>
PCI_AD<6> 6D8> 46C5< 47B4<> 48C5<> 49C6<>
62D1> PCI_AD<7> 6D8> 46C5< 47B5<> 48C5<> 49C6<>
62D1> PCI_AD<8> 6D8> 46B5< 47B5<> 48C5<> 49C6<>
62D1> PCI_AD<9> 6D8> 46B5< 47B4<> 48C5<> 49C6<>
62D1> PCI_AD<10> 6D8> 46B5< 47B5<> 48C5<> 49C6<>
62D1> PCI_AD<11> 6C8> 46B5< 47B4<> 48C5<> 49C6<>
62C1>
PCI_AD<12> 6C8> 46B5< 47B5<> 48C5<> 49C6<>62C1>
PCI_AD<13> 6C8> 46B5< 47B4<> 48C5<> 49C6<>62C1>
PCI_AD<14> 6C8> 46B5< 47B5<> 48C5<> 49C6<>62C1>
PCI_AD<15> 6C8> 46B5< 47B4<> 48C5<> 49C6<>62C1>
PCI_AD<16> 6C8> 46B5< 47C4<> 48C5<> 49C6<>62C1>
PCI_AD<17> 6C8> 45D6> 46B5< 47C3< 47C5<>
48C5<> 49B6<> 62C1> PCI_AD<18> 6C8> 46B5< 47C4<> 48C5<> 49B6<>
62C1> PCI_AD<19..18> 45D6> PCI_AD<19> 6C8> 46B5< 47C5<> 48C5<> 49B6<>
62C1>
PCI_AD<20> 6C8> 45D6> 46B5< 47C4<> 48C5<>49B6<> 62C1>
PCI_AD<21> 6C8> 45D6> 47C5<> 48C5<> 49B7<>62C1>
PCI_AD<22> 6C8> 45D6> 47C4<> 48C5<> 49B6<>
62C1> PCI_AD<23> 6C8> 45D6> 47C5<> 48C5<> 49B6<>
62C1> PCI_AD<24> 6B8> 46C3<> 47C4<> 48C5<> 49B6<>
62C1> PCI_AD<26..24> 45D6>
PCI_AD<25> 6B8> 46C3<> 47C5<> 48C5<> 49B6<>62C1>
PCI_AD<26> 6B8> 46C3<> 47C4<> 48C5<> 49B6<>62C1>
PCI_AD<27> 6B8> 45D6> 46C3<> 47C5<> 48B6<>
49B6<> 62C1> PCI_AD<28> 6B8> 46C3<> 47C4<> 48B5<> 49B6<>
62B1> PCI_AD<31..28> 45D6> PCI_AD<29> 6B8> 46C3<> 47C5<> 48B5<> 49B6<>
62B1>
PCI_AD<30> 6B8> 46C3<> 47C4<> 48B5<> 49B6<>62B1>
PCI_AD<31> 6B8> 46C3<> 47C5<> 48B5<> 49B6<>62B1>
PCI_CBE_L<0> 6A8> 47B4<> 48B5<> 49B6<> 62B1>
PCI_CBE_L<3..0> 45D6> PCI_CBE_L<1> 6A8> 47B5<> 48B5<> 49B6<> 62B1> PCI_CBE_L<2> 6A8> 47B5<> 48B5<> 49B6<> 62B1> PCI_CBE_L<3> 6A8> 47C5<> 48B5<> 49B6<> 62B1> PCI_CBUS_RESET_L_R 49A6< 49D3< PCI_CLK33M_AIRPORT 5D8< 6A8>
PCI_CLK33M_CBUS 5D8< PCI_CLK33M_SB_EXT 5C8< 25C8< 45B5< PCI_CLK33M_USB2 5D8< PCI_CLK66M_SB_INT 25B1< 25D8< 45C5< PCI_CLK66M_SB_INT_R 25B4<>
PCI_CLK_GP0 5D7> 25D1< PCI_CLK_GP0_R 25C4<> PCI_CLK_GP1 5D7> 25D1< PCI_CLK_GP1_R 25C4<> PCI_CLK_P1 5C7> 25B1< PCI_CLK_P1_R 25B4<>
PCI_CLK_P3 5D7> 25B1< PCI_CLK_P3_R 25B4<> PCI_CLK_P4 5C7> 25B1< PCI_CLK_P4_R 25B4<> PCI_DEVSEL_L 6B8> 45B2< 45D6> 47B4<> 48B5<>
49A6<> 62B1> PCI_FRAME_L 6B8> 45B2< 45D6> 47B4<> 48B5<>
49B6<> 62B1> PCI_IRDY_L 6B8> 45B2< 45D6> 47B5<> 48B5<>
49B6<> 62B1> PCI_PAR 6A8> 45D6> 47C4<> 48B5<> 49B6<>
62B1> PCI_RESET_L 5D8< 5D8< 45A2<> 46B5< 47C5<>
48A7< PCI_SB_AD<0> 45C3<> 62D2< PCI_SB_AD<1> 45B3<> 62D2<
PCI_SB_AD<2> 45B3<> 62D2< PCI_SB_AD<3> 45B3<> 62D2< PCI_SB_AD<4> 45B3<> 62D2< PCI_SB_AD<5> 45B3<> 62D2< PCI_SB_AD<6> 45B3<> 62D2< PCI_SB_AD<7> 45B3<> 62D2<
PCI_SB_AD<8> 45B3<> 62D2< PCI_SB_AD<9> 45B3<> 62D2< PCI_SB_AD<10> 45B3<> 62D2< PCI_SB_AD<11> 45B3<> 62C2< PCI_SB_AD<12> 45B3<> 62C2<
PCI_SB_AD<13> 45B3<> 62C2< PCI_SB_AD<14> 45B3<> 62C2< PCI_SB_AD<15> 45B3<> 62C2< PCI_SB_AD<16> 45B3<> 62C2< PCI_SB_AD<17> 45B3<> 62C2< PCI_SB_AD<18> 45B3<> 62C2<
PCI_SB_AD<19> 45B3<> 62C2< PCI_SB_AD<20> 45B3<> 62C2< PCI_SB_AD<21> 45B3<> 62C2< PCI_SB_AD<22> 45B3<> 62C2< PCI_SB_AD<23> 45B3<> 62C2<
PCI_SB_AD<24> 45B3<> 62C2< PCI_SB_AD<25> 45B3<> 62C2< PCI_SB_AD<26> 45B3<> 62C2< PCI_SB_AD<27> 45A3<> 48B6< 62C2< PCI_SB_AD<28> 45A3<> 62B2< PCI_SB_AD<29> 45A3<> 62B2<
PCI_SB_AD<30> 45A3<> 62B2< PCI_SB_AD<31> 45A3<> 62B2< PCI_SB_CBE_L<0> 45A3<> 62B2< PCI_SB_CBE_L<1> 45A3<> 62B2< PCI_SB_CBE_L<2> 45A3<> 62B2<
PCI_SB_CBE_L<3> 45A3<> 62B2< PCI_SB_DEVSEL_L 45A3<> 62B2< PCI_SB_FRAME_L 45A3<> 62B2< PCI_SB_IRDY_L 45A3<> 62B2< PCI_SB_PAR 45A3<> 62B2< PCI_SB_STOP_L 45A3<> 62B2<
PCI_SB_TRDY_L 45A3<> 62B2< PCI_SLOTA_GNT_L 6A8> 45B5<> 45B7< 47C4<> PCI_SLOTA_IDSEL 6A8> 47C4<> PCI_SLOTA_INT_L 6A8> 23A7< 23B3<> 47C4<> PCI_SLOTA_REQ_L 6A8> 45B5<> 45B7< 47C5<>
PCI_SLOTB_INT_L 23B3<> 23C2< PCI_SLOTC_INT_L 23B2< 23B3<> PCI_SLOTD_GNT_L 45A7< 45B5<> PCI_SLOTD_INT_L 23A7< 23B3<> PCI_SLOTD_REQ_L 45B5<> 45B7< PCI_SLOTE_GNT_L 23A7< 23C3<> 49A6<
PCI_SLOTE_IDSEL 49B6< PCI_SLOTE_INT_L 23A7< 23B3<> 49A6<> PCI_SLOTE_REQ_L 23A7< 23C3<> 49A6> PCI_SLOTF_GNT_L 23A7< 23C3<> PCI_SLOTF_INT_L 23B2< 23B3<>
PCI_SLOTF_REQ_L 23A7< 23C3<> PCI_SLOTG_GNT_L 45B5<> 45B7< 48B5< PCI_SLOTG_IDSEL 48B5< PCI_SLOTG_INT_L 23A7< 23B3<> 48B7< PCI_SLOTG_REQ_L 45B5<> 45B7< 48B5> PCI_STOP_L 6B8> 45A2< 45D6> 47B4<> 48B5<>
49A6<> 62B1> PCI_TRDY_L 6B8> 45A2< 45D6> 47B4<> 48B5<>
49A6<> 62B1> PLLLOCK 16A6< 27B6<> PLLMULT 27B6<> 28B3<
PLLRANGE0 27B6<> 28B3< PLLRANGE1 27B6<> 28B3< PLLTEST 27B6<> 28A8< PLLTESTOUT 27B6<> 28C4< PLS_CLK_66M_0_R 25C4<> PLS_CLK_66M_1_R 25C4<>
PLS_EXTCLK 25B7<> 25C8<
PLS_FORCE_P0_L_R 25B6< PLS_INTERM 25A7<
PLS_POWER_DOWN 25B6< PLS_PRES_CML 25B6<> PLS_REF15 25B6<> PLS_REF25 25B6<> PLS_REF33 25B6<>
PLS_RESET_L 25C6< PLS_SCAN_MODE 25B6<> PLS_X_ADDRSEL 25B6< PLS_X_IN 25C6< PLS_X_IN_B 25A7< PLS_X_OUT 25C6<>
PLS_X_OUT_B 25A6< PMU_SUSPEND_REQ 22D2<> PP1V2_EI_CPU 5A1<> 18C3< 27A6< 27D6< 28B2<
28B5< 28D4< 28D8< 29D4<> PP1V2_EI_NB 5B1<> 18D3< 26A8< 26B4< 26D6<
PP1V2_HT 5B1> 22D7< 43B7< 43D5< PP1V2_PULSAR 5B1> 24A4< 24C3< 24D3< PP1V2_PWRON_HT_PLLAVDD 44C5< PP1V2_PWRON_HT_PLLDVDD 44D5< PP1V2_PWRON_REG 5B5<> PP1V2_PWRON_SB_PLL45VDD 23D4<
PP1V2_PWRON_SB_PLL49VDD 23D4< PP1V2_RUN_GPU 5C6<> 6B1> PP1V2_VESTA 12B7< 12C1< PP1V2_VESTA_AVDDL 12B6< PP1V2_VESTA_FAVDDL 57C3<
PP1V2_VESTA_PLLVDD1 54D4< PP1V2_VESTA_PLLVDD2 57D4< PP1V5_AGP 5B1> 36A7< 36B3< 36C2< 36D5< 37D8<
PP1V5_AGP_NECK 39A2<> PP1V5_GPU 5A5>
PP1V5_GPU_NECK 40D2<> PP1V5_GPU_VDD15 39A3<> 39D3< PP1V5_GPU_VDD15_NECK 39A3<> PP1V5_GPU_VDD15_UF 39D5<> PP1V5_GPU_VDDP 40C6<
PP1V5_PSL_PLL1 24D7< PP1V5_PSL_PLL2 24D7< PP1V5_PSL_PLL3 24C7< PP1V5_PSL_PLL4 24C7< PP1V5_PWRON_AGP_NB_AVDD 36D7< PP1V5_PWRON_EI_NB_AVDD 26D7<
PP1V5_PWRON_HT_NB_AVDD 43D6< PP1V5_PWRON_NB_AVDD 5B3> 26D8< 33D5< 36D8< 43D7< PP1V5_PWRON_RAM_NB_AVDD 33D4< PP1V5_PWRON_REG 5B5<> PP1V5_RUN 5B6<
PP1V8_GPU 5B5> PP1V8_GPU_A2VDDQ 40C7< PP1V8_GPU_AVDD 40D6< PP1V8_GPU_LPVDD 40B6< PP1V8_GPU_LVDDR 40A6< PP1V8_GPU_MPVDD 40A6<
PP1V8_GPU_NECK 40D2<> PP1V8_GPU_PVDD 14A6<> 40D6< PP1V8_GPU_PVDD_LDO 39A3<> 40A7< 40B7< 40D7<> PP1V8_GPU_PVDD_NECK 39A3<> PP1V8_GPU_TPVDD 40B6<
PP1V8_GPU_TPVDD_LDO 40B7<> PP1V8_GPU_VDDDI 40C7< PP1V8_RUN 5B6< 5B7< 6B1> PP1V8_RUN_LDO 5B2<> PP1V25_PWRON_RAM_VREF_NB 33C4<> PP2V5_GPU 5B6>
PP2V5_GPU_A2VDD 40D7< PP2V5_GPU_LVDDR 40A6< PP2V5_GPU_NECK2 40D2<> PP2V5_HT 5C3> 43B8< 43C8< 43D5< PP2V5_PWRON 6B1>
PP2V5_PWRON_RAM 5B3> 24B5< 24D3< 33A8< 33C4< 33D2<33D8<
PP2V5_PWRON_REG 5C5<> PP2V5_PWRON_SB_XTAL18VDD 23D4< PP2V5_PWRON_SB_XTALVDD 23C4< PP2V5_RUN 5B7< 5C7<
PP2V5_RUN_CPU 5C1> 29D7< PP2V5_RUN_CPU_AVDD 29D7<> PP2V5_RUN_CPU_AVDD_R 29D6< PP2V5_RUN_CPU_AVDD_R_L 29D5<> PP2V5_RUN_NECK1 39A2<>
PP2V5_SMU_VREF 5D3< 32A6> PP2V5_VESTA 12B2< 12D1<> PP2V5_VESTA_BIASVDD1 54D4< PP2V5_VESTA_BIASVDD2 57D4< PP2V5_VESTA_FAVDDM 57D3< PP2V5_VESTA_XTALVDD1 54D4<
PP2V5_VESTA_XTALVDD2 57C4< PP3V3_AGP 5B5> 36B2< 36B2< 36C3< PP3V3_ALL 6A4> 6B1> PP3V3_ALL_SMU_AVCC 13D4< PP3V3_FW_ESD 58A6<> 58B5<> 58D5<>
PP3V3_FW_ESD_F 58A7< PP3V3_GPU 5B5> PP3V3_GPUSS_VDD 37C2< PP3V3_GPU_NECK 40D2<> PP3V3_GPU_OSC 37D2< PP3V3_GPU_VDDR3 40B2<
PP3V3_LCD 6A7> 42B4<> PP3V3_LCD_FET 42A4<> PP3V3_PSL_XTAL 24B7< PP3V3_PWRON 6A4> 17B7<> 25B7< PP3V3_PWRON_AUDIO 6B2> 61C4<>
PP3V3_PWRON_MAX1989 15D3< PP3V3_PWRON_NEC_AVDD 59D4< PP3V3_PWRON_REG 5C5<> PP3V3_RUN 5C6< 6A4> 6A8> PP3V3_SATABR_VAA 51D4< PP3V3_SI_AVCC 41D6<
PP3V3_SI_PVCC 41C8<> PP3V3_SI_VCC 41C6< PP3V3_VESTA 12A2< 12A6< 12C4< 12C6< 12D3<
12D3<> PP3V3_VESTA_FAVDDH 57D3<
PP4V6_ALL 11A4<> PP4V85_ALL_LDO 11A5<> PP5V4_CHGR_LDO 8B5<> PP5V_5V3V_VREF5 10D6<> PP5V_CPUVCORE_VCC 31D7< PP5V_GPUVCORE_VCC 38D7<
PP5V_INVERTER 6A7> 42B2<> PP5V_INVERTER_F 42B2<> PP5V_PWRON 6A4> 6B3> 11C5< PP5V_PWRON_AUDIO 6B2> 61C5<> PP5V_PWRON_REG 5D5<>
PP5V_RUN 6B4> PP5V_RUN_CPU 5D1> 16B4< 16B5< 29D8< PP5V_RUN_DDC 6C7> 42D3<> 42D5<> PP5V_RUN_DDC_F 42D6< PP5V_RUN_HD 5D1> 6A5> PP18V5_ALL_4V85ALL 11A7<>
PP18V5_ALL_DCIN 6A5> 7D5<> 11B8< PP18V5_ALL_DCIN_R 11B6<> PP18V5_ALL_INRUSH 7D2<> 8D8<> PP18V5_ALL_SENSE 8D7<> PPBATT_ALL 7A5< 8C2<
PPBATT_ALL_F 6A5> 7A7<> PPBATT_ALL_FUSEA 8C2<> 11A8<> PPBATT_ALL_FUSEA_ZENER 11A7<> PPBATT_ALL_FUSEB 8C1<> PPBATT_ALL_VSNS 7A5< 8A5< PPBATT_CHGR_OUT 8A3< 8C3<>
PPBATT_CHGR_RSNS 8B3< PPBATT_CHGR_SW 8A4<> PPBBATT_BOOST_OUT 11A8<> 17A4<> PPBUS_ALL_A 5D7< 6A3> 6A7> PPBUS_ALL_B 5D7< 6A3> 6B1>
PPBUS_FW_FUSE 12D7<> PPBUS_INVERTER 42B1<> PPDVO_GPU_VDDR4 40B2< PPFW_COMBINED 12D5<> 12D5<> PPFW_PORT1_VP 6C3> 58D2<> PPFW_PORT2_VP 6C3> 58B3<>
PPFW_PORT2_VP_F 58B3< PPFW_SWITCH 12D6<> PPLOGIC_PATA 6A5> 52C4<> PPVCC_ALL_3V5V 10D4< PPVCC_CBUS 49B1<> 49B2<> 49D1<>
PPVCC_CBUS_XW 49C4<> PPVCORE_CPU 5C5> 27D4< 29A4< 29D5<> 30D7<
31D4< 32B3< 32B7<> PPVCORE_GPU 5C5> 37A6< 39A3<> 39D4< PPVCORE_GPUFB 5B6> PPVCORE_GPUFB_VDDM 40B6<
PPVCORE_GPUFB_VDDRH 40C6<
051-6532 03
103100
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE 101
PPVCORE_GPU_NECK 39A3<> PPVCORE_GPU_REG 5C7<>
PPVCORE_GPU_VDDCI 37B5< PPVCORE_NB_REG 5B5<> PPVCORE_PULSAR 5B1> 24B4< 24C3< 24D3< PPVCORE_PWRON_NB 5B3<> PPVCORE_PWRON_PULSAR 5B3> 24B5< 24D3< 24D8<
PPVCORE_RUN_CPU 5C6> 6B1> PPVIN_1V8RUN 9D6< PPVIN_FWLM2594 12D4<> PPVIO_GPUFB 40B5< 40C1< PPVOUT_VESTA1V2 12C3< PPVPP_CBUS 49B1<> 49B2<> 49D1<>
PROCID0 27B8<> 28A6< PROCID1 27B8<> 28A6< PROCID2 27B8<> 28A6< PROC_THERM_INT_L 27B8<> 28B7< PULSESEL0 27B8<> 28B6<
PULSESEL1 27B8<> 28B6< PULSESEL2 27B8<> 28A6< PWRON_REGS_PGOOD 14B7< Q3001_B 16A6< Q3001_C 16A5< Q3002_B 16A5<
Q3002_E 16A5< Q3003_B 16A4< Q3004_D 16A4< Q3004_G 16A4< RAMSTOPENABLE 27B8<> 28C6<
RAM_A<0> 34C5< 35B4<> 35B5<> RAM_A<13..0> 62A6> RAM_A<1> 34C5< 35B3<> 35B7<> RAM_A<2> 34C5< 35B4<> 35B5<> RAM_A<3> 34C5< 35B3<> 35B7<> RAM_A<4> 34C5< 35B4<> 35B5<>
RAM_A<5> 34C5< 35B3<> 35B7<> RAM_A<6> 34C5< 35B4<> 35B5<> RAM_A<7> 34B5< 35B3<> 35B7<> RAM_A<8> 34B5< 35B4<> 35B5<> RAM_A<9> 34B5< 35B3<> 35B7<>
RAM_A<10> 34B5< 35B3<> 35B7<> RAM_A<11> 34B5< 35B4<> 35B5<> RAM_A<12> 34B5< 35B3<> 35B7<> RAM_A<13> 34B5< 35B3<> 35B7<> RAM_A_R<0> 33C2> 34C6< RAM_A_R<13..0> 62A6>
RAM_A_R<1> 33C2> 34C6< RAM_A_R<2> 33C2> 34C6< RAM_A_R<3> 33C2> 34C6< RAM_A_R<4> 33C2> 34C6< RAM_A_R<5> 33C2> 34C6<
RAM_A_R<6> 33C2> 34C6< RAM_A_R<7> 33C2> 34B6< RAM_A_R<8> 33C2> 34B6< RAM_A_R<9> 33C2> 34B6< RAM_A_R<10> 33C2> 34B6< RAM_A_R<11> 33C2> 34B6<
RAM_A_R<12> 33C2> 34B6< RAM_A_R<13> 33C2> 34B6< RAM_BA<0> 34B5< 35B3<> 35B7<> RAM_BA<1> 34B5< 35B4<> 35B5<> RAM_BA_R<0> 33D2> 34B6<
RAM_BA_R<1..0> 62A6> 62A6> RAM_BA_R<1> 33D2> 34B6< RAM_CAS_L 34A5< 35B4<> 35B5<> RAM_CAS_L_R 33D2> 34A6< 62A6> 62A6> RAM_CKE<0> 34A8< 34D5< 35B5<> 62A6> RAM_CKE<1> 34A8< 34D5< 35B7<> 62A6>
RAM_CKE<4> 34A8< 34D5< 35B4<> 62A6> RAM_CKE<5> 34A8< 34C5< 35B3<> 62A6> RAM_CKE_R<0> 33C4> 34D6< RAM_CKE_R<1..0> 62B6> RAM_CKE_R<1> 33C4> 34D6<
RAM_CKE_R<2> 5A7< 33C4> RAM_CKE_R<3> 5A7< 33C4> RAM_CKE_R<4> 33C4> 34D6< RAM_CKE_R<5..4> 62A6> RAM_CKE_R<5> 33C4> 34C6< RAM_CKE_R<6> 5A7< 33C4>
RAM_CKE_R<7> 5A7< 33C4> RAM_CLK66M_NB 25B1< 33D4< RAM_CLK66M_NB_R 25B4<> RAM_CLK_A_N 34C7< 35D7<> 62B6> RAM_CLK_A_N_R 33D4<> 34C8< 62B6>
RAM_CLK_A_P 34C7< 35D7<> 62B6> RAM_CLK_A_P_R 33D4<> 34C8< 62B6> RAM_CLK_B_N 34C7< 35A5<> 62B6> RAM_CLK_B_N_R 33D4<> 34C8< 62B6> RAM_CLK_B_P 34C7< 35A5<> 62B6> RAM_CLK_B_P_R 33D4<> 34C8< 62B6>
RAM_CLK_C_N_R 33D4<> 34D8< RAM_CLK_C_P_R 33D4<> 34D8< RAM_CLK_D_N 34B7< 35D3<> 62B6> RAM_CLK_D_N_R 33C4<> 34B8< 62B6> RAM_CLK_D_P 34C7< 35D3<> 62B6>
RAM_CLK_D_P_R 33D4<> 34C8< 62B6> RAM_CLK_E_N 34B7< 35A4<> 62B6> RAM_CLK_E_N_R 33C4<> 34B8< 62B6> RAM_CLK_E_P 34B7< 35A4<> 62B6> RAM_CLK_E_P_R 33C4<> 34B8< 62B6> RAM_CLK_F_N_R 33C4<> 34D8<
RAM_CLK_F_P_R 33C4<> 34D8< RAM_CS_L<0> 34D5< 35B7<> 62A6> RAM_CS_L<1> 34D5< 35B5<> 62A6> RAM_CS_L<8> 34D5< 35B3<> 62A6> RAM_CS_L<9> 34D5< 35B4<> 62A6>
RAM_CS_L_R<0> 33C2> 34D6< RAM_CS_L_R<1..0> 62A6> RAM_CS_L_R<1> 33C2> 34D6< RAM_CS_L_R<2> 5A7< 33C2> RAM_CS_L_R<3> 5A7< 33C2> RAM_CS_L_R<8> 33C2> 34D6<
RAM_CS_L_R<9..8> 62A6> RAM_CS_L_R<9> 33C2> 34D6< RAM_CS_L_R<10> 5A7< 33C2> RAM_CS_L_R<11> 5A7< 33C2> RAM_DQ<0> 34D4> 35D7<>
RAM_DQ<7..0> 62D6> RAM_DQ<1> 34D4> 35D7<> RAM_DQ<2> 34D4> 35D7<> RAM_DQ<3> 34D4> 35D7<> RAM_DQ<4> 34D4> 35D5<> RAM_DQ<5> 34D4> 35D5<>
RAM_DQ<6> 34D4> 35D5<> RAM_DQ<7> 34D4> 35D5<> RAM_DQ<8> 34D4> 35D7<> RAM_DQ<15..8> 62D6> RAM_DQ<9> 34D4> 35D7<>
RAM_DQ<10> 34D4> 35D7<> RAM_DQ<11> 34D4> 35D7<> RAM_DQ<12> 34D4> 35D5<> RAM_DQ<13> 34C4> 35D5<> RAM_DQ<14> 34C4> 35D5<> RAM_DQ<15> 34C4> 35D5<>
RAM_DQ<16> 34C4> 35D7<> RAM_DQ<23..16> 62C6> RAM_DQ<17> 34C4> 35C7<> RAM_DQ<18> 34C4> 35C7<> RAM_DQ<19> 34C4> 35C7<>
RAM_DQ<20> 34C4> 35D5<> RAM_DQ<21> 34C4> 35C5<> RAM_DQ<22> 34C4> 35C5<> RAM_DQ<23> 34C4> 35C5<> RAM_DQ<24> 34C4> 35C7<> RAM_DQ<31..24> 62C6>
RAM_DQ<25> 34C4> 35C7<> RAM_DQ<26> 34C4> 35C7<> RAM_DQ<27> 34C4> 35C7<> RAM_DQ<28> 34C4> 35C5<> RAM_DQ<29> 34C4> 35C5<>
RAM_DQ<30> 34B4> 35C5<> RAM_DQ<31> 34B4> 35C5<> RAM_DQ<32> 34B4> 35B7<> RAM_DQ<39..32> 62C6> RAM_DQ<33> 34B4> 35B7<> RAM_DQ<34> 34B4> 35B7<>
RAM_DQ<35> 34B4> 35B7<> RAM_DQ<36> 34B4> 35B5<> RAM_DQ<37> 34B4> 35B5<> RAM_DQ<38> 34B4> 35B5<> RAM_DQ<39> 34B4> 35B5<>
RAM_DQ<40> 34B4> 35B7<> RAM_DQ<47..40> 62C6> RAM_DQ<41> 34B4> 35B7<> RAM_DQ<42> 34B4> 35A7<> RAM_DQ<43> 34B4> 35A7<> RAM_DQ<44> 34B4> 35A5<>
RAM_DQ<45> 34B4> 35B5<>
RAM_DQ<46> 34B4> 35A5<> RAM_DQ<47> 34A4> 35B5<>
RAM_DQ<48> 34A4> 35A7<> RAM_DQ<55..48> 62C6> RAM_DQ<49> 34A4> 35A7<> RAM_DQ<50> 34A4> 35A7<> RAM_DQ<51> 34A4> 35A7<>
RAM_DQ<52> 34A4> 35A5<> RAM_DQ<53> 34A4> 35A5<> RAM_DQ<54> 34A4> 35A5<> RAM_DQ<55> 34A4> 35A5<> RAM_DQ<56> 34A4> 35A7<> RAM_DQ<63..56> 62C6>
RAM_DQ<57> 34A4> 35A7<> RAM_DQ<58> 34A4> 35A7<> RAM_DQ<59> 34A4> 35A7<> RAM_DQ<60> 34A4> 35A5<> RAM_DQ<61> 34A4> 35A5<>
RAM_DQ<62> 34A4> 35A5<> RAM_DQ<63> 34A4> 35A5<> RAM_DQ<64> 34D3> 35D3<> RAM_DQ<71..64> 62C6> RAM_DQ<65> 34D3> 35D3<> RAM_DQ<66> 34D3> 35D3<>
RAM_DQ<67> 34D3> 35D3<> RAM_DQ<68> 34D3> 35D4<> RAM_DQ<69> 34D3> 35D4<> RAM_DQ<70> 34D3> 35D4<> RAM_DQ<71> 34D3> 35D4<>
RAM_DQ<72> 34D3> 35D3<> RAM_DQ<79..72> 62C6> RAM_DQ<73> 34D3> 35D3<> RAM_DQ<74> 34D3> 35D3<> RAM_DQ<75> 34D3> 35D3<> RAM_DQ<76> 34D3> 35D4<>
RAM_DQ<77> 34C3> 35D4<> RAM_DQ<78> 34C3> 35D4<> RAM_DQ<79> 34C3> 35D4<> RAM_DQ<80> 34C3> 35D3<> RAM_DQ<87..80> 62C6>
RAM_DQ<81> 34C3> 35C3<> RAM_DQ<82> 34C3> 35C3<> RAM_DQ<83> 34C3> 35C3<> RAM_DQ<84> 34C3> 35D4<> RAM_DQ<85> 34C3> 35C4<> RAM_DQ<86> 34C3> 35C4<>
RAM_DQ<87> 34C3> 35C4<> RAM_DQ<88> 34C3> 35C3<> RAM_DQ<95..88> 62C6> RAM_DQ<89> 34C3> 35C3<> RAM_DQ<90> 34C3> 35C3<>
RAM_DQ<91> 34C3> 35C3<> RAM_DQ<92> 34C3> 35C4<> RAM_DQ<93> 34C3> 35C4<> RAM_DQ<94> 34B3> 35C4<> RAM_DQ<95> 34B3> 35C4<> RAM_DQ<96> 34B3> 35B3<>
RAM_DQ<103..96> 62C6> RAM_DQ<97> 34B3> 35B3<> RAM_DQ<98> 34B3> 35B3<> RAM_DQ<99> 34B3> 35B3<> RAM_DQ<100> 34B3> 35B4<>
RAM_DQ<101> 34B3> 35B4<> RAM_DQ<102> 34B3> 35B4<> RAM_DQ<103> 34B3> 35B4<> RAM_DQ<104> 34B3> 35B3<> RAM_DQ<111..104> 62C6> RAM_DQ<105> 34B3> 35B3<>
RAM_DQ<106> 34B3> 35A3<> RAM_DQ<107> 34B3> 35A3<> RAM_DQ<108> 34B3> 35B4<> RAM_DQ<109> 34B3> 35B4<> RAM_DQ<110> 34B3> 35A4<>
RAM_DQ<111> 34A3> 35A4<> RAM_DQ<112> 34A3> 35A3<> RAM_DQ<119..112> 62C6> RAM_DQ<113> 34A3> 35A3<> RAM_DQ<114> 34A3> 35A3<> RAM_DQ<115> 34A3> 35A3<>
RAM_DQ<116> 34A3> 35A4<> RAM_DQ<117> 34A3> 35A4<> RAM_DQ<118> 34A3> 35A4<> RAM_DQ<119> 34A3> 35A4<> RAM_DQ<120> 34A3> 35A3<>
RAM_DQ<127..120> 62B6> RAM_DQ<121> 34A3> 35A3<> RAM_DQ<122> 34A3> 35A3<> RAM_DQ<123> 34A3> 35A3<> RAM_DQ<124> 34A3> 35A4<> RAM_DQ<125> 34A3> 35A4<>
RAM_DQ<126> 34A3> 35A4<> RAM_DQ<127> 34A3> 35A4<> RAM_DQS<0> 34D1> 35D7<> 62D6> RAM_DQS<1> 34D1> 35D7<> 62D6> RAM_DQS<2> 34D1> 35C7<> 62D6>
RAM_DQS<3> 34D1> 35C7<> 62C6> RAM_DQS<4> 34D1> 35B7<> 62C6> RAM_DQS<5> 34D1> 35A7<> 62C6> RAM_DQS<6> 34D1> 35A7<> 62C6> RAM_DQS<7> 34D1> 35A7<> 62C6> RAM_DQS<8> 34D1> 35D3<> 62C6>
RAM_DQS<9> 34D1> 35D3<> 62C6> RAM_DQS<10> 34D1> 35C3<> 62C6> RAM_DQS<11> 34D1> 35C3<> 62C6> RAM_DQS<12> 34D1> 35B3<> 62C6> RAM_DQS<13> 34C1> 35A3<> 62C6>
RAM_DQS<14> 34C1> 35A3<> 62C6> RAM_DQS<15> 34C1> 35A3<> 62C6> RAM_DQS_R<0> 33B2<> 34D2< RAM_DQS_R<15..0> 62D6> RAM_DQS_R<1> 33B2<> 34D2< RAM_DQS_R<2> 33B2<> 34D2<
RAM_DQS_R<3> 33B2<> 34D2< RAM_DQS_R<4> 33B2<> 34D2< RAM_DQS_R<5> 33B2<> 34D2< RAM_DQS_R<6> 33B2<> 34D2< RAM_DQS_R<7> 33B2<> 34D2<
RAM_DQS_R<8> 33B2<> 34D2< RAM_DQS_R<9> 33B2<> 34D2< RAM_DQS_R<10> 33B2<> 34D2< RAM_DQS_R<11> 33B2<> 34D2< RAM_DQS_R<12> 33B2<> 34D2< RAM_DQS_R<13> 33B2<> 34C2<
RAM_DQS_R<14> 33B2<> 34C2< RAM_DQS_R<15> 33B2<> 34C2< RAM_DQ_R<0> 33D8<> 34D5< RAM_DQ_R<127..0> 62D6> RAM_DQ_R<1> 33D8<> 34D5<
RAM_DQ_R<2> 33D8<> 34D5< RAM_DQ_R<3> 33D8<> 34D5< RAM_DQ_R<4> 33D8<> 34D5< RAM_DQ_R<5> 33D8<> 34D5< RAM_DQ_R<6> 33D8<> 34D5< RAM_DQ_R<7> 33D8<> 34D5<
RAM_DQ_R<8> 33D8<> 34D5< RAM_DQ_R<9> 33D8<> 34D5< RAM_DQ_R<10> 33D8<> 34D5< RAM_DQ_R<11> 33C8<> 34D5< RAM_DQ_R<12> 33C8<> 34D5<
RAM_DQ_R<13> 33C8<> 34C5< RAM_DQ_R<14> 33C8<> 34C5< RAM_DQ_R<15> 33C8<> 34C5< RAM_DQ_R<16> 33C8<> 34C5< RAM_DQ_R<17> 33C8<> 34C5< RAM_DQ_R<18> 33C8<> 34C5<
RAM_DQ_R<19> 33C8<> 34C5< RAM_DQ_R<20> 33C8<> 34C5< RAM_DQ_R<21> 33C8<> 34C5< RAM_DQ_R<22> 33C8<> 34C5< RAM_DQ_R<23> 33C8<> 34C5<
RAM_DQ_R<24> 33C8<> 34C5< RAM_DQ_R<25> 33C8<> 34C5< RAM_DQ_R<26> 33C8<> 34C5< RAM_DQ_R<27> 33C8<> 34C5< RAM_DQ_R<28> 33C8<> 34C5< RAM_DQ_R<29> 33C8<> 34C5<
RAM_DQ_R<30> 33C8<> 34B5< RAM_DQ_R<31> 33C8<> 34B5< RAM_DQ_R<32> 33C8<> 34B5< RAM_DQ_R<33> 33C8<> 34B5< RAM_DQ_R<34> 33C8<> 34B5<
RAM_DQ_R<35> 33C8<> 34B5< RAM_DQ_R<36> 33C8<> 34B5< RAM_DQ_R<37> 33B8<> 34B5< RAM_DQ_R<38> 33B8<> 34B5< RAM_DQ_R<39> 33B8<> 34B5< RAM_DQ_R<40> 33B8<> 34B5<
RAM_DQ_R<41> 33B8<> 34B5<
RAM_DQ_R<42> 33B8<> 34B5< RAM_DQ_R<43> 33B8<> 34B5<
RAM_DQ_R<44> 33B8<> 34B5< RAM_DQ_R<45> 33B8<> 34B5< RAM_DQ_R<46> 33B8<> 34B5< RAM_DQ_R<47> 33B8<> 34A5< RAM_DQ_R<48> 33B8<> 34A5<
RAM_DQ_R<49> 33B8<> 34A5< RAM_DQ_R<50> 33B8<> 34A5< RAM_DQ_R<51> 33B8<> 34A5< RAM_DQ_R<52> 33B8<> 34A5< RAM_DQ_R<53> 33B8<> 34A5< RAM_DQ_R<54> 33B8<> 34A5<
RAM_DQ_R<55> 33B8<> 34A5< RAM_DQ_R<56> 33B8<> 34A5< RAM_DQ_R<57> 33B8<> 34A5< RAM_DQ_R<58> 33B8<> 34A5< RAM_DQ_R<59> 33B8<> 34A5<
RAM_DQ_R<60> 33B8<> 34A5< RAM_DQ_R<61> 33B8<> 34A5< RAM_DQ_R<62> 33B8<> 34A5< RAM_DQ_R<63> 33A8<> 34A5< RAM_DQ_R<64> 33D6<> 34D3< RAM_DQ_R<65> 33D6<> 34D3<
RAM_DQ_R<66> 33D6<> 34D3< RAM_DQ_R<67> 33D6<> 34D3< RAM_DQ_R<68> 33D6<> 34D3< RAM_DQ_R<69> 33D6<> 34D3< RAM_DQ_R<70> 33D6<> 34D3<
RAM_DQ_R<71> 33D6<> 34D3< RAM_DQ_R<72> 33D6<> 34D3< RAM_DQ_R<73> 33D6<> 34D3< RAM_DQ_R<74> 33D6<> 34D3< RAM_DQ_R<75> 33C6<> 34D3< RAM_DQ_R<76> 33C6<> 34D3<
RAM_DQ_R<77> 33C6<> 34C3< RAM_DQ_R<78> 33C6<> 34C3< RAM_DQ_R<79> 33C6<> 34C3< RAM_DQ_R<80> 33C6<> 34C3< RAM_DQ_R<81> 33C6<> 34C3<
RAM_DQ_R<82> 33C6<> 34C3< RAM_DQ_R<83> 33C6<> 34C3< RAM_DQ_R<84> 33C6<> 34C3< RAM_DQ_R<85> 33C6<> 34C3< RAM_DQ_R<86> 33C6<> 34C3< RAM_DQ_R<87> 33C6<> 34C3<
RAM_DQ_R<88> 33C6<> 34C3< RAM_DQ_R<89> 33C6<> 34C3< RAM_DQ_R<90> 33C6<> 34C3< RAM_DQ_R<91> 33C6<> 34C3< RAM_DQ_R<92> 33C6<> 34C3<
RAM_DQ_R<93> 33C6<> 34C3< RAM_DQ_R<94> 33C6<> 34B3< RAM_DQ_R<95> 33C6<> 34B3< RAM_DQ_R<96> 33C6<> 34B3< RAM_DQ_R<97> 33C6<> 34B3< RAM_DQ_R<98> 33C6<> 34B3<
RAM_DQ_R<99> 33C6<> 34B3< RAM_DQ_R<100> 33C6<> 34B3< RAM_DQ_R<101> 33B6<> 34B3< RAM_DQ_R<102> 33B6<> 34B3< RAM_DQ_R<103> 33B6<> 34B3<
RAM_DQ_R<104> 33B6<> 34B3< RAM_DQ_R<105> 33B6<> 34B3< RAM_DQ_R<106> 33B6<> 34B3< RAM_DQ_R<107> 33B6<> 34B3< RAM_DQ_R<108> 33B6<> 34B3< RAM_DQ_R<109> 33B6<> 34B3<
RAM_DQ_R<110> 33B6<> 34B3< RAM_DQ_R<111> 33B6<> 34A3< RAM_DQ_R<112> 33B6<> 34A3< RAM_DQ_R<113> 33B6<> 34A3< RAM_DQ_R<114> 33B6<> 34A3<
RAM_DQ_R<115> 33B6<> 34A3< RAM_DQ_R<116> 33B6<> 34A3< RAM_DQ_R<117> 33B6<> 34A3< RAM_DQ_R<118> 33B6<> 34A3< RAM_DQ_R<119> 33B6<> 34A3< RAM_DQ_R<120> 33B6<> 34A3<
RAM_DQ_R<121> 33B6<> 34A3< RAM_DQ_R<122> 33B6<> 34A3< RAM_DQ_R<123> 33B6<> 34A3< RAM_DQ_R<124> 33B6<> 34A3< RAM_DQ_R<125> 33B6<> 34A3<
RAM_DQ_R<126> 33B6<> 34A3< RAM_DQ_R<127> 33A6<> 34A3< RAM_MUXEN0 5A6< 33C2> RAM_MUXEN4 5A6< 33C2> RAM_RAS_L 34A5< 35B4<> 35B5<> RAM_RAS_L_R 33D2> 34A6< 62A6> 62A6>
RAM_VREF_DIMM 35D1< 35D3<> 35D4<> 35D5<> 35D7<> RAM_WE_L 34A5< 35B3<> 35B7<> RAM_WE_L_R 33D2> 34A6< 62A6> 62A6> RI_L 27B8<> 28B7< ROM_CS_L 6D1> 45A5> 46B6< 47B5<>
ROM_OE_L 6D1> 45A5> 46B5< 47B4<> ROM_ONBOARD_CS_L 6D1> 46B5< 47B5<> ROM_WE_L 6D1> 45A5> 46B5< 47B5<> ROM_WP_L 46B5< RTC_CLK32K_X1 13D1<> 13D6> RTC_CLK32K_X2 13D1<> 13D6>
RTUSB_OVERCURRENT 5C7> 17A3<> RTUSB_PWREN 5C7> 17A3<> SATABR_ISET_PD 51B4<> SATABR_RESET_L 51B5<> SATABR_RESET_ST 51B6<>
SATABR_VSS 51B4< 51D3< SATA_BR_RXD_N 51C5< 51D6> SATA_BR_RXD_P 51C5< 51D6> SATA_BR_TXD_N 51C4<> 51D6> SATA_BR_TXD_P 51C4<> 51D6> SATA_CLK25M 5C8<
SATA_CLK25M_R 25B4<> SATA_RXD_N1_C 50A5< 50D6> 51C3< SATA_RXD_N2_C 5A8< 50A5< 50D6> SATA_RXD_P1_C 50B5< 50D6> 51C3< SATA_RXD_P2_C 5A8< 50A5< 50D6>
SATA_TXD_N1 50A4> 50D6> 51C6< SATA_TXD_N2 5A8< 50A4> 50D6> SATA_TXD_P1 50B4> 50D6> 51C6< SATA_TXD_P2 5A8< 50A4> 50D6> SB_CLK18M_XTALI 23A5< 23D6> SB_CLK18M_XTALO 23A5< 23D6>
SB_CLK18M_XTALO_R 23A5<> 23D6> SB_CLK25M_ATA 23A5< 23D6> 25B1< SB_CLK25M_ATA_R 25B4<> SB_GPIO12 23B3<> 23C2< SB_GPIO23 23B2< 23B3<>
SB_GPIO24 23B2< 23B3<> SB_GPIO25 23B2< 23B3<> SB_GPIO30 23B2< 23B3<> SB_GPIO45 23A3<> 23B2< SB_GPIO46 23A3<> 23B2< SB_GPIO47 23A3<> 23B2<
SB_GPIO49 23A3<> 23B2< SB_GPIO50 23A3<> 23B2< SB_GPIO51 23A2< 23A3<> SB_GPIO52 23A2< 23A3<> SB_HT_R100_N 44B4<
SB_HT_R100_P 44B4<> SB_HT_S100M66M 44B5< SB_INT_L 23B5<> 23B7< SB_PCI_RESET_L 45A4<> SB_PCI_SEL32BIT 23B5<> SB_SATABR_RESET_L 23B3<> 23C2< 51B7<
SB_SELHT100 44B5< SB_STOPXTALS_L 13B3<> 23B5< SB_SUSPENDACK_L 13B3<> 23B5> SB_TEST_MODE_PD 23A5< SB_TO_SMU_INT_L 13B3<> 23C3<> 23D2<
SI_DDC_CLK 39B5<> 41C8<> SI_DDC_DATA 39B5<> 41C8<> SI_DUAL_MODE 41B8<> SI_HTP 41B8<> SI_I2CSEL 41C8<> SI_MEXTSWING 41A6<
SI_MSEN_OC 41C5<> SI_PRIMARY 41B8<> SI_RESET_L 39B7<> 41B8<> SI_SECONDARY 41A8<> SI_SEXTSWING 41A6<>
SI_SYNC 41B8<> SI_TMDS_CLKN 41B4< 41C5<> 62C4> SI_TMDS_CLKP 41B4< 41C5<> 62C4> SI_TMDS_DN<0> 41B4< 41B5<> 62C4> SI_TMDS_DN<1> 41B4< 41B5<> 62C4> SI_TMDS_DN<2> 41A4< 41B5<> 62C4>
SI_TMDS_DN<3> 41A4< 41B5<> 62C4>
SI_TMDS_DN<4> 41A4< 41B5<> 62B4> SI_TMDS_DN<5> 41A4< 41B5<> 62B4>
SI_TMDS_DP<0> 41B4< 41C5<> 62C4> SI_TMDS_DP<1> 41B4< 41B5<> 62C4> SI_TMDS_DP<2> 41A4< 41B5<> 62C4> SI_TMDS_DP<3> 41A4< 41B5<> 62C4> SI_TMDS_DP<4> 41A4< 41B5<> 62C4>
SI_TMDS_DP<5> 41A4< 41B5<> 62B4> SI_VREF 41A5<> SLEEPLED_ANODE 6C2> 19A3< 61B4<> SLEEPLED_ANODE_F 19B3< SLEEPLED_ANODE_F_Q 19B3< SLEEPLED_EN_L 19A3<>
SLEEPLED_EN_L_DIV 19B4< SLEWING_L_R 25B4<> SMU_ACIN 7C4<> 8C8<> 8D4<> 12C8< 13A7> SMU_ACIN_L 7C4<> 8B2<> SMU_BATT_DET_L 7A5< 13A7>
SMU_BOOT_BUSY 13D3> 16C3<> SMU_BOOT_CE 13D3> 16C4<> SMU_BOOT_CNVSS 6A1> 13B6< 16C4<> SMU_BOOT_RXD 6A1> 13C3<> 16C3<> SMU_BOOT_SCLK 13D3> 16C4<> SMU_BOOT_TXD 6A1> 13C3<> 16C3<>
SMU_CHARGE_BATT 8A6<> 8B3<> 13B6<> SMU_CHARGE_BATT_L 8A6<> SMU_CLK10M_XIN 13B6< 13D6> SMU_CLK10M_XOUT 13A6< 13D6> SMU_CLK10M_XOUT_R 13B6<> 13D6>
SMU_CPU_JTAG_OR_I2C 18C6< 18D6> SMU_ONEWIRE 13C6<> 17D5< SMU_PWRSEQ_P1_0 13C6<> 14D8< SMU_PWRSEQ_P1_1 13C6<> 14D8< SMU_PWRSEQ_P1_2 13C6<> 14C8< SMU_PWRSEQ_P1_3 13C6<> 14B8<
SMU_PWRSEQ_P1_4 13C6<> 14B8< SMU_PWRSEQ_P9_5 13B3<> 14A8< SMU_PWRSEQ_P9_6 13B3<> 14A8< SMU_RESET_L 6B1> 13B6< 16C4<> 19D4<> SMU_SLEEP 5A8< 13B1< 13B3<>
SMU_SUSPENDREQ_L 13B1< 13B3<> 22D3<> 23B5< SMU_TO_SB_INT_L 13B6< 23A2< 23A3<> SMU_WARM_RESET_L 5A8< 13B3<> 22B5<> STOP_AGP_L 36B1< 37C6< STOP_AGP_L_F 36B2< STOP_AGP_L_R 36B3<
SYNCENABLE 27B8<> 28C6< SYSCLK_TERM 27D6< SYS_COLD_RESET_L 13B1< 13C3<> 22A6> 22B8<> 51B7< SYS_DOOR_AJAR 6A4> SYS_DOOR_AJAR_L 13A8< 13C6<>
SYS_DRIVE_BAY_INT_L 13A8< 13C6<> SYS_KBDLED 13A7> 19A7<> SYS_LED 13C3<> 19A4<> SYS_LED_BLUE 13A6> SYS_LED_GREEN 13A6> SYS_LED_RED 13A6>
SYS_LID_OPEN 13A7> 17B8<> SYS_OVERTEMP_L 6A4> 13B6<> 15D3> 17A8<> 23B3<>
23D2< 25B8< SYS_PME_L 13B1< 13C3<> 23B5> 48A7< SYS_POWERFAIL_L 13A8< 13C6<>
SYS_POWERUP 6A3> 14D5<> SYS_POWERUP_L 6A1> 13C1< 13C3<> 14D8< SYS_POWERUP_L_R 14D6<> SYS_POWER_BUTTON_L 6A4> 6B1> 13B3<> 13C1< 16B4<
17A8<> 42D1< SYS_PWRSEQ_1 14D7<
SYS_PWRSEQ_2 14D7<> SYS_PWRSEQ_2_L 14D6<> SYS_PWRSEQ_3_L 14C7<> SYS_PWRSEQ_3_LS5 14C7<> SYS_PWRSEQ_4 14B7<
SYS_PWRSEQ_5 14B7< SYS_PWRSEQ_6_L 14A7<> SYS_PWRSEQ_6_LS5 14A7<> SYS_PWRSEQ_7 14A7<> SYS_RESET_BUTTON_L 6B1> 13B3<> 16B4< SYS_SLEEP 5A7> 10B6< 11B6< 25B8<
SYS_SLEWING_L 13B1< 13C3<> 23A3<> 23D2< 25B3<31C6<>
SYS_SLOT_PWR 13B3<> SYS_WARM_RESET_L 5A6< 22A6> 23B5< 45A4< 48A7< TD1 32C4<
TD2 32C4< TD3 32B3< TD4 32B3< TDIODE_NEG 29B4<> 32B5<> TDIODE_POS 29D4<> 32B5<> TD_BUFFERED 32C3<>
TD_CURRENT 32C3<> THERM_1B_N 15B6< 15B6< 15D6> THERM_1B_P 15B6< 15B6< 15D6> THERM_1_N 15B6< 15B7< 15D6> THERM_1_P 15B6< 15B7< 15D6>
THERM_2B_N 15A6< 15B6< 15D6> THERM_2B_P 15B6< 15B6< 15D6> THERM_2_N 15B6< 15B7< 15D6> THERM_2_P 15B6< 15B7< 15D6> THERM_3B_N 15A6< 15A6< 15D6> THERM_3B_P 15A6< 15A6< 15D6>
THERM_3_N 15A6< 15A7< 15D6> THERM_3_P 15A6< 15A7< 15D6> TMDS_CLKN 41B2< 41B3< 41D1< 42B6<> 62D4> TMDS_CLKP 41B3< 41B3< 41D1< 42B6<> 62D4> TMDS_CONN_CLKN 6D7> 42B5<> 42C7<> 62C4>
TMDS_CONN_CLKP 6C7> 42B5<> 42C7<> 62C4> TMDS_CONN_DN<0> 42C7<> 42D6<> 62C4> TMDS_CONN_DN<1> 42B7<> 42D5<> 62C4> TMDS_CONN_DN<2> 42B7<> 42D5<> 62C4> TMDS_CONN_DN<3> 42C5<> 42C6<> 62C4> TMDS_CONN_DN<4> 42B6<> 42C5<> 62C4>
TMDS_CONN_DN<5> 42B6<> 42C6<> 62C4> TMDS_CONN_DP<0> 42B7<> 42D6<> 62C4> TMDS_CONN_DP<1> 42B7<> 42D5<> 62C4> TMDS_CONN_DP<2> 42B7<> 42D5<> 62C4> TMDS_CONN_DP<3> 42B6<> 42C5<> 62C4>
TMDS_CONN_DP<4> 42B6<> 42C5<> 62C4> TMDS_CONN_DP<5> 42B6<> 42C6<> 62C4> TMDS_D3_CMF 41B1< TMDS_D4_CMF 41B1< TMDS_D5_CMF 41A1< TMDS_DN<0> 6D7> 41B2< 41B3< 41D1< 42C8<>
62D4> TMDS_DN<1> 6D7> 41A2< 41B3< 41C1< 42B8<>
62D4> TMDS_DN<2> 6D7> 41A2< 41A3< 41C1< 42B8<>
62D4>
TMDS_DN<3> 41A3< 41B1< 42C7<> 62D4> TMDS_DN<4> 41A3< 41B1< 42B7<> 62D4> TMDS_DN<5> 41A1< 41A3< 42B7<> 62C4> TMDS_DP<0> 6D7> 41B3< 41B3< 41D1< 42B8<>
62D4> TMDS_DP<1> 6D7> 41A3< 41B3< 41C1< 42B8<>
62D4> TMDS_DP<2> 6D7> 41A3< 41A3< 41C1< 42B8<>
62D4> TMDS_DP<3> 41A3< 41B2< 42B7<> 62D4> TMDS_DP<4> 41A3< 41B2< 42B7<> 62D4>
TMDS_DP<5> 41A2< 41A3< 42B7<> 62D4> TP_AFN 27B8<> TP_AGP_MB_AGP8X_DET_L 36B4> TP_AIRPORT_PME_L 6A8> 47C4<> TP_AIRPORT_RF_DISABLE 6A8> 47C5<> TP_ATTENTION 27B6<>
TP_CPU1_HTBEN_R 5A6> TP_DUMMY_A 22C4<> TP_DUMMY_B 22C4<> TP_EI_CPU1_CLK_N 5A6> TP_EI_CPU1_CLK_P 5A6>
TP_EI_CPU1_SYNC_R 5A6> TP_EXT_LED_L 5A7> TP_FAN_RPM2 5A7> TP_FAN_TACH2 5A7> TP_FAN_TACH3 5A7> TP_FAN_TACH4 5A7>
TP_FAN_TACH5 5A7> TP_I2C_SMU_D_SCL 5A7> TP_LVDS_L3N 39A5> TP_LVDS_L3P 39A5> TP_LVDS_U3N 39A5>
TP_LVDS_U3P 39A5> TP_NB_PMR_OBSV 5A7> TP_NB_PM_SLEEP0 22C5<> TP_NB_THMI 5A7> TP_NB_THMO 5A7> TP_NEC_AMC 48A3<
TP_NEC_NANDTEST 48A3<
TP_NEC_NTEST1 48B3< TP_NEC_SMC 48B3<
TP_NEC_SMI_L 48A5> TP_NEC_SRCLK 48A3> TP_NEC_SRDATA 48A3<> TP_NEC_SRMOD 48A3< TP_NEC_TEB 48B3<
TP_NEC_TEST 48A3< TP_PLS_CLK_66M_0 25C1< TP_PLS_CLK_66M_1 25C1< TP_PLS_REF_CML 25B6<> TP_PLS_TEST1 25B6<> TP_PLS_TEST2 25B6<>
TP_PLS_TEST3 25B6<> TP_PROC_SENSE_COMMON 32C5<> TP_PROC_TRIGGER_OUT 27B8<> TP_PSRO1 27B8<> TP_PSRO2 27B8<>
TP_PSYNCOUT 27B8<> TP_RAM_CKE_R<2> 5A6> TP_RAM_CKE_R<3> 5A6> TP_RAM_CKE_R<6> 5A6> TP_RAM_CKE_R<7> 5A6> TP_RAM_CLK_C_N 34D7>
TP_RAM_CLK_C_P 34D7> TP_RAM_CLK_F_N 34D7> TP_RAM_CLK_F_P 34D7> TP_RAM_CS_L_R<2> 5A6> TP_RAM_CS_L_R<3> 5A6>
TP_RAM_CS_L_R<10> 5A6> TP_RAM_CS_L_R<11> 5A6> TP_RAM_MUXEN0 5A5> TP_RAM_MUXEN4 5A5> TP_SATABR_CLK25M_XTLOUT 51B5> TP_SATABR_T7 51C5<>
TP_SATABR_UAI 51C5< TP_SATABR_UAO 51C5> TP_SATA_CLK25M 25B1< TP_SATA_RXD_N2 5A7> TP_SATA_RXD_P2 5A7>
TP_SATA_TXD_N2 5A7> TP_SATA_TXD_P2 5A7> TP_SB_FSTEST 23A5> TP_SB_NC_P7 59B7<> TP_SB_NC_P8 59B7<> TP_SB_NC_R3 59B7<>
TP_SB_NC_R4 59B7<> TP_SB_NC_R5 59B7<> TP_SB_NC_R6 59B7<> TP_SB_NC_R7 59B7<> TP_SB_NC_R8 59B7<>
TP_SB_NC_T1 59B7<> TP_SB_NC_T2 59B7<> TP_SB_NC_T3 59B7<> TP_SB_NC_T4 59B7<> TP_SB_NC_T5 59B7<> TP_SB_NC_T6 59B7<>
TP_SB_NC_T7 59B7<> TP_SB_NC_T8 59B7<> TP_SB_NC_U1 59B7<> TP_SB_NC_U2 59B7<> TP_SB_NC_U3 59B7<>
TP_SB_NC_U4 59B7<> TP_SB_NC_U5 59B7<> TP_SB_NC_U6 59B7<> TP_SB_NC_V1 59B7<> TP_SB_NC_V2 59B7<> TP_SB_NC_V3 59B7<>
TP_SB_NC_V4 59A7<> TP_SB_NC_W1 59A7<> TP_SB_NC_W3 59A7<> TP_SB_NC_Y1 59A7<> TP_SB_NC_Y3 59A7<>
TP_SB_PLLTEST 23A5> TP_SB_WATCHDOG 23B5> TP_SMU_SPARE_P8_3 13C3<> TP_SMU_SPARE_P10_0 13B3<> TP_USB2_PWREN2 5B7> TP_USB2_PWREN3 5B7>
TP_USB2_PWREN4 5B7> TP_VESTA_2_5V_EN 12A3< TP_VESTA_ACTLED_L 54B3> TP_VESTA_AN_EN 54B3<> TP_VESTA_DNC_B9 12A6<>
TP_VESTA_DNC_C9 12A6<> TP_VESTA_DNC_E9 12A6<> TP_VESTA_EN_10B 54B5< TP_VESTA_ER 54B5< TP_VESTA_ESDET<0> 57C5< TP_VESTA_ESDET<1> 57C5<
TP_VESTA_ESDET<2> 57C5< TP_VESTA_F1000 54B5< TP_VESTA_FDX 54B5< TP_VESTA_FDXLED_L 54B3> TP_VESTA_HUB 54B5<
TP_VESTA_LINK1_L 54B3> TP_VESTA_LINK2_L 54B3> TP_VESTA_MANMS 54B5< TP_VESTA_PHYA<0> 54B5< TP_VESTA_PHYA<1> 54B5< TP_VESTA_PHYA<2> 54B5<
TP_VESTA_PHYA<3> 54B5< TP_VESTA_PHYA<4> 54B5< TP_VESTA_RBC0 54B3<> TP_VESTA_RBC1 54B3<> TP_VESTA_REGCTL1 12A3<
TP_VESTA_REGCTL2 12A3< TP_VESTA_REGSEN1 12A3< TP_VESTA_REGSEN2 12A3< TP_VESTA_REGSUP1 12A3< TP_VESTA_REGSUP2 12A3< TP_VESTA_RGMIIEN 54B5<
TP_VESTA_SPD0 54B5< TP_VESTA_TDBL<0> 57C3> TP_VESTA_TDBL<1> 57C3> TP_VESTA_TDBL<2> 57C3> TP_VESTA_TEST<0> 54B5<
TP_VESTA_TEST<1> 54B5< TP_VESTA_TEST_1394<0> 57B5< TP_VESTA_TEST_1394<1> 57B5< TP_VESTA_TVCO 54B5<> TP_VESTA_TVCO_24 57B5<> TP_VESTA_TXC_RXC_DELAY 54B3<>
TP_VESTA_XMTLED_L 54B3> TP_VREF_CG 36B4<> TV_C 6D5> 42A6<> TV_COMP 6D5> 42A6<> TV_GND1 6D5> 42B6<>
TV_GND2 6D5> 42A6<> TV_Y 6D5> 42A6<> UATA_CS0_L 6B4> 50B1< 50D6> 52B5<> UATA_CS0_L_R 50B2< 50B4> UATA_CS1_L 6B4> 50B1< 50D6> 52B7<> UATA_CS1_L_R 50B2< 50B4>
UATA_DA<0> 6C4> 50B1< 52B5<> UATA_DA<2..0> 50D6> UATA_DA<1> 6B4> 50B1< 52B5<> UATA_DA<2> 6B4> 50B1< 52B7<> UATA_DA_R<0> 50B2< 50B4>
UATA_DA_R<1> 50B2< 50B4> UATA_DA_R<2> 50B2< 50B4> UATA_DD<0> 6D4> 50D1< 52B5<> UATA_DD<6..0> 50D6> UATA_DD<1> 6D4> 50D1< 52B5<> UATA_DD<2> 6D4> 50D1< 52B5<>
UATA_DD<3> 6D4> 50D1< 52B5<> UATA_DD<4> 6D4> 50D1< 52C5<> UATA_DD<5> 6D4> 50D1< 52C5<> UATA_DD<6> 6C4> 50C1< 52C5<> UATA_DD<7> 6C4> 50C1< 50D6> 52C5<>
UATA_DD<8> 6C4> 50C1< 52C7<> UATA_DD<15..8> 50D6> UATA_DD<9> 6C4> 50C1< 52C7<> UATA_DD<10> 6C4> 50C1< 52C7<> UATA_DD<11> 6C4> 50C1< 52C7<> UATA_DD<12> 6C4> 50C1< 52B7<>
UATA_DD<13> 6C4> 50C1< 52B7<> UATA_DD<14> 6C4> 50B1< 52B7<> UATA_DD<15> 6C4> 50B1< 52B7<> UATA_DD_R<0> 50C4<> 50D2< UATA_DD_R<1> 50C4<> 50D2<
UATA_DD_R<2> 50B4<> 50D2< UATA_DD_R<3> 50B4<> 50D2< UATA_DD_R<4> 50B4<> 50D2< UATA_DD_R<5> 50B4<> 50D2< UATA_DD_R<6> 50B4<> 50C2< UATA_DD_R<7> 50B4<> 50C2<
UATA_DD_R<8> 50B4<> 50C2<
UATA_DD_R<9> 50B4<> 50C2< UATA_DD_R<10> 50B4<> 50C2<
UATA_DD_R<11> 50B4<> 50C2< UATA_DD_R<12> 50B4<> 50C2< UATA_DD_R<13> 50B4<> 50C2< UATA_DD_R<14> 50B2< 50B4<> UATA_DD_R<15> 50B2< 50B4<>
UATA_DMACK_L 6C4> 50A1< 50D6> 52B7<> UATA_DMACK_L_R 50A2< 50B4> UATA_DMARQ 50B5< 50C6> 52B8< UATA_DMARQ_R 6C4> 52B7<> UATA_DSTROBE 50B5< 50D6> 52B5< UATA_DSTROBE_R 6B4> 52B6<>
UATA_HSTROBE 6B4> 50B1< 50D6> 52B7<> UATA_HSTROBE_R 50B2< 50B4> UATA_INTRQ 50B5< 50C6> 52B5< UATA_INTRQ_R 6B4> 52B6<> UATA_RESET_L 6B4> 50B1< 50D6> 52C5<>
UATA_RESET_L_R 50B2< 50B4> UATA_STOP 6B4> 50A1< 50D6> 52B5<> UATA_STOP_R 50A2< 50B4> UDASH_RESET_L 23B3<> 23D2< UDASH_SDOWN 6A2> 23B3<> 60B3<> USB2_LT_N 5C7> 17D6<>
USB2_LT_P 5C7> 17D6<> USB2_N<0> 5C8< 6B3> 59C2<> 59D6> USB2_N<1> 5C8< 6A3> 59C2<> 59D6> USB2_N<2> 5B8< 6B3> 59B2<> 59D6> USB2_N<3> 5B8< 6B2> 59B2<> 59D6>
USB2_N<4> 5B8< 6A4> 59A2<> 59D6> USB2_OC2_PU 5B7> USB2_OC3_PU 5B7> USB2_OC4_PU 5B7> USB2_OC<0> 5C8< 6B3> 59B6< USB2_OC<1> 5C8< 6A3> 59B6<
USB2_OC<2> 5B8< 59B6< USB2_OC<3> 5B8< 59B6< USB2_OC<4> 5B8< 59B6< USB2_P<0> 5C8< 6B3> 59C2<> 59D6> USB2_P<1> 5C8< 6A3> 59C2<> 59D6>
USB2_P<2> 5B8< 6B3> 59B2<> 59D6> USB2_P<3> 5B8< 6A2> 59B2<> 59D6> USB2_P<4> 5B8< 6A4> 59A2<> 59D6> USB2_PWREN<0> 5C8< 6B3> 59B5> USB2_PWREN<1> 5C8< 6A3> 59B5> USB2_PWREN<2> 5B8< 59B5>
USB2_PWREN<3> 5B8< 59B5> USB2_PWREN<4> 5B8< 59B5> USB2_RT_N 5C7> 17A3<> USB2_RT_P 5C7> 17A3<> USB_BT_N 5B7> 17D6<>
USB_BT_P 5B7> 17D6<> USB_MODEM_N 5B7> 60B5<> USB_MODEM_P 5B7> 60B5<> USB_NEC_N<0> 59C3<> USB_NEC_N<1> 59C3<> USB_NEC_N<2> 59B3<>
USB_NEC_N<3> 59B3<> USB_NEC_N<4> 59A3<> USB_NEC_P<0> 59C3<> USB_NEC_P<1> 59C3<> USB_NEC_P<2> 59B3<>
USB_NEC_P<3> 59B3<> USB_NEC_P<4> 59A3<> USB_TPAD_N 5B7> 17A8<> USB_TPAD_P 5B7> 17A8<> VCORE_SWITCHING 14A6> 31B4< VESTA1V2_ITH 12C2<>
VESTA1V2_ITH_RC 12C2< VESTA1V2_MODE 12C3<> VESTA1V2_RT 12C3<> VESTA1V2_SGND 12B2<> VESTA1V2_SW 12C2<>
VESTA1V2_VFB 12C2<> VESTA2V5_NOISE 12D2<> VESTA_CLK24M_XTALI 57B5< 57D6> VESTA_CLK24M_XTALO 57A4< 57D6> VESTA_CLK24M_XTALO_R 57B5<> 57D6> VESTA_CLK25M_XTALI 54B5< 54D6>
VESTA_CLK25M_XTALO 54A4< 54D6> VESTA_CLK25M_XTALO_R 54B5<> 54D6> VESTA_DS_ONLY_EN0 57B5< VESTA_ENET_LOWPWR 12C6<> 54B5< VESTA_PWR_CLASS 57B5<
VESTA_RDAC1_PD 54B3<> VESTA_RDAC2_PD 57B3<> VESTA_RESET_L 12A6< VGA_B 6C7> 42C6<> 42D7< VGA_G 6C7> 42C5<> 42D7< VGA_HSYNC 6C7> 42C6<> 42C7<
VGA_HSYNC_BUF 42C8<> VGA_R 6C7> 42C5<> 42D7< VGA_VSYNC 6C7> 42C5<> 42C7< VGA_VSYNC_BUF 42C8<> VSP_NB_CLK_N 22D6<> 25D1< 25D8<
VSP_NB_CLK_N_C 25C4<> VSP_NB_CLK_P 22D6<> 25D1< 25D8< VSP_NB_CLK_P_C 25C4<> _GND_CHASSIS_DVI_BOTTOM 5A3> 42C5<> _GND_CHASSIS_DVI_TOP 5A3> 42C4<> _GND_CHASSIS_ENET 5A3> 55A3<>
_GND_CHASSIS_FW_PORT1 5A3> 58C1<> _GND_CHASSIS_FW_PORT2 5A3> 58A2<> _GND_CHASSIS_INV 5A3> 42A1< 42A2< _GND_CHASSIS_LVDS 5A3> 42A4< 42A4<> 42B3<> _GND_CHASSIS_SVIDEO 5A3> 42A7<>
_GPU_RESET_L 5D7> 37C8< 41C8< _PCI_CBUS_RESET_L 5D7> 49A7< _PCI_CLK33M_AIRPORT 5D7> 47C4<> 47D6> _PCI_CLK33M_CBUS 5D7> 49A6< 49D6> _PCI_CLK33M_USB2 5D7> 48B5< 48D6> _PP1V2_ENETFW 12C1> 54D2< 57C1< 57D5<
_PP1V2_PWRON_1V2RUN 5B3> 9B3<> _PP1V2_PWRON_DISK_SB 5B3> 50C6< _PP1V2_PWRON_HT 5B3> 44A6< 44C3< 44D3< 44D6< _PP1V2_PWRON_REG 5B5< 9A3< _PP1V2_PWRON_SB 5B3> 23D2<
_PP1V2_RUN_FET 5B2<> 9B2<> _PP1V5_GPU_AGP 5A5< 37D6< 39A1<> 39D5<> 40C8<
40D3<> _PP1V5_PWRON_1V5RUN 5B3> 9C3<> _PP1V5_PWRON_REG 5B5< 9C4< _PP1V5_RUN_FET 5A3<> 5B2< 9C2<>
_PP1V8_GPU 5B5< 37A8< 39C8< 40A2< 40A7< 40B1<40C7< 40C7< 40D3<> 40D6< 41A5<
_PP1V8_RUN_LDO 5C2< 9D5<> _PP1V8_SATABR 5B1> 51D3< _PP2V5_ENET 5C3> 55C6<>
_PP2V5_ENETFW 12D1> 54D5< 57D1< 57D5< _PP2V5_GPU 5B6< 40A7< 40B8< 40D3<> 40D7<
40D8< _PP2V5_PCI 5C1> 49C7< _PP2V5_PWRON_1V8RUN 5C3> 9D7< _PP2V5_PWRON_2V5RUN 5C3> 11D2<>
_PP2V5_PWRON_DIMM 5C3> 35B3< 35C3< 35D2< 35D3<>35D5<> 35D5<> 35D7<>
_PP2V5_PWRON_HT 5C3> 44D3< _PP2V5_PWRON_REG 5C5< 11C1< _PP2V5_PWRON_SB 5C3> 21B2< 21C2< 23D6< 45C3< 56C6<
_PP2V5_RUN_FET 5C2< 11D1<> _PP3V3_ALL_ACIN 5D1> 7D5<> _PP3V3_ALL_DCILIM 5D1> _PP3V3_ALL_HALLEFFECT 5D1> 17B7<> _PP3V3_ALL_LDO 5D3< 11A3<
_PP3V3_ALL_RTC 5D1> 13D2< _PP3V3_ALL_SMU 5D1> 13B7< 13C2< 13D2< 13D6<
16C4<> 18B4< _PP3V3_CBUS 5C3> 49D3< _PP3V3_CPUTHERM 5C3> 32A7<
_PP3V3_CPUVCORE 5C1> 31D8< _PP3V3_ENET 12D3> 54C6< _PP3V3_ENETFW 12D3> 57D1< _PP3V3_FW 12D3> 57A4< 57C6< 58A8< _PP3V3_GPU 5B5< 37B3< 37C8< 37C8< 37D3< 37D6<
39B6< 39B7< 39C4< 39C8< 40B1< 40D1<>
_PP3V3_PATA 5C1> 52C4< _PP3V3_PCI 5C1> 23B8< 45B1< 45B8< 46B6<
46C5<> 47C5<> 48B6< 49C8< 49D7< _PP3V3_PWRON_1V8RUN 5C3> 9D7<
_PP3V3_PWRON_3V3RUN 5C3> 10B4<> _PP3V3_PWRON_ALS1 5C3> 19D7< _PP3V3_PWRON_AUDIO 5C3> 61C1< 61C3<> _PP3V3_PWRON_BT 5C3> 17D7<> _PP3V3_PWRON_MODEM 5C3> 60C5<> _PP3V3_PWRON_REG 5C5< 10C1<
_PP3V3_PWRON_SB 5C3> 18A8< 21B7< 23B6< 23C1<23C3<> 23D1< 45A3<
_PP3V3_PWRON_THERM 5C3> 15D5< _PP3V3_PWRON_USB 5C3> 59B6< 59C6< 59D5< _PP3V3_RUN_FAN 5C1> 15B2< 15C2< _PP3V3_RUN_FET 5C3< 10B3<> _PP3V3_RUN_SI 5C1> 41D5<
_PP3V3_SATABR 5C1> 51B7< 51D2< 51D6<> _PP3V3_SB_PCI 5C1> 45C7< _PP5V_CBUS 5D3> 49D3< _PP5V_CPUTHERM 5D3> 32D6< _PP5V_CPUVCORE_VDD 5D3> 31D5<> _PP5V_PATA 5D1> 52C4<>
_PP5V_PWRON_3V3ALL 5D3> 11A5<> _PP5V_PWRON_5VRUN 5D3> 10B7<> _PP5V_PWRON_AUDIO 5D3> 61C6<> _PP5V_PWRON_FAN 5D3> 15B2<> 15C2<> _PP5V_PWRON_GPUVCORE 5D3> 38D7<>
_PP5V_PWRON_LTUSB 5D3> 17D7<> _PP5V_PWRON_MODEM 5D3> 60C4<> _PP5V_PWRON_REG 5D5< 10C8< _PP5V_PWRON_RTUSB 5D3> 17A3<> _PP5V_PWRON_SERIAL 5D3> 16C3<> _PP5V_PWRON_SLEEPLED 5D3> 19B4<
_PP5V_PWRON_TPAD 5D3> 17B7<> _PP5V_RUN_AUDIO 5D1> 61C6<> _PP5V_RUN_FET 5D3< 10A5<> _PP5V_RUN_HD_FET 5D3< 10B5<> _PP5V_RUN_KBDLED 5D1> 19B7<
_PP5V_UATA 5D1> 52C7<> _PPBUSA_BBATT 5D6> 17A3<> _PPBUSB_BBATT 5D6> 17A3<> _PPBUS_ALL_A 5D6> 8B5<> 8C2<> 8D3<> 17D2<
42C2<> _PPBUS_ALL_B 5D6> 8C1<> 8D5<> 17D2<
_PPBUS_FW 5D6> 12D7< _PPBUS_INV 5D6> 42B2< _PPBU_RUN_FW 5D1> 12D5<> _PPFW_PHY 12C5> 57C5< _PPFW_PORT1 12C5> 58D3<
_PPFW_PORT2 12C5> 58B4< _PPPCI32_PWRON_SB 5C3> 21C2<> _PPPCI64_PWRON_SB 5C3> 21C2<> _PPSPD_DIMM 5C3> 35A3<> 35A4<> 35A7<> _PPVCORE_CPU_REG 5C7< 31D2<> 32C8<> 32C8<> _PPVCORE_GPUFB 5B6< 37A6<> 37B8< 40B8< 40C3<
40C8< _PPVCORE_GPU_REG 5C7< 38C1<> _PPVCORE_NB_REG 5B5< 11C8< _PPVCORE_PWRON_NB 5B3> 20D6< _PPVCORE_PWRON_SB 5B3> 21C7<
_PPVIN_1V2PWRON 5D3> 9B7< _PPVIN_1V5PWRON 5C3> 9C7< _PPVIN_2V5_NBVCORE_PWRON 5D6> 11D5<> _PPVIN_5V3VPWRON 5D6> 10D7<> _PPVIN_CPUVCORE 5D6> 31D6<> _PPVIN_GPUVCORE 5D6> 38D4<> 38D7<>
_PPVIO_PCI_CBUS 5C1> 49D4< _PPVIO_PCI_USB2 5C1> 48D5< _PPVREF_SMU 5D1> 13B6< _SATA_CLK25M 5C7> 51B5< 51D6>
051-6532 03
103101
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE 102
*** Part Cross-Reference for the entire design ***
BS510 PCB_STANDOFF 17 C700 CAP 7 C710 CAP 7 C720 CAP 7 C800 CAP 8
C801 CAP 8 C802 CAP 8 C805 CAP 8 C806 CAP 8 C807 CAP 8 C808 CAP 8
C811 CAP 8 C812 CAP 8 C813 CAP 8 C814 CAP 8 C815 CAP 8
C816 CAP 8 C817 CAP 8 C818 CAP_P 8 C820 CAP 8 C822 CAP 8 C823 CAP 8
C824 CAP 8 C825 CAP 8 C826 CAP 8 C827 CAP 8 C828 CAP 8
C829 CAP 8 C830 CAP 8 C831 CAP 8 C851 CAP 8 C860 CAP_P 17 C861 CAP_P 17
C862 CAP_P 17 C863 CAP_P 17 C864 CAP_P 17 C865 CAP_P 17 C882 CAP 8
C897 CAP 8 C940 CAP 9 C941 CAP 9 C942 CAP 9 C950 CAP 9 C951 CAP 9
C952 CAP 9 C953 CAP 9 C954 CAP 9 C955 CAP 9 C956 CAP 9
C957 CAP 9 C960 CAP 9 C961 CAP 9 C970 CAP 9 C971 CAP 9 C972 CAP 9
C980 CAP 9 C981 CAP 9 C1001 CAP_P 10 C1003 CAP 10 C1004 CAP_P 10
C1005 CAP 10 C1006 CAP 10 C1009 CAP 10 C1011 CAP 10 C1012 CAP 10 C1013 CAP_P 10
C1031 CAP 10 C1035 CAP 10 C1050 CAP 10 C1051 CAP 10 C1052 CAP 10
C1053 CAP 10 C1054 CAP 10 C1055 CAP 10 C1056 CAP 10 C1057 CAP 10 C1058 CAP 10
C1059 CAP 10 C1060 CAP 10 C1061 CAP 10 C1062 CAP 10 C1063 CAP 10
C1065 CAP 10 C1066 CAP 10 C1067 CAP 10 C1068 CAP 10 C1070 CAP 10 C1071 CAP 10
C1072 CAP 10 C1074 CAP_P 10 C1075 CAP_P 10 C1076 CAP 10 C1077 CAP 10
C1080 CAP 10 C1081 CAP 10 C1082 CAP 10 C1085 CAP 10 C1086 CAP 10 C1087 CAP_P 10
C1100 CAP 11 C1101 CAP 11 C1102 CAP 11 C1103 CAP 11 C1104 CAP 11
C1105 CAP 11 C1106 CAP 11 C1107 CAP 11 C1108 CAP 11 C1109 CAP 11 C1110 CAP 11
C1111 CAP 11 C1112 CAP 11 C1113 CAP 11 C1115 CAP 11 C1116 CAP 11
C1117 CAP 11 C1118 CAP 11 C1120 CAP 11 C1121 CAP 11 C1122 CAP 11 C1125 CAP_P 11
C1126 CAP 11 C1127 CAP 11 C1131 CAP 11 C1135 CAP 11 C1140 CAP 11
C1141 CAP 11 C1142 CAP 11 C1145 CAP 11 C1146 CAP 11 C1147 CAP_P 11 C1148 CAP_P 11
C1160 CAP 11 C1161 CAP 11 C1162 CAP 11 C1164 CAP 11 C1170 CAP 11
C1171 CAP 11 C1190 CAP 11 C1192 CAP 11 C1193 CAP_P 11 C1200 CAP 12 C1201 CAP 12
C1202 CAP 12 C1203 CAP 12 C1208 CAP 12 C1210 CAP 12 C1211 CAP 12
C1212 CAP 12 C1213 CAP 12 C1220 CAP 12 C1221 CAP 12 C1222 CAP 12 C1223 CAP 12
C1224 CAP 12 C1225 CAP 12 C1230 CAP 12 C1231 CAP 12 C1240 CAP 12
C1241 CAP 12 C1242 CAP 12 C1243 CAP 12 C1250 CAP 12 C1265 CAP 12 C1270 CAP 12
C1271 CAP_P 12
C1280 CAP 12 C1281 CAP 12
C1282 CAP 12 C1290 CAP 12 C1291 CAP 12 C1292 CAP 12 C1293 CAP 12
C1294 CAP 12 C1295 CAP 12 C1300 CAP 13 C1301 CAP 13 C1302 CAP 13 C1303 CAP 13
C1304 CAP 13 C1305 CAP 13 C1308 CAP 13 C1309 CAP 13 C1310 CAP 13
C1325 CAP 13 C1500 CAP 15 C1501 CAP 15 C1502 CAP 15 C1503 CAP 15 C1504 CAP 15
C1505 CAP 15 C1506 CAP 15 C1507 CAP 15 C1508 CAP 15 C1510 CAP 15
C1515 CAP 15 C1520 CAP 15 C1525 CAP 15 C1530 CAP 15 C1535 CAP 15 C1540 CAP 15
C1591 CAP 15 C1592 CAP 15 C1605 CAP 17 C1610 CAP 17 C2015 CAP 18
C2016 CAP 18 C2110 CAP 19 C2111 CAP 19 C2112 CAP 19 C2115 CAP 19 C2150 CAP 19
C2151 CAP 19 C2152 CAP 19 C2199 CAP 19 C2222 CAP 20 C2223 CAP 20
C2224 CAP 20 C2225 CAP 20 C2226 CAP 20 C2227 CAP 20 C2228 CAP 20 C2229 CAP 20
C2230 CAP 20 C2231 CAP 20 C2232 CAP 20 C2233 CAP 20 C2234 CAP 20
C2235 CAP 20 C2236 CAP 20 C2237 CAP 20 C2238 CAP 20 C2239 CAP 20 C2240 CAP 20
C2241 CAP 20 C2242 CAP 20 C2243 CAP 20 C2244 CAP 20 C2245 CAP 20
C2246 CAP 20 C2247 CAP 20 C2300 CAP 21 C2301 CAP 21 C2302 CAP 21 C2303 CAP 21
C2304 CAP 21 C2305 CAP 21 C2306 CAP 21 C2307 CAP 21 C2308 CAP 21
C2309 CAP 21 C2310 CAP 21 C2311 CAP 21 C2312 CAP 21 C2313 CAP 21 C2314 CAP 21
C2320 CAP 21 C2321 CAP 21 C2322 CAP 21 C2323 CAP 21 C2324 CAP 21
C2325 CAP 21 C2326 CAP 21 C2327 CAP 21 C2328 CAP 21 C2329 CAP 21 C2330 CAP 21
C2331 CAP 21 C2332 CAP 21 C2333 CAP 21 C2334 CAP 21 C2335 CAP 21
C2336 CAP 21 C2337 CAP 21 C2338 CAP 21 C2339 CAP 21 C2350 CAP 21 C2351 CAP 21
C2355 CAP 21 C2356 CAP 21 C2357 CAP 21 C2360 CAP 21 C2361 CAP 21
C2362 CAP 21 C2365 CAP 21 C2400 CAP 22 C2401 CAP 22 C2500 CAP 23 C2501 CAP 23
C2510 CAP 23 C2511 CAP 23 C2520 CAP 23 C2521 CAP 23 C2530 CAP 23
C2531 CAP 23 C2540 CAP 23 C2590 CAP 23 C2591 CAP 23 C2601 CAP 24 C2603 CAP 24
C2605 CAP 24 C2607 CAP 24 C2609 CAP 24 C2611 CAP 24 C2613 CAP 24
C2615 CAP 24 C2617 CAP 24 C2619 CAP 24 C2620 CAP 24 C2621 CAP 24 C2622 CAP 24
C2623 CAP 24 C2624 CAP 24 C2625 CAP 24 C2626 CAP 24 C2627 CAP 24
C2628 CAP 24 C2629 CAP 24 C2630 CAP 24 C2631 CAP 24 C2632 CAP 24 C2633 CAP 24
C2634 CAP 24 C2635 CAP 24 C2636 CAP 24 C2637 CAP 24 C2638 CAP 24
C2639 CAP 24 C2640 CAP 24 C2645 CAP 24 C2651 CAP 24 C2665 CAP 24 C2667 CAP 24
C2669 CAP 24
C2671 CAP 24 C2700 CAP 25
C2702 CAP 25 C2705 CAP 25 C2707 CAP 25 C2708 CAP 25 C2710 CAP 25
C2713 CAP 25 C2715 CAP 25 C2800 CAP 26 C2801 CAP 26 C2802 CAP 26 C2803 CAP 26
C2804 CAP 26 C2805 CAP 26 C2806 CAP 26 C2807 CAP 26 C2808 CAP 26
C2809 CAP 26 C2810 CAP 26 C2811 CAP 26 C2812 CAP 26 C2813 CAP 26 C2814 CAP 26
C2815 CAP 26 C2816 CAP 26 C2817 CAP 26 C2818 CAP 26 C2819 CAP 26
C2820 CAP 26 C2821 CAP 26 C2900 CAP 27 C2901 CAP 27 C2902 CAP 27 C2903 CAP 27
C2904 CAP 27 C2905 CAP 27 C2906 CAP 27 C2907 CAP 27 C2908 CAP 27
C2909 CAP 27 C2910 CAP 27 C2911 CAP 27 C2912 CAP 27 C2913 CAP 27 C2914 CAP 27
C2915 CAP 27 C2916 CAP 27 C2917 CAP 27 C2918 CAP 27 C2919 CAP 27
C2920 CAP 27 C2921 CAP 27 C2922 CAP 27 C2923 CAP 27 C2924 CAP 27 C2925 CAP 27
C2926 CAP 27 C2927 CAP 27 C2928 CAP 27 C2929 CAP 27 C2930 CAP 27
C2931 CAP 27 C2932 CAP 27 C2933 CAP 27 C2934 CAP 27 C2935 CAP 27 C2936 CAP 27
C2937 CAP 27 C2938 CAP 27 C2939 CAP 27 C2940 CAP 27 C2941 CAP 27
C2942 CAP 27 C2943 CAP 27 C2944 CAP 27 C2945 CAP 27 C2946 CAP 27 C2947 CAP 27
C2948 CAP 27 C2949 CAP 27 C2950 CAP 27 C2951 CAP 27 C2952 CAP 27
C2953 CAP 27 C2954 CAP 27 C2955 CAP 27 C2956 CAP 27 C2957 CAP 27 C2958 CAP 27
C2959 CAP 27 C2960 CAP 27 C3100 CAP 29 C3101 CAP 29 C3102 CAP 29
C3103 CAP 29 C3104 CAP 29 C3105 CAP 29 C3106 CAP 29 C3107 CAP 29 C3108 CAP 29
C3109 CAP 29 C3110 CAP 29 C3111 CAP 29 C3112 CAP 29 C3113 CAP 29
C3114 CAP 29 C3115 CAP 29 C3116 CAP 29 C3117 CAP 29 C3118 CAP 29 C3119 CAP 29
C3120 CAP 29 C3121 CAP 29 C3122 CAP 29 C3123 CAP 29 C3124 CAP 29
C3125 CAP 29 C3126 CAP 29 C3127 CAP 29 C3128 CAP 29 C3129 CAP 29 C3130 CAP 29
C3131 CAP 29 C3132 CAP 29 C3133 CAP 29 C3134 CAP 29 C3135 CAP 29
C3136 CAP 29 C3137 CAP 29 C3138 CAP 29 C3139 CAP 29 C3140 CAP 29 C3141 CAP 29
C3142 CAP 29 C3143 CAP 29 C3144 CAP 29 C3145 CAP 29 C3146 CAP 29
C3147 CAP 29 C3148 CAP 29 C3149 CAP 29 C3150 CAP 29 C3199 CAP 29 C3200 CAP 30
C3201 CAP 30 C3202 CAP 30 C3203 CAP 30 C3204 CAP 30 C3205 CAP 30
C3206 CAP 30 C3207 CAP 30 C3208 CAP 30 C3209 CAP 30 C3210 CAP 30 C3211 CAP 30
C3212 CAP 30 C3213 CAP 30 C3214 CAP 30 C3215 CAP 30 C3216 CAP 30
C3217 CAP 30 C3218 CAP 30 C3219 CAP 30 C3220 CAP 30 C3221 CAP 30 C3222 CAP 30
C3223 CAP 30
C3224 CAP 30 C3225 CAP 30
C3226 CAP 30 C3227 CAP 30 C3228 CAP 30 C3229 CAP 30 C3230 CAP 30
C3231 CAP 30 C3232 CAP 30 C3233 CAP 30 C3234 CAP 30 C3235 CAP 30 C3236 CAP 30
C3237 CAP 30 C3238 CAP 30 C3239 CAP 30 C3240 CAP 30 C3241 CAP 30
C3242 CAP 30 C3243 CAP 30 C3244 CAP 30 C3245 CAP 30 C3246 CAP 30 C3247 CAP 30
C3248 CAP 30 C3249 CAP 30 C3250 CAP 30 C3251 CAP 30 C3252 CAP 30
C3253 CAP 30 C3254 CAP 30 C3255 CAP 30 C3256 CAP 30 C3257 CAP 30 C3258 CAP 30
C3259 CAP 30 C3260 CAP 30 C3261 CAP 30 C3262 CAP 30 C3263 CAP 30
C3264 CAP 30 C3265 CAP 30 C3266 CAP 30 C3267 CAP 30 C3268 CAP 30 C3269 CAP 30
C3270 CAP 30 C3271 CAP 30 C3272 CAP 30 C3273 CAP 30 C3274 CAP 30
C3275 CAP 30 C3276 CAP 30 C3277 CAP 30 C3278 CAP 30 C3279 CAP 30 C3280 CAP 30
C3281 CAP 30 C3282 CAP 30 C3283 CAP 30 C3284 CAP 30 C3285 CAP 30
C3286 CAP 30 C3287 CAP 30 C3288 CAP 30 C3289 CAP 30 C3290 CAP 30 C3291 CAP 30
C3292 CAP 30 C3293 CAP 30 C3294 CAP 30 C3295 CAP 30 C3296 CAP 30
C3297 CAP 30 C3298 CAP 30 C3299 CAP 30 C3300 CAP 31 C3301 CAP 31 C3302 CAP 31
C3303 CAP 31 C3304 CAP 31 C3306 CAP 31 C3310 CAP 31 C3311 CAP 31
C3312 CAP 31 C3313 CAP 31 C3315 CAP 31 C3316 CAP 31 C3319 CAP 31 C3320 CAP 31
C3321 CAP 31 C3322 CAP 31 C3323 CAP 31 C3325 CAP 31 C3326 CAP 31
C3329 CAP 31 C3330 CAP 31 C3332 CAP 31 C3333 CAP 31 C3350 CAP 31 C3351 CAP 31
C3352 CAP 31 C3353 CAP 31 C3354 CAP 31 C3355 CAP 31 C3356 CAP 31
C3357 CAP 31 C3359 CAP 31 C3360 CAP_P 31 C3361 CAP_P 31 C3362 CAP_P 31 C3363 CAP_P 31
C3364 CAP_P 31 C3365 CAP_P 31 C3366 CAP_P 31 C3367 CAP_P 31 C3370 CAP 31
C3371 CAP 31 C3372 CAP 31 C3373 CAP 31 C3374 CAP 31 C3375 CAP 31 C3376 CAP 31
C3377 CAP 31 C3378 CAP 31 C3379 CAP 31 C3380 CAP 31 C3381 CAP 31
C3382 CAP 31 C3383 CAP 31 C3384 CAP 31 C3385 CAP 31 C3386 CAP 31 C3387 CAP 31
C3388 CAP 31 C3389 CAP 31 C3391 CAP 31 C3392 CAP 31 C3393 CAP 31
C3394 CAP 31 C3395 CAP 31 C3396 CAP 31 C3397 CAP 31 C3398 CAP 31 C3399 CAP 31
C3630 CAP 32 C3631 CAP 32 C3636 CAP 32 C3639 CAP 32 C3640 CAP 32
C3650 CAP 32 C3651 CAP 32 C3660 CAP 32 C3669 CAP 32 C3670 CAP 32 C3671 CAP 32
C3676 CAP 32 C3679 CAP 32 C3698 CAP 32 C3699 CAP 32 C3700 CAP 33
C3701 CAP 33 C3702 CAP 33 C3703 CAP 33 C3704 CAP 33 C3705 CAP 33 C3706 CAP 33
C3707 CAP 33
C3708 CAP 33 C3709 CAP 33
C3710 CAP 33 C3711 CAP 33 C3712 CAP 33 C3713 CAP 33 C3714 CAP 33
C3715 CAP 33 C3716 CAP 33 C3717 CAP 33 C3718 CAP 33 C3719 CAP 33 C3720 CAP 33
C3721 CAP 33 C3722 CAP 33 C3724 CAP 33 C3725 CAP 33 C3726 CAP 33
C3727 CAP 33 C3728 CAP 33 C3729 CAP 33 C3730 CAP 33 C3731 CAP 33 C3732 CAP 33
C3733 CAP 33 C3734 CAP 33 C3735 CAP 33 C3736 CAP 33 C3737 CAP 33
C3738 CAP 33 C3739 CAP 33 C3740 CAP 33 C3742 CAP 33 C3743 CAP 33 C3744 CAP 33
C3745 CAP 33 C3746 CAP 33 C3747 CAP 33 C3748 CAP 33 C4001 CAP 35
C4002 CAP 35 C4008 CAP 35 C4009 CAP 35 C4010 CAP 35 C4011 CAP 35 C4012 CAP 35
C4013 CAP 35 C4014 CAP 35 C4015 CAP 35 C4016 CAP 35 C4017 CAP 35
C4018 CAP 35 C4019 CAP 35 C4020 CAP 35 C4021 CAP 35 C4022 CAP 35 C4023 CAP 35
C4024 CAP 35 C4025 CAP 35 C4026 CAP 35 C4027 CAP 35 C4028 CAP 35
C4029 CAP 35 C4030 CAP 35 C4031 CAP 35 C4800 CAP 36 C4801 CAP 36 C4802 CAP 36
C4803 CAP 36 C4804 CAP 36 C4805 CAP 36 C4806 CAP 36 C4807 CAP 36
C4808 CAP 36 C4810 CAP 36 C4811 CAP 36 C4812 CAP 36 C4813 CAP 36 C4814 CAP 36
C4815 CAP 36 C4816 CAP 36 C4817 CAP 36 C4818 CAP 37 C4900 CAP 37
C4901 CAP 37 C4902 CAP 37 C4903 CAP 37 C4904 CAP 37 C4906 CAP 37 C4907 CAP 37
C4912 CAP 37 C4913 CAP 37 C4980 CAP 37 C4981 CAP 37 C4990 CAP 37
C4991 CAP 37 C5000 CAP 38 C5001 CAP 38 C5002 CAP 38 C5008 CAP 38 C5011 CAP 38
C5012 CAP 38 C5015 CAP 38 C5019 CAP 38 C5030 CAP 38 C5031 CAP 38
C5032 CAP 38 C5033 CAP 38 C5034 CAP 38 C5035 CAP_P 38 C5036 CAP_P 38 C5037 CAP_P 38
C5038 CAP 38 C5100 CAP 39 C5101 CAP 39 C5102 CAP 39 C5103 CAP 39
C5104 CAP 39 C5105 CAP 39 C5106 CAP 39 C5107 CAP 39 C5108 CAP 39 C5109 CAP 39
C5110 CAP 39 C5111 CAP 39 C5112 CAP 39 C5113 CAP 39 C5114 CAP 39
C5115 CAP 39 C5116 CAP 39 C5117 CAP 39 C5118 CAP 39 C5119 CAP 39 C5120 CAP 39
C5121 CAP 39 C5122 CAP 39 C5123 CAP 39 C5124 CAP 39 C5125 CAP 39
C5126 CAP 39 C5127 CAP 39 C5128 CAP 39 C5129 CAP 39 C5130 CAP 39 C5131 CAP 39
C5132 CAP 39 C5133 CAP 39 C5200 CAP 40 C5201 CAP 40 C5202 CAP 40
C5203 CAP 40 C5204 CAP 40 C5205 CAP 40 C5206 CAP 40 C5207 CAP 40 C5208 CAP 40
C5209 CAP 40 C5210 CAP 40 C5211 CAP 40 C5212 CAP 40 C5213 CAP 40
C5214 CAP 40 C5215 CAP 40 C5216 CAP 40 C5217 CAP 40 C5218 CAP 40 C5219 CAP 40
C5220 CAP 40
C5221 CAP 40 C5222 CAP 40
C5223 CAP 40 C5224 CAP 40 C5225 CAP 40 C5226 CAP 40 C5227 CAP 40
C5228 CAP 40 C5229 CAP 40 C5230 CAP 40 C5231 CAP 40 C5232 CAP 40 C5233 CAP 40
C5234 CAP 40 C5235 CAP 40 C5236 CAP 40 C5237 CAP 40 C5238 CAP 40
C5239 CAP 40 C5240 CAP 40 C5241 CAP 40 C5242 CAP 40 C5243 CAP 40 C5244 CAP 40
C5245 CAP 40 C5246 CAP 40 C5247 CAP 40 C5248 CAP 40 C5249 CAP 40
C5250 CAP 40 C5251 CAP 40 C5252 CAP 40 C5253 CAP 40 C5254 CAP 40 C5255 CAP 40
C5256 CAP 40 C5257 CAP 40 C5258 CAP 40 C5259 CAP 40 C5260 CAP 40
C5261 CAP 40 C5262 CAP 40 C5263 CAP 40 C5264 CAP 40 C5265 CAP 40 C5266 CAP 40
C5267 CAP 40 C5268 CAP 40 C5269 CAP 40 C5270 CAP 40 C5271 CAP 40
C5272 CAP 40 C5273 CAP 40 C5274 CAP 40 C5275 CAP 40 C5276 CAP 40 C5277 CAP 40
C5278 CAP 40 C5279 CAP 40 C5280 CAP 40 C5281 CAP 40 C5282 CAP 40
C5283 CAP 40 C5284 CAP 40 C5292 CAP 40 C5293 CAP 40 C5294 CAP 40 C5295 CAP 40
C5296 CAP 40 C5297 CAP 40 C5298 CAP 40 C5299 CAP 40 C5700 CAP 41
C5701 CAP 41 C5702 CAP 41 C5703 CAP 41 C5704 CAP 41 C5705 CAP 41 C5710 CAP 41
C5711 CAP 41 C5712 CAP 41 C5713 CAP 41 C5714 CAP 41 C5715 CAP 41
C5716 CAP 41 C5717 CAP 41 C5720 CAP 41 C5721 CAP 41 C5722 CAP 41 C5723 CAP 41
C5724 CAP 41 C5725 CAP 41 C5726 CAP 41 C5730 CAP 41 C5731 CAP 41
C5732 CAP 41 C5733 CAP 41 C5734 CAP 41 C5735 CAP 41 C5736 CAP 41 C5737 CAP 41
C5738 CAP 41 C5739 CAP 41 C5740 CAP 41 C5760 CAP 41 C5761 CAP 41
C5762 CAP 41 C5763 CAP 41 C5764 CAP 41 C5765 CAP 41 C5766 CAP 41 C5767 CAP 41
C5900 CAP 42 C5904 CAP 42 C5905 CAP 42 C5906 CAP 42 C5910 CAP 42
C5911 CAP 42 C5912 CAP 42 C5920 CAP 42 C5929 CAP 42 C5960 CAP 42 C5961 CAP 42
C5962 CAP 42 C5963 CAP 42 C5964 CAP 42 C5967 CAP 42 C5968 CAP 42
C5969 CAP 42 C5970 CAP 42 C5971 CAP 42 C5972 CAP 42 C5973 CAP 42 C5975 CAP 42
C5976 CAP 42 C5980 CAP 42 C5981 CAP 42 C5982 CAP 42 C5983 CAP 42
C5984 CAP 42 C5999 CAP 42 C6000 CAP 43 C6001 CAP 43 C6002 CAP 43 C6004 CAP 43
C6005 CAP 43 C6006 CAP 43 C6007 CAP 43 C6008 CAP 43 C6010 CAP 43
C6011 CAP 43 C6012 CAP 43 C6013 CAP 43 C6200 CAP 44 C6201 CAP 44 C6210 CAP 44
C6211 CAP 44 C6220 CAP 44 C6230 CAP 44 C6231 CAP 44 C6232 CAP 44
C6240 CAP 44 C6241 CAP 44 C6242 CAP 44 C6250 CAP 44 C6251 CAP 44 C6255 CAP 44
C7400 CAP 45
C7401 CAP 45 C7402 CAP 45
C7403 CAP 45 C7404 CAP 45 C7405 CAP 45 C7406 CAP 45 C7407 CAP 45
C7408 CAP 45 C7409 CAP 45 C7410 CAP 45 C7411 CAP 45 C7420 CAP 45 C7421 CAP 45
C7422 CAP 45 C7423 CAP 45 C7450 CAP 45 C7500 CAP 46 C7501 CAP 46
C7502 CAP 46 C7703 CAP 48 C7800 CAP 49 C7801 CAP 49 C7802 CAP 49 C7803 CAP 49
C7804 CAP 49 C7805 CAP 49 C7806 CAP 49 C7807 CAP 49 C7808 CAP 49
C7809 CAP 49 C7810 CAP 49 C7811 CAP 49 C8000 CAP 50 C8001 CAP 50 C8002 CAP 50
C8003 CAP 50 C8004 CAP 50 C8150 CAP 51 C8151 CAP 51 C8152 CAP 51
C8153 CAP 51 C8154 CAP 51 C8155 CAP 51 C8156 CAP 51 C8157 CAP 51 C8158 CAP 51
C8159 CAP 51 C8160 CAP 51 C8161 CAP 51 C8162 CAP 51 C8163 CAP 51
C8198 CAP 51 C8199 CAP 51 C8308 CAP 52 C8358 CAP 52 C8601 CAP 54 C8602 CAP 54
C8603 CAP 54 C8604 CAP 54 C8605 CAP 54 C8618 CAP 54 C8619 CAP 54
C8620 CAP 54 C8621 CAP 54 C8622 CAP 54 C8623 CAP 54 C8700 CAP 55 C8701 CAP 55
C8702 CAP 55 C8703 CAP 55 C8705 CAP 55 C8800 CAP 56 C8801 CAP 56
C8802 CAP 56 C8900 CAP 57 C8901 CAP 57 C8903 CAP 57 C8904 CAP 57 C8905 CAP 57
C8906 CAP 57 C8907 CAP 57 C8908 CAP 57 C8909 CAP 57 C8911 CAP 57
C8913 CAP 57 C8914 CAP 57 C8915 CAP 57 C8917 CAP 57 C8918 CAP 57 C8919 CAP 57
C8920 CAP 57 C8921 CAP 57 C8950 CAP 57 C9010 CAP 58 C9011 CAP 58
C9012 CAP 58 C9013 CAP 58 C9014 CAP 58 C9015 CAP 58 C9016 CAP 58 C9017 CAP 58
C9018 CAP 58 C9019 CAP 58 C9020 CAP 58 C9021 CAP 58 C9022 CAP 58
C9023 CAP 58 C9024 CAP 58 C9025 CAP 58 C9026 CAP 58 C9050 CAP 58 C9054 CAP 58
C9060 CAP 58 C9064 CAP 58 C9090 CAP 58 C9091 CAP 58 C9092 CAP 58
C9120 CAP 59 C9121 CAP 59 C9122 CAP 59 C9123 CAP 59 C9124 CAP 59 C9125 CAP 59
C9126 CAP 59 C9127 CAP 59 C9128 CAP 59 C9129 CAP 59 C9130 CAP 59
C9135 CAP 59 C9136 CAP 59 C9137 CAP 59 C9145 CAP 59 C9146 CAP 59 C9403 CAP 60
D790 DIODE_SCHOT 17 D800 DIODE 8 D810 DIODE_SCHOT 8 D1030 DIODE_SCHOT 10 D1031 DIODE_SCHOT 10
D1035 DIODE_SCHOT 10 D1036 DIODE_SCHOT 10 D1060 DIODE_SCHOT 10 D1110 DIODE_SCHOT 11 D1115 DIODE_SCHOT 11 D1130 DIODE_SCHOT 11
D1131 DIODE_SCHOT 11 D1135 DIODE_SCHOT 11 D1136 DIODE_SCHOT 11 D1160 DIODE_SCHOT 11 D1161 DIODE 11
D1162 DIODE_SCHOT 11 D1163 DIODE_SCHOT 11 D1164 DIODE_SCHOT 11 D1165 ZENER 11 D1265 DIODE_SCHOT 12 D1270 DIODE_SCHOT_3P2 12
D1271 DIODE_SCHOT 12 D1310 DIODE 13 D2150 DIODE_SCHOT 19 D3001 LED 16 D3002 LED 16
D3310 DIODE_3P_C 31 D3315 DIODE_SCHOT 31 D3320 DIODE_3P_C 31 D3325 DIODE_SCHOT 31 D3699 VREF_LM4050 32 D5011 DIODE_SCHOT 38
D5030 DIODE_SCHOT 38
D5900 DIODE_SCHOT 42 D9090 ZENER 58
DP800 DPAK3P 8 DP1260 DPAK3P 12 DP5190 DPAK3P 39 DP5290 DPAK3P 40 DP9010 DIODE_DUAL_6P 58
DP9011 DIODE_DUAL_6P 58 DP9020 DIODE_DUAL_6P 58 DP9021 DIODE_DUAL_6P 58 F895 FUSE 8 F899 FUSE 8 F1265 FUSE 12
F5900 FUSE 42 F9020 FUSE 58 FL5910 FILTER_LC 42 FL5911 FILTER_LC 42 FL5912 FILTER_LC 42
FL9010 FILTER_4P 58 FL9011 FILTER_4P 58 FL9020 FILTER_4P 58 FL9021 FILTER_4P 58 G4980 OSC 37 J700 CON_M4RT_S_SM 7
J750 CON_M10RT_S_SM 7 J790 CON_F14RT_S2MT_SM 17 J1591 CON_4RT_WRIB 15 J1592 CON_4RT_WRIB 15 J1600 CON_F14RT_S2MT_SM 17
J1699 CON_F16ST_D_SMA 16 J2130 CON_F14RT_S2MT_SM 17 J2700 CON_F1ST_S2MT_SM 25 J4010 CON_F200RT_DDRDIMM_SM1 35 J4020 CON_F200RT_DDRDIMM_SM2 35 J5900 CON_F30RT_T6MT_TH1 42
J5960 CON_F5RT_MINIDIN_TH 42 J5970 CON_F30RT_S2MT_SM 42 J5980 CON_4RT_WRIB 42 J7600 CON_M80ST_D2MT_SM3 47 J7800 CON_M80ST_D4MT_SM 49
J8300 CON_M50SM_5MM 52 J8350 CON_M50SM_5MM 52 J8710 CON_RJ45_SHORT_4MT_TH 55 J9010 CON_F9RT_1394B_S6MT_SMA 58 J9020 CON_F6RT_S4MT_TH1 58 J9400 CON_F16ST_D_SMA 60
J9500 CON_M40ST_D4MT_SM 61 L750 IND 7 L751 IND 7 L755 IND 7 L756 IND 7
L759 IND 7 L810 IND 8 L950 IND 9 L970 IND 9 L1060 IND 10 L1065 IND 10
L1110 IND 11 L1115 IND 11 L1200 IND 12 L1270 IND 12 L1290 IND 12
L2150 IND 19 L2199 IND 19 L2601 IND 24 L2603 IND 24 L2605 IND 24 L2607 IND 24
L2609 IND 24 L3101 IND 29 L3310 IND 31 L3320 IND 31 L4900 IND 37
L4980 IND 37 L4990 IND 37 L5030 IND_3P 38 L5126 IND 39 L5200 IND 40 L5201 IND 40
L5202 IND 40 L5203 IND 40 L5204 IND 40 L5205 IND 40 L5206 IND 40
L5207 IND 40 L5208 IND 40 L5209 IND 40 L5210 IND 40 L5211 IND 40 L5212 IND 40
L5213 IND 40 L5214 IND 40 L5280 IND 40 L5720 IND 41 L5730 IND 41
L5739 IND 41 L5900 IND 42 L5915 FILTER_4P 42 L5916 FILTER_4P 42 L5917 FILTER_4P 42 L5918 FILTER_4P 42
L5919 FILTER_4P 42 L5920 FILTER_4P 42 L5921 FILTER_4P 42 L5960 IND 42 L5961 IND 42
L5962 IND 42 L5963 IND 42 L5964 IND 42 L5975 IND 42 L5980 IND 42 L5981 IND 42
L5982 IND 42 L8155 IND 51 L8600 IND 54 L8601 IND 54 L8602 IND 54
L8900 IND 57 L8901 IND 57 L8902 IND 57 L8906 IND 57 L8909 IND 57 L8913 IND 57
L9010 IND 58 L9020 IND 58 L9090 IND 58 L9135 IND 59 L9530 IND 61
L9531 IND 61 L9532 IND 61 L9533 IND 61 L9534 IND 61 L9535 IND 61 L9536 IND 61
L9537 IND 61 L9538 IND 61 L9539 IND 61 L9540 IND 61 Q715 TRA_2N7002DW 7
Q720 TRA_SI4405DY 7 Q800 TRA_2N7002DW 8 Q810 TRA_SI4835BDY 8 Q811 TRA_MOSFET_NCHN_8P 8 Q850 TRA_SI4405DY 8 Q877 TRA_2N7002DW 8
Q880 TRA_SI4435DY 8 Q882 TRA_2N7002DW 8 Q890 TRA_SI4435DY 8 Q895 TRA_SUD45P03 8 Q899 TRA_SUD45P03 8
Q960 TRA_SI3446DV 9 Q980 TRA_SI3446DV 9 Q1003 TRA_SI3443DV 10 Q1004 TRA_SI3443DV 10 Q1007 TRA_SI3443DV 10 Q1060 TRA_IRF7821 10
Q1061 TRA_MOSFET_NCHN_8P 10 Q1065 TRA_SI4816DY 10 Q1110 TRA_IRF7821 11 Q1111 TRA_MOSFET_NCHN_8P 11 Q1115 TRA_SI7392DP 11
Q1116 TRA_MOSFET_NCHN_8P 11 Q1190 TRA_SI6467BDQ 11 Q1250 TRA_2N7002 12 Q1260 TRA_2N7002DW 12 Q1265 TRA_NDS9407 12 Q1400 TRA_2N7002DW 14
Q1435 TRA_2N7002DW 14
Q1510 TRA_2N3904 15 Q1515 TRA_2N3904 15
Q1520 TRA_2N3904 15 Q1525 TRA_2N3904 15 Q1530 TRA_2N3904 15 Q1535 TRA_2N3904 15 Q2000 TRA_2N7002DW 18
Q2191 TRA_2N7002DW 19 Q2199 TRA_2N3906 19 Q2404 TRA_2N7002DW 22 Q2407 TRA_2N7002 22 Q2408 TRA_SI2302DS 22 Q2409 TRA_2N7002DW 22
Q2412 TRA_2N7002DW 22 Q2576 TRA_2N3904 23 Q3001 TRA_2N3904 16 Q3002 TRA_2N3906 16 Q3003 TRA_2N3904 16
Q3004 TRA_2N7002 16 Q3309 TRA_2N7002 31 Q3310 TRA_SI7392DP 31 Q3312 TRA_MOSFET_NCHN_8P 31 Q3313 TRA_MOSFET_NCHN_8P 31 Q3320 TRA_SI7392DP 31
Q3322 TRA_MOSFET_NCHN_8P 31 Q3323 TRA_MOSFET_NCHN_8P 31 Q4801 TRA_2N7002DW 36 Q4802 TRA_2N3904 36 Q4803 TRA_2N7002 36
Q5030 TRA_SI7392DP 38 Q5031 TRA_MOSFET_NCHN_8P 38 Q5100 TRA_SI3446DV 39 Q5907 TRA_2N7002DW 42 Q5909 TRA_2N7002DW 19 42 Q5925 TRA_2N7002DW 42
Q5926 TRA_TP0610 42 Q5930 TRA_2N3904 42 Q5933 TRA_TP0610 42 Q5935 TRA_2N3904 42 Q5975 TRA_SI3443DV 42
Q5977 TRA_2N7002 42 Q5984 TRA_FDG6324L 42 R500 RES 5 R501 RES 5 R502 RES 5 R503 RES 5
R504 RES 5 R505 RES 5 R599 RES 5 R705 RES 7 R706 RES 7
R708 RES 7 R709 RES 7 R710 RES 7 R711 RES 7 R712 RES 7 R713 RES 7
R715 RES 7 R719 RES 7 R720 RES 7 R754 RES 7 R755 RES 7
R800 RES 8 R801 RES 8 R802 RES 8 R805 RES 8 R806 RES 8 R810 RES 8
R811 RES 8 R812 RES 8 R820 RES 8 R821 RES 8 R822 RES 8
R823 RES 8 R824 RES 8 R825 RES 8 R826 RES 8 R827 RES 8 R828 RES 8
R829 RES 8 R830 RES 8 R850 RES 8 R851 RES 8 R880 RES 8
R881 RES 8 R882 RES 8 R890 RES 8 R891 RES 8 R892 RES 8 R895 RES 8
R896 RES 8 R897 RES 8 R898 RES 8 R899 RES 8 R940 RES 9
R941 RES 9 R950 RES 9 R951 RES 9 R952 RES 9 R953 RES 9 R954 RES 9
R955 RES 9 R956 RES 9 R957 RES 9 R958 RES 9 R970 RES 9
R971 RES 9 R1031 RES 10 R1032 RES 10 R1033 RES 10 R1035 RES 10 R1036 RES 10
R1050 RES 10 R1052 RES 10 R1053 RES 10 R1070 RES 10 R1071 RES 10
R1072 RES 10 R1073 RES 10 R1080 RES 10 R1081 RES 10 R1082 RES 10 R1083 RES 10
R1100 RES 11 R1102 RES 11 R1103 RES 11 R1120 RES 11 R1121 RES 11
R1122 RES 11 R1123 RES 11 R1131 RES 11 R1132 RES 11 R1133 RES 11 R1135 RES 11
R1136 RES 11 R1140 RES 11 R1141 RES 11 R1142 RES 11 R1143 RES 11
R1161 RES 11 R1162 RES 11 R1163 RES 11 R1164 RES 11 R1166 RES 11 R1171 RES 11
R1250 RES 12 R1251 RES 12 R1260 RES 12 R1261 RES 12 R1262 RES 12
R1263 RES 12 R1265 RES 12 R1266 RES 12 R1290 RES 12 R1291 RES 12 R1292 RES 12
R1293 RES 12 R1294 RES 12 R1295 RES 12 R1296 RES 12 R1297 RES 12
R1298 RES 12 R1300 RES 13 R1302 RES 13 R1304 RES 13 R1310 RES 13 R1311 RES 13
R1312 RES 13
051-6532 03
103102
Preliminary
www.vinafix.vn
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE 103
R1313 RES 13 R1315 RES 13
R1316 RES 13 R1317 RES 13 R1322 RES 13 R1325 RES 13 R1327 RES 13
R1399 RES 13 R1400 RES 14 R1401 RES 14 R1402 RES 14 R1403 RES 14 R1410 RES 14
R1411 RES 14 R1412 RES 14 R1420 RES 14 R1421 RES 14 R1422 RES 14
R1429 RES 14 R1430 RES 14 R1435 RES 14 R1436 RES 14 R1437 RES 14 R1440 RES 14
R1441 RES 14 R1448 RES 14 R1449 RES 14 R1450 RES 14 R1451 RES 14
R1458 RES 14 R1459 RES 14 R1465 RES 14 R1466 RES 14 R1467 RES 14 R1469 RES 14
R1500 RES 15 R1510 RES 15 R1511 RES 15 R1515 RES 15 R1516 RES 15
R1520 RES 15 R1521 RES 15 R1525 RES 15 R1526 RES 15 R1530 RES 15 R1531 RES 15
R1535 RES 15 R1536 RES 15 R1591 RES 15 R1592 RES 15 R1600 RES 17
R1601 RES 17 R1610 RES 17 R1611 RES 17 R1620 RES 17 R1621 RES 17 R1690 RES 16
R1691 RES 16 R2010 RES 18 R2011 RES 18 R2015 RES 18 R2016 RES 18
R2018 RES 18 R2019 RES 18 R2020 RES 18 R2021 RES 18 R2028 RES 18 R2029 RES 18
R2030 RES 18 R2031 RES 18 R2040 RES 18 R2041 RES 18 R2050 RES 18
R2051 RES 18 R2080 RES 18 R2081 RES 18 R2082 RES 18 R2083 RES 18 R2110 RES 19
R2111 RES 19 R2112 RES 19 R2113 RES 19 R2114 RES 19 R2115 RES 19
R2116 RES 19 R2130 RES 17 R2131 RES 17 R2132 RES 17 R2150 RES 19 R2191 RES 19
R2192 RES 19 R2193 RES 19 R2199 RES 19 R2400 RES 22 R2401 RES 22
R2402 RES 22 R2403 RES 22 R2405 RES 22 R2406 RES 22 R2407 RES 22 R2408 RES 22
R2409 RES 22 R2418 RES 22 R2419 RES 22 R2420 RES 22 R2421 RES 22
R2422 RES 22 R2423 RES 22 R2424 RES 22 R2426 RES 22 R2429 RES 22 R2431 RES 22
R2433 RES 22 R2435 RES 22 R2436 RES 22 R2438 RES 22 R2442 RES 22
R2443 RES 22 R2444 RES 22 R2500 RES 23 R2501 RES 23 R2505 RES 23 R2510 RES 23
R2520 RES 23 R2530 RES 23 R2550 RES 23 R2551 RES 23 R2552 RES 23
R2553 RES 23 R2554 RES 23 R2555 RES 23 R2556 RES 23 R2557 RES 23 R2558 RES 23
R2559 RES 23 R2560 RES 23 R2561 RES 23 R2562 RES 23 R2563 RES 23
R2564 RES 23 R2565 RES 23 R2566 RES 23 R2567 RES 23 R2568 RES 23 R2575 RES 23
R2576 RES 23 R2578 RES 23 R2579 RES 23 R2580 RES 23 R2590 RES 23
R2601 RES 24 R2603 RES 24 R2605 RES 24 R2607 RES 24 R2609 RES 24 R2700 RES 25
R2701 RES 25 R2702 RES 25 R2703 RES 25 R2704 RES 25 R2705 RES 25
R2706 RES 25 R2707 RES 25 R2709 RES 25 R2711 RES 25 R2715 RES 25 R2717 RES 25
R2719 RES 25
R2720 RES 25 R2722 RES 25
R2724 RES 25 R2738 RES 25 R2740 RES 25 R2742 RES 25 R2744 RES 25
R2746 RES 25 R2748 RES 25 R2750 RES 25 R2752 RES 25 R2754 RES 25 R2756 RES 25
R2758 RES 25 R2761 RES 25 R2762 RES 25 R2764 RES 25 R2768 RES 25
R2770 RES 25 R2772 RES 25 R2775 RES 25 R2776 RES 25 R2779 RES 25 R2800 RES 26
R2801 RES 26 R2802 RES 26 R2803 RES 26 R2804 RES 26 R2805 RES 26
R2806 RES 26 R2901 RES 27 R2902 RES 27 R2903 RES 27 R2904 RES 27 R2905 RES 27
R2906 RES 27 R2907 RES 27 R2908 RES 27 R2909 RES 27 R2910 RES 27
R2911 RES 27 R3000 RES 28 R3001 RES 28 R3002 RES 28 R3003 RES 28 R3004 RES 28
R3005 RES 28 R3006 RES 28 R3007 RES 28 R3008 RES 28 R3009 RES 28
R3010 RES 28 R3012 RES 28 R3014 RES 28 R3016 RES 28 R3018 RES 28 R3020 RES 28
R3022 RES 28 R3024 RES 28 R3026 RES 28 R3028 RES 28 R3030 RES 28
R3031 RES 28 R3032 RES 28 R3033 RES 28 R3034 RES 28 R3035 RES 28 R3036 RES 28
R3037 RES 28 R3038 RES 28 R3039 RES 28 R3040 RES 28 R3041 RES 28
R3042 RES 28 R3043 RES 28 R3044 RES 16 R3045 RES 28 R3046 RES 16 R3047 RES 28
R3048 RES 16 R3049 RES 28 R3050 RES 16 R3051 RES 28 R3052 RES 16
R3053 RES 28 R3054 RES 16 R3055 RES 28 R3057 RES 28 R3059 RES 28 R3061 RES 28
R3063 RES 28 R3065 RES 28 R3067 RES 28 R3068 RES 28 R3069 RES 28
R3070 RES 16 R3071 RES 28 R3073 RES 28 R3075 RES 28 R3077 RES 28 R3079 RES 28
R3081 RES 28 R3083 RES 28 R3085 RES 28 R3087 RES 28 R3089 RES 28
R3091 RES 28 R3093 RES 28 R3095 RES 28 R3097 RES 28 R3099 RES 28 R3101 RES 29
R3103 RES 29 R3105 RES 29 R3127 RES 29 R3129 RES 29 R3131 RES 29
R3132 RES 29 R3300 RES 31 R3301 RES 31 R3302 RES 31 R3303 RES 31 R3304 RES 31
R3305 RES 31 R3306 RES 31 R3307 RES 31 R3309 RES 31 R3310 RES 31
R3311 RES 31 R3312 RES 31 R3316 RES 31 R3318 RES 31 R3319 RES 31 R3320 RES 31
R3321 RES 31 R3322 RES 31 R3326 RES 31 R3328 RES 31 R3329 RES 31
R3330 RES 31 R3331 RES 31 R3332 RES 31 R3333 RES 31 R3340 RES 31 R3341 RES 31
R3360 RES 31 R3361 RES 31 R3366 RES 31 R3370 RES 31 R3371 RES 31
R3397 RES 31 R3398 RES 31 R3399 RES 31 R3600 RES 32 R3610 RES 32 R3611 RES 32
R3620 RES 32 R3621 RES 32 R3630 RES 32 R3631 RES 32 R3635 RES 32
R3636 RES 32 R3639 RES 32 R3640 RES 32 R3655 RES 32 R3656 RES 32 R3660 RES 32
R3661 RES 32
R3662 RES 32 R3665 RES 32
R3666 RES 32 R3669 RES 32 R3670 RES 32 R3671 RES 32 R3672 RES 32
R3675 RES 32 R3676 RES 32 R3677 RES 32 R3679 RES 32 R3699 RES 32 R3700 RES 33
R3701 RES 33 R3702 RES 33 R3840 RES 34 R3841 RES 34 R3842 RES 34
R4000 RES 35 R4001 RES 35 R4800 RES 36 R4801 RES 36 R4802 RES 37 R4803 RES 37
R4807 RES 36 R4808 RES 36 R4809 RES 36 R4810 RES 36 R4811 RES 36
R4812 RES 36 R4813 RES 36 R4900 RES 37 R4901 RES 37 R4902 RES 37 R4904 RES 37
R4905 RES 37 R4906 RES 37 R4907 RES 37 R4908 RES 37 R4909 RES 37
R4910 RES 37 R4911 RES 37 R4912 RES 37 R4913 RES 37 R4914 RES 37 R4920 RES 37
R4923 RES 37 R4924 RES 37 R4980 RES 37 R4981 RES 37 R4982 RES 37
R4985 RES 37 R4990 RES 37 R4991 RES 37 R4992 RES 37 R4993 RES 37 R4995 RES 37
R5001 RES 38 R5002 RES 38 R5003 RES 38 R5004 RES 38 R5005 RES 38
R5006 RES 38 R5007 RES 38 R5008 RES 38 R5009 RES 38 R5010 RES 38 R5011 RES 38
R5012 RES 38 R5013 RES 38 R5014 RES 38 R5015 RES 38 R5016 RES 38
R5017 RES 38 R5018 RES 38 R5019 RES 38 R5034 RES 38 R5100 RES 39 R5101 RES 39
R5102 RES 39 R5103 RES 39 R5104 RES 39 R5105 RES 39 R5106 RES 39
R5107 RES 39 R5108 RES 39 R5109 RES 39 R5110 RES 39 R5111 RES 39 R5112 RES 39
R5113 RES 39 R5114 RES 39 R5115 RES 39 R5116 RES 39 R5117 RES 39
R5118 RES 39 R5119 RES 39 R5120 RES 39 R5121 RES 39 R5122 RES 39 R5123 RES 39
R5124 RES 39 R5125 RES 39 R5126 RES 39 R5127 RES 39 R5128 RES 39
R5129 RES 39 R5200 RES 40 R5201 RES 40 R5280 RES 40 R5700 RES 41 R5701 RES 41
R5702 RES 41 R5703 RES 41 R5704 RES 41 R5705 RES 41 R5707 RES 41
R5708 RES 41 R5709 RES 41 R5710 RES 41 R5711 RES 41 R5712 RES 41 R5713 RES 41
R5714 RES 41 R5740 RES 41 R5741 RES 41 R5745 RES 41 R5746 RES 41
R5750 RES 41 R5751 RES 41 R5752 RES 41 R5753 RES 41 R5754 RES 41 R5755 RES 41
R5756 RES 41 R5757 RES 41 R5758 RES 41 R5760 RES 41 R5761 RES 41
R5762 RES 41 R5763 RES 41 R5764 RES 41 R5765 RES 41 R5766 RES 41 R5767 RES 41
R5900 RES 42 R5901 RES 42 R5902 RES 42 R5903 RES 42 R5904 RES 42
R5905 RES 42 R5906 RES 42 R5907 RES 42 R5908 RES 42 R5909 RES 42 R5913 RES 42
R5914 RES 42 R5920 RES 42 R5921 RES 42 R5922 RES 42 R5923 RES 42
R5925 RES 42 R5926 RES 42 R5927 RES 42 R5928 RES 42 R5929 RES 42 R5930 RES 42
R5933 RES 42
R5934 RES 42 R5935 RES 42
R5972 RES 42 R5973 RES 42 R5976 RES 42 R5977 RES 42 R5984 RES 42
R5999 RES 42 R6000 RES 43 R6001 RES 43 R6002 RES 43 R6003 RES 43 R6004 RES 43
R6005 RES 43 R6200 RES 44 R6210 RES 44 R6250 RES 44 R6251 RES 44
R6252 RES 44 R6253 RES 44 R6254 RES 44 R6255 RES 44 R7450 RES 45 R7455 RES 45
R7500 RES 46 R7501 RES 46 R7502 RES 46 R7600 RES 47 R7601 RES 47
R7713 RES 48 R7714 RES 48 R7715 RES 48 R7716 RES 48 R7802 RES 49 R7803 RES 49
R7804 RES 49 R7805 RES 49 R7806 RES 49 R7808 RES 49 R7809 RES 49
R8000 RES 50 R8001 RES 50 R8002 RES 50 R8003 RES 50 R8004 RES 50 R8005 RES 50
R8160 RES 51 R8170 RES 51 R8171 RES 51 R8172 RES 51 R8173 RES 51
R8174 RES 51 R8175 RES 51 R8179 RES 51 R8198 RES 51 R8300 RES 52 R8301 RES 52
R8302 RES 52 R8304 RES 52 R8305 RES 52 R8307 RES 52 R8308 RES 52
R8309 RES 52 R8350 RES 52 R8351 RES 52 R8352 RES 52 R8354 RES 52 R8355 RES 52
R8357 RES 52 R8358 RES 52 R8359 RES 52 R8363 RES 52 R8365 RES 52
R8400 RES 53 R8401 RES 53 R8402 RES 53 R8600 RES 54 R8601 RES 54 R8602 RES 54
R8609 RES 54 R8613 RES 54 R8614 RES 54 R8615 RES 54 R8616 RES 54
R8617 RES 54 R8618 RES 54 R8619 RES 54 R8620 RES 54 R8621 RES 54 R8650 RES 54
R8705 RES 55 R8706 RES 55 R8707 RES 55 R8708 RES 55 R8710 RES 55
R8800 RES 56 R8900 RES 57 R8901 RES 57 R8902 RES 57 R8903 RES 57 R8904 RES 57
R8909 RES 57 R8911 RES 57 R8912 RES 57 R8914 RES 57 R8915 RES 57
R8916 RES 57 R8921 RES 57 R8956 RES 57 R9010 RES 58 R9011 RES 58 R9020 RES 58
R9050 RES 58 R9051 RES 58 R9052 RES 58 R9053 RES 58 R9054 RES 58
R9060 RES 58 R9061 RES 58 R9062 RES 58 R9063 RES 58 R9064 RES 58 R9070 RES 58
R9090 RES 58 R9100 RES 59 R9101 RES 59 R9102 RES 59 R9103 RES 59
R9104 RES 59 R9105 RES 59 R9106 RES 59 R9107 RES 59 R9108 RES 59 R9109 RES 59
R9110 RES 59 R9135 RES 59 R9138 RES 59 R9139 RES 59 R9140 RES 59
R9141 RES 59 R9145 RES 59 R9400 RES 60 R9410 RES 60 R9411 RES 60 R9504 RES 61
R9505 RES 61 R9507 RES 61 R9511 RES 61 R9515 RES 61 RD2111 PHOTODIODE_2P 19
RP2060 RPAK4P 18 RP2080 RPAK4P 18 RP2085 RPAK4P 18 RP2510 RPAK4P 23 RP2520 RPAK4P 23 RP2530 RPAK4P 23
RP2550 RPAK4P 23 RP2551 RPAK4P 23 RP2552 RPAK4P 23 RP2553 RPAK4P 23 RP3300 RPAK4P 31
RP3800 RPAK4P 34 RP3801 RPAK4P 34 RP3810 RPAK4P 34 RP3820 RPAK4P 34 RP3830 RPAK4P 34 RP3831 RPAK4P 34
RP3832 RPAK4P 34
RP3833 RPAK4P 34 RP3850 RPAK4P 34
RP5702 RPAK2P 41 RP5703 RPAK2P 41 RP5704 RPAK2P 41 RP5706 RPAK2P 41 RP5707 RPAK2P 41
RP5708 RPAK2P 41 RP5709 RPAK2P 41 RP5710 RPAK2P 41 RP5711 RPAK2P 41 RP5712 RPAK2P 41 RP5713 RPAK2P 41
RP5714 RPAK2P 41 RP5715 RPAK2P 41 RP5716 RPAK2P 41 RP5717 RPAK2P 41 RP7400 RPAK4P 45
RP7401 RPAK4P 45 RP7402 RPAK4P 45 RP7702 RPAK4P 48 RP7703 RPAK4P 48 RP7800 RPAK10P2C 49 RP8000 RPAK4P 50
RP8001 RPAK4P 50 RP8002 RPAK4P 50 RP8003 RPAK4P 50 RP8004 RPAK4P 50 RP8170 RPAK4P 51
RP8171 RPAK4P 51 RP8172 RPAK4P 51 RP8173 RPAK4P 51 RP8174 RPAK4P 51 RP8400 RPAK4P 53 RP8401 RPAK4P 53
RP8900 RPAK4P 57 RP8901 RPAK4P 57 RP9110 RPAK4P 59 SP500 SPKR_CLIP_P84 17 SP501 SPKR_CLIP_P84 17
SP502 SPKR_CLIP_P84 17 SP503 SPKR_CLIP_P84 17 SP504 SPKR_CLIP_P84 17 SP505 SPKR_CLIP_P84 17 SP9900 SPKR_CLIP_P84 17 SW2100 SWI_4W219SM_H63 19
T8700 XFR_ENET_1000BT 55 U3 U3LITE 20 22 26 33 36 43 U710 COMPARATOR_LMC7211 7 U800 MAX1535 8 U940 VREG_LP3982 9
U950 LTC3412 9 U970 TPS62050 9 U1000 TPS5120 10 U1100 TPS5120 11 U1160 VREG_LP2951 11 U1170 VREG_LP2951 11
U1270 VREG_LM2594 12 U1280 VREG_MM1572FN 12 U1290 LTC3411 12 U1300 M30280F8 13 U1301 DS1338 13
U1500 MAX1668 15 U2015 COMPARATOR_LM339A 18 U2110 OPAMP_MAX4236EUTT 19 U2150 MAX1561 19 U2300 SHASTA 21 23 44 45 50 53 56 59 U2600 PULSAR 24 25
U2900 GPUL 27 29 U3300 MAX1544 31 U3630 OPAMP_LMV2011 32 U3660 OPAMP_LMV2011 32 U3669 OPAMP_LMV2011 32
U3670 OPAMP_LMV2011 32 U4900 RAGE_MBLTY_M10_CSP64_667 37 39 40 U4990 CLK_GEN_CY25811 37 U5000 MAX1993 38 U5280 VREG_MM1571J 40 U5290 VREG_MM1571J 40
U5700 SIL1178 41 U5913 741G32 42 U5914 741G32 42 U5920 COMPARATOR_LMC7211 42 U5983 741G32 42
U7450 MC74VHC1G08 45 U7500 FEPR_1MX8 46 U7700 UPD720101_FBGA_SPLIT 48 59 U7800 PCI1510GGU 49 U7801 PWR_CNTRL_TPS2211 49 U8150 88SA8040 51
U8198 741G14 51 U8199 741G14 51 U8600 BCM5462 12 54 57 U8950 EEPROM_16KX8_M24128B 57 VR3100 VREG_MM1572FN 29
XW510 JUMPER 5 XW518 JUMPER 5 XW520 JUMPER 5 XW530 JUMPER 5 XW540 JUMPER 5 XW552 JUMPER 5
XW560 JUMPER 5 XW561 JUMPER 5 XW590 JUMPER 5 XW591 JUMPER 5 XW592 JUMPER 5
XW800 SHORT 8 XW950 SHORT 9 XW1003 SHORT 10 XW1104 SHORT 11 XW1290 SHORT 12 XW1300 SHORT 13
XW1470 SHORT 14 XW3100 SHORT 29 XW3300 SHORT 31 XW3310 SHORT 31 XW3320 SHORT 31
XW3360 SHORT 31 XW3361 SHORT 31 XW3600 SHORT 32 XW3610 SHORT 32 XW3611 SHORT 32 XW3620 SHORT 32
XW3621 SHORT 32 XW3630 SHORT 32 XW3640 SHORT 32 XW3650 SHORT 32 XW3651 SHORT 32
XW5001 SHORT 38 XW5190 SHORT 39 XW5191 SHORT 39 XW5192 SHORT 39 XW5193 SHORT 39 XW5194 SHORT 39
XW5290 SHORT 40 XW5291 SHORT 40 XW5292 SHORT 40 XW5293 SHORT 40 XW5960 SHORT 42
XW5961 SHORT 42 XW7800 SHORT 49 XW9500 SHORT 61 XW9503 SHORT 61 XW9505 SHORT 61 Y1300 CRYSTAL 13
Y1301 CRYSTAL_4PIN 13 Y2590 CRYSTAL 23 Y2701 CRYSTAL 25 Y8600 CRYSTAL 54 Y8920 CRYSTAL 57
Y9145 CRYSTAL 59 ZT500 MTGHOLE 17 ZT501 MTGHOLE 17 ZT502 MTGHOLE 17 ZT503 MTGHOLE 17 ZT504 MTGHOLE 17
ZT505 MTGHOLE 17 ZT510 MTGHOLE 17 ZT511 MTGHOLE 17 ZT2800 HOLE_VIA 26 ZT2801 HOLE_VIA 26
ZT2802 HOLE_VIA 26 ZT2803 HOLE_VIA 26 ZT2804 HOLE_VIA 26 ZT2805 HOLE_VIA 26 ZT2806 HOLE_VIA 26 ZT2807 HOLE_VIA 26
ZT2808 HOLE_VIA 26
ZT2809 HOLE_VIA 26 ZT2810 HOLE_VIA 26
ZT2811 HOLE_VIA 26 ZT2812 HOLE_VIA 26 ZT2813 HOLE_VIA 26 ZT2814 HOLE_VIA 26 ZT2815 HOLE_VIA 26
ZT2816 HOLE_VIA 26 ZT2817 HOLE_VIA 26 ZT2818 HOLE_VIA 26 ZT2819 HOLE_VIA 26 ZT2820 HOLE_VIA 26 ZT2821 HOLE_VIA 26
ZT2822 HOLE_VIA 26 ZT2823 HOLE_VIA 26 ZT2824 HOLE_VIA 26 ZT2825 HOLE_VIA 26 ZT2826 HOLE_VIA 26
ZT2827 HOLE_VIA 26 ZT2828 HOLE_VIA 26 ZT2829 HOLE_VIA 26 ZT2830 HOLE_VIA 26 ZT2831 HOLE_VIA 26 ZT2832 HOLE_VIA 26
ZT2833 HOLE_VIA 26 ZT2834 HOLE_VIA 26 ZT2835 HOLE_VIA 26 ZT2836 HOLE_VIA 26 ZT2837 HOLE_VIA 26
ZT2838 HOLE_VIA 26 ZT2839 HOLE_VIA 26 ZT2840 HOLE_VIA 26 ZT2841 HOLE_VIA 26 ZT2842 HOLE_VIA 26 ZT2843 HOLE_VIA 26
ZT2844 HOLE_VIA 26 ZT2845 HOLE_VIA 26 ZT2846 HOLE_VIA 26 ZT2847 HOLE_VIA 26 ZT2848 HOLE_VIA 26
ZT2849 HOLE_VIA 26 ZT2850 HOLE_VIA 26 ZT2851 HOLE_VIA 26 ZT2852 HOLE_VIA 26 ZT2853 HOLE_VIA 26 ZT2854 HOLE_VIA 26
ZT2855 HOLE_VIA 26 ZT2856 HOLE_VIA 26 ZT2857 HOLE_VIA 26 ZT2858 HOLE_VIA 26 ZT2859 HOLE_VIA 26
ZT2860 HOLE_VIA 26 ZT2861 HOLE_VIA 26 ZT2862 HOLE_VIA 26 ZT2863 HOLE_VIA 26 ZT2864 HOLE_VIA 26 ZT2865 HOLE_VIA 26
ZT2866 HOLE_VIA 26 ZT2867 HOLE_VIA 26 ZT2868 HOLE_VIA 26 ZT2869 HOLE_VIA 26 ZT9900 HOLE_VIA 17
ZT9901 HOLE_VIA 17 ZT9902 HOLE_VIA 17 ZT9903 HOLE_VIA 17
051-6532 03
103103
Preliminary
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