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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 2
Problem and
Motivation
Problem and
Motivations Fault simulation Problem: Given
A circuit
A sequence of test vectors
A fault model
Determine
Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
Set of undetected faults
s Motivation
Determine test quality and in turn product quality Find undetected fault targets to improve tests
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 3
Fault simulator in a
VLSI Design Process
Fault simulator in a
VLSI Design Process
Verified design
netlist
Verification
input stimuli
Fault simulator Test vectors
Modeled
fault list
Test
generator
Test
compactor
Faultcoverage
?
Remove
tested faults Delete
vectors
Add vectors
Low
Adequate
Stop
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 4
Fault Simulation
Scenario
Fault Simulation
Scenarios Circuit model: mixed-level
s Mostly logic with some switch-level for high-
impedance (Z) and bidirectional signals
s High-level models (memory, etc.) with pin faults
s
Signal states: logics Two (0, 1) or three (0, 1, X) states for purely
Boolean logic circuits
s Four states (0, 1, X, Z) for sequential MOS circuits
s Timing:s Zero-delay for combinational and synchronous
circuits
s Mostly unit-delay for circuits with feedback
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 5
Fault Simulation
Scenario (continued)
Fault Simulation
Scenario (continued)
s Faults:s Mostly single stuck-at faults
s Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common uses Equivalence fault collapsing of single stuck-at faults
s Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
s Fault sampling -- a random sample of faults issimulated when the circuit is large
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Fault Simulation
Algorithms
Fault Simulation
Algorithmss Serial
s Parallel
s Deductive
s Concurrent
s Differential
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Serial Algorithmerial Algorithm
s Algorithm: Simulate fault-free circuit and saveresponses. Repeat following steps for each fault in
the fault list:s Modify netlist by injecting one fault
s Simulate modified netlist, vector by vector, comparing
responses with saved responsess If response differs, report fault detection and suspend
simulation of remaining vectors
s Advantages:s Easy to implement; needs only a true-value simulator,
less memorys Most faults, including analog faults, can be simulated
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 8
Serial Algorithm
(Cont.)
Serial Algorithm
(Cont.)s Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
s Alternative: Simulate many faults together
Test vectors Fault-free circuit
Circuit with fault f1
Circuit with fault f2
Circuit with fault fn
Comparator f1 detected?
Comparator f2 detected?
Comparator fn detected?
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 9
Parallel Fault
Simulation
Parallel Fault
Simulations Compiled-code method; best with two-
states (0,1)
s Exploits inherent bit-parallelism of logicoperations on computer words
s
Storage: one word per line for two-statesimulation
s Multi-pass simulation: Each pass simulatesw -1 new faults, where w is the machineword length
s Speed up over serial method ~ w -1s Not suitable for circuits with timing-critical
and non-Boolean logic
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 10
Parallel Fault Sim.
Example
Parallel Fault Sim.
Example
a
bc
d
e
f
g
1 1 1
1 1 1 1 0 1
1 0 1
0 0 0
1 0 1
s-a-1
s-a-0
0 0 1
c s-a-0 detected
Bit 0: fault-free circuitBit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 11
Deductive Fault
Simulation
Deductive Fault
Simulations One-pass simulations Each line k contains a list L
k of faults
detectable on k
s Following true-value simulation of each
vector, fault lists of all gate output linesare updated using set-theoretic rules,signal values, and gate input fault lists
s PO fault lists provide detection datas
Limitations:s Set-theoretic rules difficult to derive for non-Boolean gates
s Gate delays are difficult to use
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 12
Deductive Fault Sim.
Example
Deductive Fault Sim.
Example
a
bc
d
e
f
g
1
1 1
0
1
{a 0
}
{b 0 , c 0}
{b 0}
{b 0 , d 0}
L e
= L a
U L c
U {e 0
}
= {a 0 , b 0 , c 0 , e 0}
L g = (L e L f ) U {g 0}
= {a 0 , c 0 , e 0 , g 0}
U
{b 0 , d 0 , f 1}
Notation: L k is fault list for line k
k n is s-a-n fault on line k
Faults detected by
the input vector
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Concurrent Fault
Simulation
oncurrent FaultSimulation
s Event-driven simulation of fault-free circuit and
only those parts of the faulty circuit that differ insignal states from the fault-free circuit.
s A list per gate containing copies of the gatefrom all faulty circuits in which this gate differs.
List element contains fault ID, gate input andoutput values and internal states, if any.s All events of fault-free and all faulty circuits are
implicitly simulated.s Faults can be simulated in any modeling style or
detail supported in true-value simulation (offersmost flexibility.)
s Faster than other methods, but uses mostmemory.
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 14
Conc. Fault Sim.
Example
Conc. Fault Sim.
Example
a
bc
d
e
f
g
1
1
1
0
1
1
11
1
01
1 0
0
10
1
00
1
00
1
10
1
00
1
11
1
11
0
00
0
11
0
00
0
00
0 1 0 1 1 1
a 0 b 0 c 0 e 0
a 0 b 0
b 0
c 0 e 0
d 0d 0 g 0 f 1
f 1
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 15
Fault Samplingault Sampling
s A randomly selected subset (sample) of
faults is simulated.
s Measured coverage in the sample is used
to estimate fault coverage in the entirecircuit.
s Advantage: Saving in computing resources
(CPU time and memory.)
s Disadvantage: Limited data on undetectedfaults.
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Motivation for
Sampling
Motivation for
Sampling
s Complexity of fault simulation depends on:s Number of gates
s Number of faults
s Number of vectors
s Complexity of fault simulation with fault
sampling depends on:s Number of gates
s Number of vectors
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 7 17
Random Sampling
Model
Random Sampling
Model
All faults with
a fixed but
unknown
coverage
Detectedfault
Undetectedfault
Random
picking
N p = total number of faults
(population size)
C = fault coverage (unknown)
N s = sample size
N s << N p
c = sample coverage(a random variable)
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Probability Density
of Sample Coverage,
c
Probability Densityof Sample Coverage,
c (x--C )2
-- ------------ 1 2σ 2
p (x ) = Prob(x < c < x +dx ) = -------------- e σ (2 π ) 12
p
( x
)
C C +3σC -3σ 1.0x
Sample coverage
C (1 -C )Variance , σ 2 =------------ N s Mean = C
Sampling
error σ σ
x
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Sampling Error
Bounds
Sampling Error
Bounds C (1 - C )| x - C | = 3 [ -------------- ] 1/2 N s
Solving the quadratic equation for C , we get the
3-sigma (99.7% confidence) estimate:
4.5
C 3σ= x ------- [1 + 0.44 N s x (1 - x )]
1/2
N s
Where N s is sample size and x is the measured fault
coverage in the sample.Example: A circuit with 39,096 faults has an actual
fault coverage of 87.1%. The measured coverage in
a random sample of 1,000 faults is 88.7%. The above
formula gives an estimate of 88.7% 3%. CPU time for
sample simulation was about 10% of that for all faults.
±
±
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Summaryummarys Fault simulator is an essential tool for test development.
s Concurrent fault simulation algorithm offers the bestchoice.
s For restricted class of circuits (combinational and
synchronous sequential with only Boolean primitives),
differential algorithm can provide better speed and
memory efficiency (Section 5.5.6.)s For large circuits, the accuracy of random fault sampling
only depends on the sample size (1,000 to 2,000 faults)
and not on the circuit size. The method has significant
advantages in reducing CPU time and memory needs of
the simulator.