Kick-Off Meeting
Catania – February 26, 2010
THERMINATORTHERMINATORModeling, Control and Management of Modeling, Control and Management of
Thermal Effects Thermal Effects in Electronic Circuits of the Futurein Electronic Circuits of the Future
2Enrico Macii -- [email protected]
Agenda, February 26Agenda, February 26thth 2010 2010
• 09:00 Welcome and Project highlights S. Rinaudo Round-table and presentation of each partner
• 10:00 Technical Work Plan walk-through E. Macii Deploy the operative workplan (part 1) Milestones, Deadlines, Gantt Discussion and Agreement of Project Handbook Scheduling the main governance’s Meetings
• 11:30 Project management overview and IPR G. Gangemi Project Management structure and Handbook IPCA and IPs
• 11:45 Training Workplan N. Gergely
• 12:00 Deploy the operative workplan (part 2) E. Macii R&D, Roadmap, dissemination
• 12:30 Lunch Break
• 13:30 Deploy the operative workplan (part 3) E. Macii Technical dependencies and links among partners
• 16:00 THERMINATOR Management issues R. Zafalon Press Release: draft preparation (To issue by April 2010) Pending issues to be agreed Money transferring policy from coordinator’s account to partners
• 17:30 Final Wrap-up & Action Items
Project OverviewProject Overview
E. Macii (POLITO)
4Enrico Macii -- [email protected]
Objectives and ConsortiumObjectives and Consortium
The Objectives
1. Development of new modeling and simulation capabilities.
2. Development of new thermal-aware design techniques, methodologies and prototype tools
3. Validation of thermal model accuracy against silicon measurements
4. Assessment of results of application of thermal-aware design solutions on test-chips.
5. Assessment of results of application of thermal-aware EDA prototype tools on industry-strength design cases.
STM, NXP, IFX
BME, CSEM, FHG, IMEC, CEA-LETI, OFFIS,
POLITO, UNIBO
CV,GDA,MUN,SNPS
IC Vendors
ResearchInstitutes
EDAVendors
The Consortium
15 partners
5Enrico Macii -- [email protected]
Therminator PlatformTherminator Platform
System-level thermal modeling and simulation
DesignSimulation, Modeling
Pa
cka
ge
th
erm
al m
od
elin
g
Thermal-Aware design explorationPackageselection
Thermal Interconnect
modeling
Logi-ThermalSimulation
Thermal-AwareSynthesis Circuit-level
thermal modeling and
simulation
ThermalModeling
andThermal-
AwareSimulation
Device Characterization and Thermal Compact Modeling
analog/RF digital discrete
system
sb
locks o
rco
mp
on
en
tscircu
itsd
evice
s
Thermal-AwareDesign Using
Advanced Technologies
Architecture-level Thermal
modelingThermal
Management of digital blocks
Thermal compensation for
interconnects
Exploration
Temperature-Insensitive
Library
Block-level thermal
modelling and
simulation
6Enrico Macii -- [email protected]
WorkplanWorkplan
Start date: 01/01/10Duration: 36 months
Effort: 944 p/mCost: 11 M€ EC funding: 6.4 M€
WP1: Technology Characterization, Tool Requirementsand Test Case Identification
WP2: Process, Device and Compact Modeling
WP3: Modeling,
Simulation andDesign of
Digital Blocks
WP4: Modeling andSimulation of
Analog/RFBlocks
WP5: Modeling andSimulation of
DiscreteComponents
WP7: Validation, Demonstration and Evaluation
WP8: Dissemination, Training,Exploitation and Roadmapping
WP6: Package/System Modeling andDesign Exploration under Ambient Influence
WP9: Project Management
RTD
DEM
MGT
7Enrico Macii -- [email protected]
WorkplanWorkplan
WP WP TitleType of Activity
Leader EFFORTStart
MonthEnd
MonthDeliv.
1Technology Characterization, Tool Requirements and Test Case Identification
RTD IFX 72 M1 M24From: D1.1.1 To:
D1.3.2
2Process, Device and Compact Modeling
RTD IFX 104 M1 M24From: D2.1.1
To: D2.3.4
3Modeling, Simulation and Design of Digital Blocks
RTD POLITO 201 M1 M30From: D3.1.1
To: D3.4.3
4Modeling and Simulation of Analog/RF Blocks
RTD NXP 72 M1 M30From: D4.1.1
To: D4.2.3
5Modeling and Simulation of Discrete Components
RTD ST 62 M1 M30From: D 5.1.1
To: D5.2.1
6Package/System Modeling and Design Exploration under Ambient Influence
RTD NXP 221 M1 M30From: D6.1.1
To: D6.3.3
7Validation, Demonstration and Evaluation
DEM NXP 116 M19 M36From: D7.1.1
To: D7.3.2
8Dissemination, Training, Exploitation and Roadmapping
RTD ST 62 M1 M36From: D8.1.1
To: D8.4.11
9 Project Management MGT ST 34 M1 M36From: D9.1.1
To: D9.4.4
TOTAL 944
8Enrico Macii -- [email protected]
Gantt ChartGantt Chart
T1.1 Technology characterizationT1.2 Tool requirementsT1.3 Test case identification
T2.1 Compact thermal modeling of new device structures and technologies T2.2 Compact thermal modeling of CMOS devices for integrated circuits T2.3 Physics-based compact thermal modeling for discrete devices
T3.1 Logi-thermal simulation methods and tools T3.2 Thermal effects in digital circuit design for new CMOS technologies
T3.3 Logic design methodologies for temperature-insensitive circuits T3.4 Monitoring circuits and design methodologies for thermal effect compensation
T4.1 Thermal modeling of analog/RF blocks T4.2 Analog/RF circuit analysis in presence of high temperatures and on-chip thermal gradients
T5.1 Thermal modeling of discrete components T5.2 Validation of modeling framework for discrete components
T6.1 Thermal description of the system package and ambient influence T6.2 Thermal distribution in 3D SiP stacks and 2D SoCs T6.3 System-level thermal-aware design
T7.1 Validation of models on silicon structures T7.2 Demonstration of design techniques on test chips
T7.3 Evaluation of design methods and prototype tools on test cases
T8.1 Set-up and maintenance of project web-site T8.2 Dissemination T8.3 Training T8.4 Exploitation and roadmapping
T9.1 Implementation of project management structures
T9.2 Project management
T9.3 IPR management
M0 M12 M24 M36
WP1
WP2
WP3
WP4
WP5
WP6
WP7
WP8
WP9
Dx.y.1Dx.y.2Dx.y.3Dx.y.4Dx.y.5Dx.y.6
Dx.y.7Dx.y.8Dx.y.9Dx.y.10Dx.y.11
R&D ActivitiesR&D Activities(WP1, WP2, WP3, WP4, WP5, WP6)(WP1, WP2, WP3, WP4, WP5, WP6)
10Enrico Macii -- [email protected]
WP1 (Leader: IFX)WP1 (Leader: IFX)
WP1: Technology Characterization, Tool Requirements and Test Case Identification
T1.1: Technology CharacterizationInvestigation and characterization of a wide collection of different nanoelectronic technologies and device architectures regarding temperature sensitivity and thermal effects
T1.2: Tool RequirementsSpecification of the requirements for the EDA methodologies, tools and flows that will be developed within the project
T1.3: Test Case Identification Identification by the semiconductor vendors of the test structures and of the test cases
that will be used to assess the quality of the models, design solutions and EDA methodologies and prototype tools
11Enrico Macii -- [email protected]
WP1 (Leader: IFX)WP1 (Leader: IFX)
Task Duration Partners Involved
T1.1 M1-M24 IFX, ST, NXP
T1.2 M1-M3 MUN, CV, GDA, SNPS, ST, IFX, NXP
T1.3 M1-M12 ST, IFX, NXP
12Enrico Macii -- [email protected]
WP1 (Leader: IFX)WP1 (Leader: IFX)
13Enrico Macii -- [email protected]
WP2 (Leader: IFX)WP2 (Leader: IFX)
WP2: Process, Device and Compact Modeling
T2.1: Compact thermal modeling of new device structures and technologies
Development of methods for numerical simulation of devices that utilize new semiconductor structures and technologies, down to the 32/28nm process node.
T2.2: Compact thermal modeling of CMOS devices for integrated circuits
Development of methods for numerical simulation of devices for integrated circuits implemented with traditional, state-of-the-art CMOS technologies.
T2.3: Physics-based compact thermal modeling for discrete devices Development of methods for numerical simulation of devices for discrete semiconductor devices, specifically suitable for power converters and RF applications.
14Enrico Macii -- [email protected]
WP2 (Leader: IFX)WP2 (Leader: IFX)
Task Duration Partners Involved
T2.1 M1-M24 IFX, FHG, SNPS
T2.2 M1-M24 UNIBO, FHG, SNPS
T2.3 M1-M24 NXP, ST, SNPS
15Enrico Macii -- [email protected]
WP2 (Leader: IFX)WP2 (Leader: IFX)
16Enrico Macii -- [email protected]
WP3 (Leader: POLITO)WP3 (Leader: POLITO)
WP3: Modeling, Simulation and Design of Digital Blocks T3.1: Logi-thermal simulation methods and tools
Generation of a logic/thermal co-simulator for the target technologies. This simulator will rely on thermal models of the basic design primitives (namely, logic gates, memory elements, interconnects).
T3.2: Thermal effects in digital circuit design for new CMOS technologiesThermal efficiency comparison of different implementation of a test design using the new technologies and using traditional, state-of-the-art bulk CMOS technologies.
T3.3: Logic design methodologies for temperature-insensitive circuitsInvestigation and development of innovative techniques, methodologies and prototype tools for thermal-aware synthesis.
T3.4: Monitoring circuits and design methodologies for thermal effect compensationInvestigation and development of innovative techniques, methodologies and prototype tools for thermal effect compensation, control and management.
17Enrico Macii -- [email protected]
WP3 (Leader: POLITO)WP3 (Leader: POLITO)
Task Duration Partners Involved
T3.1 M1-M30BME, GDA, POLITO, UNIBO
T3.2 M13-M30 IFX, POLITO
T3.3 M1-M30POLITO, CSEM, GDA, SNPS, ST
T3.4 M1-M30LETI, CSEM, POLITO, GDA, SNPS, ST
18Enrico Macii -- [email protected]
WP3 (Leader: POLITO)WP3 (Leader: POLITO)
19Enrico Macii -- [email protected]
WP4 (Leader: NXP)WP4 (Leader: NXP)
WP4: Modeling and Simulation of Analog/RF Blocks
T4.1: Thermal modeling of analog/RF blocksSince standard compact models, like those developed in the context of WP2, are not sufficient for such components, more accurate behavioral models are needed, which include also self heating effects. Therefore, electrical compact models have to be completed by model parts for the thermal behavior.
T4.2: Analog/RF circuit analysis in presence of high temperatures and on-chip thermal gradientsIn this Task, simulation-based methodologies to analyze and reduce the impact of thermal fluctuations on the behavior, yield or reliability of analog/RF blocks will be developed. In a first step, critical analog/RF components will be identified.
20Enrico Macii -- [email protected]
WP4 (Leader: NXP)WP4 (Leader: NXP)
Task Duration Partners Involved
T4.1 M1-M24 FHG, NXP, ST, MUN, SNPS, BME.
T4.2 M7-M30 MUN, NXP, ST
21Enrico Macii -- [email protected]
WP4 (Leader: NXP)WP4 (Leader: NXP)
22Enrico Macii -- [email protected]
WP5 (Leader: ST)WP5 (Leader: ST)
WP5: Modeling and Simulation of Discrete Components
T5.1: Thermal modeling of discrete componentsThe objective of this task is the investigation and implementation of a modeling framework for discrete components.
T5.2: Validation of modeling framework for discrete componentsThe main objective of this Task is to validate the modeling framework of Task T5.1 through comparison of the data coming from camera-based analysis to those collected by application of the modeling methodology implemented inside the framework. Validation thus requires the implementation of one or more test cases,
23Enrico Macii -- [email protected]
WP5 (Leader: ST)WP5 (Leader: ST)
Task Duration Partners Involved
T5.1 M1-M24 SNPS, ST, IMEC, UNIBO
T5.2 M19-M30 ST, IMEC, FHG
24Enrico Macii -- [email protected]
WP5 (Leader: ST)WP5 (Leader: ST)
25Enrico Macii -- [email protected]
WP6 (Leader: NXP)WP6 (Leader: NXP)
WP6: Package/System Modeling and Design Exploration under Ambient Influence
T6.1: Thermal description of the system package and ambient influenceHeat diffusion is a phenomenon where the surrounding ambient has to be considered. This naturally includes the package, as well as the influence from the outside ambient. To to analyze and describe the different thermal systems, measurements and simulations will be performed. The wide range of products of the partners, from discrete components to complex ICs, ensures a good coverage of many applications currently in the market. The thermal characterization will be conducted under different ambient influences and the results will be used as input for modeling the effects of heating.
T6.2: Thermal distribution in 3D SiP stacks and 2D SoCsWhile Task T6.1 is focussing on the macroscopic influencing factors as the package structure, this task focuses on describing the local impact of die temperature distribution due to self heating, and the description of thermal feedback.
T6.3: System-level thermal aware design In this task, thermal design space exploration and automated thermal-aware design
capabilities are developed.
26Enrico Macii -- [email protected]
WP6 (Leader: NXP)WP6 (Leader: NXP)
Task Duration Partners Involved
T6.1 M1-M24 NXP, ST, SNPS, BME, FHG
T6.2 M1-M24 OFFIS, ST, CV, GDA, IMEC, UNIBO
T6.3 M1-M30 IMEC, ST, CV, OFFIS, UNIBO
27Enrico Macii -- [email protected]
WP6 (Leader: NXP)WP6 (Leader: NXP)
Validation, Demonstration and Validation, Demonstration and Evaluation ActivitiesEvaluation Activities
(WP7)(WP7)
29Enrico Macii -- [email protected]
WP7 (Leader: NXP)WP7 (Leader: NXP)
WP7: Validation, Demonstration and Evaluation
T7.1: Validation of models on test structuresIn this task, models developed in other work-packages are validated on multiple test-structures at different levels of abstraction.
T7.2: Demonstration of design techniques on test chipIn this task, the new design techniques are validated on silicon test structures and test chips.
T7.3: Evaluation of prototype tools on test casesIn this task, prototype tools are evaluated on the test cases defined in Task T1.3, as well as on additional design examples provided by the industrial partners
30Enrico Macii -- [email protected]
WP7 (Leader: NXP)WP7 (Leader: NXP)
Task Duration Partners Involved
T7.1 M19-M36 IFX, ST, NXP, SNPS, BME, FHG, IMEC, UNIBO
T7.2 M19-M36 ST, IFX, CSEM, LETI, POLITO, UNIBO
T7.3 M19-M36 NXP, ST, CV, GDA, MUN, SNPS, BME, IMEC, LETI, OFFIS, POLITO
31Enrico Macii -- [email protected]
WP7 (Leader: NXP)WP7 (Leader: NXP)
Dissemination, Training,Dissemination, Training,Exploitation and Roadmapping Exploitation and Roadmapping
ActivitiesActivities(WP8)(WP8)
33Enrico Macii -- [email protected]
WP8 (Leader: ST)WP8 (Leader: ST)
WP8: Dissemination, Training, Exploitation, Roadmapping
T8.1: Set-up and maintenance of the project web-siteThe objective of this Task is the set-up and maintenance of a public web-site that will constitute the main point of collection of the project information, including public deliverables, summary of major scientific achievements advertisement of dissemination and training activities. Maintenance and incremental updates will take place monthly, major revisions and restructuring will occur every six months.
T8.2: DisseminationThe partners of the THERMINATOR Consortium will disseminate the project results through various means. This tasks covers all the dissemination activities.
T8.3: TrainingThe activities in this task are of two kinds. First, preparation of course material on thermal-aware design. Second, planning, advertisement, organization and execution of the courses. In the first year of the project, existing knowledge and new ideas from all partners will be collected and training material (in electronic form) will be generated by the participants of this task.
T8.4: Exploitation and RoadmappingThe partners of the THERMINATOR Consortium will exploitation the project results through various means. This tasks covers all the dissemination activities.
34Enrico Macii -- [email protected]
WP8 (Leader: ST)WP8 (Leader: ST)
Task Duration Partners Involved
T8.1 M1-M36 ST
T8.2 M1-M36 POLITO, All
T8.3 M1-M36 BME, All
T8.4 M1-M36 ST, IFX, NXP, CV, GDA, MUN, SNPS, OFFIS, POLITO
35Enrico Macii -- [email protected]
WP8 (Leader: ST)WP8 (Leader: ST)
36Enrico Macii -- [email protected]
WP8 (Leader: ST)WP8 (Leader: ST)