IE1204 Digital Design
L7: Combinational circuits,Introduction to VHDL
Masoumeh (Azin) Ebrahimi ([email protected])
Elena Dubrova ([email protected])KTH / ICT / ES
• BV 318-339, 60-65, 280-291,341-365
This lecture
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PLD (eg. PAL)
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Fan-in issue3
FPGA (eg. Cyclone II)
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Typically 50000 logicelements
Technology : MUX tree4
Multiplexer (MUX)
• The multiplexer canselect which input youare going to connectto the output
• ”If S then X, else Y”1
0
X
Y
S
Z
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Z = SX + SY
5
Multiplexer (MUX)
• The multiplexer canselect which input youare going to connectto the output
• ”If S then X, else Y”1
0
X
Y
S
Z
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Z = SX + SY1
6
Multiplexer (MUX)
• The multiplexer canselect which input youare going to connectto the output
• ”If S then X, else Y”1
0
X
Y
S
Z
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Z = SX + SY0
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Implementation of functions usingMUXes
How can the following functionsbe implemented with a 2:1multiplexer?
• Z = B (INV)• Z = AB (AND)• Z = A + B (OR)• Z = A Å B (XOR)
1
0
X
Y
S
Z
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Z = SX + SY
8
Quickie Question …
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• How to connect the inputs of the MUX inorder to implement an inverter?
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Inverter implemented with a MUX
1
0
0
1Z
Input x0
1 0
x0 0 1
NOT
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Specification:if input = ’1’ then result <= ’0’;if input = ’0’ then result <= ’1’;
0 00 0 1
Z S X S Y
x x x NOT
= × + × =
= × + × =
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Quickie Question …
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• How to connect the inputs of the MUX inorder to implement an AND gate?
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AND implemented with a MUX
• Specification:
1
0
x0
0Z
x1
0 00 1
x0x1
0
1
0 1
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01101 0 xxxxxYSSXZ ×=×+×=+=
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AND implemented with a MUX
• Specification:
1
0
x0
0Z
x1
0 00 1
x0x1
0
1
0 1
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01101 0 xxxxxYSSXZ ×=×+×=+=1
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AND implemented with a MUX
• Specification:
1
0
x0
0Z
x1
0 00 1
x0x1
0
1
0 1
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01101 0 xxxxxYSSXZ ×=×+×=+=0
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OR implemented with a Mux
• Specification:
1
0
1
X0
Z
X1
0 11 1
x0x1
0
1
0 1
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1 01 0 0 1
0 11 0 0
11 0
{ } ( )
1
Z x x x x x x
SX SY x x x x x
x x x
= + + =
= + = + + × =
= × + ×15
OR implemented with a Mux
• Specification:
1
0
1
X0
Z
X1
0 11 1
x0x1
0
1
0 1
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1 01 0 0 1
0 11 0 0
11 0
{ } ( )
1
Z x x x x x x
SX SY x x x x x
x x x
= + + =
= + = + + × =
= × + ×
1
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OR implemented with a Mux
• Specification:
1
0
1
X0
Z
X1
0 11 1
x0x1
0
1
0 1
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1 01 0 0 1
0 11 0 0
11 0
{ } ( )
1
Z x x x x x x
SX SY x x x x x
x x x
= + + =
= + = + + × =
= × + ×
0
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XOR implemented with a Mux
• Specification:
1
0
X0
X0
Z
X1
0 11 0
x0x1
0
1
0 1
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010101 xxxxxx
YSSXZ
Å=×+×=
=+=
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XOR implemented with a Mux
• Specification:
1
0
X0
X0
Z
X1
0 11 0
x0x1
0
1
0 1
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010101 xxxxxx
YSSXZ
Å=×+×=
=+= 1
19
XOR implemented with a Mux
• Specification:
1
0
X0
X0
Z
X1
0 11 0
x0x1
0
1
0 1
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010101 xxxxxx
YSSXZ
Å=×+×=
=+= 0
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Hierarchy of MUXes
1
0
X11
X10
Z
S1
1
0
1
0
X01
X00
S0
11100100
ZX01
S1S0
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X00
X10
X11
000
0X00
X10
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1 1 0 0
0 1 1 0
xyz 00 01 11 10
0
Implementation of larger functionswith MUXes
An (n + 1)-input function can be implemented with a MUX that has nselect inputs!
Choose any of the inputs as address inputs ...
... And minimize/implement function for each input.Draw new Karnaugh diagrams if necessary.
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x y
f
z 11100100
01z
zyyxxzf ++=1
22
• Any Boolean function f (xn, ..., x1, x0) can be partitioned asf(xn, ..., x1, x0) = x0 f1(xn, ..., x1,1) + x0 f0(xn, ..., x1,0)
• The function can then be implemented with a multiplexer
Mapping into MUXes:Shannon decomposition (BV 6.1.2)
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fxn
x0
x1
f1xn
1x1
f0xn
0x1
f
x0 123
• Any Boolean function f (xn, ..., x1, x0) can be partitioned asf(xn, ..., x1, x0) = x0 f (xn, ..., x1,1) + x0 f (xn, ..., x1,0)
• The function can then be implemented with a multiplexer
Mapping into MUXes:Shannon decomposition (BV 6.1.2)
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fxn
x0
x1
f1xn
1x1
f0xn
0x1
f
x0 024
Mapping to MUXes:Shannon decomposition
• Any Boolean function f (xn, ..., x1, x0) can be decomposed(recursively) as
f(xn,...,x1,x0) = x0 f1(xn, ..., x1,1) + x0 f0(xn, ..., x1,0)= x1x0 f11(xn, ..., x2,1,1) + x1x0 f10(xn, ..., x2,1,0)+ x1x0 f01(xn, ..., x2,0,1) + x1x0 f00(xn, ..., x2,0,0)
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1
0
f11
f10
f
x1
1
0
1
0
f01
f00
x0
1
0f
x0
f1
f0
f1
f0
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Proof
• Right-hand side:– If x0 = 1 then the right term is zero. Then f is equal to the left term.– If x0 = 0, the left term is zero. Then f is equal to the right term.
• Left-hand side:– if x0 = 1, then f is equal to f (xn, ..., x1,1) (= left term on the right-hand side)– if x0 = 0 then f is equal to f (xn, ..., x1,0) (= right term in the right-hand side)
• Left-hand side = Right-hand side
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)0,,...,()1,,...,(),,...,( 101001 xxfxxxfxxxxf nnn ×+×=
Right-hand sideLeft-hand side
Right termLeft term
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Mux circuits
0 1 0 1
1 0 1 0
yzx
0
1
Address
10
z
10
10
y
10
10
10
10
x
111 1
011 0
101 0
001 1
110 0
010 1
100 1
000 0
AddressBut this is a memory
(ROM, RAM ...) Address pins
Value
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00 01 11 10
XYZ
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Look-up tables (LUT)
0/1
0/1
0/1
0/1x1
x2
f
Two-input LUT
Programmablecell 1
0
1
0
1
0
A LUT with n inputs canrealize all combinationalfunctions with up to ninputs
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Example: XOR gate
0
1
1
0x1
x2
f
Two-input LUT
ProgrammedValues 1
0
1
0
1
0
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1 2
1 1 01 0 10 1 10 0 0
x x f
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• The simplest FPGA cell consists of a singletable (e.g. Look-Up-Table - LUT), a D flip-flop and a bypass MUX.
A simple FPGA cell
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LUT D Q
CLK
ABCD M
RESET
S01
D-flipflop will be explained soonin this course
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One way to identify functions...
n inputs => 2(2n) possibledifferent Boolean functions
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MSB
LSB
)(69960123 "0101100110100110"),,,( Hfxxxxf ==
The functions that are storedin a LUT are usuallynumbered after the numberthat is made up of the 1's inthe truth table / Karnaughmap.
Bit # 15 Bit # 0Bit # 1
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LUT function number
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69960123 "0101100110100110"),,,( fxxxxf ==
01236996 xxxxf ÅÅÅ=
With a LUT, all functions arerealized in the same way, so allof them have the same costOdd parity
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• Mostly used as address decoders• Only one output is active when the
'enable' (En) signal is active• The active output is selected by a1a0
Decoder
En a1 a0 y0 y1 y2 y3
1 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 10 - - 0 0 0 0
a0
a1
En
y3y2y1y0
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2-to-4 decoder
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Demultiplexer
• The demultiplexer has basically the same functionas the decoder, but it is drawn differently
• The input I is connected to a selected output
I a1 a0 y0 y1 y2 y3
1 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 10 - - 0 0 0 0
a1a0
I
y3y2y1y0
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a1a0
y3y2y1y0
10
I
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Read-Only Memory
0/1 0/1 ... 0/1
0/1 0/1 ... 0/1
.
.
.
0/1 0/1 ... 0/1
a0
a1
...am-1
Sel0
Sel1
.
.
.
Sel2m-1
En
dn-1 dn-2 …. d0
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Programablebits
Three-statebuffers
Decoder
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Encoders
• Encoder has the opposite function to adecoder, i.e. it translates 2N bit input into anN-bit code.– The information is greatly reduced
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2n
inputs
w0
w2n 1-
y0
yn 1-
noutputs
w0 w1 w2 w3 y1 y0
1 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1
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Priority Encoder
• A Priority Encoder gives back the address of the input withthe lowest (or highest) indices that are set to 1 (or 0depending on what you are looking for)
• If all inputs are 0, the output z = 0, else z = 1
w0 w1 w2 w3 z y1 y0
1 - - - 1 0 00 1 - - 1 0 10 0 1 - 1 1 00 0 0 1 1 1 10 0 0 0 0 - -
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The output is well-defined even ifseveral inputs areactive at the sametime.
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Overview
a1a0
y3y2y1y0
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S1S0
w3w2w1w0
Demultiplexer
Multiplexer
Decoder
Encoder
f y1
y0
w3w2w1w0
noutputs
w0
w1
En
y3y2y1y0
ninputs
2n
outputs
2n
inputs
Equivalent
Z Used in priorityencoders
I
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Code converters
• A code converter translates from one code toanother. Typical examples are:– Binary to BCD (Binary-Coded Decimal)– Binary to Gray code– 7-4-2-1 code– BCD to seven-segment decoder
w0
w1
w2
w3
abcdefg
a
b
c
d
e
f
g
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A variant of the 7-4-2-1code is used today tostore the bar code
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BCD-to-seven segment decoder
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1011
111
w0 a
1
b
0 1
11
1
01
101
0
0
w1
011
0
0
w2
000
0
1
w3
000
0
0
c
1010
0110
1110
0001
1001
1111
011
0
1 1
11
1
11
011
1
d
0
10
0
10
e
101
1
1
01
0
01
000
1
f
1
00
1
11
g
101
1
1
11
1
01
• BCD-to-7 segment decoder consists of 7 differentcombinatorial circuits, one for each segment
• To get optimal circuits, all 7 functions have to be minimizedsimultaneously so that common logic is shared
w0w1w2w3
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Disadvantage of binary codes
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· For safe data registration use Gray code· For data processing use binary code
Binary code, adjacent code words:1-2 double change3-4 triple change5-6 double change7-8 quadruple change!9-A double changeB-C quadruple change!D-E double changeF-0 quadruple change!
Can two bits change at exactly the same time?
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• By changing the order of the codewords in abinary code, one construct codes in which nomore than one bit is changing at a time
• Such codes are called Gray codes
Gray code
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0000, 0001, 0011, 0010, 0110, 0111, 0101, 01001100, 1101, 1111, 1110, 1010, 1011, 1001, 1000
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Conversion between binary and Gray
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Binary ® Gray:If Binary bit bn and bit bn-1 are different,the Gray code bit gn-1 is ”1", else ”0".
Gray ® Binary (most common transformation direction):If Binary bit bn and Gray code bit gn-1 are different theBinary bit bn-1 is ”1", else ”0".
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Logic for Gray to Binary conversion
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XOR-gate is ”1” if itsinputs are different! 4 bit code converter
Gray code to Binary code
Gray/Bin
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Logic for Gray to Binary conversion
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XOR-gate is ”1” if itsinputs are different! 4 bit code converter
Gray code to Binary code
Gray/Bin0 0 1 0
0 0 1 1
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Introduction to VHDL
• VHDL is a language used to specify thehardware– HDL - VHSIC Hardware Description Language– VHSIC - Very High Speed Integrated Circuit– Used mostly in Europe
• Verilog is another language used to specifythe hardware– Used mostly in the United States
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Why VHDL?
• VHDL is used to– verify that you have connected right by simulating the
circuit– describe the large structures in a simple way and then
generate the circuit by synthesis– allows for structured descriptions of a circuit
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VHDL increases the level of abstraction!
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• There are two types of VHDL code– VHDL for synthesis: The code is used as an
input to a synthesis tool which converts it intoan implementation (for example FPGA or ASIC)
– VHDL modeling and simulation code is used todescribe a system at an early stage. Since thecode can be simulated so you can checkwhether the intended functionality is correct
Types of VHDL code
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Entity
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CinAB
SCout
FA
ENTITY fulladder ISPORT( A,B,Cin : IN STD_LOGIC;
S,Cout : OUT STD_LOGIC);END fulladder;
The entity describes the ports to the outside of the circuit.The circuit as a block.
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Architecture
IE1204 Digital Design, Autumn 2015
CinAB
SCout
FA
ARCHITECTURE behave OF fulladder ISBEGIN
S <= A xor B xor Cin;Cout <= (A and B) or (A and Cin) or (B and Cin);
END behave;
Architecture describes the function inside the circuit.
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Entity
• An entity describes a component's interface with theoutside world
• PORT-declaration indicates if it is an input or an output• An Entity is a symbol of a component.
ENTITY xor_gate ISPORT (x, y: IN BIT;
q: OUT BIT);END xor_gate;
x
yqxor_gate
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Use English names for variable names in the code!
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VHDL Basics
• PORT declaration establishes interface between thecomponent and the outside world
• A port declaration contains three things:– The name of the port– The direction of the port– Port's datatype
• Example: ENTITY test ISPORT ( name : direction data_type);
END test;
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The most common data types
• Scalars (single-variable signals)– Bit ("0", "1")– Std_logic ('U', '0', ’1', 'X', 'Z', 'L', 'H', 'W', '-')– Integer– Real– Time
• Vectors (many-variable signals)– BIT_VECTOR - vector of bits– STD_LOGIC_VECTOR - vector of std_logic
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Architecture
• An architecture describes the operation of a component• An entity can have many architectures, but only one can be
active at a time• An architecture corresponds to the component diagram or
behavior
ARCHITECTURE behavior OF xor_gate ISBEGIN
q <= a xor b after 5 ns;End behavior;
x
yq
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Code for Simulation
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VHDL Example: 4/1 MUX
IE1204 Digital Design, Autumn 2015
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Multiplexer_41 IS
PORT(ce_n: IN std_logic; -- Chip Enable (active low)
data_in: IN std_logic_vector(3 DOWNTO 0);
sel: IN std_logic_vector(1 DOWNTO 0);
data_out: OUT std_logic); -- TriState Output
END ENTITY Multiplexer_41;
sel(1) sel(0)
data_out11100100
data_in(3)data_in(2)data_in(1)data_in(0)
ce_n
Ñ
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VHDL Example: 4/1 MUX (cont.)
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ARCHITECTURE RTL OF Multiplexer_41 IS
BEGIN
PROCESS(ce_n, data_in, sel)
BEGIN
IF ce_n = '1' THEN
data_out <= 'Z';
ELSE
CASE sel is
WHEN "00"=> data_out <= data_in(0);
WHEN "01"=> data_out <= data_in(1);
WHEN "10"=> data_out <= data_in(2);
WHEN "11"=> data_out <= data_in(3);
WHEN OTHERS => null;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
sel(1) sel(0)
data_out11100100
data_in(3)data_in(2)data_in(1)data_in(0)
ce_n
Ñ
56
• The study material on synthesis shows anumber of VHDL constructs and theresulting hardware
• The following slides contain extra materialThe book gives many examples anddetailed explanations of VHDL
More on VHDL
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• The course textbook contains a CD with thesynthesis tool, Quartus
• You will use Quartus in Lab 3
Synthesis tool Quartus
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• Implementation of functions with MUXes– Shannon decomposition
• Look-up tables, ROM• Decoder, encoder, code converters• Introduction to VHDL• Next lecture: BV pp. 383-418, 469-471
Summary
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VHDL (Not part of the exam)
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Signal declaration
Signal-declaration is used inside architectures to declareinternal (local) signals:
signal a, b, c, d: bit;
signal a, b, sum: bit_vector (31 downto 0);
Signal-assignment is used to describe the behavior:
sum <= a + b; signal assignment without delay
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VHDL description styles
• Structural– similar to how to connect components
• Sequential– similar to how to write desktop applications
• Data Flow– Concurrent assignments
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Sequential vs Parallel Code
• There are two types of code execution in VHDL:sequential and parallel
• Hardware can then be modeled in two different ways
– VHDL supports different levels of abstraction.
• Sequential code describes the hardware from a"programmer's" point of view and it is executed in theorder which is defined
• The parallel code is executed regardless of the order. It isasynchronous.
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Sequential style
XOR gatex
yq
Process (x, y)begin
if (x/= y) thenq <= '1';
elseq <= '0';
end if;end process;
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Data flow style
XOR gatex
yq
q <= a xor b;
- Or in behavioral dataflow style
q <= '1' When a /= b else "0";
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Structural style
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x
yq
u1: not_gate port map (x,xi);u2: not_gate port map (y,yi);u3: and_gate port map (xi,y,t3);u4: and_gate port map (yi,x,t4);u5: or_gate port map (t3,t4,q);
yi
xi t3
t4
66
Structural Code
• A component must be declared before it can be used
• It is necessary, unless it is not in a library somewhere
ARCHITECTURE Test OF test_entityCOMPONENT and_gatePort (in1, in2: IN BIT;
out1: BIT OUT);END COMPONENT;
... more statements...
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Instantiation
• Component instantiation ring connects the componentinterface with the signals in the architecture
ARCHITECTURE Test OF test_entityCOMPONENT and_gatePort (in1, in2: IN BIT;
out1: BIT OUT);END COMPONENT;SIGNAL S1, S2, S3: BIT;
BEGINGate1: and_gate PORT MAP (S1, S2, S3);
END test;
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in1
in2out1
S1
S2S3
68
Generate
• Generate-statement couples many similar elementsENTITY adder IS
GENERIC (N: integer)PORT (a, b: IN bit_vector (N-1 downto 0);
sum: OUT bit_vector (N-1 downto 0));END adder;ARCHITECTURE OF structural adder ISCOMPONENT full_adderPORT (a, b, cin: IN bit; cout, s: OUT bit);
END COMPONENT;signal c: bit_vector (N-2 downto 0);
BEGING0: for i in 1 to N-2 GenerateU0: full_adder PORT MAP (a (i), b (i), c (i-1), c (i), p (i));
end Generate; - G0U0: full_adder PORT MAP (a(0), b(0), ’0’, c(0), p(0));UN: full_adder PORT MAP (a(n-1),b(n-1),c(n-2),OPEN, s(n-1);
END structural;
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Generate n-bit adder
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FA
a1 b1
cin1FA
a0 b0
cin0
s0s1
FA
an-1 bn-1
cinn-1
sn-1
cut0cutn-1
Five lines of code generates the ripple-carry n-bit adderfrom F5!
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The test bench stimuli 1
IE1204 Digital Design, Autumn 2015
ENTITY testbench IS END testbench;
ARCHITECTURE xor_stimuli_1 of testbench ISCOMPONENT xor_gatePORT(x,y:IN bit; q:OUT bit);
END COMPONENT;signal x,y,u1:bit;
BEGINx <= not(x) after 10 ns;y <= not(y) after 20 ns;U1:xor_gate PORT MAP (x,y,ut1);
END example;
The ENTITY is empty!
Here are the testsignals generated
The circuit under test isused as a component of thetest bench program
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The test bench stimuli 2
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ENTITY testbench IS END testbench;
ARCHITECTURE xor_stimuli_2 of testbench ISCOMPONENT xor_gatePORT(x,y:IN bit;q:OUT bit);
END COMPONENT;signal x,u1,u2,u3:bit; -- Endast en in-signalfor U1:xor_gate use entity work.xor_gate(behave);for U2:xor_gate use entity work.xor_gate(data_flow);for U3:xor_gate use entity work.xor_gate(structural);
BEGINx <= not(x) after 10 ns;U1:xor_gate PORT MAP (x,x,ut1);U2:xor_gate PORT MAP (x,x,ut2);U3:xor_gate PORT MAP (x,x,ut3);
END example;
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Test bench
IE1204 Digital Design, Autumn 2015
A test bench can mark when the desired eventsoccur during the execution.
Or mark when unwanted events occur
The result of a run with a test bench can be saved in a file, as proofthat everything is ok - or as a troubleshooting aid if it did not gowell.
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