DISPLAY
HDMI
What is HDMI• HDMI – High-Definition Multimedia Interface*
– Allows for transmission of digital audiovisual content on the same physical link (DVD player, TV’s, set top boxes etc…)
– Digital interface defined around DVI1.0 specification and backwards compatible with DVI
– Command and control data (DDC)
• Content Protection via HDCP (High Definition Content Protection)
• Administered by HDMI * LLC (Limited Liability Corporation)– Licensing and Royalty fees apply
• Transfer rate depends on display mode.– Spec range 25MHz to 340MHz (dense spectrum of frequencies)– Max speed is a product decision. IBX, CPT max: 222.5MHz
HDMI Overview
EDIDROM
HDMI Sink (Rx)
HDMITransmitter
Video
Audio
Control/Status
TMDS Channel 0
HDMIReceiver
TMDS Channel 1
Display Data Channel (DDC)
HDMI Source (Tx)
Video
Audio
Control/Status
TMDS Clock Channel
TMDS Channel 2
HDMI Cable
CEC
HPD
Main Link: 250Mbps to 3.4Gbps per channel, 25-340MHz sideband clock RGB or YCbCr 444 or 422, TMDS and TERC4 encoding3.3V Rx termination, ~500mV swing based on DVI 1.0 Spec accounts for AC coupling tolerance on Sink (not Source)
DDC: 100 KHz, I2C format, 3.3 - 5VHPD: Hot Plug Detect, 2 - 5VCEC: Optional 400 Hz bus, 2.5 – 3.3V (We do not support CEC)
HDMI Overview
DDC Display Data Channel(HDMI) transmitter A device with an HDMI output.(HDMI) receiver A device with an HDMI input.
TMDS clock is used by the receiver as a frequency reference for data recovery on the three TMDS datachannels.
• HDMI has three physically separate communication channels, which are the DDC, TMDS, and the optional CEC
– The HDMI cable and connectors carry four differential pairs that make up the TMDS data and clock channels.
» Audio, video and auxiliary data is transmitted across the three TMDS data channels.
» A TMDS clock, typically running at the video pixel rate, is transmitted on the TMDS clock channel
HDMI Overview
– HDMI carries a VESA DDC channel. The DDC is used for configuration and status exchange between a single transmitter and a single receiver.
» The DDC is used by the transmitter to read the receiver’s Enhanced Extended Display Identification Data (E-EDID) in order to discover the receiver’s configuration and capabilities.
– The optional CEC protocol provides high-level control functions between all of the various audiovisual products in a user’s environment.
HDMI Overview
• There are 3 Types of HDMI connector, Type A , B and C. All three connectors carry all required HDMI signals, including a TMDS link.
• The Type B connector is slightly larger and carries a second TMDS link, which is necessary to support very high resolution displays using dual link.
• The Type C connector carries the same signals as the Type A but is more compact and intended for mobile applications.
• The HDMI connector provides a pin allowing the transmitter to supply +5.0 Volts to the cable and receiver.
• All HDMI transmitters shall assert the +5V Power signal whenever the transmitter is using the DDC or TMDS signals
HDMI Overview
HDMI Link• The HDMI link operates in one of three modes:• Video Data Period - the active pixels of an active
video line are transmitted• Data Island period - audio and auxiliary data are
transmitted using a series of packets.– This auxiliary data includes InfoFrames and other data
describing the active audio or video stream or describing the transmitter.
• Control period- It is used when no video, audio, or auxiliary data needs to be transmitted. It is required between any two periods that are not control periods.
Video Data on HDMI• Video data can have a pixel size of 24, 30, 36 or 48 bits. Color
depths greater than 24 bits are defined to be “Deep Color” modes.
• Video at the default 24-bit color depth is carried at a TMDS clock rate equal to the pixel clock rate.• Video Pixels Video Data Coding is such that the 8 bits
converted to 10 bits by HDMI transmitter.• The video pixels can be encoded in either RGB, YCBCR 4:4:4 or
YCBCR 4:2:2 formats.• Deep Color modes are optional though if an HDMI transmitter
or receiver supports any Deep Color mode*, it shall support 36-bit mode.
HDMI Frame Composition•Example frame: 1280x1024 resolution•Vertical and horizontal blanking filled by control sequences
– Color depth control information
– TERC4 encoding used
– HDMI specific controls
•Pixel periods filled with TMDS-encoded active pixel data
•Quick pixel clock Calculation:•HT*VT*Refresh Rate•1440*1054*60=91.0656MHz
EDIDExtended display identification data
• HDMI transmitter shall read the EDID and first CEA Extension to determine the capabilities supported by the receiver.
• HDMI transmitter shall check the E-EDID for the presence of an HDMI Vendor Specific Data Block within the first CEA Extension to determine whether it is an HDMI/DVI device.
• All the receiver supports 640 * 480P video format by default.
Hot-Plug detect
• An HDMI receiver shall assert high voltage level on its Hot Plug Detect pin when the E-EDID is available for reading.
• HDMI receiver shall indicate any change to the contents of the E-EDID by driving a low voltage level pulse on the Hot Plug Detect pin.
HDMI UsageHistory: HDMI is based on DVI• HDMI is REQUIRED BY SPEC to interoperate with DVI
– Simple cable adapter is all that is allowed• DVI = Digital Visual Interface; used on PC’s (and some TV’s)• Almost identical electrical spec, same coding and clocking• HDMI connector is smaller than DVI, but same digital signals• HDMI adds audio packets, “info frames”, compliance testing
Interface to Consumer Electronics displays (TV)• Set-top box to TV• DVD player to TV• Input to DVD burner (Content protection application)
Interoperate with DVI• HDMI on DVD player to DVI on PC display• DVI on PC to HDMI display
OR
External Cable
LCD Monitor
DVIHDMI HDCP
CE TV
Red 1TMDS Red
TMDS CLK
Green 1TMDS Green
Blue 1TMDS Blue
Red 2
Green 2
Blue 2
Red 3
Green 3
Blue 3
Red 4
Green 4
Blue 4
10-bitTMDS Code
10-bitTMDS Code
10-bitTMDS Code
10-bitTMDS Code
Red 5
Green 5
Blue 5
10-bitTMDS Code
TMDS Code and Clock
HPD
•HDMI main link is called the “TMDS Channel”– Three “TMDS” differential data lanes
• Red, Green, Blue each have a lane• 10 bit “TMDS” coded data
– TMDS is only used on HDMI and DVI
– TMDS Clock lane• Clock is 1/10 bit rate
– We send TMDS clock as a data pattern: 0000011111
HDMI TMDS Clock to Pixel Relationship
TMDS Clock is 1/10 bit transfer rate
8 Bit Per Component Example:
• 8 bits per color = 24 bits per pixel
• Each 8 bit color value is coded as a 10-bit TMDS code, mapped to one Tx lane
• TMDS clock runs at 1/10 the serialized bit rate, so …
• 1 TMDS clock = 1 pixel
For 1600x1200@24bpp, 60Hz refresh, pixel clock ~162MHz
TMDS Clock = 162MHz; Bit rate per lane = 1.62GT/s
Red 1TMDS Red
TMDS CLK
Green 1TMDS Green
Blue 1TMDS Blue
Red 2
Green 2
Blue 2
Red 3
Green 3
Blue 3
Red 4
Green 4
Blue 4
10-bitTMDS Code
10-bitTMDS Code
10-bitTMDS Code
10-bitTMDS Code
Red 5
Green 5
Blue 5
10-bitTMDS Code
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5
HDMI/DVI Main Link Topology
– DC coupled to Rx 3.3V termination• Process scaling issues• Back-power issues for Tx
– Signal amplitude is the same for all modes / speeds / channels
• No power or EMI savings for short cables• Signal integrity suffers at higher speed
HDMI or DVI“Spec” Tx
HDMI TVOr DVI MONITOR
AVcc = 3.3V
RT = 50ohms
RTMOTHERBOARD
HDMISOURCE SINK
HD
MI
Sou
rce
CO
NN
EC
TO
R
~11” Trace
HD
MI
Sin
kC
ON
NEC
TO
R
2m – 15m
Cable (TYP)
HDMICABLE
TMDS Data or Clock Lane:
Electrical Spec and Compliance Testing at
Connectors
HDMI* Connector DesignHDMI Type A
14 mm(W) x 5 mm(H)
37 mm(W) x 10 mm(H)
DVI1.0 Connector HDMI Type C
10.5 mm(W) x 2.5 mm(H)
• HDMI main link, HPD and DDC signals match single channel DVI• HDMI type A and C connectors have the same signals
• Type C targets small form factors• HDMI type B connectors are not in use