8/3/2019 Hardware Slides 16
1/32
DOC 112: Computer Hardware Lecture 16
Lecture 16
Random Access Memory and the FetchCycle
8/3/2019 Hardware Slides 16
2/32
DOC 112: Computer Hardware Lecture 16
Random Access Memory
We continue to put together a computersystem, and in this lecture add the memory.
We will consider first the implementation of
random access memory, and then turn to how
it is used by the central processor.
8/3/2019 Hardware Slides 16
3/32
DOC 112: Computer Hardware Lecture 16
One Bit Memory
A single D type flip flop is a one bit memory
To use it as such we need to give it an address
An address is simply a binary number
A binary number can be uniquely identified by a
decoder.
8/3/2019 Hardware Slides 16
4/32
DOC 112: Computer Hardware Lecture 16
D Q
Q'
D Q
DECODER
Address
Read
Data in
8
Data out
Clock
One bit static RAM
8/3/2019 Hardware Slides 16
5/32
DOC 112: Computer Hardware Lecture 16
A decoder is a binary to unary converter
8/3/2019 Hardware Slides 16
6/32
DOC 112: Computer Hardware Lecture 16
The circuit is asymmetric
For reading it is merely a combinatorial circuit
for writing it is a sequential circuit, the address and
data must be present and correct when the clockpulse sets the flip flop.
RAM circuits conforming to this pattern are called
static RAMs, and are used in special applications.
8/3/2019 Hardware Slides 16
7/32DOC 112: Computer Hardware Lecture 16
Buses
Buses are data highways which are common tomany circuits.
The address lines that go to the memory arereferred to as the address bus.
The read, data in and data out lines lines go toevery cell, and could also be called a bus.
8/3/2019 Hardware Slides 16
8/32DOC 112: Computer Hardware Lecture 16
Bi-Directional data buses
The data in and data out lines are never both used at thesame time.
It is convenient to use just one line as this reduces the
size and complexity of the memory circuit.
However, to make the data line bi-directional we need to
feed it from more than one place and we cannot do thiswith AND or NAND gates
8/3/2019 Hardware Slides 16
9/32DOC 112: Computer Hardware Lecture 16
1
0
8/3/2019 Hardware Slides 16
10/32DOC 112: Computer Hardware Lecture 16
BANG
8/3/2019 Hardware Slides 16
11/32DOC 112: Computer Hardware Lecture 16
Tri-State Buffer
If the control line, C, is set to zero the output followsthe input exactly
If C is set to 1 the output is neither zero nor one, butis effectively disconnected from the data line.
C
D
8/3/2019 Hardware Slides 16
12/32DOC 112: Computer Hardware Lecture 16
Bi directionalData line
D2
D3
C2
C3
D1
C1
Interfacing with tri-state buffers
8/3/2019 Hardware Slides 16
13/32DOC 112: Computer Hardware Lecture 16
ReadData
One bit
store
Row
Dec-oder
8
Column Decoder
44Address
To each cell
Read Data Enable
Diagram 16.3Layout of RAM
Row/Column organisation of RAM
8/3/2019 Hardware Slides 16
14/32
DOC 112: Computer Hardware Lecture 16
Practical RAM circuits
Each one bit memory cell is only enabled when both itsrow and the column lines are one.
In the case of a 256 bit RAM each decoder transforms a
four bit binary number into a sixteen bit unary number.
In the square array of one bit memory cells, there will
only ever be one cell for which both the row and thecolumn lines are one.
8/3/2019 Hardware Slides 16
15/32
DOC 112: Computer Hardware Lecture 16
Practical RAM circuits (again)
Each cell is connected to the same read/write line anddata line.
The data line is connected to the outside through a two
way tri state buffer, so that unless the chip is enabled no
data can pass either in or out.
This enables us to build external decoders for largercapacity RAMs made up of several banks of single chips.
8/3/2019 Hardware Slides 16
16/32
DOC 112: Computer Hardware Lecture 16
Problem Break
Given a 32 bit address bus:
1. How many bits of RAM could we address?
2. How many bytes of RAM could we
address?
3. What size decoder do we need for the row
and column decoders?
8/3/2019 Hardware Slides 16
17/32
DOC 112: Computer Hardware Lecture 16
Answer
With a 32 bit address bus we have 232 possibleaddresses which is in total 4GBytes.
Each bit of a byte will have the same addressso again we can address 4GBytes
The row and column decoders will both be 16to 64K decoders. (64K)2 = 4 GBytes
8/3/2019 Hardware Slides 16
18/32
DOC 112: Computer Hardware Lecture 16
Connecting RAM to a processor
Memory Address Register (MAR) Stores the address in memory for data transfer
Memory Data Register (MDR) or Memory BaseRegister (MBR).
Stores data to be transferred to memory
(Can be used for other purposes)
8/3/2019 Hardware Slides 16
19/32
DOC 112: Computer Hardware Lecture 16
256by 1
RAMRAM Clock
Read/Write
MAR
MDR
Address Bus
Data Bus
&c.
TSB
256by 1
RAM
Tri State Buffer
Connecting RAM to a processor
8/3/2019 Hardware Slides 16
20/32
DOC 112: Computer Hardware Lecture 16
Connecting RAM to a processor
Program Counter (PC)stores the address of the next program instruction
to be executed
Instruction Register
stores the program instruction being executed.
8/3/2019 Hardware Slides 16
21/32
DOC 112: Computer Hardware Lecture 16
MARMPX
MDR
IR
Function
Generator
Output
PC
MPX +1
To other registers
TSB
Address
Bus
Data
Bus
Connecting RAM to a processor
8/3/2019 Hardware Slides 16
22/32
DOC 112: Computer Hardware Lecture 16
256
by 1RAMRAM Clock
Read/Write
MARMPX
MDR
IR
Function
Generator
Output
Address Bus
Data Bus
PC
MPX +1
&c.
To other registers
TSB
256
by 1RAM
The whole connection
8/3/2019 Hardware Slides 16
23/32
DOC 112: Computer Hardware Lecture 16
The Fetch Cycle
The fetch cycle gets the next programinstruction from memory into the IR
It consists of just two operations
MAR PC
IR RAM[MAR], PC PC+1
The second operation consists of two register
transfers which occur in arallel.
8/3/2019 Hardware Slides 16
24/32
DOC 112: Computer Hardware Lecture 16
D Q D Q D Q
System
Clock
Clock
Control
logic
Register
Controlling individual registers
8/3/2019 Hardware Slides 16
25/32
DOC 112: Computer Hardware Lecture 16
Register Transfers
The register transfers are achieved in twoparts:
1. The multiplexers must be set to establish the
required connections
2. The clock pulses must be connected to the
registers which change their state.
8/3/2019 Hardware Slides 16
26/32
DOC 112: Computer Hardware Lecture 16
Idle(execute)
Set
MARGet
Instr.
0
11,0
1,0
The fetch cycle is a synchronous design problem
The idle state, will be replaced by an execute cycle
such as the one we used for the manual processor.
8/3/2019 Hardware Slides 16
27/32
DOC 112: Computer Hardware Lecture 16
The fetch cycle output logic
Clock Control Multiplexer Control
MAR IR PC PC Input MAR Input
Idle - - - - -Set MAR 1 0 0 X 0
Get Data 0 1 1 0 X
8/3/2019 Hardware Slides 16
28/32
DOC 112: Computer Hardware Lecture 16
Definitions
Zero sets the PC input multiplexer to select theincrementer
Zero sets the MAR input multiplexer to select theprogram counter
Using assignments
10 for theset MAR state
01 for the Get Data state
we can im lement the out ut lo ic triviall
8/3/2019 Hardware Slides 16
29/32
DOC 112: Computer Hardware Lecture 16
D Q D QFetch
IR/PC
Clock
MARClock
SystemClock
Q' Q'
8/3/2019 Hardware Slides 16
30/32
DOC 112: Computer Hardware Lecture 16
Dynamic RAMs: DRAMs
For bulk RAMs (eg >1Mbit chips) D-Q flipflops are not used since they are too big.
Instead large RAMs use only one transistor andone capacitor for each bit.
Capacitor charged = 1 state Capacitor uncharged = 0 state
8/3/2019 Hardware Slides 16
31/32
DOC 112: Computer Hardware Lecture 16
Maintaining dynamic RAM
The store is not permanent and all the cellsstoring ones drift to zero in a fraction of a
second.
So some method must be employed to restore
the capacitor charge regularly
For this reason circuits of this kind are called
d namic RAM.
8/3/2019 Hardware Slides 16
32/32
Refresh Logic
Refreshing the capacitor charges operateswhen the the computer is not accessing the
memory.
A Memory Controller must tell the DRAM to
refresh itself periodically.
This overhead is very low.