Global TriggerGlobal TriggerH. Bergauer, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, H. Bergauer, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H. Sakulin, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H. Sakulin,
J. Strauss, A. Taurok, C.-E. WulzJ. Strauss, A. Taurok, C.-E. Wulz
Vienna GroupVienna Group
presented by
Claudia-Elisabeth WulzClaudia-Elisabeth WulzTrigger Meeting, CERN, 17 Sep 2003
C.-E. Wulz 2 Trigger Meeting, Sep. 2003
A.Taurok 28 May 2003
Global Trigger56U Rack
4 Tracker Emulators,..other 6U_boards
(standard VME backplane)
GMT, GT, TCS(non-standard backplane)
Conversion boards(Fast signals,...)
(standard VME backplane)
2 S-links
JTAG
PCI-VME link
16 DT,CSC,RPC muon cables12 cables MIP/QUIET bits7 cables Calo trigger data
+1 free cable trigger data
32 TTC_data (L1A,cmd)
32 Subdetector STATUS cables8 DAQ STATUS cables
1U=1.75“=44.45mm56U racks, w=60cm, depth=90cm, h=256cm
Ethernet
2 opt. DAQ links
Note: PCs will actually be moved to top of rack
47U used
less than 9U used
PCs outside Air Flow
Rack Layout according to CMS Standard Rack: CMS-DISIR-IG-0002 v.2 (EDMS Id: 114226)
9kW cooling power3kW per crate
8 PTC STATUS cables
8 Emulator cables
2U Heat Exchanger
2U Fan Unit
9U/6U crate
2U Heat Exchanger
2U Fan Unit
9U crate
2U Heat Exchanger
2U Fan Unit
2U Heat Exchanger
2U Air Flow Guide
4U Cross Flow Fanwith Monitoring Unit
DAQ-PC
Online-PC
PrivateTest-PC
9U/6U crate
Global Trigger Rack
C.-E. Wulz 3 Trigger Meeting, Sep. 2003
All boards on front side.
Boards arranged for minimum cable length.
Global Trigger Crate
C.-E. Wulz 4 Trigger Meeting, Sep. 2003
VMEinterface PSBPSB
GTL6U
GTL_CONV
Global Trigger Prototype Crate
C.-E. Wulz 5 Trigger Meeting, Sep. 2003
VMEinterface
MEMORYSYNCchips
ROP for DAQ
Input module
Synchronisation and monitoring of trigger data
PSB6U only for the Prototype Crate
PSB-6U Prototype Board
C.-E. Wulz 6 Trigger Meeting, Sep. 2003
40, 80 MHz CLK drivers
DS92LV16 receivers
Registers for 40 80 MHz conversion
Infiniband connectors
DS92LV16 transmitter for
tests
new
PSB_IN80 for PSB-6U
C.-E. Wulz 7 Trigger Meeting, Sep. 2003
VMEinterface
CONVchips
80MHzGTL+signals
ChannelLinkRec
+1.5V supply
VME to GTL6U
GTL_CONV is used only in the Prototype Crate
ChannelLink
signals
GTL Conversion Board
C.-E. Wulz 8 Trigger Meeting, Sep. 2003
Calculates 64 trigger algorithms
GTL6U will be used in the prototype crate as well as in the final GT-crate
GTL-6U Logic Board (right side)
VME
REC chips
COND chips
GTL+signals
4x4 calo objects
4 muons
C.-E. Wulz 9 Trigger Meeting, Sep. 2003
TIM chip
TTCrx
CLOCK circuits
LVDS driversCLK, BCRES, L1A,
RESETto each VME slot
VME
TIM-6U will be used in the prototype as well as in the final GT and DTTF crates.
Front Panel
new
TIM-6U Timing Module
C.-E. Wulz 10 Trigger Meeting, Sep. 2003
A.T. 21.2.03
FDL-9U Final Decision Logic
VME
ALGO bits to DAQ
ALGO bits to EVM
Final OR bits to TCS
Techn.Trigger bitsfrom PSB
ALGO bits from GTL
FDL chipon
MEZZ896
C.-E. Wulz 11 Trigger Meeting, Sep. 2003
TCS-9U Central Trigger Control Board
VME
FastSigs24 part‘s
+ 8DAQ part‘s
TCS statusto 8 DAQ part‘s
L1A,...to 32 TTCvi
FastSigs from8 Emulators
TCS_MON chip TCS chip Clock
EVM+DAQ records
C.-E. Wulz 12 Trigger Meeting, Sep. 2003
bottom sidetop side50 Ohm
connectorsXC2V2000-4FF896C
BGA: 1mm pitch, track width=83 m
Mezzanine Board (MEZZ896)
MEZZ896 will be used in TCS-9U and FDL-9U
C.-E. Wulz 13 Trigger Meeting, Sep. 2003
GCT/GT integration test setup
TTCvi
clk_in
A BTIM
clk_x
orbit_x NIM
NIM
ECL
SIGNAL GENERATOR
A
B
clk_outorbit_out
clk_out
clk_in
ECL
100kHz-1GHz
CLKboard
TTCrx
IM
bcres
clk
diff PECL
PSB +PSBin80
trans
return
rec
Serial Link 1280 Mbps
BGo command: 0001
AC
Global Trigger
GlobalCalorimeter
Trigger
TTC units
TTCvx
Infiniband cable 1m / 5m
GCT-trigger data
opticalfibre
Bristol + Vienna groups, Vienna, July 2003
C.-E. Wulz 14 Trigger Meeting, Sep. 2003
GCT/GT integration test results and plans
Link latency50 ns with 1m cable, 65 ns with 5m cable.
Data exchange64 bits per 25 ns sent over one two-pair Infiniband cable.Different sets of patterns have been programmed at the transmitterend of the link and successfully read from a memory on the PSB.
ClockPLL-based clock drivers to stabilize the TTC clock signals can beused.
Long term stabilityFull test still to be made.20000 LHC orbits equivalent to 5 . 109 bit cycles tested.
Further testsPlanned in Vienna with boards from Bristol in autumn 2003.
C.-E. Wulz 15 Trigger Meeting, Sep. 2003
GT on-line and ORCA software
C++ test programs exist to run the following boards both stand-alone and as a system : PSB-6U, GTL-CONV, GTL-6U, TIM-6U, TTCvi.
The programs are being implemented as XDAQ-plugins.
The GT setup definition is planned in .xml format, also to be used by ORCA.
We are working on the SETUP program, including on a concept with a GUI.
BackplaneGlobal TriggerSetup Program
Database.sof, .pof.bit.xml.rbf, .bit, .rbt.vhd.vhd.sof, .pofHAL.rbf
C.-E. Wulz 16 Trigger Meeting, Sep. 2003
Milestones updated • Custom Backplane for VME 9U crate
6U Prototype: Channel Links ... exists MS 03/02– 9U Backplane: 80MHz GTLp and Channel Links, ... design in progress MS 03/03 09/03 12/03
• PSB Input board (synchronisation, monitoring)
6 channel 6U Prototype: Channel Link receivers ... board tested MS 03/02 PSB-IN80: DS92LV16 serial receivers ... board tested
– 12 channel board: memories inside FPGAs ...conceptual design MS 06/04• GTL Logic board:
Conversion board for prototype ... board tested MS 03/02– GTL-6U prototype: 20 channels …hardware is tested MS 06/03
• Signal transfer tested with test patterns -> ok … working on firmware• XDAQ compatible test program in C++ exists• Loading of conditions not tested yet (software under development)
– GTL-9U board: 32 channels ...conceptual design MS 11/04
• 4, 4 isol. e/, 4e/, 4 central jets, 4 fwd jets, 4 -jets, ET, ET mis, HT, 12 jet counts
• TIM Timing board ... board tested MS 06/03 09/04 6U size, TTCrx, clock and L1A distribution, also used by DTTF; working on version for new TTCrx
• MEZZ896 Mezzanine boards (used on TCS-9U, FDL-9U) ... boards produced MS 06/03
• FDL-9U Final Decision board ... design in progress MS 06/03 11/03 02/04
• TCS-9U Central Trigger Control board ... Layout finished MS 04/03 09/03 12/03
• GTFE-9U Readout board ... conceptual design MS 12/03 03/04 02/05
Global Trigger Status and Milestones Sept. 2003Global Trigger Status and Milestones Sept. 2003
C.-E. Wulz 17 Trigger Meeting, Sep. 2003
Production, Full Chain and Slice Tests, Integration
GTL-6U hardware ok
TIM-6U 09/04 (version for new TTCrx)
TCS-9U 09/03 12/03
BACK-9U 09/03 12/03
FDL-9U 11/03 02/04
System test (full chain) of 20-channel GT (without GTFE) 06/04
GT system tests 6/05
Global Trigger
PSB-9U 06/04
Integration of GT/GMT with DAQ 01/06
Slice tests performed in Vienna as boards become available.Installation and commissioning in USC55 planned in phase with other subsystems (GCT, regional muon trigger systems) during second half of 2005.
GTFE 03/04 02/05
GTL-9U 11/04
Global Muon Trigger
FPGA design 12/03
Board production 06/04
GMT system tests 01/05
Global Trigger PROTOTYPEBACK-6U ok PSB-6U okPSB-IN80 okGTL-CONV okGTL-6U hardware tested (Milestone 6/03)TIM-6U done (Milestone 6/03) - prototype will be
used as spare module for final systemIntegration test with GCT done (July 2003)
C.-E. Wulz 18 Trigger Meeting, Sep. 2003
Conclusions
GTL-6U Logic board produced and tested
TIM-6U Timing module produced and tested
TCS-9U Layout of TCS module finished
FDL-9U Final Decision Logic is in progress
PSB_IN80, GTL_CONV, MEZZ896 Auxiliary boards produced and tested
XDAQ compatible on-line software is under development
ORCA software is being updated