Plenary, Indium Phosphide and Related Materials Conference, May 15-18, Matsue, Japan
Frequency Limits of InP-based Integrated Circuits
Mark Rodwell , E. Lind, Z. Griffith, S. R. Bank, A. M. CrookU Si i tti M Wi t G B k A C G d
Sponsors
U. Singisetti, M. Wistey, G. Burek, A.C. GossardUniversity of California, Santa Barbara
Collaborators (III-V MOS)A. Gossard, S. Stemmer, C. Van de Walle University of California Santa Barbara
pJ. Zolper, S. Pappert, M. RoskerDARPA (TFAST, SWIFT, FLARE)D. Purdy, I. MackOffice of Naval ResearchKwok Ng, Jim HutchbySemiconductor Research y
P. Asbeck, A. Kummel, Y. Taur, University of California San Diego J. Harris, P. McIntyre,Stanford UniversityC. Palmstrøm,University of Minnesota
Semiconductor Research Corporation
Collaborators (HBT)M. Urteaga, R. Pierson , P. Rowell, M-J Choe, B. BrarTeledyne Scientific CompanyX M Fang D Lubyshev Y Wu J M Fastenau W K Liu
[email protected] 805-893-3244, 805-893-5705 fax
University of MinnesotaM. Fischetti University of Massachusetts Amherst
X. M. Fang, D. Lubyshev, Y. Wu, J. M. Fastenau, W.K. Liu International Quantum Epitaxy, Inc.S. MohneyPenn State University
Specific Acknowledgements
(Prof.) Erik Lind125 HBT
Dr. Zach Griffith Dr. Mark Wistey I G A MOSFET125 nm HBTs
process technologytheory / epi design
500 & 250 nm HBTs150 GHz Logic100 GHz op-amps
InGaAs MOSFETprocess technologytheory / epi design
THz Transistors are coming soon; both InP & Silicon
InP Bipolars: 250 nm generation: → 780 GHz f 424 GHz f 4 5 V BV
8
10
μm2
InP Bipolars: 250 nm generation: → 780 GHz fmax , 424 GHz fτ , 4-5 V BVCEO
125 nm & 62 nm nodes 30
40
B
U
Z. Griffith
0
2
4
6
0 1 2 3 4 5
mA
/μ→ ~THz devices
0
10
20
109 1010 1011 1012
dB H21
fτ = 424 GHz
fmax
= 780 GHz
Vce
IBM IEDM '06: 65 nm SOI CMOS → 450 GHz fmax , ~1 V operationI t l J '07 45 / hi h K / t l t
10 10 10 10Hz
Intel Jan '07: 45 nm / high-K / metal gate continued rapid progress→ continued pressure on III-V technologies→ continued pressure on III V technologies
If you can't beat them, join them !y junclear if Si MOSFETs will work well at sub-22-nm gate lengthInGaAs/InAs/InP channels under serious investigation for CMOS VLSI.
Datta, DelAlamo, Sadana, ...
THz InP vs. near-THz CMOS: different opportunities
65 / 45 / 33 / 22 CMOS65 / 45 / 33 / 22 ... nm CMOSvast #s of very fast transistors
having low breakdown sloppy DC parameters ... having low breakdown, sloppy DC parameters what NEW mm-wave applications will this enable ?
massive monolithic mm-wave arrays→ 1 Gb/s over ~1 km mm-wave MIMO
DC parameters limit analog precision...
THz InP vs. near-THz CMOS: different opportunities
InP HBT: THz bandwidths good breakdown analog precision InP HBT: THz bandwidths, good breakdown, analog precision
8
10
μm2
10-6
10-4
10-2
(A)
Ic
Ib
30
40
B
U
&0
2
4
6
0 1 2 3 4 5
mA
/μ
10-12
10-10
10-8
10 6
0 0 25 0 5 0 75 1
I c , I
b b
0
10
20
109 1010 1011 1012
dB H21
fτ = 424 GHz
fmax
= 780 GHz &0 1 2 3 4 5
Vce
0 0.25 0.5 0.75 1
Vbe
(V)
340 GHz, 70 mW amplifiers (design)In future: 700 or 1000 GHz amplifiers ?
10 10 10 10Hz
p
200 GHz digital logic (design)
M. Jones
g gIn future: 450 GHz clock rate ?
Z. Griffith
30-50 GHz gain-bandwidth op-amps→ low IM3 @ 2 GHz In future: 200 GHz op-amps for low-IM3 10 GHz amplifiers?M. Urteaga
(Teledyne)
Z. Griffith
Transistor Benchmarks
f BVCEO i t th l lt li itfmax matters40
H
no gain above 10
BVCEO is not the only voltage limit
10
20
30
dB
U
H21 218 GHz
4
6
8
(mA
/μm
2 )
6.8 V BVCEO
4
6
8
(mA
/μm
2 ) !0
10
9 10 11 12
ft = 660 GHz
fmax
= 218 GHz0
2
4
0 1 2 3 4 5 6 7 8
J e
0
2
4
0 1 2 3 4 5 6 7 8
J e
109 1010 1011 1012
Hz
Tuned amplifiers: fmax sets bandwidth
0 1 2 3 4 5 6 7 8V
ce (V)
0 1 2 3 4 5 6 7 8V
ce (V)
Need Safe Operating Areaat least BV /2 at J /2
Mixed-signal: CcbΔV/ Ic , CjeΔV/ Ic , RexIc/ΔV , RbbIc/ΔV ,
...at least BVceo/2 at Jmax/2
thermal resistance, high-current breakdownhigh temperature operation ( 75 C) ?ex c bb c
τf high-temperature operation (~75 C) ?
Goal is >1 THz fτ and fmax<50 fs CΔV / I charging delays
→ emphasize InP-collector DHBTs
HBT Scaling LawsHBT Scaling Laws
InP DHBTs: May 2007
700
800RSC
500 GHz400 GHz300 GHz200 GHz maxffτ=600 GHz
Teledyne 2/) (alone or
max
max
ffff
+τ
τ :metrics popular
250 300nm
600
700 UIUC DHBT
NTT
Fujitsu HEMT)
)11(
1
max
max
ff
ff
+ −τ
τ
250-300nm
400
500 SFU
UIUC SHBT
UCSB
max
(GH
z)
mW/ gain, associated PAE,
:amplifierspower
mμ
:metrics better much600nm
200
300 NGST
Pohang SHBT
HRL
f m
:digital gain, associated ,F
:amplifiers noise low mW/
min
mμ
300-400nm
0
100
0 100 200 300 400 500 600 700 800
IBM SiGe
VitesseUpdated March 2007
),/( ),/(
hence , g
cex
ccb
clock
VIRIVC
f
ΔΔ
0 100 200 300 400 500 600 700 800
ft (GHz) )(
),/(
cb
cbb
ττVIR
+Δ
HBT Scaling RoadmapsHBT Scaling Roadmaps
2005: InP DHBTs @ 500 nm Scaling Generation
emitter 500 nm width16 Ω⋅μm2 contact ρ
✓✓
base 300 width, 20 Ω⋅μm2 contact ρ ✓
✓
✓collector 150 nm thick, 5 mA/μm2 current density5 V, breakdown
✓✓✓
fτ 400 GHzfmax 500 GHz
power amplifiers 250 GHz di it l l k t 160 GH
✓✓
✓✓
(178 GHz)(150 GH )digital clock rate 160 GHz
(static dividers)✓ (150 GHz)
2006: 250 nm Scaling Generation, 1.414:1 faster
emitter 500 250 nm width 16 9 Ω⋅μm2 access ρ
✓✓
base 300 150 width, 20 10 Ω⋅μm2 contact ρ ✓
✓
✓collector 150 100 nm thick, 5 10 mA/μm2 current density5 3.5 V, breakdown
✓✓✓
fτ 400 500 GHzfmax 500 700 GHz
power amplifiers 250 350 GHz di it l l k t 160 230 GH
✓✓(425 GHz)
(780 GHz)
digital clock rate 160 230 GHz(static dividers)
2007: 125 nm Scaling Generation → almost-THz HBT
emitter 500 250 125 nm width16 9 4 Ω⋅μm2 access ρ ✓
✓
base 300 150 75 width, 20 10 5 Ω⋅μm2 contact ρ ✓
✓
✓collector 150 100 75 nm thick, 5 10 20 mA/μm2 current density5 3.5 3 V, breakdown
✓✓
✓
fτ 400 500 700 GHzfmax 500 700 1000 GHz
power amplifiers 250 350 500 GHz di it l l k t 160 230 330 GHdigital clock rate 160 230 330 GHz(static dividers)
2008-9: 65 nm Scaling Generation→beyond 1-THz HBT
emitter 500 250 125 63 nm width16 9 4 2.5 Ω⋅μm2 access ρ ✓
base 300 150 75 70 nm width, 20 10 5 5 Ω⋅μm2 contact ρ ✓
collector 150 100 75 53 nm thick, 5 10 20 35 mA/μm2 current density5 3.5 3 2.5 V, breakdown
fτ 400 500 700 1000 GHzfmax 500 700 1000 1500 GHz
power amplifiers 250 350 500 750 GHz di it l l k t 160 230 330 450 GHdigital clock rate 160 230 330 450 GHz(static dividers)
HBT Scaling HBT Scaling ChallengesChallenges
Scaling challenges: What looks easy, what looks hard ?key device parameter required changekey device parameter required change
collector depletion layer thickness decrease 2:1
base thickness decrease 1.414:1
emitter junction width decrease 4:1
ll t j ti idth d 4 1collector junction width decrease 4:1
emitter resistance per unit emitter area decrease 4:1
current density increase 4:1
base contact resistivity(if contacts lie above collector junction)
decrease 4:1
base contact resistivity(if contacts do not lie above collector junction)
unchanged
Hard:Hard:Thermal resistance (ICs)Emitter contact + access resistanceYield in deep submicron processesp pContact electromigration (?), dark-line defects (?)
Probably not as hard :Probably not as hard :Maintaining adequate breakdown for 3 V operation...
Temperature Rise: Transistor, Substrate, Packageflowheatlcylindrica flowspherical flowplanar
⎟⎠⎞
⎜⎝⎛ −
⋅+⎟⎟⎠
⎞⎜⎜⎝
⎛−+⎟⎟
⎠
⎞⎜⎜⎝
⎛≅Δ 2substrate
2/11lnDDT
KP
DLKP
WL
LKPT sube
ππ
junctionnear flowheat lcylindrica
eLr >for flowspherical
2/for flowplanar
HBTDr >
⎠⎝⎟⎠
⎜⎝
⎟⎠
⎜⎝ DKDLKWLK InPEInPeEInP ππ
callylogarithmi increases
variationantinsignific
constant is iflly quadraticaincreases
subT
chipCu
chippackage WK
PT ⎟
⎠⎞
⎜⎝⎛ +≅Δ
211
π
lenghts,Wiring100
150
se, K
elvi
n
total)/GHz 150( m 40 clocksub fT ⋅= μ
eddemonstrat from scaled etc.
densities,power rates,clock
g ,g
50
100
on te
mpe
ratu
re ri
package
substrate: cylindrical + spherical regions
ICs digital GHz 150
eddemonstrat
0100 200 300 400 500 600 700
junc
tio
master-slave D-Flip-Flop clock frequency, GHz
substrate: planar regionpackage
HBTs:HBTs:500 G ti500 nm Generation
500 nm Generation in Manufacturing: Teledyne Self-aligned Dielectric Sidewall Process
Emitter Contact
Dielectric
No short-circuits from liftoff defects.Emitter can be much thinner
Base Contact
Dielectric Sidewall
Emitter can be much thinner→ small etch undercut.
30
40
e) (d
B)
fτ = 405GHzfmax = 392 GHz
10
20
|(red
), U
(blu
e
JE = 6.5 mA/um2
VCE = 1.5 V
emitterEB grade
base
emittermetal
basemetal
dielectricsidewallspacer base contact
window
10 11 120
Frequency (GHz)
|H21
RF Gains Electroplate emitter contactEtch emitter semiconductor
Dielectric sidewall depositionBase contact patterning
Selectively deposit base metal
M. Urteaga et al, 2004 IEEE Device Research Conference, June 21-23, 2004
c.f. also Minh Le et al IEDM 2006 (Vitesse)
Example ICs in 500 nm HBT
142 GHz 800 mW 128 GHz 206 mW 175 GHz 7 5 mW
V. PaidiZ. Griffith
M. UrteagaP. Rowell
D. PiersonB. Brar142 GHz, 800 mW
master/slave latch128 GHz, 206 mW master/slave latch
175 GHz, 7.5 mW medium-power amp.
Fe
N+S.I.
N+N+ N+Fe
mesa HBT sidewall /pedestal HBTmesa HBT mesa HBT UCSB
sidewall /pedestal HBTTeledyne
mesa HBT UCSB
Other Results:160 Gb/s multiplexer (T. Swahn et al, Chalmers / Vitesse)~5000-HBT direct-digital frequency synthesis ICs (Vitesse, Teledyne)
HBTs: HBTs: 250 G ti250 nm Generation
250 nm scaling generation InP DHBTs
Emitter contact resistance 5 Ω⋅μm2
B t t i t i 5 Ω 2Base contact resistance is < 5 Ω⋅μm2
Z. GriffithE. Lind
DHBTs: 250 nm Scaling Generation
150 nm thick collector 60 nm thick collector
Z. GriffithE. Lind
30
40
U
H21
150 nm thick collector 60 nm thick collector
30
40
B
U
10
20dB
f 660 GHfmax
= 218 GHz10
20dB H21
f = 424 GHz
fmax
= 780 GHz
0109 1010 1011 1012
Hz
ft= 660 GHz
30
0109 1010 1011 1012
Hz
fτ = 424 GHz
6
8
10
A/μ
m2
20
30
μm2
0
2
4mA
10mA
/μ
0 1 2 3 4 5V
ce
00 1 2 3
Vce
Emitter access: 5.1 Ω⋅μm2
Base contact: 6.3 Ω⋅μm2
Example IC Designs in 250 nm HBT M. JonesZ. Griffith
200 GHz master-slave latches
340 GHz, 70 mW, medium-power amplifiers
...fabrication on hold......fabrication planned summer/fall 2007
125 nm InP HBT125 nm InP HBTdevelopmentdevelopment
Emitter Access Resistance
125 ti i 5 Ω 2 itt i ti iti
Erik LindAdam Crook
Seth BankUttam Singisetti
125 nm generation requires 5 Ω - μm2 emitter resistivities 65 nm generation requires 1-2 Ω - μm2
Recent Results:ErAs/Mb MBE in-situ 1.5 Ω - μm2
Mb MBE in-situ 0.6 Ω - μm2Mb MBE in situ 0.6 Ω μmTiPdAu ex-situ 0.5 Ω - μm2
TiW ex-situ 0.7 Ω - μm2
Degeneracy contributes 1 Ω - μm2
102
20 nm emitter-base depletion layer contributes 1 Ω - μm2 resistance
10-1
100
101
J(m
A/u
m^2
)
Fermi-Dirac
Te=0 nm
10 nm steps
10-3
10-2
-0.3 -0.2 -0.1 0 0.1 0.2V
be- φ
Equivalent series resistance approximation
Boltzmann
)()(
xqnJ
xxE fn −
=∂
∂ Te=100 nm
p
Epitaxial Layer Development for 125 nm Generation
I G A b l h t i ti it l t it ti b t ll t t b d d
Erik Lind
InGaAs base: low sheet resistivity, low transit time, but collector must be graded
low-current breakdown d i t d b
B-C grade redesign: thin the setback, thin the grade
102
104
106
)1.5
dominated by tunneling in setback layer 1) less superlattice periods...
0.51
1.5
10-4
10-2
100
Cur
rent
(A/c
m2)
1 5-1.0-0.50.00.51.0
eV
collectorbase
calculation-2.5-2
-1.5-1
-0.50
eV
1 2 3 4 510-6
Vcb (V)
Vcb
= 0.0 V-2.0-1.5
0 10 20 30 40 50 60 70 80nm
30
2) thinner (sub-monolayer) superlattice periods→ random alloy grade
: Zach Griffith
calculation0 20 40 60 80 100nm
10
20
mA
/μm
2
3) thin GaAs/InGaAs strained-layer grade
00 1 2 3
Vce
DC data shows expected increase in breakdown.Transport (RF) data is pending.
125 nm Emitter Process
Bl k t tt d iti TiW itt t t t l
Erik Lind
Blanket sputter deposition TiW emitter contact metalOptical lithography → ICP reactive-ion etchingICP RIE etch of InGaAs/InP semiconductorICP RIE etch of InGaAs/InP semiconductor,Selective wet etch to base
125 nm emitter 500 nm undercut at emitter ends
61 nm junction:40 nm lateral undercut
UCSB 125 nm DHBT DevelopmentErik Lind
Adam Crook
125 nm emitter processemitter contact resistivity~ 0 7 Ω μm2
EmitterMetal
~ 0.7 Ω - μm2
base contact resistivityInGaAs/InP
base contact resistivity~ 3-5 Ω -μm2
Target performance ~ 700-900 GHz simultaneous ft & fmax , 3-4 V breakdown
How might we build the 62.5 nm HBT ?
Mesa process: control of etch undercut with dry+wet process
Alternatives:dielectric sidewall process- dielectric sidewall process
- sidewall process with extrinsic base regrowth: allows thinner base
InP-based FETs; InP based FETs; MOSFET & HEMTMOSFETs & HEMTs
InP-based HEMTs & MOSFETs : Why ?
6
7
8
dB GHz 200=τf
InGaAs/InP HEMTs: mm-wave low-noise amplifiers
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅Γ+++≈ffRRRgF igsmi )(1min
3
4
5
6
imu
m N
ois
e F
igu
re,
A ~2.5:1 fτ / fsignal ratio provides 3 dB noise figure.
Low-noise 100-300 GHz
⎠⎝ τf
20 40 60 80 100 120 140 160 1800 200
1
2
0
Frequency, GHz
Min
i
GHz 500=τfLow-noise 100-300 GHz
preamplification is a key application for 1-THz-fτ HEMTs
Frequency, GHz
InGaAs/InP MOSFETs: post-22-nm VLSI (?)Higher mobility and peak electron velocity than in Silicon
→ higher ( Id / Wg ) and lower ( CΔV / I ) at sub-22-nm scaling (?)
Some Encouraging Initial Data . . .-- non-parabolic bands (variable m*) significantly increase feasible sheet chargenon parabolic bands (variable m ) significantly increase feasible sheet charge
Asbeck / Fischetti / Taur simulate drive currents much larger than for constant-m* model
-- mobilities seem to be acceptable even in thin wellsmobilities seem to be acceptable even in thin wells
M. Wisteypreliminary data
and o r c rrent de ice designs . . . and our current device designs . . .
metal gatesource contact drain contact
well: 2.5 nm InGaAs, 2.5 nm InP
barrier
undoped
InGaAs channeldielectric
N+ regrowth N+ regrowth
source contact drain contact
undoped
InP sub-channel
device design and fabrication:Asbeck group: UCSD
N+ InGaAs/InAs extrinsic source & drain by regrowth
P + substrateundopedsubstrate
undopedsubstrate
Asbeck group: UCSDTaur group: UCSDFischetti group: U. MassRodwell group: UCSBPalmstrøm group: U. Minn
Frequency Limits of InP-based Integrated Circuits
Scaling limits: contact resistivities, device and IC thermal resistances.InP Bipolar Transistors
62 (1 TH f 1 5 TH f ) li ti i f ibl62 nm (1 THz fτ , 1.5 THz fmax ) scaling generation is feasible.700 GHz amplifiers, 450 GHz digital logic
Is the 32 nm (1 THz amplifiers) generation feasible ?Is the 32 nm (1 THz amplifiers) generation feasible ?
InP Field-Effect TransistorsInP Field Effect TransistorsLow electron effective mass → difficulties with further scalingGuarded optimism regarding 22 nm generation for VLSIGuarded optimism regarding 22 nm generation for VLSISerious difficulties beyond.
(end)
non-animated non animated versions of the three versions of the three
key scaling slideskey scaling slides
HBT scaling laws
WGoal: double transistor bandwidth when used in any circuiteW
bcWcTbT
y→ keep constant all resistances, voltages, currents→ reduce 2:1 all capacitances and all transport delays
vTDT bnbb /22 +=τ → thin base ~1.414:1
vTcc 2=τ
cccb /TAC ∝AR /
→ thin collector 2:1
→ reduce junction areas 4:1reduce emitter contact resistivity 4:1
( )ELlength emitter ecex AR /ρ=
2, / ceKirkc TAI ∝
→ reduce emitter contact resistivity 4:1(current remains constant, as desired )
PLP ⎞⎛ need to reduce junction areas 4:1
EInPe
e
EInP LKP
WL
LKPT
ππ+⎟⎟
⎠
⎞⎜⎜⎝
⎛≅Δ ln
need to reduce junction areas 4:1reduce widths 2:1 & reduce length 2:1 → doubles ΔTreducing widths 4:1, keep constant length→ small ΔT increase ✓
contacts
c
e
bcs
e
esbb AL
WLWR ρρρ
++≅612
→ reduce base contact resistivity 4:1
reduce widths 2:1 & reduce length 2:1 → constant Rbbreducing widths 4:1, keep constant length → reduced Rbb
✓✓✓g , p g bb
Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.
Back-of-Envelope FET ScalingGoal double transistor bandwidth when used in any circuit
→ reduce 2:1 all capacitances and all transport delays→ keep constant all resistances, voltages, currents
)(~ VVVWvcI thgsgexiteqd Δ−−
μ/LvVΔ
2/1*)/(~ mkTvexit (non-degenerate)
μ/~ gexit LvVΔ
thi l 2 1wellwoxoxeq TTc εε 2//~/1 + ceq doubledthin layers 2:1
gexiteqm Wvcg ~ ✓gm , Id held constant reduce Wg 2:1
✓C reduced 2:1WWLcC ~ α+ reduce Lg 2:1 ✓Cgs reduced 2:1 gggeqgs WWLcC 1~ α+dielectric fringing
✓(Cgd , Cs-b , Cd-b ) all reduced 2:1 ( ) gbdbsgd WCCC toalproportion all , , −−
g
✓(Rs , Rd ) held constant g
DSs
DSg
cs W
LLW
R /
/
ρρ+= reduce Ls/d 2:1 ,reduce ρc 4:1
2:1 vertical scaling → 2:1 increased ( gm / Wg ) → 2:1 reduced Wg→ 2:1 reduced fringing capacitances
FETs no longer scale well
t li th h id hi h K di l t i (if f ibl )tunneling through oxide → high-K dielectrics (if feasible)
Thin layers & low effective mass limit channel sheet charge density( ) *( ) */mqnEE swellf ∝−
( ) *2 /1 mTEE wellcwell ∝−
high sheet charge in thin wellinfinite well approximation
Low density of states limits drive current Solomon & Laux, 2001 IEDM
high sheet-charge in thin well→ populate higher-mass band minima
Low density of states limits drive current
density-of-states term dominates , limits ( gm / Wg )and ( Id / Wg ) f i i & b t t it l l d i t C
wellwoxoxeeqgeqm TTmqcWvcg εεπ 2///)2(~/1 where~ *22 ++⋅ h
→ fringing & substrate capacitances no longer scale, can dominate over Cgs
Thin quantum wells have low mobilityLi SST 2005; Gold et al, SSC 1987; Sakaki et al, APL 1987
( ) 62/ wellTWE ∝∂∂∝ −μ
; , ; ,
InP DHBT: 500 nm Scaling GenerationZ. Griffith
30
40U
h21
10
20dB ft = 450 GHz,
fmax
= 490 GHz
0109 1010 1011 1012
Hz
600 nm wide emitter, 120 nm thick collector, 30 nm thick base
Recommended
