EUVL readiness for 7nm Mark Phillips, Britt Turkot
Intel Corporation
EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
After ~30 years of hard work…
EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
H. Kinoshita et al., JVST B 7, 1648 (1989)
Two years of solid progress and momentum towards HVM
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Outline
• Trajectory over last two years
• Remaining gaps
• EUVL infrastructure
• High NA
EUVL Symposium, 5 October 2015, Maastricht, The Netherlands Mark Phillips / Intel
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Source power roadmap has lost credibility
Tool lead time
As presented at 2013 Source Workshop
EUVL Symposium, 5 October 2015, Maastricht, The Netherlands Mark Phillips / Intel
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Conclusions
• Realization of 40~80W stable MOPA+PP sources in the field linked to NXE:3300B scanners over next two quarters looks feasible
• This would enable meaningful integrated process development with 0.33 NA EUVL and re-establish confidence in a source power roadmap to HVM levels
• Need to re-invigorate EUVL infrastructure development, especially:
− Exposure source power scaling beyond 250W with dramatically improved COO
− Actinic metrology source development to meet performance, productivity, COO and schedule
− Commercial EUV pellicle infrastructure
As presented at 2013 Source Workshop
Two years of solid progress on source power
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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Worldwide fleet 40-80W
Slide courtesy ASML
As of PMJ in April
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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Now six months later…
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Slide courtesy ASML / Alberto Pirati, 2015 EUVL Symposium
• Technology Development requires rapid information turns
− Availability: tool must be up to run TD wafers without delay
• HVM requires reasonable COO and predictability, driven by:
− Productivity (mostly source power)
− Availability (mostly source availability)
− OpEx (mostly source consumables)
What about exposure tool performance gates committing a process node to EUV?
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
As presented at 2013 Source Workshop
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• Technology Development requires rapid information turns
− Availability: tool must be up to run TD wafers without delay – This is the critical, gating concern today
• HVM requires reasonable COO and predictability, driven by:
− Productivity (mostly source power) – Good progress versus HVM need date
− Availability (mostly source availability) – Long way to go, but making progress and have some time
− OpEx (mostly source consumables) – Long way to go, but making progress and have some time
What about exposure tool performance gates committing a process node to EUV?
Scored as of today
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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However…
Availability and predictability are still poor
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
As of 2015 EUVL Workshop (June)
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Extended demo of availability and predictability
• 21hrs/day wafer cycling with mix of test-chip wafers (CDs, overlay, in-line defects, e-test) and bare silicon
• 3-hr daily Intel engineering window (no tool work)
• Availability counted 24hrs/day. Wafer output targets set for 21hrs/day in 40W config.
• Only good wafers (meeting dose control specs) counted
• Goal: demonstrate tool can run as advertised for 40W config today, including imaging and overlay
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Presented at 2015 Litho Workshop (June)
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Demo cumulative wafers per week Presented at 2015 Litho Workshop (June)
EUVL Symposium, 5 October 2015, Maastricht, The Netherlands Mark Phillips / Intel
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Demo overlay trend
X-max
Y-max
Time (4 weeks), each point is one wafer; each cluster is one lot
Green = NXE (EUV) to NXT (193i) Red = NXT to NXT (MMO)
• OK. No overlay penalty for EUV-193i versus 193i-193i MMO.
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Presented at 2015 Litho Workshop (June)
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Demo availability (4 weeks)
• Far from OK for production, but better than expected for current 40W config
As of 2015 EUVL Workshop (June)
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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NXE:3300 (40W config) availability trend
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
• 80W config vs 40W previously
• 1 quarter vs 4 weeks
• More integrated wafers and metrology
• Expanded comparison to 193i baseline
• Higher goals
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Current demo activity
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
• Example of one of many availability improvement projects
• Most are difficult to develop, qualify and proliferate to field 19
New DG is a significant improvement…
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Slide courtesy ASML / Alberto Pirati, 2015 EUVL Symposium
Outline
• Trajectory over last two years
• Remaining gaps
• EUVL infrastructure
• High NA
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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Conclusions
• Solid progress in last year, with realization of 40~80W stable MOPA+PP sources in the field
• Availability is not adequate for process development and needs substantial improvement over next two quarters
• In situ collector cleaning looks promising, but needs to be delivered to field to gain confidence in OpEx and stable productivity
• Continued progress on source power per roadmap is required to build confidence in long-term productivity targets and COO
• EUV infrastructure is now lagging scanner and source, and needs increased focus
As presented at 2014 Source Workshop
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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Summary of EUVL status
• Two years of solid progress on EUVL
— Eight 0.33NA systems shipped, generally meeting all performance specs not related to source power
— 80W config proliferating quickly, and 100W (@IF) MOPA/PP demonstrated in the field
— ~500wpd, then ~1000wpd in short-term (1-2 day) demonstrations
— 4 week demonstration of availability and output consistent with 40W tool configuration, and stable imaging and overlay performance
• Introduction in production is a question of “when” rather than “if”
— Availability, stability and operating cost are still concerns
— Need to ensure infrastructure does not gate HVM
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
As of 2015 EUVL Workshop (June)
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See this presentation for full report on impressive EUV mask progress in 2015:
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
EUV Infrastructure Readiness Snapshot EUV infrastructure has 8 key programs
2 are ready or near-ready now, 4 are in development, 2 have significant gaps
E-beam Mask Inspection: HVM capable tool exists
Actinic Blank Inspection (ABI): EIDEC-led tool development program
EUV resist QC: Industry-wide QC center finalizing definition
AIMS Mask Inspection: SEMATECH-led tool development program
EUV blank quality: Process and yield improvements ongoing
Pellicle: ASML commercializing
Blank multi-layer deposition tool: Improving defect results. Multiple deposition techniques being evaluated to define HVM tool approach.
Post-pellicle mask inspection: APMI not on timeline for insertion. Need other options.
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
As of PMJ in April
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Updated EUV Infrastructure Readiness Snapshot
EUV infrastructure has 8 key programs
2 are ready or near-ready now, 5 are in development, 1 has significant gaps
E-beam Mask Inspection: In use for low volume production. Need TPT increase.
Actinic Blank Inspection (ABI): Transitioning to a QC center in 2016
EUV resist QC: QC center at IMEC expected online in 2017
AIMS Mask Inspection: Imaging demonstrated
EUV blank quality: Process and yield improvements ongoing
Pellicle: ASML commercializing – production phase in 2H 2016
Blank multi-layer deposition tool: Improving defect results. Multiple deposition techniques being evaluated to define HVM tool approach.
Post-pellicle mask inspection: High resolution PWI for fab. Still need actinic inspection in mask shop.
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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Bottom line: N7 mask with no printing defects
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Slide from Ted Liang, 2015 BACUS
Updated EUV Infrastructure Readiness Snapshot
EUV infrastructure has 8 key programs
2 are ready or near-ready now, 5 are in development, 1 has significant gaps
E-beam Mask Inspection: In use for low volume production. Need TPT increase.
Actinic Blank Inspection (ABI): Transitioning to a QC center in 2016
EUV resist QC: QC center at IMEC expected online in 2017
AIMS Mask Inspection: Imaging demonstrated
EUV blank quality: Process and yield improvements ongoing
Pellicle: ASML commercializing – production phase in 2H 2016
Blank multi-layer deposition tool: Improving defect results. Multiple deposition techniques being evaluated to define HVM tool approach.
Post-pellicle mask inspection: High resolution PWI for fab. Still need actinic inspection in mask shop.
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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Remarkable progress in last 2 years
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Slide courtesy ASML / Carmen Zoldesi, 2015 BACUS
Commercialization timeline tight but OK
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Slide courtesy ASML / Carmen Zoldesi, 2015 BACUS
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
• Reticle front side defect-free solution
• protects reticle front side from fall-on defects
• particle free material combination and mounting technology to prevent particle generation
• additional particle suppression towards pattern area
• Designed for use in NXE scanner
• pump down/vent cycles compatible
• vacuum and H2 environment compatible
• meets outgassing requirements
• no overlay impact, distortion-free mounting
• Compatible with standard EUV mask flow
• concept supports any type of pattern mask inspection: optical, e-beam, and actinic; both at mask shop and fab
• allows for reticle repel cycle
Key features Slide 30
Reticle interface (stud)
Pellicle frame + membrane
Flexures
Interchangeable NXE Pellicle concept
Allowing multiple inspection schemes
Slide courtesy ASML.
1. Pellicle frame is not sealed. 200um
gap needed for pump-down
2. ASML simulation predicts 1/200
attenuation of small particles
3. Critical to verify!
As presented at PMJ 2015
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Gap verification in process…
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Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Slide courtesy ASML / Carmen Zoldesi, 2015 BACUS
Especially reticles, for example:
N7 via mask with no printing defects
Improved pod qualified, and modified to support pelliclized masks
ABI tool supporting blank manufacturers and mask shops
First fully integrated pellicle, and commercialization plan
RBI qualification
AIMS imaging demonstrated
Champion blanks with no large defects and ~10 small defects (allows pattern shift mitigation)
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Good progress on infrastructure in last year
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Outline
• Trajectory over last two years
• Remaining gaps
• EUVL infrastructure
• High NA
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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• ~2014 designs not attractive (e.g. limited NA, QF, 9” ret, low TPT)
• HF 0.55NA anamorphic optics, higher transmission, fast stages, offer attractive wafer cost / process simplification proposition
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Solid progress on High NA design proposal in last year
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Slide courtesy ASML / Jan van Schoot, BACUS 2015
• Ability to use to use full resolution of proposed High NA tools will require Total EPE budget ~1/3 the feature size
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As presented at 2013 ASML Technology Symposium
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
• Resolution potential of 0.55NA tool should allow at least two 0.33NA masks to be replaced with one 0.55NA mask, assuming an adequate Total EPE budget
• Higher dose target (60mJ/cm2) makes sense to manage stochastics of small features, but actual requirement with resists available in ~2020 is not known
• Wafer cost benefit and process simplification (elimination of mask splits) is attractive at ASML target performance
• Many areas of EUVL infrastructure will need further development
− E.g. 500W pellicles, reticle inspection, high-resolution resists, AIMS
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High NA conclusions
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
Conclusions
• Two years of solid progress on source power have debunked claims that EUVL can never achieve high productivity
• Availability, stability and predictability of source are still a problem, but are gradually improving
• Performance of NXE:3300s in field has reinvigorated progress on EUV infrastructure
• High NA proposal has come a long way in the last year, offering attractive wafer cost / process simplification proposition at targeted performance
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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Acknowledgements Frank Abboud (Intel) Steve Carson (Intel) Tim Crimmins (Intel) Jeff Farnsworth (Intel) Steve Johnston (Intel) Sang Lee (Intel) Ted Liang (Intel) Brian McCool (Intel) Rajesh Nagpal (Intel) Sam Sivakumar (Intel) Eric Stenehjem (Intel) Guojing Zhang (Intel) Dan Smith (ASML) Alberto Pirati (ASML) Jan van Schoot Carmen Zoldesi (ASML)
Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands
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