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Editing the standard Editing the standard MOCMOSMOCMOS
technology of GNU Electrictechnology of GNU Electricversion 8.08version 8.08
by Kazzz (a Japanese engineer)Revision: 0.5Date: June 07th, 2009
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Revision history
Revision Work periods ※ Remarks
0.5① March 16th - April 10th, 2009
② May 11th - May 15th, 2009
③ June 5th – June 7th, 2009
Initial effort to invite some valuable feedbacks from the user community
※ Mostly spending after the office hours …
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Objectives
① To enhance the standard MOCMOS technology so that it has two resistor types below for analog circuit design N-well resistor Poly-2 high-resistor
② To make the entire technology including the newly added resistors NCC tool applicable DRC tool applicable
③ To make the newly added resistor types SPICE-parameter- extraction applicable
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Acknowledgments Thanks to Dr. Steven M. Rubin and all the developers of this
VLSI design suite for providing such a fascinating tool under GNU General Public License.
Availability of this tool has made me decide to re-study integrated circuit design, especially CMOS, after about 2-decade gap.
More than 20 years ago, having this kind of tool on a personal computer was beyond dream, especially for those who were using the first generation of GE Calma® on a mini-computer having only 64-KByte of main memory!
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Warnings
① Throughout this document, the physical parameters such as sheet resistance, parasitic capacitance per unit length, design rules, etc. are all artificial and do not aspire to any accuracy.
② As stated in the previous slide, the main aim of this document is to capture and clarify different steps that may be required to introduce a new technology to GNU Electric.
③ For more realistic design and simulation, we MUST consult our foundry or in-house process engineers about those parameters and need fine tunings.
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References
Please refer to :
[1]
[2] http://java.com/en/ for Java
[3] http://www.eclipse.org/ for Eclipse
[4] http://www.staticfreesoft.com/productsFree.html for GNU Electric
✔
last updated June 2
nd , 2009
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Java Runtime and SDK The tools listed below are assumed as Java runtime and development environment
Tool Version Install location
OSWindows XP SP3
Japanese
C:\Windows
this may look like
Java RuntimeJava 6
Update 13C:\Program Files\Java\jre6\
Java 3D 1.5.2 C:\Program Files\Java\Java3D\1.5.2\
Java SDKJava SED Kit 6
Update 13C:\Program Files\Java\jdk1.6.0_13\
The images were captured on Japanese Windows throughout this document. Therefore, wherever you see a Yen mark in a file path, please understand that it corresponds to a “back slash” character in the non-Japanese world.
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Some icons used throughout this presentation
8.2 Section of the manual to be referred to
# 02# 01
# 03
Duplicate the N-well
Micro-steps to be followed sequentially
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The final course materials
Here is the latest and final course materials as of June 07th, 2009.
You will find some intermediate materials embedded in this document, which were created while studying about this theme.
Return to this slide after reaching the end of this document; far more than 240 slides.
mocmos-plus-20090607.zip
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IndexIndex
Part-IPart-I Editing the Technology SkeletonEditing the Technology Skeleton
Part-IIPart-II Testing the Technology SkeletonTesting the Technology Skeleton
Part-IIIPart-III Tuning the Technology for LT-Spice SimulationTuning the Technology for LT-Spice Simulation
Part-IVPart-IV Editing the Design RulesEditing the Design Rules
Part-VPart-V Testing the Design RulesTesting the Design Rules
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01. Convert the existing technology for editing
8.2
Assume use of 3 metal layers
# 01
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OK Cancel
※ Images are captured on Japanese Windows XP
# 02
# 03
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# 04 # 05
# 06
Let the new technology name be “mocmos-plus.”
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02. Editing layer cells for N-well resistor
8.4
The manual says …
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P-Base
N-Well-Resistor
Metal-1
N-Well-Resistor-Plus
OxideOxide
The cross-sectional view of an N-Well resistor under its contact node will be …
Physically the same as but logically different from N-Well layer
Physically the same as but logically different from N-Select layer
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8.4
# 02# 01
# 03
Duplicate the N-well to derive “N-Well-Resistor”
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# 04
Don’t change GDS-II layer as this has the same physical layer as “N-Well”
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# 05
# 06
Let the boarder be “solid-thick” style
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Duplicate the N-select for better Ohmic contact
# 07 # 08
# 09
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# 10
Don’t change GDS-II layer as this has the same physical layer as “N-Select”
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# 11
Change the layer function and boarder style
# 12
# 13
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03. Editing a layer cell for Polysilicon-2 resistor
Polysilicon-2 resistor will be made as below
Polysilicon-2-HighResistor
Polysilicon-2-Resistor = Polysilicon-2
Polysilicon-2-HighResistor prevents Polysilicon-2-Resistor from being highly doped, hence, high sheet resistance.
Physically the same as but logically different from Polysilicon-2 layer Regions uncovered by Polysilicon-2-HighReistor will be highly doped,
hence, low ohmic contact resistance
Top view
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P-Base
Metal-1
OxideOxide Polysilicon-2-Resistor
The cross-sectional view of a Polysilicon-2 resistor under its contact node will be …
Physically the same as but logically different from Polysilicon-2 layer
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Duplicate the polysilicon-2
# 01 # 02
# 03
8.4
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# 04
Just a guess
Don’t change GDS-II layer as this has the same physical layer as “Polysilicon-2”
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Change the boarder style and color
# 05
# 06
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# 07
# 08
Confirm that these 3 layers have been added
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Duplicate the polysilicon-2
# 01 # 02
# 03
8.4
04. Editing a layer cell for Polysilicon-2 high-resistor
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# 04
Just a place filler
Above Poly2 by 1.0
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Confirm that these 4 layers have been added
# 05
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05. Editing an arc cell for N-well resistor
8.5
Duplicate the N-well
# 01 # 02
# 03
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# 04
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Change the layer to “N-Well-Resistor”
# 05
# 06 Notice that the boarder style has been changed
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# 07
Change the min. y size of both the boxes to “5”
# 08 Then optionally move them down so that the top y-coordinate be zero (at the origin)
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Duplicate the Polysilicon-2
# 01 # 02
# 03
06. Editing an arc cell for Polysilicon-2 resistor
8.5
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# 04
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# 05
# 06 Notice that the boarder style and color have been changed
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# 07
Keep the min. y size of both the boxes to “3”
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Confirm that these 2 arcs have been added
# 08
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Duplicate the Polysilicon-2
# 01 # 02
# 03
07. Editing an arc cell for Polysilicon-2 high-resistor
8.5
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# 04
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# 05
# 06 Notice that the boarder style and color have been changed
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# 07
Keep the min. y size of both the boxes to “3”
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Confirm that these 3 arcs have been added
# 08
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Duplicate the N-well pin
# 01
08. Editing a pin node for N-well resistor
8.6
# 02
# 03
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# 04
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# 05
Change the layer of each of the four boxes to “N-Well-Resistor”
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# 07
Confirm the layer used
# 06
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# 08
Change the port name of each of the four examples
# 09
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# 10
Change the connectivity of the main example
Only “N-Well-Resistor” layer can connect to this port
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# 11
Confirm that the connectivity of the other examples is all disallowed
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Duplicate the N-well node
# 01 # 02
# 03
09. Editing a pure node for N-well resistor
8.6
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# 04
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Change the function
# 05
# 06
# 07
Change the layer of each box of the four examples
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# 08 Notice that the boarder style has been changed
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# 09
As this node is to be a resistor, there must be two ports!
Delete the current port “well” from each of the four examples
n-well-res-1 n-well-res-2
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# 10
After deleting the ports, only two boxes should exist for each example
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# 11
Add new ports using “artwork technology”
# 12
Name the port
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# 13
Change the size of port so that it fits the left-side edge
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# 14
Move the port onto the left-side edge
# 15
Similarly create a port on right-side edge
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# 16
Repeat the steps to add ports to the other examples
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# 17
Confirm the layers used
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# 18
Confirm the ports created
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# 19
Set the connectivity of the ports for the main example
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Confirm that the connectivity of the other examples is all disallowed
# 20
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Check the number of objects contained in this cell
# 21
1 x 4 examples
1 x 4 examples
2 ports x 4 examples
2 ports x 4 examples
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Duplicate the Metal-1-N-Well-Con node
# 01 # 02
10. Editing a contact node for N-well resistor
8.6
# 03
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# 04
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Change the function
# 05
# 06
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# 07
Change the layer of each box of the four examples
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# 08
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# 09
Change the outer-most box (N-well resistor) size as below
12x12 29x12
29x2912x29
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# 10
Change the port name of the four examples
# 11
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# 12
Confirm the layers used
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# 13
Confirm the ports created
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# 14
Set the connectivity of the port for the main example
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Confirm that the connectivity of the other examples is all disallowed
# 15
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Check the number of objects contained in this cell
# 16
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Duplicate the Polysilicon-2 pin
# 01
11. Editing a pin node for Polysilicon-2 resistor
8.6
# 02
# 03
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# 04
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# 05
Change the layer of each of the four boxes to “Polysilicon-2-Resistor”
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# 06
# 07
Confirm the layer used
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# 08
Change the port name of each of the four examples
# 09
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# 10
Change the connectivity of the main example
Only “Polysilicon-2-Resistor” layer can connect to this port
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# 11
Confirm that the connectivity of the other examples is all disallowed
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Duplicate the Polysilicon-2 pin
# 01
12. Editing a pin node for Polysilicon-2 high-resistor
8.6
# 02
# 03
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# 04
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# 05
Change the layer of each of the four boxes to “Polysilicon-2-HighResistor”
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# 06
# 07
Confirm the layer used
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# 08
Change the port name of each of the four examples
# 09
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# 10
Change the connectivity of the main example
Only “Polysilicon-2-HighResistor” layer can connect to this port
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# 11
Confirm that the connectivity of the other examples is all disallowed
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Duplicate the Polysilicon-2 node
# 01 # 02
# 03
13. Editing a pure node for Polysilicon-2 resistor
8.6
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# 04
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Change the function
# 05
# 06
# 07
Change the layer of each box of the four examples
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# 08 Notice that the boarder style and color have been changed
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# 09
As this node is to be a resistor, there must be two ports!
Delete the current port “polysilicon-2” from each of the four examples
poly-2-res-1 poly-2-res-2
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# 10
After deleting the ports, only two boxes should exist for each example
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# 11
Add new ports using “artwork technology”
# 12
Name the port
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# 13
Change the size of port so that it fits the left-side edge
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# 14
Move the port onto the left-side edge
# 15
Similarly create a port on right-side edge
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# 16
Repeat the steps to add ports to the other examples
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# 17
Confirm the layers used
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# 18
Confirm the ports created
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# 19
Set the connectivity of the ports for the main example
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Confirm that the connectivity of the other examples is all disallowed
# 20
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Check the number of objects contained in this cell
# 21
1 x 4 examples
1 x 4 examples
2 ports x 4 examples
2 ports x 4 examples
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Duplicate the Polysilicon-2 node
# 01 # 02
# 03
14. Editing a pure node for Polysilicon-2 high-resistor
8.6
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# 04
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Change the function
# 05
# 06
# 07
Change the layer of each box of the four examples
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# 08 Notice that the boarder style and color have been changed
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# 09
As this node is to be a resistor, there must be two ports!
Delete the current port “polysilicon-2” from each of the four examples
poly-2-hres-1 poly-2-hres-2
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# 10
After deleting the ports, only two boxes should exist for each example
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# 11
Create different components for the main example modifying the existing ones
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# 12
Copy and edit the components for the main example to create the others
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# 13
Assemble the components for each example
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# 14
Confirm the layers used
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# 15
Confirm the ports created
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# 16
Set the connectivity of the ports for the main example
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Confirm that the connectivity of the other examples is all disallowed
# 17
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Check the number of objects contained in this cell
# 18
2 x 4 examples
1 x 4 examples
2 ports x 4 examples
2 ports x 4 examples
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Duplicate the Metal-1-Polysilicon-2-Con node
# 01 # 02
15. Editing a contact node Polysilicon-2 resistor
8.6
# 03
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# 04
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Confirm the function
# 05
# 06
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# 07
Change the layer of each box of the four examples
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# 08
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# 09
Confirm the outer-most box (Polysilicon-2 resistor) size as below
10x10 14x10
14x1410x14
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# 10
Change the port name of the four examples
# 11
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# 12
Confirm the layers used
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# 13
Confirm the ports created
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# 14
Set the connectivity of the port for the main example
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Confirm that the connectivity of the other examples is all disallowed
# 15
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Check the number of objects contained in this cell
# 16
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12. Delete two scalable transistors to avoid errors when converting the library to a new technology
This is a tentative patch.There must be another solution.
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13. Convert the library to technology
# 01 # 02
# 03
8.2
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# 04
Edit the component menu as you like
# 05
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# 06
Save this menu into the library
Edit the component menu as you like
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# 07
Skeleton of components are ready to use
These are newly generated resistors
Save this library
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Reload the library “mocmos-plus.jelib” then convert it to technology
# 08
Generate an XML file for permanent use of this technology
# 09
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# 10
Add the newly generated technology file in XML format to the Project Settings so that the technology is automatically loaded and created at the invocation of the tool.
Specify the XML file you created
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01. Creating a 10-kΩ resistor from N-well Let’s create a new library “MyCircuit00” and “10K_N_Well” cell for {schematic}
# 01
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Edit “10K_N_Well{sch}”
# 02
① Choose “N-Well Resistor” from the schematic component menu.② Set “length” attribute to 120.0; “width” attribute to 12.0. That is, the aspect ratio i
s 10:1, which yields about 10kΩ if the sheet resistance is about 1kΩ/□.③ Export “L” and “R” port as shown.
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Let’s create a new “10K_N_Well{lay}” cell
# 03
# 04
Place a N-Well-Resistor-Node
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Change the length to 120.0 using the property editor
# 05
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# 06
Gee!“Width” and “Length” are interchanged!
Is this a bug of Electric? Or… See the next slide for a fix.
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# 07
Graphically stretch the shape by using Ctrl-B then …
Both “Width” and “Length” are properly set. This shape will be the body of the resistor. Two ports are at both side ends.
n-well-res-1 n-well-res-2
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# 08
Add the two contact terminals at both the ends
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# 09
Run NCC expecting an obvious error
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# 10
Connect a contact and a port of the resistor body by an “N-Well-Resistor Arc”
# 11
Adjust the position of the contact so that the inside edge of the contact cut coincides with the outside edge of the resistor body
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# 12
Export the two terminals as “L” and “R” respectively and name the node
node name
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# 13
Confirm existence of expected objects
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# 14
Rerun NCC to confirm consistency.
# 15
Check the 3-D view
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02. SPICE simulation using the N-Well10-kΩ resistor Let create a new cell for SPICE simulation
# 01
Voltage divider is simulated.
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Write a SPICE deck file
# 02
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Run the SPICE simulation with the schematic
# 03
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Edit the layout and run NCC
# 04
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Write a SPICE deck file
# 05
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Run the SPICE simulation with the layout
# 06
Obviously, subcircuit information is missing! Finer tuning is necessary! The main theme of Part-III.
Web search for “rnwod” results some SPICE model files for H-SPICE
for example, visit
http://ecow.engr.wisc.edu/cgi-bin/get/ece/541/lal/mm0355v.l
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03. Creating a 2-kΩ resistor from Polysilicon-2 high-resistor Let’s create a “2K_Poly2” cell for {schematic}
# 01
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Edit “2K_Poly2{sch}”
# 02
① Choose “N-Poly Resistor” from the schematic component menu.② Set “length” attribute to 55.0; “width” attribute to 5.0. That is, the aspect ratio is 1
1:1, which yields about 2kΩ if the sheet resistance is about 180Ω/□.③ Export “L” and “R” port as shown.
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Let’s create a new “2K_Poly2{lay}” cell
# 03
# 04
Place a Polysilicon-2-HighResistor-Node
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Change the length to 50.0 using the property editor
# 05
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# 06
Gee!“Width” and “Length” are interchanged again!
Is this a bug of Electric? Or… See the next slide for a fix.
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# 07
Graphically stretch the shape by using Ctrl-B then …
Both “Width” and “Length” are properly set. This shape will be the body of the resistor. Two ports are at both side ends.
poly-2-hres-1 poly-2-hres-2
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# 08
Add the two contact terminals at both the ends
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# 09
Run NCC expecting an obvious error
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# 10
Connect a contact and a port of the resistor body by an “Polysilicon-2-Resistor Arc”
# 11
Adjust the position of the contact so that the inside edge of the contact pad (Poly2) coincides with the outside edge of the resistor body
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# 12
Export the two terminals as “L” and “R” respectively and name the node
node name
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# 13
Confirm existence of expected objects
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# 14
Rerun NCC to confirm consistency.
# 15
Check the 3-D view
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04. SPICE simulation using the Poly2 2-kΩ resistor Let create a new cell for SPICE simulation
# 01
Voltage divider is simulated.
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Write a SPICE deck file
# 02
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Run the SPICE simulation with the schematic
# 03
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Edit the layout and run NCC
# 04
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Write a SPICE deck file
# 05
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Run the SPICE simulation with the layout
# 06
Obviously, subcircuit information is missing! Finer tuning is necessary! The main theme of Part-III.
Web search for “rnpo1rpo” results some SPICE model files for H-SPICE
for example, visit
http://www.ax-09.ru/gruppa/materials/biblioteka/Shemotehnika/Chung-Yu%20Wu_Analog%20Integrated%20Circuits%20-%20II/025.l.txt
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05. Modify technology for {lay} When creating a new layout cell, I should have selected “mocmos-plus” technology but selected “mocmos” instead
# 01
Then, whenever I select a {lay} cell, “Components” menu alters to “mocmos”
Because of this mistake, some exceptions were thrown when ran DRC, which led to the motivation to prepare the reference [1]. In fact, I noticed this mistake while running Electric under the Eclipse debugger.
Added this section on May 11th, 2009
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Modify the technology of each {lay} cell
# 02
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Confirm that the technology has been set normally
# 03
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01. Editing layer cells for N-well resistor
# 01
Let’s assume these parasitic values
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02. Editing a pure node for N-well resistor
Let’s add a SPICE template; more specifically for LT-Spice
# 01
① This resistor is to be modeled by a subcircuit in SPICE where URC (Uniform RC-line) will be used as a base element.
② The subcircuit instance name will be “X followed by the node name.”③ The subcircuit has three terminals. Two of them will be connected to the ports attached to this
node. The last one is always connected to “node number 0” which is GND.④ The subcircuit will take two parameters, that is, “L” and “W” which further accesses the physic
al size of this node by substituting $(length) and $(width). Such substitution is Electric’s job while generating a SPICE deck.
⑤ “LAMBDA” is a physical scale (like 500nm) that is to be given by a .param command in a SPICE deck.
⑥ A pair of curly braces { } is required to evaluate a parameter expression in LT-Spice
9.4.4
n-well-res-1 n-well-res-2
0; GND
modeled as URC
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How they are translated into a SPICE deck
# 02$(width)=12.0
$(length)=120.0
$(node_name)=
exported port name “L”is connected to $(n-well-res-1)by an arc
the subcircuit has to be defined somewhere (e.g. in a library)
exported port name “R”is connected to $(n-well-res-2)by an arc
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A sample subcircuit definition
# 03
Refer to LT-Spice manual for more details.
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Modify the SPICE statements for a transient analysis at different temperatures
# 01
03. Simulation with the modified technology
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Write a SPICE deck file
# 02
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Run the SPICE simulation with the layout
# 03
For high frequency, this is rather an LFP than a voltage divider
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Manually modify the SPICE deck for a step response
# 04
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Rerun the SPICE simulation for a step response
# 05
Ramp-up takes some time
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Let’s reduce the capacitance to 1/10 then…
# 06
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Rerun the same simulation as #03
# 07
Improved a bit, but …
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Let’s reduce both the capacitance and the sheet resistance to 1/10 then…
# 08
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Rerun the same simulation as #03
# 09
Now, this can be seen as a voltage divider for this freq.
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04. Editing a pure node for Polysilicon-2 high-resistor
Let’s add a SPICE template; more specifically for LT-Spice
# 01
① This resistor is to be modeled by a subcircuit in SPICE where URC (Uniform RC-line) will be used as a base element.
② The subcircuit instance name will be “X followed by the node name.”③ The subcircuit has three terminals. Two of them will be connected to the ports attached to this
node. The last one is always connected to “node number 0” which is GND.④ The subcircuit will take two parameters, that is, “L” and “W” which further accesses the physic
al size of this node by substituting $(length) and $(width). Such substitution is Electric’s job while generating a SPICE deck.
⑤ “LAMBDA” is a physical scale (like 500nm) that is to be given by a .param command in a SPICE deck.
⑥ A pair of curly braces { } is required to evaluate a parameter expression in LT-Spice
9.4.4
poly-2-hres-1 poly-2-hres-2
0; GND
modeled as URC
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How they are translated into a SPICE deck
# 02$(width)=5.0
$(length)=55.0
$(node_name)=
exported port name “L”is connected to $(poly-2-hres-1)by an arc
the subcircuit has to be defined somewhere (e.g. in a library)
exported port name “R”is connected to $(poly-2-hres-2)by an arc
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A sample subcircuit definition
# 03
Refer to LT-Spice manual for more details.
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Modify the SPICE statements for a transient analysis at different temperatures
# 01
05. Simulation with the modified technology
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Write a SPICE deck file
# 02
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Run the SPICE simulation with the layout
# 03
Response is much faster than N-well resistor divider
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Manually modify the SPICE deck for a step response
# 04
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Rerun the SPICE simulation for a step response
# 05
Ramp-up is also much faster than N-well resistor
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Let’s reduce the capacitance to 1/10 then…
# 06
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Rerun the same simulation as #03
# 07
Almost perfect!
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06. Works done so far
As of March 28, 2009, I reached here.
mocmos-plus-20090328.zip
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01. Preparing the source files
8.7
As this technology has been derived from mocmos, we have to refer to the original technology file describing the same, which resides in the source code JAR file.
mocmos-plus.jelib mocmos-plus.xml
mocmos.xml(the full-set description of mocmos
technology existing in the source code)
➂ copy relevant lines ➃ manually edit to finish➀ graphically edit
➁ convert
✔✔
Clearly understand the steps to be followed for editing the design rules
# 01
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Get the source code
# 02
This jar file contains the source codes; not “Binary”
Unpack the archive file using “jar” command available in JDK (for example)
# 03
# 04
Files and holders shown below will be extracted
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The original XML file is here
# 05
Copy this file as mocmos-source.xml to the currently working directory and set on R/O flag Copy mocmos-plus.xml as mocmos-plus-work.xml Copy mocmos-plus.xml as mocmos-plus-org.xml and set on R/O flag
# 06
I’m going to edit this file.
“r” for safety
I’m going to rename/restore these files while testing.
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02. Comparing the two XML files Using an appropriate tool, examine the differences one by one
# 01
The source (reference) XML file The XML file being edited
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Find major differences in mocmos-source.xml and attempt to interpret them
# 02
Some keywords are self-explanatory like ruleName, layerName, and value. layerNames (plural) followed by curly braces { } may make combination of layers. type may specify different type of design rules but its value like UCONSPA is not e
asy to guess what it means. when may specify when the rule is applied to but its value like SC is not very clear. the vertical bar | may mean logical OR. If you search the Electric manual for UCONSPA, you will find none. On the other ha
nd, you will find plenty of candidate sections for SC.
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Let’s hack the source code
# 01
Going to search all the *.java files (including subdirectories) for UCONSPA
03. Hacking the source code
This tool is @ http://www.ghisler.com/
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Found 9 suspicious files
# 02
Examine these files one by one with a text editor then …
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Tips: Using Eclipse software development environment
# 03
If you have the Eclipse software development environment as explained in the reference [1], you can also use its File Search function as shown here.
This tool is very smart and useful!
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Bingo! DRCTemplate.java declares enumeration types as DRCRuleType
# 04
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Similarly DRCTemplate.java declares enumeration types as DRCMode
# 05
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The meaning of type in the DRC table
# 06 Keyword / Enumeration type Meanings
NONE nothing chosen
MINWID a minimum-width rule
MINWIDCOND a conditional minimum-width rule
NODSIZ a node size rule
SURROUND a general surround rule
SPACING a spacing rule
SPACINGE an edge spacing rule
CONSPA a connected spacing rule
UCONSPA an unconnected spacing rule
UCONSPA2D a spacing rule for 2D cuts
CUTSURX X contact cut surround rule
CUTSURY Y contact cut surround rule
ASURROUND arc surround rule
MINAREA minimum area rule
MINENCLOSEDAREA enclosed area rule
EXTENSION extension rule
FORBIDDEN forbidden rule
EXTENSIONGATE extension gate rule
SLOTSIZE slot size rule
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The meaning of when in the DRC table
# 07 Keyword / Enumeration type Meanings
NONE None
ALL always
M23 only applies if there are 2-3 metal layers in process
M2 only applies if there are 2 metal layers in process
M3 only applies if there are 3 metal layers in process
M456 only applies if there are 4-6 metal layers in process
M4 only applies if there are 4 metal layers in process
M56 only applies if there are 5-6 metal layers in process
M5 only applies if there are 5 metal layers in process
M6 only applies if there are 6 metal layers in process
M7 / M8 / M9 / M10 / M11 / M12only applies if there are 7 / 8 / 9 / 10 / 11 / 12 metal layers in process, respectively
AN only applies if analog (npn-transistor) rules are in effect
AC only applies if alternate contact rules are in effect
NAC only applies if alternate contact rules are not in effect
SV only applies if stacked vias are allowed
NSV only applies if stacked vias are not allowed
DE only applies if deep rules are in effect
SU only applies if submicron rules are in effect
SC only applies if scmos rules are in effect
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Let’s compare each line with the MOSIS rules
# 01
04. Interpretation of the DRC descriptions
http://www.mosis.com/Technical/Designrules/scmos/scmos-well.html
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More precisely …
# 02
① The minimum width for P-Well layer is defined in Rule 1.1.② The rule type is abbreviated as MINWID.③ when DEep or SUbmicron rules are in effect, the Lambda value should be 12.0.
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Furthermore …
# 03
① The minimum width for P-Well layer is defined in Rule 1.1.② The rule type is abbreviated as MINWID.③ when SCMOS rules are in effect, the Lambda value should be 10.0.
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05. Writing our own DRC descriptions It is right time to start writing our own DRC descriptions in mocmos-plus.xml
As of May 11, 2009, I reached here.
Good luck!
mocmos-plus-20090511.zip
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01. Writing our own DRC descriptions
# 01
Write well-commented XML file for better understanding
After a few trials, I noticed that incrementally testing these rules using Export DRC Deck and Import DRC Deck is a right way instead of restarting Electric again and again after editing XML files for “Added Technologies.”
In other words, a DRC deck can be dynamically replaced while keeping Electric active.
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02. Exporting the design rules My own DRC descriptions in mocmos-plus.xml will be loaded once at invocation of Electric To enable dynamically change the rules without restarting Electric, export a DRC deck
# 01
Let’s export as “testDRC.xml”
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Open the XML file to check whether rules are described as intended
# 02
In “mocmos-plus.xml” file, I have named the customized rule as MOSISP (call capital) for easy eye catch.
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Run DRC for 10K_N_Well{lay} view
# 01
12.0
03. Checking the MINWID rule
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Change the value to constitute a minimum width violation
# 02
Import the modified DRC Deck
# 03
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Rerun DRC for 10K_N_Well{lay} view
# 04
12.0
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Examine each error
# 05
Looks reasonable
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Restore the initial value for further testing
# 06
Confirm that there is no violation
# 07
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Create a new DRC_N_Well{lay} cell
# 01
04. Checking the CONSPA rule
Place two instances of 10K resistor too close to each other
# 02
4.0
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Run DRC
# 03
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Examine each error
# 04
Looks reasonable
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Move the top object by dY= +2.0 and rerun DRC
# 056.0
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Place a pure P-Well object and change its size interactively
# 01
05. Checking the SPACING rules
7.0 pure P-Well
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Run DRC
# 02
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Examine each error
# 03
Looks reasonable
pure P-Well
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Move the P-Well object by dY= +3.0 and rerun DRC
# 0410.0 pure P-Well
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Place a pure N-Well object and change its size interactively
# 05
5.0
pure N-Well
pure P-Well
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Run DRC
# 06
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Examine each error
# 07
Looks reasonable
pure P-Well
pure N-Well
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Move the N-Well object by dY= -5.0 and rerun DRC
# 08
10.0
pure N-Well
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Summary
① Studied a flow to incorporate a new user-defined technology to Electric including:a. Adding new TECHNOLOGY LAYERSb. Adding new TECHNOLOGY ARCSc. Adding new TECHNOLOGY NODESd. Writing SPICE Template to work with LT-Spice
② Studied how to manually edit an XML file for user-defined DRC.
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① More design rules have to be added and tested against different test cases.
② More realistic physical parameters are required to improve usefulness.
③ And many more whatever insufficient!
[The End of File]
To Do