University of the EastCaloocan CampusCollege of EngineeringElectronics Engineering (ECE) Department

Logic Circuits and Switching Theory (Laboratory)NCP 323 1 ECT

Final Project (Documentation):Digital Alarm Clock

Submitted by:Dayawon, Ronnel P.Dimla, Mary Rose C.

Submitted to:Engr. Rommel G. RamosMarch 24, 2014

The Schematic Diagram

The most important aspect of the whole project making was the designing the schematic diagram of the circuit. This documentation intends to focus on the detailed operation of the digital clock rather than its implementation on the project board and later on, on the printed circuit board.

The foundation of the whole circuit (the one part which makes the circuit classified as synchronous sequential logic circuit) is the clock pulse generator.The clock pulse generator consisted of a few components (two resistors and two capacitors) and the 555 timer IC. One of these capacitors (0.1microfarad) doesnt affect the clock pulse but instead, it is connected to Pin 5 (for control voltage). The resistor and Light Emitting Diode (LED) on pin 3 is just for indication of the working clock pulse.The schematic is retrieved from the internet (Paleotechnologists website)

The main components that affect the frequency and the time high and time low of the pulse is R1, R2 and C1.The values used for R1 is 1k, value of the second resistance (R2) is 6.8 k and lastly C1 has a capacitance 100F. The following shows the computation for the frequency and the duty cycle.

The data obtained through the computation verified the schematic to be almost one second for every negative edge (majority of the flip-flops and counter used in the schematic is negative edge triggered). The (almost) 50% duty cycle shows that the time the clock is logic high is (almost) equal to the time the clock is at low-level. This duty cycle, however, would not affect the circuit in any way since the duty cycle would not affect the distance between the negative edges. The duty cycle only determines the time between the negative edge and the positive edge (which would serve no purpose to the overall circuit design).For additional information, using the astable configuration of the 555 timer (the one used in the design) the 50% (exact value) as a duty cycle cannot be achieved since it would require R1 to be almost 0 ohms, which would make the 555 timer misaligned to its normal operation.However, a 50% duty cycle can be achieved by placing a diode parallel to R2 of the schematic.

After the foundation of the circuit (clock pulse generator), comes the most crucial part of the designing. This next stage of the schematic consisted of counters and flip-flops which is responsible for the sequence of numbers to be displayed on the 7-segment common anode display.Before moving further, let us assume variables to represent each Binary-Coded Decimal (BCD) digit present on the Digital Clock of the circuit to promote consistency throughout the report.

Each of the digit/number present on the clock is represented by four bits (A, B, C and D) with D as the most significant and A as the least significant bit. These variables (A, B, C, and D) are also the one used in datasheets and pin configuration of the IC which can be easily accessed through the internet. The AM/PM is represented only by one bit since there are only 2 possible combinations for the time of the day (Morning AM, and Afternoon PM), each of which corresponds to a specific logic level (HIGH or LOW).

Going back to topic, the second stage of the digital clock consisted of the counters and flip-flops. The following is the list of ICs which are used for this stage of the project.(4) 74LS90 (mod-10/decade counter)(1) 74LS192 (presettable decade counter w/ clear input)(1) 74LS73 (negative edge triggered dual JK flip-flop)

The four 74LS90 were used for the counting for seconds and minutes (M2, M1, S2 and S1). The 74LS192 was used for counting for the Hours first digit (H1). Lastly the 74LS73 was used for both the second digit of the hour (H2) and the AM/PM function, with each of the two have their individual JK flip-flop in the design.

The following is the pin configuration for the 74LS90

One awesome thing about the use of this IC is its flexibility to any mod (modulus) in counting. Mod-n can also be written as divide by n counter. The modulus of a counter is the number of unique states that a counter may have before the sequence repeats.

To set an example, lets use the digits of the clock to further define the modulus of a counter. S1 is in mod-1 since its counting is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and it will return to 0 and start the cycle again. There are 10 unique states before the cycle repeats, so the S1 (first digit for seconds) requires a mod-10 or a divide-by-10 counter.S2 is different. It counts from 0, 1, 2, 3, 4, 5 and it will immediately return to zero with completing all decimal values. There are 6 unique states before it repeated the cycle, so S2 (the second digit for seconds) requires a mod-6 counter.

The 7490 can be a mod-10 or a mod-6 counter without any use of external gates which is a good thing for the minimizing the design. This IC can also function in other modulus through simple modifications of the circuit.

The secret of the modulus counting of the 7490 lies in the two reset to 0 pins of the IC (pin 2 and pin 3)

This is the internal connection for the reset pins of the 7490. A NAND gate activates the active low reset of the JK flip-flops which is responsible for returning the count into its zero value. To simplify the operation of the reset, think that the two inverter bubbles would just cancel each other. This line of thought would result into an AND gate-like operation for the reset.The two pins for reset needs to be both at high-level logic to activate it. For the mod-10 counters (M1 and S1), since the 7490 is naturally a decade counter, there is no need to set a reset value for it, since it naturally resets itself to zero.Only when is it at mod-6 will it require a reset value. BCD digits M2 and S2 will utilize this type of counting.

The counter will need to reset it when the counter is at six. This does not mean that the counting will end at six, but once the IC recognizes a 6 value, it will immediately return to 0 (therefore, itll not display 6). 6 has a BCD value 0110. both B and C bits are 1 so it is proper to input the B and C bits of M2 and S2 to the reset to 0 pins of the IC. Once it reaches six, both reset pins will be high, therefore activating the reset.

The clock pulse of S1 would be coming from the clock but the clock pulse for S2 will be from a different source since they will not be changing their current states simultaneously.The 7490 has a negative edge triggered clock which requires a transition form the logic high to logic low.

The clock pulse for S2 is connected to the D bit of S1. The reason for this can be observed by showing the sequence.DCBA, 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 0000

S1 has its D bit change from 1 to 0 only at the point where it changes from the value 1001 (9) towards 0000 (0). S2 would therefore go to its next state the moment S1 instantaneously changes from 9 to 0Illustration: 45, 46, 47, 48, 49, 50, 51S2 changed from 4 to its next state 5 as S1 changes from 9 to 0.

The clock pulse for M1 is connected to the C-pin of S2 for the same reason. S2 will have the following sequenceDCBA, 0000, 0001, 0010, 0011, 0100, 0101, 0000Using pin D, will not be an option because it is at low-level throughout the cycle. However, the C bit has a negative edge (transition from 1 to 0) between its 0101 (5) and 0000 (0) values. M1 would go to its next state once S2 changes from 5 and then back to 0.Illustration: 7:57, 7:58, 7:59, 8:00M1 changed from 7 to its next state 8, as S2 changes from 5 and then back to 0.

The same logic can be applied for the clock pulse of M2 being connected to the D bit of M1.

The challenging bit for designing the counter is for the digit H1. H1 has the weirdest counting scheme it starts at 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, and then back to 1. 7490 would not be applicable since the counting resets at 1. Another thing that makes the counting hard to visualize is that the counting resets once the second 3 value arrives. This counting can be considered as a mod-12 counter, but its values doesnt follow the typical sequence of a mod-12 counter (which would usually employ the use of hexadecimal digits eg. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, 0)

To be able to design H1, we need to analyze it simultaneously with its second digit, H2. The counting would then be more logical. It starts from 01, 02, 03, 04, 05, 06, 07, 08, 09, 10, 11, 12, 01 etc.Since H2 has only two values, it can be represented by only one bit. The single H2 bit is then made sequential through the use of a JK flip-flop (7473). Both JK inputs are connected to logic 1 meaning it is permanently in toggle (complement) When output Q is 0, it will cause a blank display and when Q is 1, it will display 1. The flip-flop will only interchange between these states. Q is used in connection to the display since the common anode requires a logic 0 to light up. The flip-flop will change its state once the clock pulse has a negative edge trigger.H1 digit utilizes the 74LS192 as its counter. An advantage of this IC is that the designer can input a certain value to which the counting would return (once loaded) (in this case it is at 1). The counting would return to 1 once pin 11 (load pin) receives a logic low level.

The following is the pin configuration of the 74192

pin 9 (D) - logic 0pin 10 (C) logic 0pin 1 (B) logic 0pin 15 (A) logic 1The counting would return to (0001) value once pin 11 (load) receives a low-logic level.

The counting requires the reset value to be at 13. This is the reason why a three-input NAND gate is used. A NAND gate instead of an AND gate is used to cancel the effect of the inverting bubble of the active-low load pin (pin 11).The inputs of the NAND gate is the Q of the JK flip-flop for H2 and QA and QB for the 74192.Observe to when all three of these values would all reach logic 1.Q-DCBA (H2, H1) 0-0000, 0-0001, 0-0010, 0-0011, 0-0100, 0-0101, 0-0110, 0-0111, 0-1000, 0-1001, 1-0000, 1-0001, 1-0010, 1-0011

All three values all became logic 1 when H2H1 value is at 13.When all this values are logic 1, the normally high-output of the NAND gate becomes low, therefore activating the load pin, thus returning the 1 value the instant the clock recognizes 13.Clock pulse for the 74192 is at pin 5. One of the disadvantages of using the 74192 in this circuit is its inconsistency with the type of clock pulse. All of the ICs used in the schematic is negative edge triggered. 74192 is the exception. This situation therefore, required an inverter gate as a remedy for the problem.A 2N3904 NPN transistor is used as an inverter to minimize IC usage.

Operation of this inverter is simple. When input is HIGH, collector and emitter terminals are shorted, therefore the VCC is pulled to the ground which makes the output at logic-low level. Low input of the base does nothing. This would mean the 5V VCC will be the output since there is no ground connected to it.The C bit of the M2 is used as CLK for H1 and the D bit for H1 is used as CLK for H2 for the same reason as discussed earlier.

Last counter used in this IC is the remaining JK flip-flop of the 7473 which is used for AM/PM.Q of H2 is connected to the B and C display, which should display 1 when both are at logic 0. This would mean Q is at 1 (simply because Q is the complement of Q)Q of H2 is connected to the clock of AM/PM since once H2 changes from 1 to 0, AM/PM should go to its next stateIllustration:12:59:57pm, 12:59:58pm, 12:59:59pm, 12:00:00amEach output (Q and Q) for the JK flip-flop of AM/PM is connected to a specific LED. One of the LEDs would represent AM and the other one for PM.This would now complete the counting stage of the schematic.

Last stage of the circuit (and is mainly for the output) is the display and the display decoders.The display decoder used is the 74LS47 (BCD to seven segment decoder). This IC has an active low output since this circuit will drive a common anode seven segment display which requires a low logic level to light up individual segments.

Although the schematic for the clock is complete, an additional feature is required for the project making, which is the alarm.This would require the use of the 4-bit magnitude comparator (74LS85) which is used during one of experimentations and will now be applied for practical uses in the project.The project used a total of 4 comparators and without going to a technical discussion, its function is simple; to compare the counters output, with the manual switches if theyre equal or not.Logically, equal values should trigger the alarm, and unequal values should have no effect on the alarm.The alarm itself is a simple 5V buzzer. It will emit a high pitched sound once it receives 5V (logic high) and without any applied voltage (logic low) the buzzer will have no reaction.The manual switches is used to set the values in which the alarm should be activated (for a 1-minute duration)

Project Implementation

video screenshot of the early stages of breadboarding (minute/second)

working alarm circuit (showing the buzzer, 74LS85 and the 8-dipswitch)

Trace for one of the circuits used in the project

developer solution, water and ferric chloride for PCB fabrication

Light exposure

Complete Clock circuit displaying 3:37:18pm (right LED on top represents PM)(3 breadboards)

Final project board design (with alarm), displaying 2:26:48pm

Schematic Diagram (Hour counter and Display)

schematic diagram (minute/second counter and display)

CONCLUSION

The final project, Digital Alarm Clock was composed of a total of 17 ICs (Integrated Circuits) which are the following: (4) 74LS85 4-bit Magnitude Comparator, (5) 74LS47 BCD to 7-segment display decoder, (4) 74LS90 binary decade counter, (1) 74LS192 pre-settable binary decade counter, (1) 74LS73 dual JK flip-flop with clear and pre-set, (1) 74LS10 triple three input NAND gate, (1) NE555 timer. Additional components are included for the function of the final project which includes (6) common anode 7 segment display for the display of the timer, (1) 2N3904 transistor used as an inverter for the clock to be inputted in the 74LS192, (1) tact switch for the increment of the hour timer, (4) LEDs for the indicator of the AM/PM function of the timer and also for the indicator of the alarm, (2) 8 dip switch for setting of the alarm, (1) buzzer for alarm, and other components for connection.The group encountered different problems in constructing the digital clock, both for the project boarding and the PCB fabrication stage. The main problem encountered that the 74LS90 is a high-current device. The counting for the 7490IC is usually different from the expected output when the voltage supply isnt sufficient for the proper operation. The usual display for the malfunctioning displays invalid numbers or the display presents a sequence of numbers which doesnt follow the proper order. The solution for this certain type of problem is finding an AC/DC adaptor with a higher maximum current supply or using a proper DC source from the laboratorys tool room.Another problem encountered is that there are multiple traces that are unintentionally connected from the developing and the soldering stage of the PCB making. To remedy this problem, the group used cutters to disconnect the traces, but this method damages the PCB and can be unpleasing to the eye when seen.The final project basically is an application of sequential logic. Sequential logic circuits is a type of logic circuit which not only base their output on the present, but also on the previous inputs of the circuit. Counters are the majority of the ICs used in the project which is an application of sequential logic.The combinational logic circuit used in the project is the comparator, which compares two lines of binary data. The main function of this comparator is for the equal function. Once the input from the clock and the input from the switching are equal, the LED will light up and the buzzer will emit a high-pitch sound which functions as the alarm.

PCB ImplementationThe PCB implementation of the digital clock is composed of 8 different PCB designs. This circuits are (1) clock pulse generator/voltage source, (1) Second/Minute counter, (2) Second/Minute Display, (1) Hour Display, (1) Hour Counter, (1) Minute Alarm and (1) Hour alarm.