Digital Integrated Circuits
YuZhuo Fucontact:[email protected]
Office location:417 roomWeiDianZi building,No 800 DongChuan road,MinHang
Campus
1.Introduction
If the automobile had followed the same development cycle as the computer, a Rolls-
Royce would today cost $100, get one million miles to the gallon and explode once
a year
outline
• Course Introduction
• a brief history
• Design Metrics
• DIC characteristics
• Design partitioning/CMOS logic
• Semiconductor processing
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course instruction
• Course named:Digital Integrated Circuit
• Course code:SOME-021
• Course type:fundamental
• credit:68 hours/4 credits
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Textbook
• Digital integrated circuit Jan M.Rabaey
• CMOS VLSI design- a circuits and systems perspective Meil H.E.Weste, addison wesley press
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http://bwrc.eecs.berkeley.edu/icbook/
Textbook
• Reference
– “Computer organization and design” John.l.hennessy
– “CMOS IC layout”, dan clein
– “Reuse Methodology manual for system-on-chip designs”, Michael Keating
– “Microelectronic Circuits:Analysis and Design” Muhammad H.Rashid
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Method of course
• Time, location– 1-16 weeks– Tues. 7-8[14:00-15:40], Room 东下院110– Fri. 1-2[08:00-09:40], Room 东下院110
• materials– slides– Please pre-read the slides before the lessons– Do not note the materials which slides have!
• Download address– Ic.sjtu.edu.cn/
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exam授课方式
(课时)作业(份)
实验(课时)
考试Office Hours
(次/周)
课堂
教学讨论
讲座
习题课
作业
文献
报告课内
课外
测验
考试
主课教师 助教
48 4 2 4 6 4 6 4 4 2 1 1
作业实验报告
文献报告
课程评价报告递交
考试
测验期中考试
期末考试
6*4 4*4 4*2+ 1*4 4*2 20 20
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Lab assistant
• teacher:prof. yuzhuo fu– contact:[email protected]– Office location:417 room– Office hours:??– microelectronic blgs,No 800 DongChuan
road,MinHang Campus
• pre:digital logic, circuit basic• Lab assistant:
– [email protected]– weidianzi blgs 214– Office hours:??
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target
• Understanding the basic principle of Digital IC– Inverter analysis
– Combinational logic
– Sequential logic
– Clocking issues
– Wire and interconnection issues
– Datapath design
• Skills– SPICE
– layout
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what is this book all about?
• Introduction to digital integrated circuits.– CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.
• What will you learn?– Understanding, designing, and optimizing digital
circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
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Why digital circuits ?
• Design and implement the module libraries• Critical timing path still need circuit design• Some technologies tend to be pushed to its limit need
circuit design• Abstraction-based approach is only correct to a certain
degree, such as interconnect parasitics, etc• Scaling tends to emphasize some other deficiencies of
the abstraction-based model• New design issues and constraints tend to emerge over
time• Model not always show the truth
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Some references
• http://www.itrs.net/
• http://www.lib.sjtu.edu.cn(IEEE conferences and journals)
• IEEE Journal of Solid-State Circuits (JSSC)
• IEEE International Solid-State Circuits Conference(ISSCC)
• Symposium on VLSI Circuits (VLSI)
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outline
• Course Introduction
• a brief history
• Design Metrics
• MOS transistor
• DIC characteristics
• Design partitioning/CMOS logic
• Semiconductor processing
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The First Computer
[1] The Babbage Pages http://www.ex.ac.uk/BABBAGE/
[2] J. A. N. Lee 写的传记 http://ei.cs.vt.edu/~history/Babbage.html
[3] Charles Babbage Institute http://www.cbi.umn.edu/charles.htm
[4] Howard Rheingold 写的书,电子版:Tools For Thought http://www.rheingold.com/texts/tft/index.html
[5] Ada 的笔记和一段日记 http://www.cs.yale.edu/homes/tap/Files/ada-lovelace-notes.html
[6] Dr. Betty Toole 写的 Ada 小传 http://www.cs.yale.edu/homes/tap/Files/ada-bio.html
[7] 《科学的新娘─浪漫、理性和拜伦的女儿》,班哲明‧伍列着,席玉苹译[9] 《经度:一个孤独的天才解决他所处时代最大难题的真实故事》索贝尔著,上海人民出版社
The babbage difference engine(1832)25,000 parts cost: £ 17,470
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ENIAC - The first electronic computer (1946)
http://www.seas.upenn.edu/~museum/
John Mauchly and J. Presper Eckert 16/54
The Transistor Revolution
First transistorBell Labs, 1948
William Shockley
John Bardeen
Walter BrattainT-R-A-N-S-I-S-T-O-RResistor which can amplify electrical signals as they are transferred
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Greatest persons
Jack S.Kilby(1923-2005) William Shockley(1910-1989) Robert Noyce,1927-1990
他们的伟大发明而带来的亿万颗芯片,正在世界的每一个角落一刻也不停息地跳动着,上至太空,下至海底,已经成为人类社会不可缺少的一部分。他们和福特、爱迪生、莱特兄弟一起,改变了我们的世界。
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Moore’s Law
• In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
• He made a prediction that semiconductor technology will double its effectiveness every 18 months
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Moore’s Law
161514131211109876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LO
G2 O
F T
HE
NU
MB
ER
OF
CO
MP
ON
EN
TS
PE
R IN
TE
GR
AT
ED
FU
NC
TIO
N
Electronics, April 19, 1965.
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Transistor Counts
1,000,000
100,000
10,000
1,000
10
100
1
1975 1980 1985 1990 1995 2000 2005 2010
8086
80286i386
i486Pentium®
Pentium® Pro
K1 Billion
Transistors
Source: Intel
Projected
Pentium® II
Pentium® III
Courtesy, Intel
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Moore’s law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010
Year
Tra
nsis
tors
(M
T)
2X growth in 26 months)!
Transistors on Lead Microprocessors double every 2 years
Courtesy, Intel
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Die Size Growth
40048008
80808085
8086286
386486Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010
Year
Die
siz
e (
mm
)
~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
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Frequency
P6
Pentium ® proc486
38628680868085
8080
80084004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Fre
qu
en
cy (
Mh
z)
Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
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Power Dissipation
P6Pentium ® proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Po
wer
(Watt
s)
Lead Microprocessors power continues to increase
Courtesy, Intel
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Power will be a major problem
5KW 18KW
1.5KW
500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Year
Po
wer
(Watt
s)
Power delivery and dissipation will be prohibitive
Courtesy, Intel
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Power density
40048008
80808085
8086
286386
486Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Po
wer
De
nsit
y (
W/c
m2)
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low temp
Courtesy, Intel
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Which one slow down the law?
• Technic
• Economic
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Processing CDProcessing R&D
cost (BUSD)IC Design cost
MUSDBreakeven
M chips
32/28 1.2 50-90 30-40
22/20 2.1-3 120-500 60-100
Next G cost 90-65 32 22 14
IC Design 15-20M 60-70M 100-150M 200-300M
Fab 2.5-3B 3.5-4B 4.5-6B 7-10B
Processing 200-400M 600-800M 1-1.3B 1.7-2.5B
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
20
03
19
81
19
83
19
85
19
87
19
89
19
91
19
93
19
95
19
97
19
99
20
01
20
05
20
07
20
09
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Lo
gic
Tra
nsis
tor
per
Ch
ip(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
cti
vit
y
(K)
Tra
ns./S
taff
-M
o.
Source: Sematech
Complexity outpaces design productivity
Co
mp
lex
ity
Courtesy, ITRS Roadmap
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Why Scaling?
• Technology shrinks by 0.7/generation• With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
• Cost of a function decreases by 2x• But …
– How to design chips with more and more functions?– Design engineering population does not double every
two years…
• Hence, a need for more efficient design methods– Exploit different levels of abstraction
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High K Intel 2007
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On Nov. 12, Intel shipped the first 45-nanometer
microprocessors using high-k metal-gate technology.
Whether to underscore the significance of the event or
to reinforce that his famous law remains on track,
Gordon Moore has become a central figure in the
marketing of Intel's 45-nm technology. Moore describes
the innovations as "the biggest change in transistor
technology since the introduction of polysilicon-gate
MOS transistors in the late 1960s." Even Time magazine
recognized the Intel Penryn microprocessor as one of
the best inventions of 2007
outline
• Course Introduction
• a brief history
• Design Metrics-COST
• DIC characteristics
• Design partitioning/CMOS logic
• Semiconductor processing
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Design Metrics
• How to evaluate performance of a digital circuit (gate, block, …)?
• Cost• Reliability• Scalability• Speed (delay, operating frequency) • Power dissipation• Energy to perform a function
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Cost of Integrated Circuits
• NRE (non-recurrent engineering) costs
– design time and effort, mask generation
– one-time cost factor
• Recurrent costs
– silicon processing, packaging, test
– proportional to volume
– proportional to chip area
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Design Economics
• Non-recurring engineering costs(NREs)
• Recurring costs
• Fixed costs
Stotal=Ctotal
(1-m)
Ctotal is the manufacturing cost of a single IC to the vendor, m is the desired profit margin
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Non-recurring engineering costs
• Spent once during the design of integrated circuit Ftotal
• Engineering design cost Etotal
• Prototype manufacturing cost Ptotal
• The NRE costs can be amortized over the lifetime volume of the chips
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Non-recurring engineering costs
• Spent once during the design of integrated circuit Ftotal
– Ftotal= Etotal + Ptotal
• Engineering design cost Etotal
• Prototype manufacturing cost Ptotal
• The NRE costs can be amortized over the lifetime volume of the chips
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Non-recurring engineering costs
• Spent once during the design of integrated circuit Ftotal
• Engineering design cost Etotal
– The cost of designing the IC Etotal hopefully will happen once during the chip design process
– Personnel cost• Architectural design
• Logic capture
• Simulation for functionality
• Layout of modules and chip
• Timing verification
• DRC and tapout procedures
• Test generation
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Non-recurring engineering costs
• Spent once during the design of integrated circuit Ftotal
• Engineering design cost Etotal
– The cost of designing the IC Etotal hopefully will happen once during the chip design process
– Support costs
• Computer costs
• CAD software costs
• Education or re-education costs
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Non-recurring engineering costs
• Spent once during the design of integrated circuit Ftotal
• Engineering design cost Etotal
– The cost of designing the IC Etotal hopefully will happen once during the chip design process
– Costs reference(2010)• Salary $50-$100K
• Overhead $10-$30K
• Computer costs $4K
• CAD software costs – Digital $10K
– Analog $100K
– Back end $1M
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Non-recurring engineering costs
• Spent once during the design of integrated circuit Ftotal
– Ftotal= Etotal + Ptotal
• Engineering design cost Etotal
• Prototype manufacturing cost Ptotal
– The mask costs($500K-$1M for 130nm process)
– Test fixture costs($1K-$50K)
– Package tooling
– MPW is an economical way of prototype(MOSIS)
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An example of NRE
You are starting a company to commercialize yourbrilliant research idea. Estimate the cost to prototype amixed-signal chip. Assume you have 7 digital designers.3 analog designers and 5 support personnel and thatthe prototype takes 2 fabrication runs and 2 years
Digital designers:7*($70K+$20K+$10K+$4K)=$728KAnalog designers:3*($100K+$30K+$100K+$4K)=$702KSupport personnel:5*($40K+$20K+$4K)=$320K2 fabrication:$2MTotal:$4*2M=$5M
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Design Economics
• Non-recurring engineering costs(NREs)
• Recurring costs
• Fixed costs
)m1(C
S totaltotal
Ctotal is the manufacturing cost of a single IC to the vendor
M is the desired profit margin
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Recurring costs
• Rtotal=Rprocess+Rpackage+Rtest
• Rprocess process cost
• Rprocess=W/(N.Yw.Ypa)
• W=wafer cost($500-$3000) depending on process and wafer size
• N= gross die per wafer
• Yw=die yield wafer(should be 70%-90% for moderate sized dice in a mature process)
• Ypa=packaging yield (should be 95%-99%)
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Yield
%100per wafer chips ofnumber Total
per wafer chips good of No.Y
yield Dieper wafer Dies
costWafer cost Die
area die2
diameterwafer
area die
diameter/2wafer per wafer Dies
2
Wasted area around the edges of a circular wafer
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Design Economics
• Non-recurring engineering costs(NREs)
• Recurring costs
• Fixed costs
– Once a chip has been designed and put into manufacture, the cost to support that chip from an engineering viewpoint may face a few sources
– Data sheets___characteristics
– Application notes
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An example of NRESuppose your startup seeks a return on investment of 5, the wafers cost $2000 and hold 400 gross die with a yield of 70%. If packaging, test and fixed costs are negligible.
– How much do you need to charge per chip to have a 60% profit margin?
– How many chips do you need to sell to obtain a 5-fold return on your $8M investment
• Rtotal=Rprocess=2000/(400*0.7)=$7.14
• Chip are sold at $7.14/(1-0.6)=$17.86
• Profit per unit is $17.86-$7.14=$10.72
• 8M*5/10.72=3.73M(assuming 1.5 year lifetime)
• 3.73/1.5*12=207K/month
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Chinese innovation ability is too weak
40%Logitech
20%Shopkeeper
17%Device Vendors3%
Total Manufacturing57/54