Differential 2R Crosspoint RRAM for
Memory system in Mobile Electronics with Zero Standby Current
Pi-Feng Chiu, Pengpeng Lu, Zeying Xin
EECS, UC Berkeley05/06/2013
Outline• Introduction
o Memory Hierarchyo RRAM switching mechanism
• Issues of Crosspoint Array• Proposed Differential 2R cell
o Cell Characteristicso Differential 2R cell and array design
• Circuit Implementationo Divided WL and Sense-before
• Simulation Results• Comparison• Conclusion
Memory Hierarchy
CPU Register
CacheL1L2
Main Memory(DRAM)
Permanent StorageHard Disk Drive, Solid State Drive
Hig
h m
emor
y de
nsity
High speed
Perfect Memory:NonvolatileHigh speedSmall AreaLow powerHigh Endurance
Leakage issue
Slow
RRAM switching mechanism
• RRAM: Resistive Random Access Memory• Sandwiched cell structure • SET: Switching to Low Resistance State (LRS)• RESET: Switching to High Resistance State (HRS)
Crosspoint Issues
(a)
(b)
(c)
1T1R Crosspoint structure
Leakage issues:Write – write energy efficiencyRead – read margin
Write Disturbance n: BL number, m: WL number
Cell Characteristics• Tradeoffs
o RLow vs. write energyo Write time vs. Write voltageo Write energy vs. Write voltageo Read margin vs. Rlowo Sensitivity to Write time
Differential 2R cell
Write-1 Write-0
Ra SET RESET
Rb RESET SET
WL Vwrite 0
BL 0 Vwrite
Assumption:VSET=VRESET=Vwrite
WLa[1]
WLb[1]WLa[0]
WLb[0]
BL0 BL1 BL2
Ra
Rb
1 cell
+
-
+
-
In read operation, WLa=Vread, WLb=0Voltage-sensing VBL
VBL=Vread*Rb/(Ra+Rb)
Divided WL
GWLaGWLb
LWLa
LWLb
Ra
Rb
BL
SWa SWb
…
• To constrain overall write current to 100~200uA, WL length need to be set to 4-cell wide
• Divided WL: decouple local WLs and connect to global WL by switches.
• Tradeoff between leakage current and area penalty
BEOL process enables stack ability
Sense-before-Write• Resistance value drops if a SET pulse repeatedly
access to the cell.
• Solution:
I(cell) Targeted resistance valueLowest resistance value
Write?
Read
If DIN=DOUT
?DOUT
DIN
Pass
Write
Yes
No
Block diagram
...B
lock
[0]
Blo
ck [1
]
Blo
ck [2
]
Blo
ck [6
2]
Blo
ck [6
3]
WL
mul
tiple
xer
and
driv
er
WERE
CLK
DIN[7:0]A[7:0] SAEN
BL multiplexer and driver
VwriteVhalfVread
VrefStrongARM Sense Amplifier
DOUT[7:0]
Control circuit
LWLGWL
I/O[7:0]
VBL VREF
VOUT
SAENb
SAENb SAENb
SAENb
WLa[0]
WLb[0]
WLa[1]
WLb[1]
BL[1]
DOUT
I(cell01b)
I(cell01a)
Write-0to cell01
0
~Vwrite/2
~Vwrite
SET
RESET
Write-1to cell11
R1R0
Vref
Write operationRead operation
Features
ComparisonDifferential 2R RRAM
SRAM
Performance 500MHz > 1GHz
Active Power Large (DC current)
Small (Static Logic)
Standby Leakage
0 570pJ/cell
Area 0.04 um2 (*) 0.1 um2 (22nm)
Endurance ~108 >1014*: assume metal width and space are 50nm, area = (0.05*4)2
Fit for L2/L3 cache in mobile electronics to save battery life
Conclusion• Differential 2R crosspoint RRAM design
o 64KB RRAM circuit o Divided WL and Sense-before-Write approacho 28/32nm PTM, RRAM cell model, Eldo simulator
• Crosspoint RRAM Cache?o Area: yeso Power: depending on applicationo Endurance
• Future Work:o Cell characterization o Leakage reduction, Cell distribution
?
Thanks!
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