B.C.A 2017
PES DEGREE COLLEGE BANGALORE SOUTH CAMPUS Affiliated to Bangalore University
MICROPROCESSOR AND ASSEMBLY LANGUAGE
MODULE SPECIFICATION SHEET
Course Outline The objective of the course is to expose to the students to the
architecture and instruction set of typical 8-bit microprocessor.
Microprocessors: Historical background; Organization &
Architectural Features of Microprocessor & Micro Controllers; The
Instruction Set: Instruction format, addressing modes; Assembly
language programming of 8085; Interfacing of memory devices; Data
transfer techniques and I/O ports; Interfacing of keyboard and display
devices; Programmable Interrupt and DMA controllers; Interfacing of
sensors, transducers, actuators, A/D & D/A Converters, Analog Signal
Conditioning Circuits, Data acquisition systems; Standard Interfaces –
RS232, USB; Development aids and troubleshooting techniques;
Application examples; Advanced microprocessors and
microcontrollers.
Faculty Details JAJI NEKKANTI
Assistant Professor Department of BCA
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1. GENERAL INFORMATION
Academic Year : 2017
Semester : V
Title Code Duration
MICROPROCESSOR AND ASSEMBLY
LANGUAGE BCA505T
Lectures 65
Tutorials 11
Total: 76
2. PRE REQUIREMENT STATEMENT
The students should have good background on digital circuits (should have attended the
course Switching Circuits and Logic Design).
3. COURSE RELEVANCE
This course is intended as a first level course for microcomputer and embedded system
design. Designer of an embedded system must have a thorough understanding of hardware,
software and system integration. In view of this, various aspects of hardware design, such
as interfacing of memory and different types of I/O devices, will be covered in details. As
it is customary to write software in machine or assembly language for embedded system
applications, laboratory assignments will be on assembly language programming of 8085.
4. LEARNING OUTCOMES
After completing the course students should be able to
1. Describe the architecture and comprehend the instruction set of 8085.
2. Understand and apply the principles of Assembly Language Programming in developing
microprocessor based applications.
3. Work with standard microprocessor interfaces like serial ports, digital-to-analog Converters
and analog-to-digital converters etc.
5. VENUE AND HOURS/WEEK
All lectures will normally be held on VIII Floor.
Lecture Sessions / Week: 6
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6. MODULE MAP
Class
(Sessi
on #)
Chapters Topic Details Cumulati-
ve % of
Portions
Covered
1.
UNIT 1
Architecture
and Operation
Introduction to 8085, Schematic diagram of digital
computer system
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.2 – 1.9
22%
2.
Key features, The Registers and System Bus of 8085
Microprocessor System.
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.10 – 1.14
3.
Machine Language, Assembly and High level Language
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.15 – 1.17
4.
Architecture of 8085 Microprocessor System
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.17 – 1.20
5.
Pin configuration of 8085 Microprocessor System.
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.20 – 1.24
6.
Block diagram of 8085 Microprocessor Based System
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.25 – 1.27
7.
Timing Diagrams (Opcode Fetch operation, Memory Read
operation, MVI R, Data)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.27 – 1.32
8.
Timing Diagrams (Memory write operation, I/O Read
operation, I/O write operation)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 1.33 – 1.35
9.
Memory interfacing –Introduction, Basic Memory Element
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 2.2 – 2.7
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10.
Basic concepts in Memory interfacing, Address decoding
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 2.7 – 2.10
11. Memory Mapping & Memory Addresses
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 2.11 – 2.19 12.
13.
Interfacing I/O devices – Introduction
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 3.1 – 3.2
14.
Methods of I/O Operations
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 3.2 – 3.2
15.
Peripheral – Mapped I/O
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 3.3 – 3.5
16.
Memory-Mapped I/O
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 3.6 – 3.12
17.
UNIT 2
Programming
the 8085
Introduction, Programming Model of 8085 Microprocessor
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.1 – 4.3
40%
18.
Instruction Format, Instruction Word size
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.4 – 4.5
19.
Addressing Modes
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.5 – 4.6
20.
Instruction Set Classification-Data transfer Group
instructions
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.7 – 4.3
21.
Arithmetic Group instructions (ADD R, ADD M, ADC R)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.15 – 4.18
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22.
Arithmetic Group instructions (ADC M, ADI 8-bit data,
ACI 8-bit data, DAD Rp)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.19 – 4.20
23.
Arithmetic Group instructions (SUB R, SUB M, SBB R)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.20 – 4.23
24.
Arithmetic Group instructions (SBB M, SUI 8-bit data, SBI
8-bit data, INR R)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.24 – 4.25
25.
Arithmetic Group instructions (INR M, DCR R, DCR M,
INX Rp)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.25 – 4.27
26.
Arithmetic Group instructions (DCX Rp, DAA)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.28 – 4.30
27.
Logical Group instructions (AND and OR operations)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.31 – 4.33
28.
Logical Group instructions (OR and XOR operations)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.33 – 4.36
29.
Compare instructions
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.37 – 4.39
30.
Rotate instructions
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.39 – 4.43
31.
Branch Control Group
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 4.43 – 4.52
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32.
UNIT 3
Programming
techniques
Looping Counting and Indexing
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.2 – 5.4
70%
33.
16 bit arithmetic operations – basics
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.4 – 5.7
34.
Addition and Subtraction of Two 8-bit Hex numbers Using
Memory pointer
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.7 – 5.10
35.
Addition of Two 16 bit numbers, Addition of N-byte
numbers
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.10 – 5.13
36.
Addition of Two N-byte Numbers
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.14– 5.15
37.
Subtraction of Two 16 bit numbers
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.16– 5.17
38.
Subtraction of Two N-byte Numbers
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.18 – 5.19
39.
Program for Block transfer, Program for Block Exchange
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.20 – 5.22
40.
Program for Exchange of Two Ten Byte Numbers
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.23 – 5.24
41.
Logic operations - rotate operations
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.25 – 5.32
42.
Logic operations – Compare
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.32 – 5.41
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43.
BCD Addition – Example 1, 2
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.41 – 5.46
44.
BCD Addition – Example 3, 4
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.47 – 5.51
45.
BCD Subtraction
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.52 – 5.54
46.
BCD Multiplication and division
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 5.54 – 5.58
47.
Counters and Time delays – Introduction, Time delay
calculation for one register
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 6.2 – 6.7
48.
Time delay using a loop within a loop technique
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 6.7 – 6.10
49.
Modulo Ten Counter, Hexadecimal counter
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 6.10 – 6.14
50.
Generation of pulse waveforms
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 6.15 – 6.16
51.
Stacks and subroutines
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 7.2 – 7.8
52.
Conditional CALL and RETURN instructions.
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 7.9 – 7.16
53.
BCD to Binary Conversion
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 7.17 – 7.19
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54.
Binary to BCD Conversion
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 7.19 – 7.21
55.
BCD to Seven Segment LED Code Conversion
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 7.21 – 7.23
56.
Binary to ASCII and ASCII to Binary code conversion
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 7.23 – 7.25
57.
UNIT 4
Memory
Interface and
Interrupts
The 8085 interrupts
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 8.8 – 8.13
82% 58.
8085 vectored interrupts
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 8.14 – 8.18
59.
Interrupt Instructions
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 8.18 – 8.20
60.
Pending Interrupts
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 8.21 – 8.23
61.
Serial Input and Output Data Transfer
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 8.23 – 8.24
62.
Additional I/O concepts and processes.
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 8.25 – 8.27
63.
8255 Programmable Peripheral Interface
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.2 – 9.5
64.
Block diagram of 8255 Programmable Peripheral Interface
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.5 – 9.9
65. Operational Modes of 8255A
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66.
UNIT 5
Interfacing of
peripherals
(I/Os) and
applications
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.10 – 9.21
100%
67.
Bit Set/Reset (BSR) Mode of 8255A
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.22 – 9.23
68.
Programmable Interrupt Controller (8259A) – pin diagram
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.23 – 9.24
69.
Block diagram of 8259A Programmable Interrupt
Controller
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.25 – 9.28
70.
Direct Memory Access (DMA) – pin diagram
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.29 – 9.30
71. Block diagram of 8257 DMA Controller
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.31– 9.36 72.
73. Programmable Keyboard and Display Interface (8279)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.37 – 9.43 74.
75.
Serial Communication and Programmable Communication
Interface (8251)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.44 – 9.48
76.
Interfacing Digital to Analog Converter (DAC)
Author: Mohana H K, Nethra H S, Bharathi A.
Page No: 9.48 – 9.50
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7. RECOMMENDED BOOKS/JOURNALS/WEBSITES
A. PRESCRIBED TEXTBOOK
T1 (Text Book 1) - Stallings, “Data and Computer Communications”, 7th Edition, Pearson
Education, 2012.
B. REFERENCE BOOKS
a. Mohana H K, Nethra H S, Bharathi A, Skyward Publications.
b. Andrew S Tanenbaim, “Computer Networks”, 4th Edition, Pearson Education.
c. 2. Behrouz Ferouzan, Introduction to Data Communication & Networking TMH,
1999.
d. 3. Larry &Peterson & Bruce S Davis; Computer networks Second Edition , Morgan
Kaufman, 2000.
8. ASSIGNMENTS
ASSIGNMENT 1
1. What are the functions of an accumulator?
2. Draw and explain the architecture of 8085.
3. Draw the pin diagram of 8085?
4. How many address lines are required to access 512MB bytes?
5. Mention the memory capacities corresponding to the number of address lines 10, 11, 12,
13, 14, 15 and 16.
ASSIGNMENT 2
1. Differentiate between the following instructions
a. LDA 8000H and STA 8000H
b. LHLD 9000H and SHLD 9000H
2. Write the instructions for below questions and mention the status of flags before and after
the execution.
a. Assume register pair BC contains 2498H and register pair DE contains 54A1H.
Add these two 16-bit numbers and save the result in BC registers.
b. Add the content of registers B (24H) and D (54H) by placing the contents of one
register in the ‘A’. Now the instruction ADC is required to add the contents of [B]
and [D] with carry from the addition of [C] and [E] register contents. Save the high-
order 8-bits results in register B.
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c. Assume the contents of the accumulator are 37H and the contents of the memory
location 2050H is 40H. Write a program to subtract M from the ‘A’ and store the
difference in register C.
3. Explain Time delay calculation.
4. Write an assembly language program to count a hexadecimal number continuously from
FFH to 00H with one millisecond (ms) delay between each count and display the number
at one of the output port. Assume the system frequency is 2MHz.
ASSIGNMENT 3
1. Write a program to add ten one byte hexadecimal numbers stored in a memory locations
starting at 8050H. Store the result in memory locations starting at 8700H.
2. Explain the steps to convert BCD to binary conversion with an example.
3. Draw the architectural block diagram of 8255PPI and mention different operating
modes.
4. Write an assembly language program to check if RST 5.5 is pending, enable it without
affecting any other interrupt else return to main program.
9. THEORY ASSESSMENT
A. WRITTEN EXAMINATION
The Theory Examination is for 70 Marks which will be held for duration of 3 Hrs.
The Scheme and Blue Print will be released to the students once the Bangalore
University releases it.
B. CONTINUOUS ASSESSMENT
The Continuous Assessment is conducted as per the following parameters.
Parameter MARKS WEIGHTAGE % 12 MARKS
Internal Test 35 MARKS 75% 9 MARKS
Assignment 10 MARKS 12.5% 1.5 MARKS
Class Test 10 MARKS 12.5% 1.5 MARKS
Total 55 MARKS 100% 12 MARKS
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The students are hereby required to note that every internal test weightage will calculated
for 12 Marks. This includes timely submission of assignments and attending class tests as
conducted.
The Sum of Best Two Performances in Internal Terms will be taken.
Parameter MARKS
Internal Test 01 12 MARKS
Internal Test 02 12 MARKS
Internal Test 03 12 MARKS
Final Internal Marks (Sum of Best Two Marks Of The Three
Internal Tests)
24 MARKS
Attendance
>95 % : 06 Marks
90 - 95 % : 05 Marks
85 - 90 % : 04 Marks
80 - 85 % : 03 Marks
75 - 80 % : 02 Marks
06 MARKS
Total 30 MARKS
10. ASSESSMENT / ASSIGNMENT / CLASS TEST / ACTIVITY PLANNER
Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Internal
Test T1 T2 T3
Assignments
Submission A1 A2 A3
Class Test C1 C2 C3
Legend Meaning Test Topics Examinable
T1, T2,T3 Internal Tests T1 Class 1 – 30
A1, A2, A3 Assignments T2 Class 31 – 52
C1,C2,C3 Class Test T3 Class 53 - 76
LT Problems 1-20
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11. MODEL QUESTION PAPERS
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12. PREVIOUS QUESTION PAPER
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