[CSt031] Graphics and Console Hardwareand Real-time Rendering
5th Lecture :: The XBOX 360 ArchitectureDr. Michael Manzke
Trinity College Dublin
Dr. Michael Manzke :: CS7031 :: 5th Lecture :: The XBOX 360 Architecture :: October 20, 2010 – p. 1/22
A First Look at the XBOX 360Architecture
So far we covered general CPU and simple cacheorganisations.
We have not yet considered advanced optimisation.
This part of the course is about graphics and consolehardware.
In this lecture we look at the first console hardware.
This will help us to identify aspects or computerarchitecture that we need to investigate further.
You will use the Xbox 360 intensively for your shaderprograming in the second part.
A good appreciation of the underlying architectureshould help you with this.
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The XBOX System Architecture Paper
The following slides are based on Andrews’ andBacker’s "XBOX 360 System Architecture"paper [AB06]. Figures on these slides are take fromthe paper.
A link to the paper, that can only be accessed bystudents in college, will be made available on thecourse’s web page.
[AB06] Jeff Andrews and Nick Baker. Xbox 360system architecture. IEEE Micro, 26(2):25–37, 2006.
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System Overview
The live cycle of game consoles is approximately 5years.
Consequently we see greater advances than we wouldexpect in desktop or server architectures.
The figure on the next slide shows a top-level systemdiagram (Figure on Slide 10).
We can clearly idenfy the main components in thistop-level system diagram:
CPUGraphics Processing Unit (GPU)MemoryI/O
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Top-level System Diagram
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Design Objectives
The architecture should provide a balanced hardware for the software pipe.
Rendering
Animation
Physics
AI
Console design must meet the the power requirements.
The design choices include:
Number of CPU cores.
Number of GPU shaders
CPU L2 size
Bus bandwidths
Memory size
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Design Features
The CPU has three cores that share:
A 8-way set-associative L2 cache.
The L2 cache has 1MB and is clocked at 3.2 GHz
Each of the three cores hold four-way single-instruction, multiple data (SIMD)vector units.
These components are optimised for graphics and game workloads.
The front-side bus (FSB) operates at 10.8 GB/s for reads and writes.
With 16 logical pins in each direction.
The FSB and L2 design allows the GPU to directly access the L2 cache.
The system’s I/O chip provides:
Xbox media audio XMA decoder.
on-the-fly decoding of compressed audio streams.
NAND flash controller
System management controller (SMC)
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The Graphics Processing Unit andMain Memory
The GPU has:
48 parallel, unified shaders.10 MB embedded DRAM EDRAM
Operats at 256 GB/sFor hight bandwidth to frame buffer and z-buffer.
The Main Memory has:
512 MB unified memoryIs a 700-MHz graphics douple-data-rate-3 (GDDR3)memory.22.4 GB/s memory bandwidth
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The CPU Component
PowerPC instruction set architecture
VMX SIMD vector instruction set (VMX128)
Customized for graphics workloads.
Shared L2 cache
Fine-graind, dynamic allocation of cache lines between the six threads
CPU core has two-per-cycle, in-order instruction issuance.
Two hardware threads per core.
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CPU Chip Diagram
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CPU Cached Data Streaming
The figure on the next slide is from the XBOX 360 SystemArchitecture Paper (Figure on Slide 12).
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CPU Cached Data Streaming Diagram
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A :: X360BlockDiagram04 (IBM)
The figure on the next slide is from the XBOX 360 SystemArchitecture Paper (Figure on Slide 14).
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The CPU Die Photo (IBM)
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The GPU Design
The figure on the next slide is from the XBOX 360 SystemArchitecture Paper (Figure on Slide 16).
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GPU Block Diagram (ATI)
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The GPU Die
The figure on the next slide is from the XBOX 360 SystemArchitecture Paper (Figure on Slide 18).
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The GPU Die Photo
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The ERAM Die
The figure on the next slide is from the XBOX 360 SystemArchitecture Paper (Figure on Slide 20).
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The ERAM Die Photo
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XNA Studio Integrated DevelopmentEnvironment (IDE)
The figure on the next slide is from the XBOX 360 SystemArchitecture Paper (Figure on Slide 22).
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XNA Studio (IDE) Screen Shot
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