CMOS
INTRODUCTIONINTRODUCTION
Integrated circuits: many transistors on single chip.
Metal Oxide Semiconductor (MOS) transistor
Fast, cheap, low-power transistors
Complementary: mixture of n- and p-type leads to less power
INTRODUCTIONINTRODUCTION
MOSFET
CMOSPMOSNMOS
SourceDrain
Gate
Metal Oxide Semiconductor Field Effect Transistor
Source ( Phosphorous, Boron)
Drain ( Phosphorous, Boron)
Gate (Aluminum, Polysilicon)
MOSFET
NMOS
P-type substrate
N-type dopant for Source & Drain
Inversion layer is formed to conduct electricity
PMOS
N-type substrate
P-type dopant for Source & Drain
Inversion layer is formed to conduct electricity
CMOS
A combination of both NMOS & PMOS technology
Most basic example: inverter
WELL FORMATIONWELL FORMATION
ISOLATION FORMATIONISOLATION FORMATION
TRANSISTOR MAKINGTRANSISTOR MAKING
INTERCONNECTIONINTERCONNECTION
PROCESS FLOWPROCESS FLOW
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
Start with clean p-type substrate (p-type wafer)
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
Grow epitaxy layer (made from SiO2) as mask layer for well formation
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
By photolithography and etching process, well opening are made
photolithography and etch processes are shown in next slides
Well will be formed here
PHOTOLITHOGRAPHY (CED)PHOTOLITHOGRAPHY (CED)
Photoresist coating (C)
Masking and exposure under UV light(E)
Resist dissolved after developed (D)◦Pre-shape the well pattern at
resist layer
P-substrateSi02
photoresist
P-substrate
mask
UV light
Opaque area
Transparent area
ETCHINGETCHING
Removing the unwanted pattern by wet etching
Resist cleanDesired pattern formed
P-substrate
P-substrate
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
Ion bombardment by ion implantationSiO2 as mask, uncovered area will exposed
to dopant ion
Phosphorus ion
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSIsolation formationIsolation formation
Increase SiO2 thickness by oxidation at high temperature
Oxide will electrically isolates nmos and pmos devices
Thick oxide
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESStransistor makingtransistor making
By photolithography and etching process, pmos and nmos areas are defined
pmos will be formed
here
nmos will be formed
here
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESStransistor makingtransistor making
Grow very thin gate oxide at elevated temperature in very short time
Gate oxide
CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Deposit polisilicon layer
polisilicon
CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Photolithography (photo) and etching to form gate pattern
gate
CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Photo process to define the nmos active (source and drain) area and VDD contact
Ion implantation with Arsenic ion for n+ dopant.
Photoresist and polysilicon gate act as mask
photoresist
Arsenic ion
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESStransistor makingtransistor making
Nmos’s Source and drain with VDD contact formation
Resist removal
source drainVDD
contact
CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Photo process to define the GND contact and pmos active area (source and drain)
Ion implantation with boron for p+ dopantPhotoresist and gate act as mask
Boron ion
photoresist
CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Pmos’s source and drain formation with GND contact
Resist removal
GND contact Pmos’
source
Pmos’s drain
CMOS FABRICATION CMOS FABRICATION PROCESSPROCESSinterconnectioninterconnection
Deposit CVD Oxide layer through out wafer surface
CVD
Oxide
Photo and etching process to make contact
CMOS FABRICATION PROCESSInterconnection
contact
CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSinterconnectioninterconnection
Metal 1 deposition throughout wafer surface
Metal 1
CMOS FABRICATION CMOS FABRICATION PROCESSPROCESSinterconnectioninterconnection
Photo and etching processes to pattern interconnection
ADVANTAGESADVANTAGES
High operating speed
Low cost
Very low static power consumption
High degree of noise immunity.
Optical lithography is limited by the light frequency.
Material limitations
Space limitations
DISADVANTAGESDISADVANTAGES
APPLICATIONSAPPLICATIONS
Integrated Circuits
Data converters
Integrated transceivers
Image sensors
Logic circuits
CONCLUSION
CMOS Transistors are stack of gate, oxide, silicon
Build logic gates out of switches
Draw masks to specify layout of transistors