1 © CMOS Digital Integrated Circuits – 3rd Edition
CMOS Digital Integrated Circuits
Chapter 1 Introduction
S.M. Kang and Y. Leblebici
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
2 © CMOS Digital Integrated Circuits – 3rd Edition
Some History
Invention of the transistor (BJT) 1947Shockley, Bardeen, Brattain – Bell Labs
Single-transistor integrated circuit 1958Jack Kilby – Texas Instruments
Invention of CMOS logic gates 1963Wanlass & Sah – Fairchild Semiconductor
First microprocessor (Intel 4004) 19702,300 MOS transistors, 740 kHz clock frequency
Very Large Scale Integration 1978Chips with more than ~20,000 devices
3 © CMOS Digital Integrated Circuits – 3rd Edition
More Recently
Ultra Large Scale Integration
System on Chip (SoC)
20 ~ 30 million transistors in 2002
The chip complexity has increased by a factor of 1000 since its first introduction, but the term VLSI remained virtually universal to denote digital integrated systems with high complexity.
7 © CMOS Digital Integrated Circuits – 3rd Edition
Some Leading-Edge Examples
9 © CMOS Digital Integrated Circuits – 3rd Edition
Evolution of Minimum Feature Size
11 © CMOS Digital Integrated Circuits – 3rd Edition
Moore’s Law
12 © CMOS Digital Integrated Circuits – 3rd Edition
Evolution of Memory Capacity
14 © CMOS Digital Integrated Circuits – 3rd Edition
YEAR 2002 2005 2008 2011 2014
TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm
CHIP SIZE 400 mm2 600 mm2 750 mm2 800 mm2 900 mm2
NUMBER OFTRANSISTORS(LOGIC)
400 M 1 Billion 3 Billion 6 Billion 16 Billion
DRAMCAPACITY 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits
MAXIMUMCLOCKFREQUENCY
1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz
MINIMUMSUPPLYVOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUMPOWERDISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUMNUMBER OFI/O PINS
2500 4000 4500 5500 6000
Shrinking Device Dimensions
15 © CMOS Digital Integrated Circuits – 3rd Edition
YEAR 2002 2005 2008 2011 2014
TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm
CHIP SIZE 400 mm2 600 mm2 750 mm2 800 mm2 900 mm2
NUMBER OFTRANSISTORS(LOGIC)
400 M 1 Billion 3 Billion 6 Billion 16 Billion
DRAMCAPACITY 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits
MAXIMUMCLOCKFREQUENCY
1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz
MINIMUMSUPPLYVOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUMPOWERDISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUMNUMBER OFI/O PINS
2500 4000 4500 5500 6000
Increasing Function Density
16 © CMOS Digital Integrated Circuits – 3rd Edition
YEAR 2002 2005 2008 2011 2014
TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm
CHIP SIZE 400 mm2 600 mm2 750 mm2 800 mm2 900 mm2
NUMBER OFTRANSISTORS(LOGIC)
400 M 1 Billion 3 Billion 6 Billion 16 Billion
DRAMCAPACITY 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits
MAXIMUMCLOCKFREQUENCY
1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz
MINIMUMSUPPLYVOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUMPOWERDISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUMNUMBER OFI/O PINS
2500 4000 4500 5500 6000
Increasing Clock Frequency
17 © CMOS Digital Integrated Circuits – 3rd Edition
YEAR 2002 2005 2008 2011 2014
TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm
CHIP SIZE 400 mm2 600 mm2 750 mm2 800 mm2 900 mm2
NUMBER OFTRANSISTORS(LOGIC)
400 M 1 Billion 3 Billion 6 Billion 16 Billion
DRAMCAPACITY 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits
MAXIMUMCLOCKFREQUENCY
1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz
MINIMUMSUPPLYVOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUMPOWERDISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUMNUMBER OFI/O PINS
2500 4000 4500 5500 6000
Decreasing Supply Voltage
20 © CMOS Digital Integrated Circuits – 3rd Edition
5-layer cross-section of chip
21 © CMOS Digital Integrated Circuits – 3rd Edition
Global
Intermediate
LocaE ·
.. - Passlmloo
Dlaleemric .,._ __ diffusl'on
barrier
22 © CMOS Digital Integrated Circuits – 3rd Edition
System-on-Chip
Integrating all or most of the components of a hybrid system on a single substrate (silicon or MCM), rather than building a conventional printed circuit board.
1. More compact system realization
2. Higher speed / performance
• Better reliability
• Less expensive !
23 © CMOS Digital Integrated Circuits – 3rd Edition
-::!l c:r. c::
0 > Q
.:.......:m ..... CSS
Comm µC
Audio Ollllplllt Processor
Audio ...... --1 FreqJJ@11cy
Synt~i1er
I MPEG·2 Yideo detoder
S,ste~n Frequency S y11tllesi zer
'"=i== c D/A A111d lo O llt?Llt.
Subp cture and OSD proce!Sor
Scalelf
-3 .e, 3
M emary · lnm~r I :'. M a_naget"Jlllllt 32-bit j Unit RISC CPU .,,,.
SD RAM
24 © CMOS Digital Integrated Circuits – 3rd Edition
New Direction: System-on-Chip (SoC)
ASIC CoreMemory
Embedded ProcessorCore
AnalogFunctions
Com
mun
icat
ion
SensorInterface
29 © CMOS Digital Integrated Circuits – 3rd Edition
The Y-Chart
Notice: There is a need for structured design methodologies to handle the high level of complexity !
30 © CMOS Digital Integrated Circuits – 3rd Edition
Simplified VLSI Design Flow
Top-down
Bottom-up
Top-down vs. bottom-up design
• Top-down design adds functional detail.
- Create lower levels of abstraction from upper levels.
• Bottom-up design creates abstractions from low-level behavior.
• Good design needs both top-down and
bottom-up efforts.
43
VLSI Design Cycle
[ • l• I J• I e
Behavioral
' VHDL, C
10 St ructural .. w VHDL
t ' ] ... I 1 ... 1
X=(AB*CD)+ (A+D)
- ! Y=(A(B+q+
AC+D)
44
VLSI Design Cycle
• System Specification - A high level representation of the system - Considered factors
» Performance Fabrication Technology
» Functionality · H De)ignTechniques
» Physical dimensions (die size)
- Result Specs - size, speed, power, and
functionality
45
VLSI Design Cycle
• Architectural Design - RISC (Reduced Instruction Set Computer)
versus CISC (Complex Instruction Set Computer)
- Number of ALUs, Floating Point Units
- Number and structure of pipelines
- Cache size
- Prediction on die size, power, and speed based on existing design
- Early estimation are very important here
46
VLSI Design Cycle
Behavioral or Functional Design - Only behavior and timing without
implementation issue - Specify behavior based on Input+ output+
timing - Fast emulation and debugging for the
system always @(posedge elk);
begin if (enable_ == l 'bO)
data= O; else
data = dat.a + 1; end
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45 © CMOS Digital Integrated Circuits – 3rd Edition
HDL-Based Design
1980’sHardware Description Languages (HDL) were conceived to facilitate the information exchange between design groups.
1990’sThe increasing computation power led to the introduction of logic synthesizers that can translate the description in HDL into a synthesized gate-level net-list of the design.
2000’sModern synthesis algorithms can optimize a digital design and explore different alternatives to identify the design that best meets the requirements.
VLSI Design Cycle
• Logic Design - Control flow, word widths, register allocation,
arithmetic operations, and logic operations - RTL (Register Transfer Level) - HDL (Hardware Description Language) » Verilog - most popular » VHDL - Europe and Eastern » Literal + Timing Information
X= (AB• CD)+ (A-r D)
Y= (A(B- C)-r AC+ D)
Boolean Expression
Timing lnfonnarion
48
VLSI Design Cycle
• Logic Design - More actual simulation and testing
a----b----c----d----
()
1
sa 1 sa CJ Y
- High Level Synthesis: Produce a RTL description from a behavioral description of the design
49
VLSI Design Cycle
Circuit Design - Boolean Expression - Circuit Elements (Cells, Macros, Gates, Transistors) + Interconnection - Each component has specific timing and power
Info. - Circuit Simulation : Verify the correctness and
timing - Terms - Netlist, Schematic - Logic Synthesis Tools : RTL -- Netlist
50
VLSI Design Cycle
Physical Design - Netlist - Layout (Geometry Representation)
» Design rules of applied fabrication process - Layout Synthesis Tools
» Automatic conversion (Fully/Partially) » Area and performance penalty
- Crucial Challenges - Area/Delay
VLSI Design Cycle
Fabrication - Layout~ Photo-lithographic mask
» One mask for each layer - Wafer : Silicon crystal are grown & sliced - Deposition, and diffusion of various materials on
the wafer : each step uses one mask - Term : Tape Out, 8 inch/20cm, 12 inch/30cm
- -, 'I
J "
' ,
'- ~ 52 ...... ,-
VLSI Design Cycle
Packaging, Testing, and Debugging - For PCB (Printed Circuit Board) : DIP (Dual In-line
Package), PGA (Pin Grid Array), BGA (Ball Grid Array), and QFP (Quad Flat Package)
- For MCM (Multi-Chip Modules): no packaged - Testing
» Before Package - Probe line testing » After Package - Tester machine applies test
patterns.
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31 © CMOS Digital Integrated Circuits – 3rd Edition
Structured Design Principles
Hierarchy: “Divide and conquer” technique involves dividing a module into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable.
Regularity: The hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction.
Modularity: The various functional blocks which make up the larger system must have well-defined functions and interfaces.
Locality: Internal details remain at the local level. The concept of locality also ensures that connections are mostly between neighboring modules,avoiding long-distance connections as much as possible.
32 © CMOS Digital Integrated Circuits – 3rd Edition
Hierarchy of a 4-bit Carry Ripple Adder
37 © CMOS Digital Integrated Circuits – 3rd Edition
Regularity
2-input MUX
DFF
38 © CMOS Digital Integrated Circuits – 3rd Edition
VLSI Design Styles
FPGA
39 © CMOS Digital Integrated Circuits – 3rd Edition
Full Custom Design
Following the partitioning, the transistor level design of the building block is generated and simulated.
The example shows a 1-bit full-adder schematic and its SPICE simulation results.
40 © CMOS Digital Integrated Circuits – 3rd Edition
Full Custom Design
The main objective of full custom design is to ensure fine-grained regularity and modularity.
41 © CMOS Digital Integrated Circuits – 3rd Edition
Full Custom Design
A carefully crafted full custom block can be placed both along the X and Y axis to form an interconnected two-dimensional array.
Example:
Data-path cells
42 © CMOS Digital Integrated Circuits – 3rd Edition
Full Custom SRAM Cell Design
43 © CMOS Digital Integrated Circuits – 3rd Edition
Mapping the Design into Layout
Manual full-custom design can be very challenging and time consuming, especially if the low level regularity is not well defined !
44 © CMOS Digital Integrated Circuits – 3rd Edition
VLSI Design Styles
FPGA
47 © CMOS Digital Integrated Circuits – 3rd Edition
Standard Cells
AND DFF INV XOR
48 © CMOS Digital Integrated Circuits – 3rd Edition
Standard Cells
49 © CMOS Digital Integrated Circuits – 3rd Edition
Standard Cells
50 © CMOS Digital Integrated Circuits – 3rd Edition
Standard Cells
Rows of standard cells with routing channels between them
Memory array
51 © CMOS Digital Integrated Circuits – 3rd Edition
Standard Cells
52 © CMOS Digital Integrated Circuits – 3rd Edition
VLSI Design Styles
FPGA
53 © CMOS Digital Integrated Circuits – 3rd Edition
Mask Gate Array
54 © CMOS Digital Integrated Circuits – 3rd Edition
Mask Gate Array
Before customization
55 © CMOS Digital Integrated Circuits – 3rd Edition
VLSI Design Styles
FPGA
56 © CMOS Digital Integrated Circuits – 3rd Edition
Field Programmable Gate Array
57 © CMOS Digital Integrated Circuits – 3rd Edition
Field Programmable Gate Array
Internal structure of a CLB
58 © CMOS Digital Integrated Circuits – 3rd Edition
Field Programmable Gate Array
• 1.2 Objective and Organization of the Book
Increasing Conl>lexily
Device Eleetronlcl
Two-Translstot Cin:ults
(ln1111ners)
Combinational and Sequential Logic Circuits .
. i Regular Structures , VLSI Sub-SystemS
ROMS, RAMs, Pl.As : Adde1'8, Multipliers . ···-----------------·-········ ..... ···---------------------------
System-Related Issues. Relabltlty, Manufaclurablllty, Tes1al>lllty
----- Breadth of Toplcs -----
Fig11rt 1.4. The ordering of topics covered in a typical digital integrated circuits course.
°'II""' Cln:uta
P1611r, J.S. Clan,ficalion of CMOS digilal circuit ty~s.
CVSL: Cascade Voltage Switch Logic NORA: NO RAce circuits TSPC: True-Single Phase Clock
TSPC L.ocfe Cl .......
•
25
1.3 A Circuit Design Example
Fall
Syst om Roquir oment.s
Architecture Definition and Logic O eslgn
Logic d iagr-am I description
, -------------------- ------------------------------------------------------------~ Teenno1<>gy
VLSI Design •nd ~yout Design A ·Uies Oovico Modola
: :
·----------=~~~~-~·:~~~~:~~~~---------------~~~~~-~~~~~~:.~~=~~------_] Pass
Mask Genor-atlon
Silicon Processing
T o : Wt11fer Testing Packaging Reliability Ouoliticotion
Figure 1 .e The flow of c i rcuit design procech.•re-s.
-
27
One-bit Full-Adder Circuit Design:
Using O.Bum twin-well CMOS technology with specification:
1) Propagation delay times of sum and carry-out signals <1.2ns (worst) 2) Transition delay times of sum- and carry-out signals < 1.2ns (worst) 3) Circuit area < 1500 µ m2
4) Dynamic power dissipation (@V00 = 5V and fmax = 20MHz) < 1mW
A B c
FullAdder
sum_out carry_out
Sum out= AEBBEBC - = ABC+ABC+ABC+ABC
Carry_out =AB+ AC+ BC
Sum_out =ABC+ (A+B+C)carry_out
ABC
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
sum_out carry_out
0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1
28
~ A B c
A B c
r·-- ···•• •••••• •••• ••••••••••••••••• • ••• ••••••••,
~-··········---········ ········· ··· · ··· ···-··-·-·
························-··········-··························'
Figure 1. 7 Gate-level schematic of the one-bit full-adder circlit
carry_out
sum
29
I
c---1 f-- A '"m
f--A A---1 e---1 f-e f--e -::
A---1 e---l c---l f-- c
Figure 1.8 Transistor-level schematic of the one-bit fuD·adder circuit.
30
Ill
Yoo
,.----, a-, r e ,.____, o-, c-, 1-c ;lll'!Y. Wt
I-a Yoo
c---4 }-A r" l\lffl
c~ ~ A I-A l- 11
A~ 8~ ~8 A--l a--j c--l
Figure 1,9 Alternate transistor-level schematic of the one-bit full-adder circuit (note that the nMOS and pMOS networks are completely symmetric).
31
B
I
I 1 I. '
c
! i I
I . I
CO P"oly in verti::::··~~tal in horizontal. SUM Figure 1.10 Initial layout of the full-adder circuit using minimum-size transistors.
Area= 21X54 um2 = 1134 um2 32
SPICE simulation ~~ s.zc. ,:-.,.. Ai:k::lil!l,r-. (.atn:x:t~ .....
•• • C-,, N
. :I 1 ..... . ~ a s.a
:I l I ] f ..... ~, · . l n I I •••
~~:i ... ·~ ~~ ~ r----2. . t :
- . ~· ~~~....::;::;::._~.....::;;:::::::::::;::===:;::::::::....___._.., -~·-.....
I:kc:\ . . .... n . 9 . r .. 2~ iolate 1.2ns ~load
Figure 1 .1 1 Simulated input and ou1j:)Ut waveforms ot the ~adder- cirouit.
- in ut s ,/
... ---
(
> ~ l
" ] 2 . s
j 2
l \
18 19 20 21 22 Time ( 11• )
INP17r CAJ\JtY --
I SVK •••·· ---+7-·-.. ··-·-------
___ ..... -·· ;~
_,/sum_out
Figure 1 . 12 Simulated ouqx.it waveforms of the full adder circuit with minimum transistor droensions. showing the signal propagabori delay during one of the worst-case transitions.
34
-A B c
] Area = 43X30 um2 = 1290 um2
VDD
SUM
GND
c;::J OIFF. D NWELL DP+ - POLY O MET- 1
- MET-2
Figure 1 .13 Modified layout of the full-adder circuit, with optimized transistor dimensions.
35
Worst Case Delay, Optimized Size Transiscors, EXTRACTED
-> 41 'O :, u .... .... j
sum UlPlIT -CARRY ••••
5 1--------+~·(\carry \
SUM ..... ......... .-o•-•-•-•••--.o-.oo••-••uo-.• .•·
./ 4
3
2.5
2
l f
: I : : - :--·
;-
' - ·-1
i . ' I .
--t - +: ,<1.23ns
' r ; ; ~ :
\! ..
·-+-
~· :\ .. 0 --·-·-----·-·_....., -·'---..,....:..'' - 'a::· ... • _________ _..._
18 19 20 2J, 22 T.ime (ns)
23 24
Figure 1.14 Simulated output wavef0<ms o f the full-adder circuit with optimized transistor dimensions, showing the signal propagation delay
25
-
during the same worst-case transition.. Power dissipation= 460 µ W 36
Full Adder c, (FA)
s,
Full Adder C2 (FA)
Full Adder C3 C, Full Adeler (FA) (FA)
Rgur. 1 .15 Block diagram of a cany ripple aclder chain consisting of full adders. Si., s, s., s~
37 Figure 1 . 1 8 Mask layout ol the 4 ·bt carry npple adder array.
• &I r'1A ,,,,,_,. A ll!Olt) lN 1¥ 191! I·?:? @ J,p l'l • (Ob'lI• I:t 1¥ Im lu IP ri .....,.,. Ml(U
su,.1(1) -----= ----~-:====~--......... __ ~ ';::::==::;-' ___ .:.......,!:;---
51.11,1(~~---~----...:..~;----';:::: SUU(S) ----~ rl Sl.l\lCQ -·------::========·~r--,- ~:;--~J SUWl'1) ~
.Ul ,-----,...._ __ n ,.---,__ ~
SlN(WSll~l----~---~"----' .. .__ ___ ~ ____ ....., . ~ ••• 7 • • : C...,. .. el loll Mot,,, 51«.
-~.ot::l = · -~-[,~4.- Ho V:..---.-::\===:=../ __ • H ~lL •••
-~~l:.::::,: =9'.M(l')=:::=,...::::::::;·~, ........... ---...... ~ ... ~ ....... ....:;;:;::;::;:;;:~'~~~~~ ................. .!::::=;:;::;::.:::;:;:.......,_...:.:::.;::.:= -~ ... ,. .. ::=] ...... , .. J ·°= •••
_:3 ••
) .). .. , I
Flgure 1.17 Slmu1ated Input and output waveforms of the 8-bit carry ripple adder circuit. showing a maximum signal propagation delay of about 7 ns.