Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-1
Chapter 16. MOS fundamentals
• Metal-oxide-semiconductor field effect
transistor (MOSFET) is the most important
device in modern microelectronics.
• In this chapter, we will study:
– Ideal MOS structure electrostatics
– MOS band diagram under applied bias
– Gate voltage relationship
– Capacitance-voltage relationship under low
frequency and under high frequency.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-2
MOSFET
N-channel MOSFET
(n-MMOSFET) uses
p-type substrate.
p-Si
When a positive VG is
applied to the gate
relative to the substrate,
mobile negative charges
(electrons) gets attracted
to Si-oxide interface.
These induced electrons
form the channel.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-3
MOSFET operation
pinch-off
For a given value of VG, the current ID increases with VD, and
finally saturates.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-4
Ideal MOS capacitor
2. The oxide is a perfect insulator with
zero current flowing through the oxide
layer under all biasing conditions.
The assumptions are:
3. There is no charge centers in the oxide or at the interface
between the oxide and semiconductor.
4. The semiconductor is uniformly doped.
6. An ohmic contact has been established between M and S.
7. The MOS capacitor is a one-dimensional structure.
1. Metallic gate is an equipotential
region under a.c. and d.c. biasing
conditions.
5. The semiconductor is thick so that the bulk is field-free.
8. M = S = + (EC – EF)FB flat band
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-5
Ideal MOS capacitor: band diagram
metal oxide semiconductor
under equilibrium
(zero-bias)
The ideal MOS has a flat band in equilibrium!
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-6
Effect of an applied bias
Let’s ground the semiconductor and
apply d.c. bias (VG) to the gate.
When VG ≠ 0, the semiconductor Fermi
level is unaffected by VG and remains
invariant as a function of position, because
of zero current flow through the MOS.
When VG ≠ 0 , the metal Fermi level is also invariant as a
function of position.
However, the applied bias separates the Fermi energies of M
and S by qVG, EF, metal – EF, semiconductor = – q VG
The EF,semiconductor is fixed (i.e., grounded), the EF,metal moves,
downward if VG > 0 upward if VG < 0
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-7
Effect of an applied bias
Since oxide has no charge,
according to the Poisson’s equation,
0ε
ρ
dx
dE
Therefore E-field inside the oxide is constant.
x
E
qx
E
qx
E
q
oxideVoxideCoxidei
oxide
,,, 111constantE
Therefore EC and EV are linear function of position with
a constant slope.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-8
n-MOS under VG > 0
VG > 0
E
When VG > 0, the EF of metal is
lowered relative to the EF of
semiconductor.
Accumulation of electrons (majority
carrier) near the interface of O and S.
The application of VG > 0 places
positive charges on the M gate.
kTEEnn iFi /)(exp
M O S
Ei(surface)
moves
downward
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-9
n-MOS under small VG < 0
VG (small) < 0
When VG < 0, the EF of metal is
raised relative to the EF of
semiconductor.
Deletion of electrons (majority carrier) near the interface of O
and S. positively-charged donor ions are exposed.
The application of VG < 0 places
negative charges on the M gate.
EM O S
Ei(surface)
moves
upward
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-10
n-MOS under more negative VG As VG increases more negatively, the energy band will bend up
more and more.
VG (small) < 0
E
E
VG < 0
(more negative)
Ei(surface) further
moves upward
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-11
kTEEnn iFi /)(exp
When Ei(surface) = EF,
Surface carrier concentrations
kTEEnp Fii /)(exp
iss nnp
Therefore the surface concentrations of electrons (ns)
and holes (ps) are kTsurfaceEEnn iFis /)(exp
kTEsurfaceEnp Fiis /)(exp
When Ei(surface) < EF, isis nnnp and
VG < 0
When Ei(surface) > EF, isis nnnp and
Especially when Ei(surface) – EF = EF – Ei(bulk)
DbulkiFis NnkTbulkEEnp /)(exp
or Ei(surface) – Ei(bulk) = 2[EF – Ei(bulk)]
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-12
For n-MOS capacitor, the applied negative voltage for ps = ND
is called threshold voltage (VT). onset of inversion
DbulkiFis NnkTbulkEEnp /)(exp
At this voltage, the surface is no longer depleted, because the
hole concentration in the surface is equal to the concentration
of ionized donors.
n-MOS under VG = VT
Ei(surface) – EF = EF – Ei(bulk)
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-13
n-MOS under VG < VT
For further increase in negative bias (VG < VT), ps exceeds
nbulk = ND.
The surface minority carrier concentration exceeds the
bulk majority carrier concentration.
It is called inversion.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-14
Ideal p-MOS
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-15
Ideal p-MOS v.s. n-MOS
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 16 - Lec 17-16
Announcements
• Next lecture: p. 571 ~ 584