Custom IC Design Lab (Fall 2011-12)Experiment Date: 18th
September 2011 Submitted Date: 2th November 2011Name: LITHIN BAL
!11"#D001$%8& 'o(t )a*out de)a* +a)+u)ation u(in, -./
0B1E.TI#E:To perform the RCX check and calculate the post layout
propagation delay of the CMOS Inverter CMOS NAN gate! Comple"
com#inational circuit !A!B2.%2D%3.I-.IT DIA4-A":Circuit iagramand
layout of CMOS Inverter $ate% Circuit iagramand layout of NAN
$ate%
"ethod(:Custom IC Design Lab (Fall 2011-12) ra& the
schematic diagram of the CMOS NAN gate as sho&n in the
a#ovecircuit! Assigned input 'ins (A) *) +dd) +ss, and output pin
(+out,! After checking and saving the circuit) layout is plotted
using layout X- tool! Run the RCX check and av e"tracted vie&
is o#tained! 'ost layout propagation delay is calculated for NAN
gate and compared &ithpropagation delay calculated circuit
stimulation!Circuit iagramand layout ofCom#inational
circuit!A!B2.%2D%3 % "ethod(: ra&the schematic diagramof the
Com#inational
circuit!A!B2.%2D%3assho&ninthea#ovecircuit!Assignedinput
'ins(A) *)C)) +dd) +ss, andoutput pin (.,! After checking and
saving the circuit) layout is plotted using layout X- tool! Run the
RCX check and av e"tracted vie& is o#tained! 'ost layout
propagationdelay is calculatedforCombinational
circuit!A!B2.%2D%3and compared &ith propagation delay
calculated circuitstimulation!Custom IC Design Lab (Fall
2011-12)0BSE-#ATI0NS:/! RCX Result for CMOS inverter $ate%'ost
layout simulation%Custom IC Design Lab (Fall 2011-12)0! RCX Result
for NAN $ate%'ost layout simulation%1! RCX Result forComple"
com#inational circuit (A(*2C,2,3%Custom IC Design Lab (Fall
2011-12)'ost layout simulation%Ta#le%/Custom IC Design Lab (Fall
2011-12)'re4layoutsimulation'ost layoutsimulationt'5-(ps, t'-5(ps,
t'5-(ps, t'-5(ps,CMOSIN+6RT6R17!18 /19!: :/!/ /:7!0NAN $AT6 1!891
/:7!/ /8!;/ /7;!*est Case>>1*est Case Input Com#ination% A @
/4?A *@/4?A C@?A @?A-ESLTS:RCXrunisperformedandthepost layout
delayiscalculatedfor thefollo&ingcircuits% CMOS Inverter CMOS
NAN gate! Comple" com#inational circuit !A!B2.%2D%3It i( ob(erved
that propa,ation de)a* i( in+rea(ed ()i,ht)* due to pre(en+e o5 the
re(i(tan+e and +apa+itan+e in )a*out )a*er-E6E-EN.ES Bigital
Integrated CircuitsC#yM! Ra#aey
