INDEX
1. BLOCK TRANSFER AND BLOCK EXCHANGE OF DATA
BYTES
2. ARRANGING ELEMENTS OF A BLOCK OF DATA IN
ASCENDING AND DESCENDING ORDER.
3. MULTIPLICATION OF TWO 8-BIT NUMBERS USING THE
METHOD OF SUCCESSIVE ADDITION AND SHIFT AND
ADD.
4. CONVERTING TWO DIGIT NUMBER TO THEIR
EQUIVALENTS
5. GENERATION OF FIBONACCI SERIES
6. INTERFACING DAC 0808
7. INTERFACING OF THUMBWHEEL SWITCH.
8. ARRANGING BLOCK IN DESCENDING AND ASCENDING
9. 8051 TIMER BASED EXPERIMENT.
10. INTERFACING OF DOT MATRIX DISPLAY USING 8051
EXPERIMENT NO – 1
BLOCK TRANSFER
AND BLOCK
EXCHANGE OF DATA
BYTES
BLOCK TRANSFER AND BLOCK EXCHANGE OF
DATA BYTES
Program Statement:
Write a program to transfer block of bytes from location
2040 to 2050. Then exchange block of data at 2040 and 2050. Block length is
stored at 203F.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS
VMC-8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
1. How transfer byte from one location to other?
2. Use of indirect addressing mode.
3. Exchange of data between two memory locations.
Logic:
BLOCK TRANSFER:
Block length is copied from location 203F and is used as
counter. Data from memory location 2040 is copied to accumulator and from
accumulator to 2050.After data is copied pointers for source and destination
block is incremented by one and counter is decremented. Procedure is
repeated till counter is not zero.
BLOCK EXCHANGE:
Content of memory location pointed by HL pair is copied
to register B and from location pointed by DE pair to accumulator. Then data
from accumulator is copied to location pointed by HL pair and from Reg. B to
location pointed by DE pair and thus exchange is carried out. HL and DE pair
is incremented counter is decremented . Exchange is carried out till counter is
not zero.
ALGORITHM:
BLOCK TRANSFER:
1. Start
2. Copy length of block
3. Initialize memory pointer of source block
4. Initialize memory pointer of destination block
5. Copy content of memory location from source block to accumulator
6. Copy content of memory location from accumulator to destination
block
7. Increment both pointers
8. Decrement counter
9. If counter is not zero go to step 5
10. Stop
No Yes
Copy length of block
Is counter = 0 ?
Increment both pointers
Initialize source block pointer
Initialize destination block pointer
Copy content to destination memory
location
Decrement counter
Copy content from source memory location
Stop
Stop
BLOCK EXCHANGE
No Yes
Copy length of block
Is counter = 0 ?
Increment both pointers
Initialize source block pointer
Initialize destination block pointer
Decrement counter
Exchange content of source and destination
memory location
Stop
Stop
BLOCK TRANSFER OF DATA BYTES
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 21 LXI H, 203F Point where lengthIs stored2001 3F
2002 202003 4E MOV C, M Copy length2004 23 INX H2005 11 LXI D,2050 Initialize destination2006 50 pointer2007 202008 7E BACK: MOV A,M2009 12 STAX D200A 23 INX H Increment source pointer
200B 13 INX DIncrement destination pointer
200C 0D DCR C200D C2 JNZ BACK
Check counter is zero or not?
200E 08200F 202010 EF RST 5
BLOCK EXCHANGE OF DATA BYTES
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 21 LXI H, 203F Point where lengthIs stored2001 3F
2002 202003 4E MOV C,M Copy count value2004 23 INX H2005 11 LXI D,2050 Initialize pointer2006 502007 202008 46 BACK: MOV B,M2009 1A LDAX D200A 77 MOV M,A200B 78 MOV A,B200C 12 STAX D200D 23 INX H Increment pointer200E 13 INX D200F 0D DCR C2010 C2 JNZ BACK2011 082012 202013 EF RST 5
Result:
Block transfer:
Exchange Data Bytes:
MemoryAddress
Data
2040 112041 222042 552043 782044 632045 482046 542047 872048 232049 65
MemoryAddress
Data
2050 112051 222052 552053 782054 632055 482056 542057 872058 232059 65
MemoryAddress
Data
2050 872051 782052 652053 632054 552055 542056 482057 232058 222059 11
MemoryAddress
Data
2040 112041 222042 552043 782044 632045 482046 542047 872048 232049 65
MemoryAddress
Data
2050 112051 222052 552053 782054 632055 482056 542057 872058 232059 65
MemoryAddress
Data
2040 872041 782042 652043 632044 552045 542046 482047 232048 222049 11
EXPERIMENT NO – 2
ARRANGING
ELEMENTS OF
BLOCK IN
ASCENDING AND
DESCENDING ORDER
ARRANGING BLOCK OF DATA IN ASCENDING AND
DESCENDING ORDER
Program Statement:
Write a program to arrange given block of data starting
from 2051h in ascending order and descending order. Store result from 2070
for ascending order and from 2080 for descending order. Length of data is
stored in memory location 2050h.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS
VMC-8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
1. How to arrange block in ascending and descending order?
2. Why to use two counters?
3. Use of compare instruction.
4. Effect of compare instruction on flag.
Logic:
Ascending Order:
Technique to arrange data bytes in ascending order is to
compare two bytes at a time and arrange them at same time. Two counters
are used for arranging data in ascending order. Two Numbers at successive
memory locations are compared. Smaller number is stored at first memory
location and larger number stored at next memory location. First counter is
decremented by one and when first counter is zero then second counter is
decremented by one and first counter is loaded again. So when second
counter is also zero block is arranged in ascending order.
Descending Order:
Technique to arrange data bytes in descending order is to
compare two bytes at a time and arrange them at same time. Two counters
are used for arranging data in descending order. Two Numbers at successive
memory locations are compared. Larger number is stored at first memory
location and smaller number at next memory location. First counter is
decremented by one and when first counter is zero then second counter is
decremented by one and first counter is loaded again. So when second
counter is also zero block is arranged in descending order.
Algorithm:
Ascending Order:
1. Start
2. Copy length of block
3. Initialize outer counter
4. Initialize inner counter
5. Initialize memory pointer
6. Compare two numbers
7. If carry flag is set go to step 9
8. If carry flag is not set exchange numbers
9. Decrement inner counter
10. If counter is not zero increment memory pointer go to step 6
11. If counter is zero decrement outer counter
12. If counter is not zero go to step 4
13.Stop
Descending Order:
1. Start
2. Copy length of block
3. Initialize outer counter
4. Initialize inner counter
5. Initialize memory pointer
6. Compare two numbers
7. If carry flag is reset go to step 9
8. If carry flag is set exchange numbers
9. Decrement inner counter
10. If counter is not zero increment memory pointer go to step 6
11. If counter is zero decrement outer counter
12. If counter is not zero go to step 4
13. Stop
SORTING IN ASCENDING ORDER
No
Yes
No
Yes
Yes
No
Yes
Yes
Copy length of block
Is carry flag set?
Exchange two numbers
Is counter = 0 ?
Decrement outer counter
Is counter = 0 ?
Initialize outer counter
Initialize inner counter
Compare two numbers
Decrement inner counter
Initialize memory pointers
Increment memory pointers
Start
Stop
SORTING IN DESCENDING ORDER
No
Yes
No
Yes
Yes
No
Yes
Yes
Copy length of block
Is carry flag
reset?
Exchange two numbers
Is counter = 0 ?
Decrement outer counter
Is counter = 0 ?
Initialize outer counter
Initialize inner counter
Compare two numbers
Decrement inner counter
Initialize memory pointers
Increment memory pointers
Start
Stop
SORTING IN ASCENDING ORDER
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 21 LXI H, 204F Point where lengthIs stored2001 4F
2002 202003 46 MOV B, M Copy length2004 35 DCR M2005 5E MOV E, M2006 4B LOOP2: MOV C, E Initialize inner counter2007 21 LXI H, 20512008 51 LOOP1: MOV A, M2009 20 INX H200A BE CMP M Compare two numbers200B DA JC NEXT200C 13200D 20200E 56 MOV D, M Exchange if carry is
Not created200F 77 MOV M, A2010 2B DCX H2011 72 MOV M, D2012 23 INX H2013 0D NEXT: DCR C Decrement inner counter2014 C2 JNZ LOOP12015 082016 202017 05 DCR B Decrement outer counter2018 C2 JNZ LOOP22019 06201A 20201B EF RST 5
SORTING IN DESCENDING ORDER
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 21 LXI H, 2050 Point where lengthIs stored2001 50
2002 202003 46 MOV B, M Copy length2004 35 DCR M2005 5E MOV E, M2006 4B LOOP2: MOV C, E Initialize inner counter2007 21 LXI H, 20502008 50 LOOP1: MOV A, M2009 20 INX H200A BE CMP M Compare two numbers200B DA JNC NEXT200C 13200D 20200E 56 MOV D, M Exchange if carry is
created200F 77 MOV M, A2010 2B DCX H2011 72 MOV M, D2012 23 INX H2013 0D NEXT: DCR C Decrement inner counter2014 C2 JNZ LOOP12015 082016 202017 05 DCR B Decrement outer counter2018 C2 JNZ LOOP22019 06201A 20201B EF RST 5
Result:
Ascending order: Before sorting After sorting
Descending order:
Before sorting After sorting
MemoryAddress
Data
2051 112052 222053 552054 782055 632056 482057 542058 872059 23205A 65
MemoryAddress
Data
0500 110501 220502 230503 480504 540505 550506 630507 650508 780509 87Memory
AddressData
2051 112052 222053 552054 782055 632056 482057 542058 872059 23205A 65
MemoryAddress
Data
0500 870501 780502 650503 630504 550505 540506 480507 230508 220509 11
Question Bank
1. Compare instructions SUB B and CMP B.
2. How compare instruction will affect on flags?
3. Where result of comparison is stored?
EXPERIMENT NO – 3
MULTIPLICATION OF
TWO 8 BIT
NUMBERS
MULTIPLICATION BY SHIFT AND ADD METHOD
Program Statement:
Write a program to multiply two 8-bit numbers by shift and add
method. Numbers are present at memory location 2100(multiplier) and
2101(multiplicand). The result is 16 bit and is to be stored in memory
location2102 and 2103.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS VMC-
8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
a) Methods of multiplication.
b) Shift and add method for multiplication.
c) Use of DAD h in shift and add method.
Logic:
The technique used to multiply two 8 bit numbers is same as
used to multiply two binary numbers. In this method each bit of the multiplier
bit is multiplied with multiplicand. Each partial product is to be shifted left so
as to double the number.
If the multiplier bit is 0 the multiplicand is doubled placed as the
partial product. Therefore if multiplier ‘ n’ bit number of partial product will be
‘n’ if multiplicand is ‘m’ bits the product length will be 2 * m.
1101 (multiplicand)
*0011(multiplier)
---------------------------------
1101 (partial products)
1011x
0000 x x
0000 x x x
----------------------------------------------
00100011 (result)
MULTIPLICATION BY SHIFT AND ADD METHOD
Algorithm:
1. Start.
2. Set partial product register pair to 0.
3. Set up register pair as multiplicand, get multiplier is register C
as counter.
4. Double the partial product for next summand.
5. If multiplier is zero go to step 7.
6. If multiplier is not zero add multiplicand to the previous partial
product.
7. Decrement counter by 1.
8. If counter is not zero go to step 4.
9. If counter is zero save result in register pair in memory.
10. Stop.
MULTIPLICATION BY SHIFT AND ADD METHOD
Yes
No
No
Yes
Set partial product register pair to 0
Double the partial product for next summand
Is multiplier zero?
Add multiplicand to the previous partial product
Is counter zero?
Decrement counter by 1
Set up register pair as multiplicand; get multiplier in
register C as counter
Save result in register pair in memory
Start
Stop
MULTIPLICATION BY SHIFT AND ADD METHOD
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 2A LHLD 2050Initialize memory pointer2001 50
2002 202003 5D MOV E,L2004 16 MVI D,00H2005 002006 43 MOV B,H2007 21 LXI H,0000H2008 002009 00200A 0E MVI C,08H Number of times to be 200B 08 rotated200C 29 UP: DAD H200D 78 MOV A,B200E 07 RLC200F 47 MOV B,A2010 D2 JNC NEXT2011 142012 202013 19 DAD D2014 0D NEXT: DCR C2015 C2 JNZ UP2016 0C2017 202018 22 SHLD 20522019 52201A 20201B EF RST 5
Result:
INPUT OUTPUT
Address Data2100 3Fh2101 70h
Address Data2102 1Bh2103 90h
MULTIPLICATION BY SUCCESSIVE ADDITION
Algorithm:
1. Start
2. Copy contents of memory location to HL pair(First number)
3. Copy content of memory location to register C(Second number)
4. Add first number in itself
5. Decrement reg C
6. If not zero go to step 4
7. Store result
8. Stop.
MULTIPLICATION BY SUCCESSIVE ADDITION
No
Yes
Copy 1st number from memory location to register pair
Add first number in itselfHL+DE Decrement reg C
Is reg C zero?
Copy second number from memory location to register C
Copy first number in DE pair
Store result in memory location
Start
Stop
MULTIPLICATION BY SUCCESSIVE ADDITION
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 01 LXI B,2200 Load BC pair with content Of memory location2200
2001 002002 222003 0A LDAX B2004 6F MOV L,A Copy first number2005 26 MVI H,002006 002007 03 INX B2008 0A LDAX B2009 3D DCR A200A 4F MOV C,A Copy second number200B 5D MOV E,L200C 16 MVI D,00200D 00200E 19 LOOP: DAD D200F 0D DCR C2010 C2 JNZ LOOP2011 0E2012 202013 01 LXI B, 20022014 022015 202016 7D MOV A,L Store result2017 02 STAX B2018 03 INX B2019 7C MOV A,H Store result201A 02 STAX B201B EF RST 5
Result:
INPUT OUTPUT
Address Data2200 AA H2201 AA H
Address Data2202 E4 H2203 70 H
Question Bank
1. Compare RAR and RRC.
2. Explain following instructions
a) SHLD 2100
b) DAD D
c) XCHG
d) LHLD 2100
3. What is difference between hardware and software
interrupts?
4. What are vectored interrupts?
5. What are maskable and non maskable interrupts?
CONVERTING TWO DIGIT NUMBERS TO THEIR
EQUIVALENTS
Program Statement:
Write a program to convert two digit number from BCD to HEX.
Number is at location 2040 store result at location 2041.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS VMC-
8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
1. Unpacking of BCD number.
2. Division of number.
Logic:
BCD TO HEX CONVERSION:
BCD number is unpacked and LSB and MSB is
unpacked. MSB is multiplied by 10 and LSB is added in resulting value of
multiplication.
HEX TO BCD CODE CONVERSION:
EXPERIMENT NO – 4
CONVERTING TWO
DIGIT NUMBER
TO THEIR
EQUIVALENTS
HEX number is divided by 100 which is MSB.
Remaining value is divided by 10 and remainder will be LSB.
Algorithm:
BCD TO HEX CONVERSION:
1. Start
2. Copy number from memory location
3. Unpack both digits
4. Multiply MSB by 10
5. Add LSB into previous multiplication result
6. Store result
7. Stop
HEX TO BCD CODE CONVERSION:
1. Start
2. Copy number from memory location
3. Divide number by 100 it will give MSB
4. Divide number by 10
5. Remainder is LSB
6. Store result
7. Stop
BCD TO HEX CONVERSION
Copy number from memory location
Multiply MSB by 10 add LSB into it
Unpack number and separate LSB and MSB
Start
Store result in memory location
Stop
HEX TO BCD CONVERSION
Copy number from memory location
Divide number by 10,Remainder is LSB
Divide number by 100(MSB)
Start
Store result in memory locations
Stop
BCD TO HEX CODE CONVERSION:
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 21 LXI H,2040 Load HL pair with address of memory location2001 40
2002 202003 46 MOV B,M2004 7E MOV A,M Unpack LSB2005 E6 ANI 0FH2006 0F2007 4F MOV C,A2008 78 MOV A,B2009 E6 ANI F0H Unpack MSB200A F0200B CA JZ NEXT200C 1B200D 20200E 0F RRC200F 0F RRC2010 0F RRC2011 0F RRC2012 57 MOV D,A2013 AF XRA A2014 1E MVI E,0AH Multiply MSB by 102015 0A2016 83 ADD: ADD E Add both2017 15 DCR D2018 C2 JNZ ADD2019 16201A 20201B 81 ADD C201C 23 INX H201D 77 MOV M,A Store result201E EF RST 5
Result:Input: Output:
Address Data2040 12
Address Data2041 0C
HEX TO BCD CODE CONVERSION
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 21 LXI H,2040 Load HL pair with address of memory location2001 40
2002 202003 7E MOV A,M2004 06 MVI B,64H2005 642006 23 INX H2007 36 MVI M,FFH2008 FF2009 90 NEXT: SUB B Divide number by 100200A 34 INR M200B D2 JNC NEXT200C 09200D 20200E 80 ADD B200F 23 INX H2010 36 MVI M,FFH2011 FF2012 06 MVI B,0AH2013 0A2014 90 NEXT1: SUB B Divide number by 102015 34 INR M2016 D2 JNC NEXT12017 142018 202019 80 ADD B201A 23 INX H201B 77 MOV M,A201C EF RST 5
Result:Input: Output:
Address Data2040 FF
Address Data2041 022042 052043 05
GENERATION OF FIBONACCI SERIES
Program Statement:
Write a program to generate Fibonacci series starting from
location 2040.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS VMC-
8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
a. Generation of series
Logic:
Copy first two numbers to locations. For generating next
number add previous two numbers and store result. Go on repeating same
procedure till counter is not zero.
Algorithm:
1. Start
2. Initialize pointer
EXPERIMENT NO – 5
GENERATION OF
FIBONACCI
SERIES
3. Initialize counter
4. Copy first two numbers
5. Generate next number by adding previous two
6. Store result
7. Increment Pointer
8. Decrement counter
9. If counter is not zero go to step 5
10. Stop
GENERATION OF FIBONACCI SERIES
No Yes
Copy first two numbers
Is counter = 0 ?
Initialize pointer and counter
Generate next number by addition of previous
numbers
Increment pointer
Decrement counter
Store result
Stop
Start
GENERATION OF FIBONACCI SERIES
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 21 LXI H,2040HInitialize memory pointer2001 40
2002 202003 0E MVI C,09H Initialize counter 2004 092005 36 MVI M,00H Copy first number2006 002007 23 INX H2008 36 MVI M,01H Copy second number2009 01200A 7E BACK: MOV A,M200B 2B DCX H200C 86 ADD M Generate next number200D 23 INX H200E 23 INX H200F 77 MOV M,A Store result2010 0D DCR C2011 C2 JNZ BACK2012 0A2013 202014 EF RST 5
Result:
Address Data2040 002041 012042 012043 022044 032045 052046 082047 0D2048 15
EXPERIMENT NO – 6
INTERFACING OF DAC
0808
INTERFACING OF DAC 0808
Program Statement:
Write program to generate triangular waveform using DAC 0808
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS VMC-
8501),Scratch Pad RAM used from 2000h to 2770h, Cathode Ray
Oscilloscope.
Learning Objective:
a) DAC 0808
b) OUT instruction
c) How to generate triangular wave?
Logic:
R-2R Ladder DAC: R
2R R R R
2R 2R 2R 2R
+ 5 VOnly two values of resistors are used but result is same, input current is
proportional to bit inputs.
Features of DAC 0808 are:
a) It has 8 data inputs.
b) Fast setting time 150ns.
c) Low power consumption 33mW.
d) +5V power supply.
e) TTL and CMOS compatible.
TRIANGULAR WAVE GENERATION USING DAC 0808
Algorithm:
1. Initialize accumulator to 00H.
2. Output register A to DAC buffer A0H.
3. Increment accumulator.
4. Compare accumulator content with FFH.
5. If not zero go to step 2 or go to step 6.
6. Decrement accumulator.
7. Output register A to DAC buffer A0H.
8. Compare accumulator content with 00H.
9. If not zero go to step 6 or go to step 10.
10. Go to step 1.
TRIANGULAR WAVE GENERATION USING DAC 0808
No
Yes
No
Yes
Load accumulator with 00H
Increment accumulator
Decrement accumulator
Compare A with FFH
Start
Out accumulator content on A0H
Is ZF=1?
Out accumulator content on A0H
Compare A with 00H
Is ZF=1?
TRIANGULAR WAVE GENERATION USING DAC 0808
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 3E NEXT: MVI A, 00H Load A with 00H2001 002002 D3 NEXTINR: OUT A0H Output A to DAC2003 A02004 3C INR A Increment A2005 FE CPI FFH2006 FF2007 C2 JNZ NEXTINR2008 022009 20200A 3D NEXTDCR: DCR A Decrement A200B D3 OUT A0H200C A0200D FE CPI 00H200E 00200F C2 JNZ NEXTDCR2010 0A2011 202012 C2 JMP NEXT Jump to start again2013 002014 20
Question Bank
1. Draw complete interfacing diagram and discuss a scheme
for generation of ramp waveform using DAC IC 8255 PPI
and 8085
2. Draw timing diagram of OUT 20H instruction and explain it
in detail.
EXPERIMENT NO – 4
INTERFACING
THUMBWHEEL
SWITCH
THUMBWHEEL SWITCH INTERFACE USING PPI 8255
Program Statement:
To interface thumbwheel switch to 8085 through PPI 8255.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS VMC-
8501), Scratch Pad RAM used from 2000h to 2770h, Thumbwheel Switch Kit.
Memory Address Subroutine
0347h Clear Display
05D0h Character display
03BCh Delay
16h is the character code used to keep display blank; stored at memory
locations 2050 to 2054.
Learning Objective:
a) IN instruction.
b) Effect of XRA A instruction.
c) PPI 8255.
Logic:
Thumbwheel switch is interfaced to 8085 using PPI 8255. Each
time thumbwheel switch is rotated by one step corresponding BCD number is
read through PORT A by 8085 and that digit is displayed by using display
subroutine.
THUMBWHEEL SWITCH INTERFACE USING PPI 8255
Algorithm:
1. Initialize stack
2. Call clear subroutine stored at 0347H
3. Load accumulator with control word and out it on control word
register.
4. Clear accumulator and register B to enable address field of display.
5. Load HL pair with starting address of data for address field display.
6. Call output subroutine at 05D0H.
7. Copy contents of port A into accumulator.
8. Mask upper four bits.
9. Load HL pair with starting address of data for data field display.
10. Copy contents of accumulator in 2055H.
11. Load accumulator with 01H and register B with 00H to enable data
field display.
12. Call display subroutine.
13. Load DE pair with 0000H as counter required by delay routine.
14. Call delay at 03BCH.
15. Go to step 7.
THUMBWHEEL SWITCH INTERFACE USING PPI 8255
Initialize stack
Initialize 8255 ports
Clear register A and B
Initialize HL pair with 2050
Start
Copy data from Port A
Mask upper four bits
Load DE pair with count
Call Delay Subroutine
Call output display
subroutine
Call output display subroutine
Call clear subroutine
THUMBWHEEL SWITCH INTERFACE USING PPI 8255
MemoryAddress
OPCODE
Label Mnemonic Comment
2000 31 LXI SP,2100H Initialize stack2001 002002 212003 CD CALL CLEAR2004 472005 032006 3E MVI A,90H2007 902008 D3 OUT 03H2009 03200A AF UP: XRA A200B 47 MOV B,A200C 21 LXI H,2050H Memory pointer for
Character code200D 50200E 20200F CD CALL OUTPUT Output subroutine2010 D02011 052012 DB IN 00H2013 002014 E6 ANI OFH2015 0F2016 21 LXI H,2054H2017 542018 202019 32 STA 2055H201A 55201B 20201C 3E MVI A,01H Enable data field of
display201D 01201E 06 MVI B,00H Disable dot of
display201F 002020 CD CALL OUTPUT Output subroutine2021 D02022 052023 11 LXI D,0000H2024 002025 00
THUMBWHEEL SWITCH INTERFACE USING PPI 8255
MemoryAddress
OPCODE
Label Mnemonic Comment
2026 CD CALL DELAY Delay subroutine2027 BC2028 032029 C3 JMP UP Repeat again202A 0A202B 20
2050 16H2051 16H2052 16H2053 16H2054 16H2055 00H
Question Bank
1. Compare the execution of following instructions
a) MVI A, 00H
b) XRA A
c) SUB A
d) ANI 00H
2. Draw timing diagram of handshaking signals of 8255 in mode 1, input,
along with INTR, RD.
3. Give BSR control word and explain bi-directional mode of operation of
8255
EXPERIMENT NO – 8
ARRANGING BLOCK IN
DESCENDING
AND
ASCENDING
USING 8051
ARRANGING BLOCK OF DATA IN DESCENDING AND
ASCENDING ORDER
Program Statement:
Arrange given block of ten bytes in descending and
ascending order. Block is stored from location 30H.
Apparatus:
8031 based single chip Microcontroller kit (ANSHUMAN –
8031/V51), Scratch Pad RAM used from 6000h to 7FFFh, Power Supply.
Learning Objective:
1. How to use memory pointer?
2. Comparison between two numbers
3. Use of one of the sorting technique as Bubble sort
4. Using two counters nesting is done.
Logic:
For arranging block in descending order two memory
pointers are used. Both are pointing successive memory locations. First
pointers are pointing 30h and 31h both numbers are compared and larger
number is stored at location 30h and smaller at 31h.Both pointers are
incremented and counter is decremented. After comparing all numbers same
procedure is repeated for ten times for that second counter is used.
When second counter is decremented both pointers are
pointing again 30h and 31h and first counter is loaded with 09. Above steps
are repeated till second counter is zero. When second counter is zero block is
arranged in descending order. Two counters are used as first counter is for
comparison between two successive numbers and second for repeating the
comparison 9 times to arrange them in descending order.
ARRANGING BLOCK OF DATA IN DESCENDING ORDER
No
Yes
No
Yes
No
Yes
Counter1=0Ah
Pointer1=30hPointer2=31h
Is number pointed by pointer1 > pointer2 ?
Increment Pointers decrement counter2
Copy larger no. pointed by pointer1 smaller at pointed by pointer2
Is counter2
zero?
Decrement counter1
Is counter1
zero?
Counter2=09h
Start
Stop
ARRANGING BLOCK OF DATA IN ASCENDING ORDER
No
Yes
No
Yes
No
Yes
Counter1=0Ah
Pointer1=30hPointer2=31h
Is number pointed by pointer1 < pointer2 ?
Increment Pointers decrement counter2
Copy larger no. pointed by pointer1 smaller at pointed by pointer2
Is counter2
zero?
Decrement counter1
Is counter1
zero?
Counter2=09h
Start
Stop
ARRANGING BLOCK IN DESCENDING ORDER
MemoryAddress
OPCODE
LableMnemonic And
OperandComment
6000 7A MOV R2, #0AH ;Load counter16001 0A6002 7B PASS2: MOV R3, #09H ;Load counter26003 096004 78 MOV R0, #30H ;Initialize Pointer16005 306006 79 MOV R1, #31H ;Initialize Pointer26007 316008 E6 PASS: MOV A, @R06009 87 MOV 40H, @R1600A 40600B B5 CJNE A, 40H,NEXT ;Compare values
Pointed by pointers
600C 40600D 02600E 80 SJMP LOOP600F 046010 50 NEXT: JNC LOOP6011 026012 C7 XCH A, @R16013 F6 MOV @R0, A6014 08 LOOP: INC R06015 09 INC R16016 DB DJNZ R3, PASS6017 F06018 BA DJNZ R2, PASS26019 E8601A 80 HERE: SJMP HERE601B FE
ARRANGING BLOCK IN ASCENDING ORDER
MemoryAddress
OPCODE
LableMnemonic And
OperandComment
6000 7A MOV R2, #0AH ;Load counter16001 0A6002 7B PASS2: MOV R3, #09H ;Load counter26003 096004 78 MOV R0, #30H ;Initialize Pointer16005 306006 79 MOV R1, #31H ;Initialize Pointer26007 316008 E6 PASS: MOV A, @R06009 87 MOV 40H, @R1600A 40600B B5 CJNE A, 40H,NEXT ;Compare values
Pointed by pointers
600C 40600D 02600E 80 SJMP LOOP600F 046010 50 NEXT: JC LOOP6011 026012 C7 XCH A, @R16013 F6 MOV @R0, A6014 08 LOOP: INC R06015 09 INC R16016 DB DJNZ R3, PASS6017 F06018 BA DJNZ R2, PASS26019 E8601A 80 HERE: SJMP HERE601B FE
Result: Ascending and Descending
Input Block: Output Block:
Input Block: Output Block:
MemoryAddress
Data
30 0131 0332 0533 0634 0735 0836 0A37 0B38 0D39 0F
MemoryAddress
Data
30 0A31 0532 0F33 0634 0135 0B36 0D37 0838 0339 07
MemoryAddress
Data
30 0F31 0D32 0B33 0A34 0835 0736 0637 0538 0339 01
MemoryAddress
Data
30 0A31 0532 0F33 0634 0135 0B36 0D37 0838 0339 07
Question Bank
1. Why two pointers are required in this program?
2. How numbers are arranged in descending order?
3. Explain following instructions:
a) CJNE A, #data, relative address
b) DJNZ R1, relative address
c) XCH A, @R1
4. Which registers are allowed to be used for register indirect
addressing mode when accessing data in RAM?
EXPERIMENT NO – 8
SQUARE WAVE
GENERATION
USING TIMER
OF 8051
SQUARE WAVE GENERATION USING TIMER OF 8051
Program Statement:
Generation of square wave using timer of 8051.
Apparatus:
8031 based single chip Microcontroller kit (ANSHUMAN –8031/
V51), Scratch Pad RAM used from 6000h to 7FFFh, Cathode Ray
Oscilloscope, Power Supply.
Learning Objective:
1. Timers of 8051
2. Working of timer of 8051
3. Generation of square using timer of 8051
4. Calculating count to be loaded in timer register
5. Role of overflow flag in timer
6. Generating delay using timer
Logic:
For generating square wave port pin P1.1 is used. P1.1 is high
for delay period generated by timer and low for the same delay period.
TIMER0 in MODE1 is used. Count value is loaded in TH0 and
TL0. Count value is calculated according to the frequency of square wave to
be generated. P1.1 is made high. Timer is started and overflow flag is
checked. When timer will roll over from FFFFH to 0000H overflow flag will be
set. When overflow flag is set; P1.1 is complemented. Then stop the timer and
procedure is repeated for continuous generation of square wave. As delay is
same for high and low period square wave is having 50% duty cycle.
Algorithm:
1. Initialize timer and mode of timer.
2. Make P1.1 high
3. Load count value in THx and TLx
4. Start timer
5. Check overflow flag
6. When overflow flag is set complement P1.1
7. Clear overflow flag
8. Stop timer
9. For continuous display of square wave go to step 3
SQUARE WAVE GENERATION USING TIMER OF 8051
No
Yes
Initialize timer and mode
Make P1.1 high
Load count value
Start timer
Is overflow
flag set?
Complement P1.1
Clear overflow flag
Stop Timer
Start
SQUARE WAVE GENERATION USING TIMER OF 8051
MemoryAddress
OPCODE
LableMnemonic And
OperandComment
6000 75 MOV TMOD, #01H ;Initialize mode and timer6001 89
6002 016003 D2 SETB P1.16004 916005 75 UP: MOV TL0, #0FDH ;TL0 count6006 8A6007 FD6008 75 MOV TH0, #0FFH ;TH0 count6009 8C600A FF600B D2 SETB TR0 ;Start timer600C 8C600D 30 LOOP: JNB TF0, LOOP ;Check overflow flag600E 8D600F FD6010 B2 CPL P1.16011 916012 C2 CLR TF06013 8D6014 C2 CLR TR0 ;Stop timer6015 8C6016 80 SJMP UP ;For continuous
wave6017 ED
Question Bank
1. How many timers do 8051 have?
2. How timer is initialized?
3. How count value, which is to be loaded in timer is calculated?
4. What is the use of overflow flag?
5. What is role of timer in serial communication?
6. Explain TMOD register.
7. Write assembly language program to generate square wave of
1KHz at P1.0 (bit 0 at port 1).
8. What bit addresses are assigned to TCON register?
EXPERIMENT NO – 6
INTERFACING OF
DOT MATRIX
DISPLAY USING
8051
INTERFACING OF DOT MATRIX DISPLAY USING
8051
Program Statement:
Interfacing of 5 x 7 dot matrix display.
Apparatus:
8031 based single chip Microcontroller kit (ANSHUMAN – 8031/
V51), Scratch Pad RAM used from 6000h to 7FFFh, Dot Matrix Kit, Power
Supply.
Learning Objective:
1. How to display number on matrix display?
2. How to use single bit of port?
3. Calling subroutine from different memory page.
Logic:
For interfacing of 5x7 dot matrix display port 1 and port 3 are
used. Seven rows as R1 to R7 are interfaced with port 1 from P1.0 to P1.6.
Pin P1.7 is used for column 5. Four columns are interfaced using port 3 as C1
using P3.1, C2 using P3.3, C3 using P3.4 and C4 using P3.5.
For displaying character rows and columns are enabled accordingly.
By making port pins low of port 1 rows are enabled. And by making port pins of port
3 high columns are enabled. According to data to be displayed on matrix display,
rows and columns are enabled and delay is called.
Algorithm:
1. Make display blank by disabling all rows and columns.
2. Enable all rows and C3
3. Call delay
4. Disable all rows and C3
5. Enable all columns and R7.
6. Call delay
7. Disable all columns and R7
8. Enable R3 and C1
9. Call delay
10.Disable R3 and C1
11.Enable R2 and C2
12.Call delay
13.Disable R2 and C2
14.For continuous display go to step2.
INTERFACING OF DOT MATRIX DISPLAY USING 8051
Make display blank
Enable all rows and C3
Call delay
Disable all rows and C3
Enable all columnsand R7
Call delay
Disable all columns and R7
Enable R3 and C1
Call display
Disable R3 and C1
Enable R2 and C2
Disable R2 and C2
Start
Call delay
INTERFACING OF DOT MATRIX DISPLAY USING 8051
MemoryAddress
OPCODE
LableMnemonic And
OperandComment
6000 75 MOV SP, #50H ;Initialize stack6001 816002 506003 75 MOV P1, #7FH ;Blank Display6004 906005 7F6006 75 MOV P3, #00H ;Blank Display6007 B06008 006009 75 UP: MOV P1, #00H ;Enable all rows600A 90600B 00600C D2 SETB P3.4 ;Enable column C3600D B4600E 12 LCALL DELAY600F 606010 406011 C2 CLR P3.4 ;Disable column C36012 B46013 75 MOV P1, #7FH ;Disable all rows6014 906015 7F6016 75 MOV P3, #0FFH ;Enable all columns6017 B06018 FF6019 D2 SETB P1.7 ;Enable C5601A 97601B C2 CLR P1.6 ;Enable R7601C 96601D 12 LCALL DELAY601E 60601F 406020 C2 CLR P1.7 ;Disable C56021 976022 D2 SETB P1.6 ;Disable R76023 966024 75 MOV P3, #00H ;Disable all columns6025 B06026 506027 C2 CLR P1.2 ;Enable R36028 92
Continued……….
INTERFACING OF DOT MATRIX DISPLAY USING 8051
MemoryAddress
OPCODE
LableMnemonic And
OperandComment
6029 D2 SETB P3.1 ;Enable C1602A B1602B 12 LCALL DELAY602C 60602D 40602E D2 SETB P1.2 ;Disable R2602F 926030 C2 CLR P3.1 ;Disable C16031 B16032 C2 CLR P1.1 ;Enable R26033 916034 D2 SETB P3.3 ;Enable C26035 B36036 12 LCALL DELAY6037 606038 406039 D2 SETB P1.1 ;Disable R2603A 91603B C2 CLR P3.3 ;Disable C2603C B3603D 02 LJMP UP603E 60603F 09
6040 76 DELAY: MOV R0, #0FFH ;Initialize counter6041 FF6042 D8 HERE: DJNZ R0, HERE ;Decrement counter if
not zero go to HERE6043 FE6044 22 RET
Question Bank
1. How a port can be made input port?
2. Give memory organization of 8051 family.
3. How an element on matrix display can be made on?
4. Explain the difference between LJMP and SJMP.
5.How to calculate the relative address for forward and backward
jump?
6. What bit addresses are assigned to P3?