7/31/2019 1st Evolution(1)
1/23
7/31/2019 1st Evolution(1)
2/23
7/31/2019 1st Evolution(1)
3/23
7/31/2019 1st Evolution(1)
4/23
First Evolution Task
7/31/2019 1st Evolution(1)
5/23
FPGA Altera Kit
7/31/2019 1st Evolution(1)
6/23
Hardware is provided By DE2-115 board
The following : USB Blaster (on board) for programming; both JTAG and Active
Serial (AS) programming modes are supported 2MB SRAM Two 64MB SDRAM 8MB Flash memory SD Card socket 4 Push-buttons 18 Slide switches 18 Red user LEDs 9 Green user LEDs 50MHz oscillator for clock sources 24-bit CD-quality audio CODEC with line-in, line-out, VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
2 Gigabit Ethernet PHY with RJ45 connectors USB Host/Slave Controller with USB type A and type B connectors RS-232 transceiver and 9-pin connector PS/2 mouse/keyboard connector IR Receiver 2 SMA connectors for external clock input/output
7/31/2019 1st Evolution(1)
7/23
TV Decoder
The DE2-115 board is equipped with an Analog Device ADV7180TV decoder chip.The ADV7180 is an integrated video decoder that automaticallydetects and converts a standard analog base band televisionsignals (NTSC, PAL, and SECAM) into 4:2:2 component video data compatible with the 8-bit ITU-R
BT.656 interface standard.The ADV7180 is compatible with a broad range of video devices,including DVD players, tape-based sources, broadcast sources, andsecurity/surveillance cameras.
7/31/2019 1st Evolution(1)
8/23
Connections between FPGA and TV Decoder
7/31/2019 1st Evolution(1)
9/23
Implementing a TV Encoder
Although the DE2-115 board does not includea TV encoder chip, the ADV7123 (10-bit high-speed triple ADCs) can be used to implement
a professional-quality TV encoder with thedigital processing part implemented in theCyclone IV E FPGA
7/31/2019 1st Evolution(1)
10/23
A TV Encoder that uses the Cyclone IV E FPGA
and the ADV7123
7/31/2019 1st Evolution(1)
11/23
TV decoderADV7180
VGA DACADV7123
ITU_R656Decoder
LockedDetector
I2c
SDRAMframe buffer
MUX
YUV4:2:2to
YUV4:4:4
control
VGAcontroller
Ycbcrto
RGB
TD_Data
TD_HS
TD_VS
I2c_SCLK
I2c_SDAT
YUV4:2:2
VYU422
it
RGB
VGA_HS
VGA_VS
7/31/2019 1st Evolution(1)
12/23
Block diagram of the TV box demonstration
7/31/2019 1st Evolution(1)
13/23
Introduction Tv Decoder ADV7180
ITU_R 656 Decoder
I2c_V Config YUV4:2:2_ to_ YUV4:4:4
Ycbcr _to _RGB
VGA Controller LCD Display
Refrences
7/31/2019 1st Evolution(1)
14/23
7/31/2019 1st Evolution(1)
15/23
Convert analog signal into worldwidestanders(NTS,PAL etc)
Convert worldwide standers into 4:2:2
video components
Output signals synchronous
Programmed by 2wires serial
Bidirectioal port
7/31/2019 1st Evolution(1)
16/23
It describes how to embed video timinginformation in the 4:2:2 bit parallelsampling scheme of the Ycrcb color space
definition.
7/31/2019 1st Evolution(1)
17/23
Used for communication b/w FPGA coreand tv decoder ADV7180
I2c clock
I2c SData
7/31/2019 1st Evolution(1)
18/23
7/31/2019 1st Evolution(1)
19/23
7/31/2019 1st Evolution(1)
20/23
Horizontal sync: digital signal, used forsynchronisation of the video
Vertical sync: digital signal, used for
synchronisation of the video Red (R): analog signal (0-0.7 v), used to
control the color
Green (G): analog signal (0-0.7 v), used tocontrol the color
Blue (B): analog signal (0-0.7 v), used tocontrol the color
7/31/2019 1st Evolution(1)
21/23
Video display on LCD by VGA DACADV7123.
7/31/2019 1st Evolution(1)
22/23
7/31/2019 1st Evolution(1)
23/23