Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
Hybrid
• Configuration via SPECS on VELO Control Board -> I2C– 4 hybrids, each:
• 16 Beetles, each:– 18 Bytes registers– 2 X 16 Byte registers– 128 Bytes comparator thresholds
• Total: ~ 11k Byte• Configuration time: seconds• FSM: Trigger & DAQ Domain• PVSS software by VELO group
– Maybe small modifications for comparator specific registers
Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
Optical station
• Configuration via SPECS on VELO control board -> I2C
• 8 optical boards, each:– 12 GOL, each:
• 5 Byte config/stat registers– 3 FPGA Sync/Mux logic, each:
• EEPROM based (not configurable via ECS)• 32 Byte data sync registers• 12 bit Bcid offset• 16 Byte conf,status,SEU & debug registers
• Total: ~ 2k Bytes• Configuration time: < 1second• FSM: Trigger & Daq Domain• PVSS Software by Pile-Up group
Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
VEPROB
• Configuration via CCPC -> I2C/Local bus/JTAG
• 4 Vertex processor boards, each:– 20 Byte TTCrx registers– 32 Mbit FPGA conf (per det. pos.)– 4 events X 2kbit testpatterns– 16 Byte control/debug/status registers– 24 Byte link status registers– 2 X 1 Byte threshold registers
• Total: 1272 Bytes (registers & debug RAM)• Total: 16MByte (FPGA configuration)• FPGA configuration time: many seconds (tbd)• Register Configuration time: < 1 second• FSM: Trigger & DAQ Domain• PVSS software by Pile-Up group
TTCrq
CCPCGluecard
ORC-card
ORC-card
Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
Output Board
• Configuration via CCPC -> Local bus / JTAG– 16 Mbit FPGA Configuration
– 16 Byte Control status & debug registers
– 80 kByte Histograms• Readout via CCPC into PVSS ??
• Total: ~ 80kByte register & histogram RAM• Total: 16 Mbit FPGA configuration• Register/RAM Configuration time: < 1 second• FPGA Configuration time: many seconds (tbd)• FSM: Trigger & DAQ Domain• PVSS software by Pile-Up group
Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
Velo Control Board
• 3 VELO control boards used in Pile-Up– 2 VCB for 8 Optical tx Boards– 1 VCB for 4 hybrids
• Per control board– FPGA configuration EEPROM based (not configurable via ECS?)– TTCrx settings
• 20 Bytes Clock delay– 6 Delay25 chips
• 6 Bytes each– SPECS Slave
• ? Bytes– FPGA control registers
• ? Bytes– Hybrid temperature monitoring
• ? Bytes• PVSS software by VELO group
Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
TELL1
• Analog TELL1– Identical to VELO– PVSS software by VELO ?
• Optical TELL1– Pile-Up specific– PVSS software:
• Based on other TELL1 PVSS software• Modifications by Pile-Up group
Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
FSM: Other domains
• DAQ & trigger infrastructure– Power Supply of processor crate
• Standard LHCb crate (standard software?)
– PS of optical station crate• Maraton supply (standard software?)
– PS of hybrids• Identical to VELO hybrid PS (copy of VELO software)
• Detector infrastructure domain– Temperature sensors on hybrid/repeater cards
• Identical to VELO
• HV domain– Bias of silicon sensors
• Identical to VELO
Wilco Vink / Martin van Beuzekom / L. Wiggers11/01/2006
Histogram # bins per histogram
type of storage
peak 1 position 256 bins / bx-type 4*256 memory locations
peak 1 contents 256 bins / bx-type 4*256 memory locations
peak 2 position 256 bins / bx-type 4*256 memory locations
peak 2 contents 256 bins / bx-type 4*256 memory locations
# vertices / BCID 4 bins / BCID 3564*4 memory locations
# vertices / bx-type
4 bins / bx-type 4*4 hardwired counters
# hits (multiplicity) 256 bins / bx-type 4*256 memory locations
error conditions 1616 memory locations / counters