1
Electronics for RICH DetectorsVeljko Radeka, BNLRICH 2004 Workshop
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
2
Acknowledgements:
• Gianluigi De Geronimo
• Paul O’Connor
• Sergio Rescia
• Pavel Rehak
• Craig Woody
• Bo Yu
… my BNL colleagues.
3
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
4
CMOS Technology Roadmap
Year 1991
1993 1995 1997 1999 2001 2004 2008
Min. feature size [nm]
800 500 350 250 180 130 90 60
Oxide thickness [nm]
16 11 7.7 5.5 4 2.7 2.2 1.8
Power supply [V] 5 5/3.3 3.3 2.5 1.8 1.5 1.2 0.9
Threshold voltage [V]
0.7 0.65 0.6 0.5 0.38 0.28 0.22 0.17
Cutoff frequency [GHz]
12 19 28 40 65 75 100 165
• Driven by digital VLSI circuit needs• Goals: in each generation
– 2X increase in density– 1.5X increase in speed
5
CMOS scaling:
10
100
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
Vo
lts
kT
/q
Supply voltage
Threshold voltage
10
100
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
Vo
lts
kT
/q
Supply voltage
Threshold voltage
0
5
10
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
t ox/d
Si
0
5
10
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
t ox/d
Si
Oxide Thickness:
6
Threshold mismatch due to discrete dopant distribution
0
500
1000
0.25 0.18 0.15 0.13 0.1 0.07
Lmin, m
Do
pa
nt
ato
ms
pe
r M
OS
FE
T
0
500
1000
0.25 0.18 0.15 0.13 0.1 0.07
Lmin, m
Do
pa
nt
ato
ms
pe
r M
OS
FE
TVT
3D p-MOSFET simulation with stochastically placed dopants
D.J. Frank, IBM J. Res. Dev. 46, 235-244, Mar./May 2002
7
But: Gate tunneling current !!!
• Gate current expected to increase 100
– 200 x per generation below 0.18 mm
• Jox ~ 100 A/cm2 projected for Lmin = 0.1
mm generation with nitrided SiO2
• Considered tolerable for digital circuits
(total gate area per chip ~ 0.1 cm2)
• Typical CSA input FET would have
IG ~ 1 - 10 µA; ENCp ~ 2000 - 7000
rms e- at 1 µsec
• Good for radiation resistance – bad
for ENC.
SiO2 gate leakage current (Lo et al., Electron Dev. Letters 1997)
8 LHC Boston Sept 04 PA
FPGAs - Thirteen Years of ProgressFPGAs - Thirteen Years of Progress
200x More Logicplus memory, µP,
DSP, MGT
40x Faster
50x Lower Powerper function x MHz
500x Lower Costper function
CLB CapacitySpeedPower per MHzPriceITRS Roadmap
Virtex &Virtex-E
XC4000
100x
10x
1x
Spartan-2
1000x
Virtex-II &Virtex-II Pro
Virtex-4
XC4000 &Spartan
Spartan-3
'91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04
Year
P. Alfke
9 LHC Boston Sept 04 PA
Higher Leakage Current…Higher Leakage Current…High Leakage current = static power consumption
Was <100 microamps, now > 100 mA, even amps (!)
Caused by:Gate leakage due to 16 Å gate thicknessSub-threshold leakage current incomplete turn-off because threshold does not scale
Tyranny of numbers:10 nA x 100 million transistors = 1 A
evenly distributed, thus no reliability problem
Sub-100 nm is not ideal for portable designs
P. Alfke
10 LHC Boston Sept 04 PA
VLSI ASIC Costs ….VLSI ASIC Costs ….Mask set >$1M + design + verification + risk
0
0.5
1
1.5
2
250 nm 180 nm 130 nm 90 nm 65 nm
Technology Generation
Ma
sk
Co
sts
(in
mil
lio
n $
)
0
0.5
1
1.5
2
250 nm 180 nm 130 nm 90 nm 65 nm
Technology Generation
Ma
sk
Co
sts
(in
mil
lio
n $
)
Source:IBM
P. Alfke
11
Multiproject foundry services
• Combine designs from many institutions on one maskset
• Arrange for regular runs with a variety of popular foundries
• Design support
• Models• Design rules
– Process monitoring• Amortize cost of run over many
users
Custom monolithics: technology access
multiproject wafer
12
Front-End Electronics – Preamplifier PowerFront-End Electronics – Preamplifier Power
32-channel ASIC - layout is pad-limited 3 x 3 mm² power / channel 1mW (preamplifier < 200µW) energy resolution < 250 rms electrons (600ns peaking time, 5pF)
32-channel ASIC - layout is pad-limited 3 x 3 mm² power / channel 1mW (preamplifier < 200µW) energy resolution < 250 rms electrons (600ns peaking time, 5pF)
0.01 0.1 1100
200
300
400 TECHNOLOGY SUPPLY COST/RUN
0.35µm 3.3V 14k$ 0.25µm 2.5V 19k$ 0.18µm 1.8V 32k$
Ene
rgy
Res
olut
ion
[EN
C]
Preamplifier Power [mW]
13
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
14
15
Single Electron Detection and Timing vs Avalanche Gain Gav
Detection (Yes/No): Gav ≥ ~ 10 ENC/qe
“Common” Timing: Gav ≥ (ENC/qe) (tp/σt) ; tp = peaking time after shaping > signal current width
Optimum timing:
----------------------------------------
1. Coarse timing: ~ 1 – 2 ns , for tp = 20ns → Gav ≥ 10 ENC/qe
= 100 ns → ≥ 50 ENC/qe
2. Precision timing: ~ 100 – 200 ps , for tp = 20 ns → Gav ≥ 100 ENC/qe
ENC = ?(Note: Optimum filter for timing is different from opt. filter for charge measurement)
16Power Pd is in input leg only. Add minimum 30µW for signal processingPower Pd is in input leg only. Add minimum 30µW for signal processing
10-14
10-13
10-12
10-11
10
100
1000
Pd=1mW
Pd=100µW
Pd=10µW
TSMC 0.25µmP-MOS, T
p=20ns
EN
Co
pt [
r.m
.s. e
lect
rons
]
Input capacitance Cin [F]
Optimum ENC vs Input CapacitanceOptimum ENC vs Input Capacitance
10 pF10 fF
17Power Pd is in input leg only. Add minimum 30µW for signal processingPower Pd is in input leg only. Add minimum 30µW for signal processing
10-14
10-13
10-12
10-11
1
10
100
1000
Pd=1mW
Pd=100µW
Pd=10µW
TSMC 0.25µmP-MOS, T
p=200ns
E
NC
op
t [r.
m.s
. ele
ctro
ns]
Input capacitance Cin [F]
Optimum ENC vs Input CapacitanceOptimum ENC vs Input Capacitance
10 pF10 fF
18
“Why is the detector capacitance so important in determining the noise performance?”
It is illustrative to express the noise performance in terms of signal and noise “energy” on the detector capacitance. From matched filter theory and the well known relations for ENC:
=transistor carrier transit time ≈ Cgs/gm ; tm= integration time ; Kf is the 1/f noise constant [Joules]; kB= Boltzmann constant.
Numerical (dimensionless) constants aw , a1/f , contain capacitance matching constraints (Cd/Cgs ratio), weighting function shape parameters, but are independent of the transistor width.
Amplifier noise energy referred to the detector capacitance is independent of the detector capacitance. The signal energy is inversely proportional to the detector capacitance. (Cd here includes stray capacitances.)
For a “gut feeling”: Charge at higher potential energy is easier to detect – 1 electron on 1 atofarad (quantum dot) is readily detectable – while not so at higher capacitances.
2 2
2
1
2 1
2 1
w B e m
f f
d
d
d
d
e
S SignalEnergy Q
N NoiseEnergy a k T t
Q
a K
CC
CC
2 2
2
1
2 1
2 1
w B e m
f f
d
d
d
d
e
S SignalEnergy Q
N NoiseEnergy a k T t
Q
a K
CC
CC
for white series noise
for 1/f series noise
VR 06/17/04
19
Pixel density – detector trends
STAR TPC
PHX MVD
PHX PAD
M'pix2
EXAFS
PET
XAMPS1
barcode
LHC pixels
MAPS
LSST
DEPFET2DEPFET1
gamma cam
1E-2
1E-1
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E-1
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1998 2000 2002 2004 2006 2008 2010
Doubling every 5 monthsDoubling every 5 months
Year
pix
els
/cm
2
20
Power density
• On-detector power density is limited by cooling capability.
• Electronics for high-density detector must be extremely low power.
21
Silicon sensor (for EXAFS spectroscopy)• 384 pixels
• 1 x 1 x 0.25 mm Si pad detector
• rate > 10 MHz/cm2
• 8.2 mW/chan
• FWHM < 300eV, noise < 28 e-
• preamps + digital integrated on-chip
sample
sensor
G. De Geronimo et al., Proc. PIXEL2002 International Workshop, Carmel, CA, 2002
22
Optimized noise vs. power
ln0.4
ln
d N
d P
(MOSFET optimized at each power level and shaping time)
Note:
4.0dP
dN
Cd = 1pF0.25 µm CMOS
10
100
1000
10 100 1000 10000
Power (W)
No
ise
(rm
s e-
)
10 ns
30
100
300
1000
3000
Shapingtime:
G. DE Geronimo, P. O`Connor
23
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
24
Detector – FE interconnect choices• board-to-backplane
– easy to test, repair– large boards possible– connector pins are failure points– coarse pitch and high capacitance (> 1pF)
• standard SMT package soldered to board (QFP or BGA)– easy to test, difficult to repair– capacitance down to 0.2 pF for small packages– board area limited by reflow oven capacity
• wirebonded chip-on-board– difficult to test, assemble, and repair– board area limited by wirebonder– fragile– low capacitance (0.1 pF)
• bump-bonded flip-chip– can match pixels with pitch from ~30 – 1000
m– difficult to test, assemble, and repair– circuitry has to fit in same area as pixel
• monolithic detector/electronics– interconnect is created as part of the detector
fabrication process– ultra-low capacitance (few fF)
25
Interpolating Pad Readout for GEM (Gas Electron Multiplier)
Window
Anode Pad Plane
Upper GEM
Lower GEM
<100µm rms position resolution with 2mm pad pitch
26
Time Projection Chamber (TPC) – (for Laser Electron Gamma Source) Time Projection Chamber (TPC) – (for Laser Electron Gamma Source)
Spin ASYmmetry Array (SASY)
TPC Can double-GEM planes
anode pad planeelectronics per pad
~ 8000 channels
anode pad planeelectronics per pad
~ 8000 channels
HV mesh plane and UV window forlaser calibration
27
Board layout for a TPC – GEM anode plane.
32 channels per ASIC.
~ 8000 channels →
~ 10 watts on 35 cm dia plane
28
Board layout for a TPC – GEM anode
plane.
ASICS
GEM foils
Blind vias
29
ASIC LayoutASIC Layout
TSMC 0.25µm 32 channels 3.1 x 3.6 mm² (~0.35 mm2/channel) 47k MOSFETs 43mW QFN package (56)
TSMC 0.25µm 32 channels 3.1 x 3.6 mm² (~0.35 mm2/channel) 47k MOSFETs 43mW QFN package (56)
buffer
channel
logicbias
30
ASIC Readout Channel - Block DiagramASIC Readout Channel - Block Diagram
continuous reset
INPUT n-MOSFET• optimized for operating region• ENC<250 rms electrons• NIM A480, p.713
CONTINUOUS RESET• feedback MOSFET• self adaptive• low noise• fully compensated• US patent 5,793,254• NIM A421, p.322• TNS 47, p.1458
INPUT n-MOSFET• optimized for operating region• ENC<250 rms electrons• NIM A480, p.713
CONTINUOUS RESET• feedback MOSFET• self adaptive• low noise• fully compensated• US patent 5,793,254• NIM A421, p.322• TNS 47, p.1458
350 µW
mux1 PD
peak detector
threshold
PEAK DETECTOR• two-phase configuration• offset error cancellation• high absolute accuracy < 0.2%• US patent 6,512,399• NIM A484, p.544
TIMING DETECTOR• time-to-amplitude converter • internal or external ramp• two-phase configuration• timing resolution < 20ns rms
PEAK DETECTOR• two-phase configuration• offset error cancellation• high absolute accuracy < 0.2%• US patent 6,512,399• NIM A484, p.544
TIMING DETECTOR• time-to-amplitude converter • internal or external ramp• two-phase configuration• timing resolution < 20ns rms
timing detector
neighbors
mux2 TDramp
flag
900 µW
baseline stabilizer
SHAPER• amplifier with passive feedback• dual stage multiple feedback • 2nd order, 600ns peaking time• adjustable channel gain (3-bit)
BASELINE STABILIZER (BLH)
• band-gap referenced• low-frequency feedback• slew-rate limited follower• high dc stability < 1mV• low channel dispersion < 4mV• TNS 47, p.818
SHAPER• amplifier with passive feedback• dual stage multiple feedback • 2nd order, 600ns peaking time• adjustable channel gain (3-bit)
BASELINE STABILIZER (BLH)
• band-gap referenced• low-frequency feedback• slew-rate limited follower• high dc stability < 1mV• low channel dispersion < 4mV• TNS 47, p.818
2nd ordershaper
31
32
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
33
GEM Readout of the GEM Readout of the HBDHBD
Prototype HBD detector
• Triple GEM - can be made insensitive to charged particles - minimizes photon feedback and ion backflow
• Modest gain (~ 5 x 103)
• CsI photocathode deposited on top surface of uppermost GEM foil
• CF4 used as working gas and Cherenkov radiator - can achieve high gain and good transmission down into deep VUV ( large N0)
34
Readout Board and PreampsReadout Board and Preamps
Hybrid Preampswith line drivers
~ ¾”honeycomb
Read pads ~ 3x3 cm2
Preamp signals to shaper + ADC
wires
GEMs
• Being developed by BNL Instrumentation
• Based on IO-535
•± input signal
•± 2.5 V output
• Need almost one full rack for the readout electronics
35
The HBD DetectorThe HBD Detector
Dilepton pairBeam Pipe
HBD Gas Volume: Filled with CF4 Radiator (nCF4=1.000620, LRADIATOR = 50 cm)
Cherenkov forms “blobs” on an image plane(max = cos-1(1/n)~36 mrad rBLOB~3.6cm)
Triple GEM detectors (8 panels per side)
Space allocated for services
Windowless Cherenkov DetectorRadiator gas = Working Gas
Electron pairs produce Cherenkov light, but hadrons with P < 4 GeV/c do notProximity focused
Coarse granularity readout (~ 2x2 cm2)
5 cm
55 cme-
e+
Pair Opening
Angle
36
Low-Noise preamplifier – thick film ceramic hybrid
• single channel
• 29 components
• 44 solder joints
• 8 connections to PCB
• 20 x 14 x 2.5 mm
37
Highly segmented detectors
Benefits:• Position Resolution
– pixel pitch ~ 1/N• Energy resolution (ENC)
– CDET ~ 1/N– IDARK ~ 1/N– pulse shaping time ~ N
• Rate capability– pileup ~ 1/N
• “Small pixel” effect– improve energy resolution in
semiconductor detectors with poor hole transport
Benefits:• Position Resolution
– pixel pitch ~ 1/N• Energy resolution (ENC)
– CDET ~ 1/N– IDARK ~ 1/N– pulse shaping time ~ N
• Rate capability– pileup ~ 1/N
• “Small pixel” effect– improve energy resolution in
semiconductor detectors with poor hole transport
N=1 N=9 N=25 N=49
Drawbacks:• Interconnect density ~ N
→ bump bonding; BGAs
• Electronics channel count ~ N
But these are not “old channels”!
• Power/channel ~1/N
Noise is reduced more due to lower C, than increased due to lower power.
Drawbacks:• Interconnect density ~ N
→ bump bonding; BGAs
• Electronics channel count ~ N
But these are not “old channels”!
• Power/channel ~1/N
Noise is reduced more due to lower C, than increased due to lower power.
38
39
Concluding remarks:• Microelectronics technology allows us to take advantage of fine electrode segmentation
• This leads to lower noise and lower avalanche gain
• Tough luck to very large electrode pads – not well matched to microelectronics
• Detector, detector electrodes, interconnections and the ASIC are all constituents of an interactive design.
• Scaling of digital electronics (powerful FPGAs) allows real time processing close to or on detector
40
ASIC Designer vs the Rest of the Collaboration