Republic of Korea

gene therapy in vitro and in vivo.

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Zero-static-power nonvolatile logic-in-memory circuits

for flexible electronics

Byung Chul Jang1, Sang Yoon Yang1, Hyejeong Seong2, Sung Kyu Kim3, Junhwan Choi2, Sung Gap

Im2, and Sung-Yool Choi1 ()

Nano Res., Just Accepted Manuscript • DOI: 10.1007/s12274-017-1449-y

http://www.thenanoresearch.com on Jan. 03, 2017

© Tsinghua University Press 2016

Just Accepted

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Nano Research

DOI 10.1007/s12274-017-1449-y

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TABLE OF CONTENTS (TOC)

Zero-Static-Power Nonvolatile Logic-in-Memory

Circuits for Flexible Electronics

Byung Chul Jang1, Sang Yoon Yang1, Hyejeong

Seong2, Sung Kyu Kim3, Junhwan Choi2, Sung Gap Im2,

and Sung-Yool Choi1,*

1School of Electrical Engineering, Graphene/2D

Materials Research Center, Korea Advanced Institute of

Science and Technology (KAIST), Daejeon 34141, Korea

2Department of Chemical and Biomolecular

Engineering, Graphene/2D Materials Research Center,

Korea Advanced Institute of Science and Technology

(KAIST), Daejeon 34141, Korea

3Department of Materials Science and Engineering, Korea

Advanced Institute of Science and Technology (KAIST),

Daejeon 34141, Korea

Flexible nonvolatile logic-in-memory circuit enabling

normally-off-computing can be implemented using pV3D3-memristor

array. For the first time, we experimentally demonstrate our

implementation of MAGIC-NOT and -NOR gates during multiple

cycles and even under bent conditions. Other functions, such as OR,

AND, NAND, and a half adder, are also realized within crossbar array.

Author 1, http://mndl.kaist.ac.kr

Author 2, http://ftfl.kaist.ac.kr

Author 3, http://hrtem.kaist.ac.kr

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Zero-Static-Power Nonvolatile Logic-in-Memory Circuits for Flexible Electronics

Byung Chul Jang1, Sang Yoon Yang

1, Hyejeong Seong

2, Sung Kyu Kim

3, Junhwan Choi

2, Sung Gap Im

2, and

Sung-Yool Choi1 ()

1School of Electrical Engineering, Graphene/2D Materials Research Center, Korea Advanced Institute of Science and Technology

(KAIST), Daejeon 34141, Korea

2Department of Chemical and Biomolecular Engineering, Graphene/2D Materials Research Center, Korea Advanced Institute of

Science and Technology (KAIST), Daejeon 34141, Korea

3Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon

34141, Korea

Received: day month year / Revised: day month year / Accepted: day month year (automatically inserted by the publisher)

© Tsinghua University Press and Springer-Verlag Berlin Heidelberg 2011

ABSTRACT

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we demonstrate that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-memristor array. Albeit memristive logic-in-memory circuits have been previously reported, the requirements of additional components and large variation of memristors have limited demonstrations to simple gates within a few operation cycles on only rigid substrate. Using memristor-aided logic (MAGIC) architecture requiring only memristors and pV3D3-memristor with good uniformity on flexible substrate, for the first time, we experimentally demonstrate our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within crossbar array. This research advances the development of novel

Nano Res DOI (automatically inserted by the publisher)

Research Article

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computing architecture with zero static power consumption for battery-power flexible electronic systems.

KEYWORDS

memristor, memristive logic circuit, flexible nonvolatile logic-in-memory circuit, normally-off-computing,

memristor-aided logic (MAGIC) architecture

————————————

Address correspondence to Sung-Yool Choi, sungyool.choi@kaist.ac.kr

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1. Introduction

Flexible electronics with a stylish form factor, such

as smart bands, curved TV, and so on, are now

integrated in our daily lives. For realization of

multifunctional flexible electronic systems, various

electronic devices, such as logic gates, circuits,

memory, sensors, radio frequency identification

(RFID), and actuators have been developed onto a

flexible platform [1-5]. In particular, developments

for flexible logic and memory devices are essential

on account of their roles of information processing,

storage, and communication with external devices.

Furthermore, it is necessary to develop

battery-powered flexible devices with ultra-low

static power dissipation of approximately 5 nW (Pstatic

= VLowest,DD IDeep suspend) based on the 2015

International Technology Roadmap for

Semiconductors (ITRS) [6] because they have limited

batteries and long standby periods.

Several research groups have developed a variety of

flexible memories and logic gates based on the

organic thin-film transistor (OTFT). However, these

OTFT-based devices still face significant challenges

in the development of high-density devices with

high performance and low power consumption.

These challenges result from the inherent material

properties, incompatible lithography processes, and

volatile complementary logic circuits [7-9].

Compared to devices based on OTFT, the

polymer-based memristor or memristive device,

which is a nanoscale two-terminal passive device,

has been well known as a promising flexible

nonvolatile memory device owing to its simple

structure, fast switching speed, high packing density,

excellent flexibility, and low operating voltage

[10-13]. Memristors [14] and memristive devices [15]

were predicted by Chua in 1971 as the fourth basic

circuit element, which was later demonstrated by a

Hewlett-Packard (HP) laboratory team in 2008 [16].

The unique property of the memristor is the

variation of its nonvolatile resistance state depending

on the current or voltage history across it. While

numerous research groups and semiconductor

industries have developed memristors primarily for

memory applications, memristors can also be used as

functional blocks for logic gates, artificial neuron

networks, and analog circuits [17-19]. In particular,

the memristive logic gates can perform a nonvolatile

logic-in-memory circuit, enabling normally-off

computing with the static power dissipation of 0 W

[20-22]. They furthermore enable development of an

advanced computer architecture that is different

from the conventional von Neumann architecture

with its physically separate memory and logic

circuits that suffer from the data transfer rate

between the central processing unit and memory

[23].

A representative approach of the memristive

nonvolatile logic-in-memory circuit is the

memristor-based material implication (IMP) logic

gate, in which resistance is used as the logical state

[17,24,25]. The input and output of the logic gates are

stored on memristors within the crossbar array, and

the IMP and FALSE operations (where the FALSE

operation always yields the logical ‘0’) form basic

Boolean functions. This architecture, however,

requires two voltage pulses to perform logic

operations. It furthermore requires an additional

resistor within each row of the crossbar, which

necessitates a complicated control circuit design and

dissipates high power. Moreover, the output result is

stored not by a dedicated output memristor, but by

one of the inputs.

Another memristive nonvolatile logic-in-memory

circuit, memristor-aided logic (MAGIC) architecture,

was theoretically proposed [26]. Unlike IMP logic,

memristors for the input and output are separated,

and output is written to a dedicated memristor.

Without an additional resistor, a single voltage pulse

is only required to operate logic gates. The MAGIC

architecture is thereby advantageous over IMP logic

in terms of latency and energy consumption.

Specifically, it is 2.4 times faster than IMP logic and

consumes 33.7% of the total energy consumed in IMP

logic [27]. Furthermore, the simple architecture of

MAGIC can enable a memristive nonvolatile

logic-in-memory circuit to be reliably implemented

on flexible substrate over IMP logic. However, the

large device-to-device variation within the crossbar

array may result in the implementation of simple

gates with few cycles of operation [17,22,28]. This

leads to applications of IMP logic gate on only rigid

substrate and hinders MAGIC architecture from

being experimentally implemented. It is therefore

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necessary to develop a polymer-based memristor

array with good uniformity and reliable switching

characteristics that are robust to electrical and

mechanical stresses on flexible substrate in order to

realize a flexible electronic system with ultra-low

static power consumption via MAGIC architecture.

Recently, we developed a

poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane)

(pV3D3)-based unipolar memristor array fabricated

via initiated chemical vapor deposition (iCVD) with

a solvent-free process on a flexible substrate [29]. The

pV3D3-memristor appears very attractive compared

to other polymer-based flexible memristors on

account of its reliable switching characteristics

without a passivation layer, as well as its superior

mechanical stability, good uniformity in terms of

device-to-device distribution, and compatibility with

photolithography technology on flexible substrate.

These characteristics result from the mechanically

and electrically robust, highly uniform, and

outstanding chemically stable pV3D3 thin film

deposited via a solvent-free iCVD process. In

particular, because these outstanding characteristics

of pV3D3-memristor on flexible substrate are

essential factors for enabling compact and reliable

nonvolatile logic-in-memory circuits, the

pV3D3-memristor array shows considerable

potential for nonvolatile logic-in-memory circuits on

flexible substrate.

In this study, we experimentally realized the

pV3D3-memristive nonvolatile logic-in-memory

circuits, thereby enabling static power consumption

of 0 W on flexible polyethersulfone (PES) substrate

using only the theoretically proposed MAGIC

architecture. Unlike existing reports on memristive

nonvolatile logic-in-memory circuits with few

operation cycles on rigid substrate, we demonstrated

that the basic Boolean functions were reliably

implemented on flexible substrate during multiple

cycles, and even under bent conditions, at the

bending radius of 3.8 mm. This achievement resulted

from the reliable switching performance

characteristics that are robust to electrical and

mechanical stresses, the good uniformity of the

memristor array, and the simple MAGIC architecture.

To the best of our knowledge, this demonstration is

the first successful one of its kind. Consequently, we

succeeded in realizing NOR, NOT, OR, AND, and

NAND logic gates within the crossbar array that

contains input memristors without external

components. This enables efficient computing within

the memory array. Moreover, we experimentally

demonstrated that only five memristors can perform

a half adder, thus demonstrating the feasibility of the

memristive nonvolatile logic-in-memory circuit for

complex integrated circuits on flexible substrate.

2. Results and discussion

Figure 1a schematically illustrates the

pV3D3-memristor with an 8 8 array on a PES

substrate. The pV3D3-memristor consists of a Cu top

electrode (TE), pV3D3 films as material for the

memristor (its chemical structure is shown in the

Figure 1a inset with the green dotted line), and an Al

bottom electrode (BE). As depicted with the orange

dotted line in the Figure 1a inset, the

pV3D3-memristor operates with a Cu filament,

whose formation and rupture inside the pV3D3

material induces the low resistance state (LRS) and

high resistance state (HRS), thereby indicating

logical ‘1’ and ‘0,’ respectively [29]. The inset with the

black dotted line of Figure 1a shows that the

pV3D3-memristor array can realize basic Boolean

functions, such as NOT, NOR, OR, AND, and NAND

operations, as will be discussed below in more detail.

Figure 1b presents a photograph of the fabricated

flexible pV3D3-memristor array on PES substrate.

The inset displays a magnified optical image of the

pV3D3-memristor array with a unit memristor cell

area of approximately 5㎛ 5㎛. This area of the

pV3D3-memristor fabricated via a photolithography

technique is relatively smaller than that of

polymer-based devices fabricated through a shadow

mask. It thus indicates the feasibility for realization

of flexible devices with high density. As shown in

Figure 1c, the uniform and thin (~20 nm) pV3D3 film

between Cu TE and Al BE was confirmed via a

cross-sectional high-resolution transmission electron

microcopy (HRTEM). It demonstrates good

uniformity of the pV3D3 film characteristic arising

from gas-phase polymerization of the iCVD process.

Figure 1d shows a current–voltage (I-V) curve of a

typical pV3D3-memristor measured with a voltage

sweeping mode under air environment. After a

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forming process with high voltage and a compliance

current of 10 A, the resistance of the

pV3D3-memristor could be reproducibly switched

from LRS to HRS, or vice versa. The

pV3D3-memristor showed a typical unipolar

resistive switching behavior, where both SET and

RESET processes were independent of the voltage

polarity.

When the voltage sweep was applied to the Cu TE

from 0 to 3 V with compliance current, the current

abruptly increased at approximately 3.0 V, which

was designated as the set voltage. This SET process

occurs by the electrochemical reaction, enabling

formation of Cu filaments into pV3D3 film [29].

Afterward, by re-sweeping the applied voltage

without compliance current, the current rapidly

Figure 1. (a) A schematic illustration of pV3D3-memristor with an 8 8 crossbar array on a plastic substrate. The inset with the

orange dotted line shows the logical states of the pV3D3-memristor; the inset with the green dotted line displays the molecular structure

of pV3D3, and the inset with the black dotted line depicts the feasible logic gates using the pV3D3-memristor. (b) A photograph of a

flexible pV3D3-memristor on a PES substrate. The inset shows a magnified optical image of the flexible pV3D3-memristor array (scale

bar: 20㎛). (c) Cross-sectional HRTEM image of the flexible pV3D3-memristor. (d) I-V characteristics of the pV3D3-memristor. (e)

Cycling endurance and retention characteristics of the pV3D3-memristor.

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decreased at approximately 0.5 V, which was defined

as the reset voltage. This RESET process results from

the rupture of Cu filaments by Joule heating arising

from the high currents flowing through the Cu

filaments. The pV3D3-memristor had a wide

memory window above the 107 at 0.2 V reading

voltage, which corresponded to the ratio of HRS to

LRS.

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As shown in Figure 1e, pV3D3-memristor exhibited

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stable retention times for 105 s under air and a wide

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memory window above 107 without noticeable

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degradation during cycling endurance tests via the

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DC sweep mode and the repeated pulse voltages

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(Figure S1). Furthermore, the pV3D3-memristor

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array showed good uniformity in terms of

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device-to-device distributions of forming voltage and

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resistance of virgin devices (not electroformed)

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(Figure S2). This good uniformity of the

Figure 2. (a) Schematic of logic-in-memory operations within the crossbar array via the MAGIC method. (b) The MAGIC-NOT gate

within the crossbar array and its equivalent circuit. The logic gate consists of an input memristor and an output memristor. (c)

Experimental results of the MAGIC-NOT gate during 50 cycles. (d) MAGIC-NOR gate within the crossbar array and its equivalent

circuit. The logic gate consists of two input memristors and an output memristor. (e) Experimental results of the MAGIC-NOR gate for

all input memristor combinations during 50 cycles.

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pV3D3-memristor array resulted from the highly

uniform pV3D3 films, as shown in Figure 1c.

However, in the solution-processed polymer-based

memristors, it was challenging to achieve good

uniformity on account of the residual solvent or

pinhole formation in thicknesses below several

hundred nanometers of polymer film. Therefore, the

reliable switching performance and good uniformity

of the pV3D3-memristor array fabricated via the

solvent-free iCVD process made the

pV3D3-memristor array desirable for reliable

memristive nonvolatile logic-in-memory circuits on

flexible substrate.

Figure 2 illustrates the operation of NOT and NOR

gates via the MAGIC architecture. As schematically

illustrated in Figure 2a, the logic gates are realized

using the information stored in memristors on the

crossbar array, thereby enabling the logic-in-memory

operation. The logic operation of MAGIC works via

two sequential steps. The first step initializes the

output memristor to logical ‘1.’ In the second step,

voltage V0 is applied across the memristors for logic

operation, as shown in Figures 2b and d. For a

specific combination of input memristors, the logical

state of the initialized output memristor can be

changed during application of V0.

Because voltage drop across the output memristor

during application of V0 should be sufficiently high

to switch its logical state, it is necessary to choose

voltage V0 with a sufficient margin, which includes a

reset voltage cycle-to-cycle variation and

device-to-device variation (Figure S3). Thus, for

convenience of measurement, we selected 2 V as the

pulse voltage V0 with a pulse width of 5 ms. The

following logic operation employed this value of

voltage as V0.

We previously reported that the switching speed for

the reset process is 500 ns in the pV3D3-memristor

without device process optimization [29]. Note that

the feasible switching speed of the memristor is 85 ps

[30]. Therefore, the switching speed of the

pV3D3-memristor can possibly be improved by

scaling the pV3D3thickness or by a specifically

designed structure with the transmission line [30].

Accordingly, low energy consumption per logic

operation and fast logic-in-memory operations with

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the pV3D3-memristor would be enabled.

Figure 2b presents a schematic of the MAGIC-NOT

gate within a crossbar array and its equivalent circuit.

The MAGIC-NOT gate consists of an input

memristor and an output memristor, which are

connected in series with an opposite polarity. The

NOT gate was realized in two steps. The output

memristor was initialized into a logical ‘1,’ followed

by application of voltage V0 at the input memristor.

The applied voltage formed the voltage divider

between the input and output memristors, leading to

a change in the state of the output memristor

depending on the input memristor state. For the case

in which the input memristor was logical ‘1,’ the

voltage drop across the output memristor was higher

than its reset voltage. Hence, the output memristor

state was changed to the logical ‘0.’

On the other hand, in the case of the input

memristor logical ‘0,’ the applied voltage V0 dropped

mainly across the input memristor. This did not

change the output memristor state. Thus, the output

memristor maintained the logical ‘1.’ We

implemented the MAGIC-NOT operation using the

pV3D3-memristor during 50 cycles, as shown in

Figure 2c.

The MAGIC-NOR gate can additionally be

implemented within a crossbar array, as shown in

Figure 2d. The two input memristors are connected

in parallel and linked in series with an output

memristor. As in the NOT operation, two execution

steps are required in the NOR operation. In the first

execution, the logical ‘1’ is written at the output

memristor. The second execution induces the

conditional logic operation of output memristor by

applying voltage V0. In the condition in which both

input memristors are logical ‘0,’ the voltage drop

across the output memristor is lower than its reset

voltage by the voltage divider, resulting in the

output memristor initial logical ‘1.’ However, for all

other input combinations (input 1, input 2: 01, 10, 11),

the output memristor voltage is higher than its reset

voltage, thus switching output memristor to logical

‘0’.

Figure 2e shows that the reliable MAGIC-NOR

operation using the pV3D3-memristor during the 50

cycles is guaranteed. Most reported memristive logic

operations via IMP logic have shown limited

experimental results for a few cycles of operations,

which may have been on account of the memristor

device-to-device variation [17,22,28]. Therefore,

reliable multi-cycle operations of MAGIC-NOT and

-NOR gates benefit from the reliable

pV3D3-memristor array with highly uniform and

electrically robust pV3D3 film.

It should be noted that, the states of the output

memristors in our study exhibited broad

distributions during the operation of NOR and NOT

gates via the MAGIC architecture. These

distributions may have been related to the state drift

phenomenon [23] and the variations of the ruptured

filament path length [31] during the MAGIC

operation. However, the output memristors after

MAGIC operations showed a wide memory window

above 106 between states of logical ‘1’ and ‘0.’ This

result was on account of the pV3D3-memristor

inherent high on/off ratio, which enabled the reliable

sensing operation of the output memristor logical

state.

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After NOT and NOR operations, the output

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memristor state showed stable retention times for 104

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s (Figure S4). Such a nonvolatile characteristic of the

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pV3D3-memristive logic gates can effectively

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suppress the static power dissipation compared with

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complementary logic circuits, which suffer from the

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sub-threshold leakage current of transistors, because

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no need exists for supplying voltage to maintain the

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output logical state [21,22,32]. Therefore, the

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pV3D3-memristive logic gates performed the

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normally-off computing with the static power

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consumption of 0 W, thereby achieving the static

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power consumption target of battery-powered

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devices reported in the 2015 ITRS [6]. In addition, the

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output memristor nonvolatile characteristic enabled

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its state to be used as an input for the other logic gate,

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which indicates its feasibility for the cascade logic

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operation required in functionally complete logic

Figure 3. (a) Schematic of the MAGIC-OR gate within the crossbar array. The logic gate is linked in series with a MAGIC-NOR gate

and a MAGIC-NOT gate. (b) OR gate symbol and its truth table. (c) Experimental results of the MAGIC-NOR gate. (d) Schematic of

the MAGIC-AND gate within a crossbar array. The logic gate is linked in series with two MAGIC-NOT gates and an MAGIC-NOR

gate. (e) AND gate symbol and its truth table. (f) Experimental results of the MAGIC-AND gate. (g) Schematic of the MAGIC-NAND

gate within a crossbar array. The logic gate is sequentially linked in series with two MAGIC-NOT gates, a MAGIC-NOR gate, and a

MAGIC-NOT gate. (h) NAND gate symbol and its truth table. (i) Experimental results of the MAGIC-NAND gate.

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circuits.

Using the theoretically proposed MAGIC

architecture, additional logic gates were designed

with the aid of the external memristors located

outside the active input memristors array [26]. In

contrast, we designed the basic Boolean functions,

such as OR, AND, and NAND gates, via the

appropriate network of NOT and NOR gates

renowned as the universal logic gate, inside the

active crossbar array that included input memristors.

This approach enabled more efficient data

processing than the architecture that employs

external components.

Using the same operation scheme depicted in

Figure 2, the additional MAGIC logic gates were

realized (Figure 3). The MAGIC-OR gate was

realized in three steps (Figures 3a-c). First, the

initialization of memristors (logical ‘1’ for the output

memristor and the input values for the input

memristors) was necessary for the MAGIC operation.

Second, the MAGIC-NOR operation with input

memristors A and B was implemented and served as

the input for the next step. Third, we implemented

the MAGIC-NOT operation with the output

memristor of MAGIC-NOR. Figure 3c shows that the

MAGIC-OR gate was successfully implemented with

the sequential operations.

The MAGIC-AND operation was additionally

performed in three sequential steps, as shown in

Figures 3d-f. First, the memristors were initialized in

preparation for the MAGIC operation. Second, the

MAGIC-NOT operations were implemented for

input memristors A and B. To complete the

MAGIC-AND operation, the two output memristors

of the MAGIC-NOT operation were used as the

input memristors of the MAGIC-NOR operation.

After the MAGIC-NOR operation, the MAGIC-AND

gate was completely achieved, as shown in the

measurement results of Figure 3f.

The schematic and illustration of the

MAGIC-NAND operation are shown in Figures 3g-i.

The first execution step was the initialization of the

memristors. Next, input memristors A and B were

used for the MAGIC-NOT operation. The

MAGIC-NOR operation was performed with the

output memristors of the MAGIC-NOT operation.

For finalization of the MAGIC-NAND operations,

the output memristor of the MAGIC-NOR operation

Figure 4. (a) Schematic of the MAGIC-NOT gate within the crossbar array under a bent condition. The inset shows a photograph of an

I-V measurement being performed under a fixed condition. (b) Experimental results of the MAGIC-NOT gate under the bent condition.

(c) Schematic of MAGIC-NOR gate within the crossbar array under the bent condition. (d) Experimental results of the MAGIC-NOR

gate for all input memristor combinations under the bent condition.

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was used as the input memristor of the MAGIC-NOT

operation. The measurement results of Figure 3i

show the perfect operation of the MAGIC-NAND

gate.

We therefore demonstrated that the

pV3D3-memristor array on flexible substrate can

perform the logic-in-memory operation by

implementing basic Boolean functions, such as NOT,

NOR, OR, AND, and NAND gates, within the

crossbar array. Although the initialization process of

output memristor can cause the long latency in

pV3D3-memristive nonvolatile logic-in-memory

circuit, more memristors including output and

intermediate memristors can be initialized

simultaneously to lower the latency [27]. This

strategy can eliminate the requirement for multiple

intermediate initializations, but increasing the

utilized area. Therefore, any memristive logic circuits

can be optimized for the latency and area constraints

of the application. We believe that the

pV3D3-memristive nonvolatile logic-in-circuits are

very promising not only for implementing the

advanced computing architecture to solve the von

Neumann bottleneck, but also for achieving

normally-off computing with static power

consumption of 0 W in the flexible electronic system.

To confirm the operation of flexible memristive

logic circuits under mechanical deformation, a

bending test was carried out for the implementation

of MACIC-NOT and -NOR gates. We previously

reported that our pV3D3-memristor showed reliable

switching characteristics at the bending radius of 3.8

mm [29]. Hence, the MAGIC-NOT and -NOR

operations were performed at the bending radius of

3.8 mm. MAGIC-NOT (Figure 4a and b) and -NOR

gates (Figure 4c and d) were implemented under a

bent circumstance without significant degradation.

Furthermore, after the repeated bending over 1000

cycles at the bending radius of 3.8 mm, MAGIC-NOT

and -NOR gates were successfully realized (Figure

S5). The outstanding mechanical robustness of the

pV3D3-memristive logic gates benefitted from both

the elastic nature of the hexagonal siloxane network

of the pV3D3 film [33] and the memristor device

characteristics with a nanometer-scale vertical

channel.

When an external strain is applied to a device,

tensile or compressive strain primarily occurs in a

lateral direction. In conventional FETs based on

lateral active channels, the external strain applied to

Figure 5. (a) Schematic for realization of a half adder within the crossbar array. (b) Circuit schematic of the half adder using a

combination of NOT and NOR gates, and its truth table. (c) Experimental results of the half adder using five memristors within a

crossbar array. (d) Comparison table for a MOSFET and the memristor device count required for the logic gates and half adder.

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the channel induces band structure modifications,

resulting in the change of mobility of FETs [34].

However, in the case of a memristor device operated

with a metal filament, the metal filament with a

nanometer-scale vertical channel is minimally

vulnerable to the magnitude and direction of

external strain [35]. Owing to this robust logic

operation of the pV3D3-memristor against

mechanical stress, we therefore experimentally

showed, for the first time, that the memristive logic

gate can work reliably under a bent circumstance,

thereby enabling the pV3D3-mermistive nonvolatile

logic-in-memory circuit to be suitable for building a

flexible electronic system with ultra-low static power

dissipation.

Using the logic gates designed via MAGIC

architecture, the basic building block of computation,

such as adder logic, can be realized for

demonstration of practical application. Here, we

report a half adder that consists of 1 XOR and 1 OR

gates (Figure 5a). The half adder usually adds the

two single binary digits, A and B, to calculate Sum

and carry out Carry (Figure 5b). The half adder can

be realized using 3 NOR and 2 NOT gates via five

memristors in a 1 5 crossbar array, as schematically

illustrated in Figures 5a and b.

During operation of the half adder, the memristors

in other rows either did not undergo the forming

process, or they were programmed into HRS, which

mitigated unintentional leakage currents in the

crossbar array structure. To implement the half

adder shown in Figure 5b, a sequence of steps was

necessary (Figure S6). First, M1 and M2 of the

memristors were written to the input values of A and

B, and the other memristors were initialized. The

second and third steps were involved in operating

the NOT logic gates of A and B, where the output

was stored into M3 and M4, respectively. Fourth, the

Carry bit was acquired from M5, which was the

output of the NOR logic gates of M3 and M4. Fifth,

M3 was initialized and then processed by the NOR

logic operation with input M1 and M2. Lastly, the

Sum bit was extracted from M4, which resulted from

the NOR logic operation with input M3 and M5.

The implementation stream of the half adder is

shown in Figure S6, and the experimental results are

given in Figure 5c. In the latter figure, the half adder

using only five memristors is successfully achieved.

Figure 5d shows the number of metal-oxide

semiconductor field-effect transistors (MOSFETs)

and memristors required for implementing the logic

gates and adder circuit. Considering that the

memristor size was smaller than that of the transistor,

the memristive functional blocks could be fabricated

on a relatively smaller area, i.e., more logic functions

on a single chip, which can accomplish more than

Moore’s law without tremendous device scaling.

Therefore, the pV3D3-memristor shows the potential

of practical applications to complex circuit designs

on flexible substrate for building flexible electronic

systems with ultra-low static power consumption.

The memristive logic circuits via MAGIC

architecture have two advantages compared with

conventional complementary logic circuits. The first

is the nonvolatile logic-in-memory circuit in which

the same device can work for computing and

memory functionalities. This originates from the

memristor nonvolatile characteristics. It can realize

the standardized logic circuits with both ultra-low

power consumption and a short interconnection

delay. This differs from the conventional

complementary logic circuits in which the length of

the global interconnection in the advanced

very-large-scale integrated circuit (VLSI) results in

an increase of both dynamic power consumption and

interconnection delay [20]. In addition, the

nonvolatile logic-in-memory circuit can achieve the

static power consumption of 0 W during standby

mode because the electronic system with nonvolatile

logic gates cannot suffer from the sub-threshold

leakage current.

The second advantage is the sequential cascading

operation of the memristive logic circuits. The

cascading operation is required for implementing a

functionally complete logic, which enables all

essential functions in the arithmetic logic unit (ALU)

and central processing unit (CPU). The sequential

cascading operation additionally enables the

memristive logic circuit to occupy a much smaller

area for implementing the equivalent circuits

compared with the complementary logic circuit: five

memristors compared to fourteen transistors in the

case of the half adder circuit. Furthermore, while the

complementary logic circuits depend on the specific

gate topology to achieve a specific function, the

memristive logic circuits enable implementation of

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the reconfigurable circuits, which can achieve any

logic functions relying on their configuration inside

the crossbar array. Therefore, memristors within the

limited area can realize many logic functions, which

enables their effective implementation of the

complex functions, such as the adder.

3. Conclusions

In summary, for the first time, we experimentally

demonstrated that mechanically deformable,

nonvolatile logic-in-memory circuits enabling

normally-off computing can be realized using a

pV3D3-memristor array built on flexible substrate.

The working principle is based on the theoretically

proposed MAGIC architecture. Previous reports on

memristive nonvolatile logic-in-memory circuits

have shown the limitation of implementation for

simple gates within a few operation cycles on only

rigid substrate. On the other hand, we achieved a

successful implementation of the basic elements for

the universal logic gate, i.e., MAGIC-NOT and

-NOR gates with pV3D3-memristors during

multiple cycles, and even under bent conditions at a

bending radius of 3.8 mm, resulting from high

uniformity, outstanding mechanical stability, and

electrical robustness of the pV3D3 film. Other basic

Boolean functions, such as OR, AND, and NAND

gates, were successfully implemented by various

combinations of basic NOT and NOR gates.

For the practical application, we demonstrated that

these combinations of MAGIC-based logic gates

could also be extended to an implementation of a

half adder, which utilized only five memristors

through the appropriate network of NOT and NOR

gates. This indicated the feasibility of the

pV3D3-memristor array for a much more complex

integrated circuit design. We believe that our

research presents an importance milestone for

development of a battery-powered flexible

electronic system with not only static power

consumption of 0 W, but also the advanced

computing architecture that solves the von

Neumann bottleneck.

4. Methods

4.1 Device fabrication

Flexible pV3D3-memristor, illustrated in the inset

of Figure 1(a), were fabricated with crossbar

structures. First, 60 nm-thick Al electrodes were

patterned on PES substrate by photolithography

and subsequent thermal evaporation. A 20 nm-thick

pV3D3 film was then deposited on the Al electrodes

via the iCVD reactor, as described elsewhere [36].

Device fabrication was completed by depositing the

60 nm-thick Cu electrode lines via

photolithography and subsequent thermal

evaporation, perpendicular to the bottom electrodes,

for the 8 8 cross bar array. Line widths of both top

Cu and bottom Al electrodes were identical at about

5 ㎛ (the active area of memory: 5 ㎛ 5 ㎛ ).

Electrochemically active copper was selected as the

top electrode for supplying the source of the

conducting filaments, and aluminum was chosen an

inert bottom electrode.

4.2 Electrical characterization

In order to investigate the electrical characteristics

of the fabricated devices, a bias was applied to the

Cu electrode with the Al electrode grounded, via a

Keithley 4200 semiconductor parameter analyzer

without any device encapsulation in air atmosphere.

During the SET process, the compliance current was

set to protect the device.

Acknowledgements

This research was supported by the Global Frontier

Center for Advanced Soft Electronics (2011-0031640),

the Creative Research Program of the ETRI

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(15ZE1110), Wearable Platform Materials Technology

Center (WMC) funded by the National Research

Foundation of Korea (NRF) Grant of the Korean

Government (MSIP) (2016R1A5A1009926), and

Samsung Research Funding Center of Samsung

Electronics (SRFC-MA1402-04).

Electronic Supplementary Material: Supplementary

material (The cycling endurance result of

pV3D3-memristor via the repeated pulse voltages,

distribution of switching parameters in terms of

cycle-to-cycle and device-to-device, nonvolatile

characteristics of pV3D3-memristor after MAGIC

operation, MAGIC operation of pV3D3-memristor

after bending fatigue test, and half adder via MAGIC

method) is available in the online version of this

article at http://dx.doi.org/10.1007/s12274-***-****-*

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